Display device

Abstract

The present application relates to a display device. The display device includes a substrate including an active area and a non-active area surrounding the active area and including a pad area in which a plurality of touch pads are disposed; a plurality of sensing electrodes in the active area of the substrate; a plurality of sensing signal lines connected to each of the sensing electrodes; a multiplexer connected to the plurality of sensing signal lines; a pad multiplexer connection line connecting the multiplexer and the touch pads; and a lateral electric field blocking pattern between the pad multiplexer connection line and the substrate, wherein the lateral electric field blocking pattern covers the pad multiplexer connection line.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0171738, filed on December 20, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] Aspects of some example embodiments of the present application relate to display apparatuses. BACKGROUND

[0004] A display apparatus for displaying an image can be used in or included in various electronic apparatuses for displaying an image to a user. Such electronic apparatuses can include, for example, a smart phone, a tablet, a digital camera, a notebook computer, a navigation device, and a television. The display apparatus can include a display panel for generating and displaying an image and various input apparatuses.

[0005] In various electronic apparatuses, for example, in the field of smart phones and tablet computers, a touch panel for recognizing a touch input can be used together with a display apparatus. The touch panel determines (recognizes) whether a touch input of a user is provided and calculates a corresponding position as a touch input coordinate.

[0006] The touch panel can include an electrode unit. In this case, as the area of the electrode unit increases, a parasitic capacitance formed with a conductive layer of the display panel can increase.

[0007] The above information disclosed in the Background section is only for the purpose of understanding the background of the inventive concepts, and therefore, it can contain information that does not constitute prior art. SUMMARY

[0008] Aspects of some example embodiments of the present application include a display apparatus that relatively improves interference of a driving circuit adjacent to a connection line connecting an electrode unit of a touch sensor and a touch pad.

[0009] Additional features of some example embodiments of the present application will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of example embodiments of the inventive concepts.

[0010] According to some exemplary embodiments of the present disclosure, a display device includes: a substrate including an effective region and an ineffective region, the ineffective region surrounding the effective region and including a pad region in which a plurality of touch pads are disposed; a plurality of sensing electrodes disposed in the effective region of the substrate; a plurality of sensing signal lines connected to each of the sensing electrodes; a multiplexer connected to the plurality of sensing signal lines; a pad multiplexer connection line connecting the multiplexer and the touch pads; and a lateral electric field blocking pattern between the pad multiplexer connection line and the substrate, wherein the lateral electric field blocking pattern covers the pad multiplexer connection line.

[0011] According to some exemplary embodiments, each of the multiple sensing signal lines is connected one-to-one to each of the sensing electrodes.

[0012] According to some exemplary embodiments, the display device further includes a driving circuit adjacent to the pad multiplexer connection line, wherein the lateral electric field blocking pattern is configured to block the lateral electric field between the driving circuit and the pad multiplexer connection line.

[0013] According to some exemplary embodiments, the display device further includes a cathode electrode between the pad multiplexer connection line and the sensing electrode, wherein the cathode electrode covers the pad multiplexer connection line and the driving circuitry.

[0014] According to some exemplary embodiments, the driving circuit includes a light emission control driving circuit or a scanning driving circuit.

[0015] According to some exemplary embodiments, the driving circuit includes a thin-film transistor, and the pad multiplexer connection line extends parallel to the input signal line of the gate electrode of the thin-film transistor connected to the driving circuit.

[0016] According to some exemplary embodiments, the display device also includes a ground wire between the pad multiplexer connection line and the input signal line.

[0017] According to some exemplary embodiments, the lateral electric field blocking pattern is electrically connected to the ground wire.

[0018] According to some exemplary embodiments, the multiplexer includes a thin-film transistor, and the thin-film transistor of the multiplexer includes a drain electrode connected to a sensing signal line, a source electrode connected to a pad multiplexer connection line, and a gate electrode below the drain electrode and the source electrode.

[0019] According to some exemplary embodiments, the sensing signal line is electrically connected to a source connection electrode below the sensing signal line, and the source connection electrode is electrically connected to a drain electrode.

[0020] According to some exemplary embodiments, the source connection electrode is electrically connected to the gate connection electrode below the source connection electrode, and the gate connection electrode is electrically connected to the drain electrode.

[0021] According to some exemplary embodiments, the gate electrode is electrically connected to the select signal line of the multiplexer.

[0022] According to some exemplary embodiments, the display device further includes a driving substrate attached to a pad region, wherein the driving substrate is configured to apply an input signal to a sensing electrode and apply an output signal output from the sensing electrode.

[0023] According to some exemplary embodiments, the display device further includes a lateral electric field blocking pattern pad located in the pad region and electrically connected to the lateral electric field blocking pattern, wherein voltage is applied to the lateral electric field blocking pattern through the lateral electric field blocking pattern pad.

[0024] According to some exemplary embodiments, the voltage applied to the transverse electric field blocking pattern is equal to at least one of the voltage of the input signal and the voltage of the output signal.

[0025] According to some exemplary embodiments, the cathode electrode overlaps with and is electrically connected to the transverse electric field blocking pattern.

[0026] According to some exemplary embodiments of the present disclosure, a display device includes: a substrate including an effective region and an ineffective region, the ineffective region surrounding the effective region and including a pad region in which a plurality of touch pads are disposed; a plurality of light-emitting elements disposed in the effective region of the substrate; an encapsulation layer on the plurality of light-emitting elements and extending over the effective and ineffective regions; a touch sensor on the encapsulation layer, the touch sensor including a plurality of sensing electrodes disposed on the encapsulation layer in the effective region and a plurality of sensing signal lines connected to each of the sensing electrodes; a multiplexer connected to the plurality of sensing signal lines; a pad multiplexer connection line connecting the multiplexer and the touch pads; and a lateral electric field blocking pattern between the pad multiplexer connection line and the substrate, wherein the lateral electric field blocking pattern covers the pad multiplexer connection line.

[0027] According to some exemplary embodiments, each of the multiple sensing signal lines is connected one-to-one to each of the sensing electrodes.

[0028] According to some exemplary embodiments, the display device also includes a drive circuit adjacent to the pad multiplexer connection line, wherein the lateral electric field blocking pattern is configured to block the lateral electric field between the drive circuit and the pad multiplexer connection line.

[0029] According to some exemplary embodiments, the display device further includes a cathode electrode between the pad multiplexer connection line and the sensing electrode, wherein the cathode electrode covers the pad multiplexer connection line and the driving circuit, and the driving circuit includes a light emission control driving circuit or a scanning driving circuit.

[0030] However, the aspects of the invention according to exemplary embodiments are not limited to those set forth herein. These and other aspects of the invention will become more apparent to those skilled in the art from the following detailed description of the invention. Attached Figure Description

[0031] The above and other aspects and features of the invention will become more apparent from the accompanying drawings, which describe some exemplary embodiments of the invention in more detail with reference to the drawings, in which:

[0032] Figure 1 This is a plan view of a display device according to some exemplary embodiments;

[0033] Figure 2 This is a schematic partial cross-sectional view of a display device according to some exemplary embodiments;

[0034] Figure 3 This is a schematic cross-sectional view illustrating an exemplary laminated structure of a display panel according to some exemplary embodiments;

[0035] Figure 4 This is a schematic plan view of a display panel according to some exemplary embodiments;

[0036] Figure 5 yes Figure 4 A magnified view of a portion;

[0037] Figure 6 This is a circuit diagram of a multiplexer included in a multiplexer unit of a display device, according to some exemplary embodiments;

[0038] Figure 7 This is an enlarged view of the sensing electrodes and sensing signal lines according to some exemplary embodiments;

[0039] Figure 8 It is along Figure 7 A sectional view taken by line I-I';

[0040] Figure 9 It is a layout diagram illustrating the arrangement relationship between the pixels of the display unit and the grid pattern of the touch component according to some exemplary embodiments;

[0041] Figure 10 It is along Figure 9A sectional view taken from line II-II';

[0042] Figure 11 This is a cross-sectional view of a display panel according to some exemplary embodiments;

[0043] Figure 12 It is a cross-sectional view showing the arrangement relationship between the lateral electric field blocking pattern and the lateral electric field blocking pattern pads;

[0044] Figure 13 It is a plan view showing the arrangement relationship between the pad multiplexer connection lines and the input signal lines of the external drive circuit;

[0045] Figure 14 yes Figure 13 A schematic cross-sectional view;

[0046] Figure 15 This is a cross-sectional view of a display panel according to some exemplary embodiments;

[0047] Figure 16 This is a cross-sectional view of a display panel according to some exemplary embodiments;

[0048] Figure 17 This is a cross-sectional view of a display panel according to some exemplary embodiments;

[0049] Figure 18 This is a cross-sectional view of a display panel according to some exemplary embodiments;

[0050] Figure 19 This is a schematic plan view of a display panel according to some exemplary embodiments;

[0051] Figure 20 This is a plan view illustrating the arrangement of pad multiplexer connection lines and input signal lines of external drive circuitry according to some exemplary embodiments; and

[0052] Figure 21 It is along Figure 20 The sectional view taken from line III-III'. Detailed Implementation

[0053] The specific structural and functional descriptions of some exemplary embodiments of the invention disclosed herein are for illustrative purposes only. The invention can be embodied in many different forms without departing from its spirit and distinctive features. Therefore, embodiments of the invention are disclosed for illustrative purposes only and should not be construed as limiting the invention. That is, the invention is defined only by the scope of the claims.

[0054] It will be understood that when an element is referred to as being related to another element, such as by being “connected” or “linked” to another element, then that element may be directly connected to or directly linked to the other element, or there may be an intermediary element between them. Conversely, it should be understood that when an element is referred to as being related to another element, such as by being “directly connected” or “directly linked” to another element, then there is no intermediary element. Other expressions explaining the relationship between elements (such as “between,” “directly between,” “proximately to,” or “directly adjacent to”) should be interpreted in the same manner.

[0055] Throughout the specification, the same reference numerals will refer to the same or similar parts.

[0056] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both singular and plural forms unless the context clearly indicates otherwise. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the relevant listed items. It will be further understood that, when used in this specification, the terms “comprises” and / or “comprising” or “includes” and / or “including” specify the presence of the described features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0058] Furthermore, relative terms such as “lower” or “bottom” and “upper” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, relative terms are intended to encompass different orientations of the device. For example, if the device in one of the drawings is flipped, an element described as being “below” the other element will subsequently be oriented “upper” the other element. Thus, depending on the specific orientation of the drawing, the exemplary term “lower” can include both “lower” and “upper” orientations. Similarly, if the device in one of the drawings is flipped, an element described as being “below” or “under” the other element will subsequently be oriented “above” the other element. Thus, the exemplary term “below” or “under” can encompass both “upper” and “lower” orientations.

[0059] As used herein, “about” or “approximately” includes the value as well as the average of the values ​​within an acceptable range of deviations from the particular value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value.

[0060] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0061] This document describes aspects of some exemplary embodiments with reference to cross-sectional views, which are schematic diagrams of idealized embodiments. Thus, variations in the illustrated shapes should be expected, for example, due to manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific region shapes shown herein, but should include, for example, deviations in shape due to manufacturing processes. For example, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the precise shape of the regions, nor are they intended to limit the scope of the claims.

[0062] In the following description, some exemplary embodiments of the invention will be described in more detail with reference to the accompanying drawings.

[0063] Figure 1 This is a plan view of a display device according to some exemplary embodiments, and Figure 2 This is a schematic partial cross-sectional view of a display device according to some exemplary embodiments.

[0064] According to some exemplary embodiments, the first direction DR1 and the second direction DR2 intersect each other in different directions (e.g., in the vertical direction). Figure 1 In the plan view, for ease of description, a first direction DR1 is defined as the vertical direction and a second direction DR2 is defined as the horizontal direction. In the following description of some exemplary embodiments, one side of the first direction DR1 refers to the upward direction in the plan view, and the other side of the first direction DR1 refers to the downward direction in the plan view; one side of the second direction DR2 refers to the right direction in the plan view, and the other side of the second direction DR2 refers to the left direction in the plan view. However, the directions mentioned in the exemplary embodiments should be understood as relative directions, and the embodiments are not limited to the directions mentioned above.

[0065] Reference Figure 1 and Figure 2 Display device 1 can refer to any electronic device that provides a display screen. Examples of display device 1 can include various products such as televisions, laptops, monitors, billboards and Internet of Things, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigators and ultra-mobile PCs (UMPs).

[0066] Display device 1 includes an active area AAR and an inactive area NAR. In display device 1, when a portion of the display screen (or the area displaying an image) is defined as a display area, a portion of the screen not displayed (or the area not displaying an image) is defined as a non-display area, and the area where touch input is detected is defined as a touch area. The display area and the touch area can be included in the active area AAR. The display area and the touch area can overlap each other. That is, the active area AAR can be an area that performs display and also detects touch input. The shape of the active area AAR can be a rectangle or a rectangle with rounded corners. For example, the shape of the active area AAR is a rectangle with rounded corners, wherein the side in the first direction DR1 is longer than the side in the second direction DR2. However, the embodiments according to the present invention are not limited to this, and the active area AAR can have various shapes, such as a rectangle, square, other polygons, circle, or ellipse, where the side in the second direction DR2 is longer than the side in the first direction DR1.

[0067] The non-active area NAR is located or arranged around the active area AAR. For example, the non-active area NAR can be a border area. The non-active area NAR can surround all sides of the active area AAR (the four sides in the figure). However, the embodiments according to the present invention are not limited to this. For example, the non-active area NAR may not be located around the upper side of the active area AAR or around the left and right sides of the active area AAR, and the active area AAR may extend to the edge of the display device 1 without including the border area.

[0068] Signal lines or drive circuitry for applying signals to the active area AAR (display area or touch area) can be arranged in the inactive area NAR. The inactive area NAR may not include the display area. Furthermore, the inactive area NAR may not include the touch area. According to some exemplary embodiments, the inactive area NAR may include a portion of the touch area, and a sensing element such as a pressure sensor may be located in the corresponding area. According to some exemplary embodiments, the active area AAR may be the exact same area as the display area of ​​the display screen, and the inactive area NAR may be the same area as the non-display area where no screen is displayed.

[0069] Display device 1 includes a display panel 10 that provides a display screen. Examples of display panels 10 may include organic light-emitting display panels, micro LED display panels, nano LED display panels, quantum dot light-emitting display panels, liquid crystal display panels, plasma display panels, field emission display panels, electrophoretic display panels, and electrowetting display panels. Hereinafter, as an example of display panel 10, an organic light-emitting display panel is shown. However, embodiments of the present invention are not limited thereto, and the same technical concept can be applied to other display panels.

[0070] The display panel 10 may include a plurality of pixels. The plurality of pixels may be arranged in a matrix direction or in a matrix configuration. The shape of each pixel in a planar view may be rectangular or square, but is not limited thereto according to embodiments of the present disclosure, and each pixel may have a rhombus shape, wherein each side is inclined relative to the first direction DR1. Each pixel may include a light-emitting area. Each light-emitting area may have the same shape as the pixel, or may have a different shape than the pixel. For example, when the pixel has a rectangular shape, the light-emitting area of ​​the corresponding pixel may have various shapes, such as rectangle, rhombus, hexagon, octagon, or circle. Details of each pixel and each light-emitting area will be described in more detail below.

[0071] The display device 1 may further include a touch component for detecting touch input. The touch component may be configured as a panel or film separate from the display panel 10 and attached to the display panel 10, or the touch component may be configured as a touch layer located inside the display panel 10. According to some exemplary embodiments, exemplary embodiments in which the touch component is disposed inside the display panel 10 to be included in the display panel 10 are shown, but embodiments according to the present invention are not limited thereto.

[0072] The display panel 10 may include a flexible substrate, which may include a flexible polymer material such as polyimide. Therefore, the display panel 10 can be bent, warped, folded, or rolled up.

[0073] The display panel 10 may include a curved region BR in which the panel is curved. Based on the curved region BR, the display panel 10 may be divided into a main region MR located on one side of the curved region BR and a sub-region SR located on the other side of the curved region BR.

[0074] The display area of ​​the display panel 10 is located in the main region MR. According to some exemplary embodiments, the edge surrounding the display area, the entire curved region BR, and the entire sub-region SR in the main region MR may be non-display areas. However, embodiments according to the present invention are not limited thereto, and the curved region BR and / or the sub-region SR may include the display area.

[0075] The main region MR can typically have a shape similar to the planar appearance of the display device 1. The main region MR can be a flat area located in a plane. However, embodiments according to the invention are not limited to this, and at least one of the remaining edges (edges) other than the edge (side) connected to the curved region BR can be curved in the main region MR to form a curved surface or bend in the vertical direction. When at least one of the remaining edges (edges) other than the edge (side) connected to the curved region BR can be curved or bent in the main region MR, the display area can also be arranged at the corresponding edge. However, embodiments according to the invention are not limited to this, and the curved or bent edge can be a non-display area that does not display a screen, or the display area and non-display area can be mixed in the corresponding portions.

[0076] The curved region BR connects to one side of the main region MR in the first direction DR1. For example, the curved region BR can connect to the lower short side of the main region MR. The width of the curved region BR can be less than (or narrower than) the width (short side width) of the main region MR. The connection between the main region MR and the curved region BR can have an L-shaped cut.

[0077] Within the curved region BR, the display panel 10 can be bent with a certain curvature in the downward direction (i.e., the direction opposite to the display surface) in the thickness direction. The curved region BR can have a constant radius of curvature, but embodiments according to this disclosure are not limited thereto, and some exemplary embodiments may have different radii of curvature for each portion. Because the display panel 10 is bent within the curved region BR, the surface of the display panel 10 can be reversed. That is, an upward-facing surface of the display panel 10 can be changed through the curved region BR to face outwards and then downwards.

[0078] Sub-region SR extends from the curved region BR. Immediately after the bending is completed, sub-region SR may extend in a direction parallel to the main region MR. Sub-region SR may overlap with the main region MR in the thickness direction of the display panel 10. That is, according to some exemplary embodiments, the display panel 10 may be bent at the curved region BR such that the sub-region SR is located behind or below the main region MR, such that the sub-region SR overlaps with the main region MR in a direction perpendicular to the plane of the main region MR. The width of the sub-region SR (width in the second direction DR2) may be equal to the width of the curved region BR, but is not limited to this according to embodiments of the invention.

[0079] The driver chip 20 may be located in the sub-region SR. The driver chip 20 may include an integrated circuit for driving the display panel 10. The integrated circuit may include an integrated circuit for the display.

[0080] The pad unit may be located at the end of a sub-region SR of the display panel 10. The pad unit may include multiple display signal line pads and multiple touch signal line pads. A driving substrate 30 may be connected to the pad unit located at the end of the sub-region SR of the display panel 10. The driving substrate 30 may be a flexible printed circuit board or a film. The driving substrate 30 may include a substrate driving chip 35. The substrate driving chip 35 may include an integrated circuit for the touch unit. According to some exemplary embodiments, the integrated circuit for the display and the integrated circuit for the touch unit may be configured as separate chips. However, embodiments of the present invention are not limited thereto, and the integrated circuit for the display and the integrated circuit for the touch unit may be configured to be integrated into a single chip.

[0081] Figure 3 This is a schematic cross-sectional view illustrating an exemplary laminated structure of a display panel according to some exemplary embodiments.

[0082] Reference Figure 3 The display panel 10 may include a circuit driving layer DRL located on the substrate SUB. The circuit driving layer DRL may include circuitry for driving the light-emitting layer EML of the pixels. The circuit driving layer DRL may include a plurality of thin-film transistors.

[0083] The emissive layer (EML) can be located on or formed on the circuit driving layer (DRL). The EML may include an organic emissive layer. The EML can emit light with various brightness levels based on or according to a driving signal transmitted from the circuit driving layer (DRL).

[0084] The encapsulation layer ENL can be located on or formed on the light-emitting layer EML. The encapsulation layer ENL can include an inorganic film or a laminate of an inorganic film and an organic film. As another example, glass or an encapsulation film can be used as the encapsulation layer ENL.

[0085] The touch layer (TSL) or touch sensor can be located on the encapsulation layer (ENL). The touch layer (TSL) is the layer that recognizes touch input and can be used as a touch component. The touch layer (TSL) may include multiple sensing areas and multiple sensing electrodes.

[0086] A polarizing layer (POL) can be located on the touch layer (TSL). The polarizing layer (POL) can be used to reduce external light reflection. The polarizing layer (POL) can be attached to the touch layer (TSL) via an adhesive layer. However, according to some exemplary embodiments, the polarizing layer (POL) can be omitted.

[0087] The protective layer WDL can be located on or formed on the polarizing layer POL. The protective layer WDL may include, for example, a window component. The protective layer WDL can be attached to the polarizing layer POL using an optically transparent adhesive or the like.

[0088] Figure 4 This is a schematic plan view of a display panel according to some exemplary embodiments. Figure 5 yes Figure 4 A magnified image of a portion. Figure 6 This is a circuit diagram of a multiplexer included in a multiplexer unit of a display device, according to some exemplary embodiments. Figure 7 These are enlarged views of the sensing electrodes and sensing signal lines according to some exemplary embodiments. Figure 8 It is along Figure 7 A cross-sectional view taken by line I-I'. Figure 9 This is a layout diagram illustrating the arrangement relationship between the pixels of a display unit and the grid pattern of a touch component according to some exemplary embodiments. Figure 10 It is along Figure 9 A sectional view taken from line II-II'. Figure 11 This is a cross-sectional view of a display panel according to some exemplary embodiments, and Figure 12 It is a cross-sectional view showing the arrangement relationship between the lateral electric field blocking pattern and the lateral electric field blocking pattern pads.

[0089] For ease of explanation, although in Figure 4 and Figure 5The text shows a comparison with... Figure 1 The inefficient region NAR in the text is relatively wide, but the size and shape of the inefficient region NAR can be compared with... Figure 1 The size and shape of the non-effective region NAR are basically the same.

[0090] First, refer to Figure 4 and Figure 5 Multiple sensing electrodes TE and multiple sensing signal lines TL connected to the multiple sensing electrodes TE are arranged in the effective area AAR of the display panel 10, and the ineffective area NAR of the display panel 10 may include a contact unit CP, a multiplexer unit MUXP, and an external drive circuit unit OCP located at the left edge of the effective area AAR in the figure. The ineffective area NAR of the display panel 10 may also include a pad area PA to which the drive substrate 30 is attached.

[0091] Although the contact unit CP, multiplexer unit MUXP, and external drive circuit unit OCP are shown in this embodiment at the left edge of the effective area AAR, the embodiments according to the present invention are not limited thereto, and the contact unit CP, multiplexer unit MUXP, and external drive circuit unit OCP may be located at the right edge of the effective area AAR, or may be located at both the left and right sides of the effective area AAR. Hereinafter, the location of the contact unit CP, multiplexer unit MUXP, and external drive circuit unit OCP at the left edge of the effective area AAR will be described primarily.

[0092] Multiple sensing electrodes TE can be arranged in the effective area AAR of the display panel 10. The multiple sensing electrodes TE can be electrodes used for sensing touch input. The multiple sensing electrodes TE can be arranged along a first direction DR1 and a second direction DR2. The multiple sensing electrodes TE can be arranged along a matrix direction.

[0093] At least some of the sensing electrodes TE may have a rhombus shape. Some sensing electrodes TE may have a graphic shape cut from a rhombus shape. The dimensions and shapes of the rhombus-shaped sensing electrodes TE may be substantially the same as each other.

[0094] However, the implementation is not limited to the implementation described above, and the shape and size of the sensing electrode TE can be modified in different ways.

[0095] Each of the sensing electrodes TE can include a planar pattern or a grid pattern. When the sensing electrode TE includes a planar pattern, the sensing electrode TE can be formed from a transparent conductive layer. Figure 7 and Figure 9As shown, when the sensing electrode TE comprises a grid pattern arranged along the non-light-emitting area, it can avoid interfering with the light-emitting process despite the application of an opaque, low-resistance metal. The following description will use the case where each sensing electrode TE comprises a grid pattern as an example, but the embodiments according to the present invention are not limited thereto.

[0096] A single sensing electrode TE can constitute a unit sensing region. That is, multiple unit sensing regions can be arranged in the matrix direction.

[0097] In each unit sensing area, the capacitance value between a sensing electrode TE and a user's touch from outside the display device 1 can be measured to determine whether a touch input has been performed and to calculate the corresponding position as touch input coordinates. Touch sensing can be performed using a self-capacitance method. Compared to when touch sensing can be performed using a mutual capacitance method, the area of ​​the unit sensing area can be smaller when touch sensing can be performed using a self-capacitance method. When the area of ​​the unit sensing area is smaller, the parasitic capacitance with the conductive layer of the display panel 10 located below the sensing electrode TE can be reduced.

[0098] Each sensing signal line TL can be connected one-to-one to each sensing electrode TE. A multiplexer unit MUXP can be located between the contact unit CP and the active area AAR, and an external drive circuit unit OCP can be located between the multiplexer unit MUXP and the active area AAR. Each sensing signal line TL connected to each sensing electrode TE can extend through the external drive circuit unit OCP and the multiplexer unit MUXP to the contact unit CP.

[0099] The sensing signal line TL extending to the contact unit CP can be electrically connected to the multiplexer contact line MCL that passes through the contact unit CP and the multiplexer unit MUXP.

[0100] The multiplexer contact line MCL and the sensing signal line TL can be electrically connected to each other in a one-to-one correspondence. Figure 11 The connecting electrodes CE1 and CE2 shown can be arranged in the contact unit CP. The sensing signal line TL extending to the contact unit CP can physically contact the second connecting electrode CE2 to be electrically connected to it, and the second connecting electrode CE2 can be connected through the third contact hole CNT3 (see...). Figure 11 It is electrically connected to the first connection electrode CE1. Figure 5 Multiplexer contact lines (MCL) may include Figure 11 The first connecting electrode CE1 and the second connecting electrode CE2.

[0101] Simultaneously, each sensing electrode TE receives an input signal from the substrate driving chip 35 of the driving substrate 30, and provides an output signal, such as a touch input signal, to the substrate driving chip 35 via a touch pad. Since the sensing electrodes TE according to this embodiment are electrically connected one-to-one to each sensing signal line TL, the number of touch pads can be increased. Therefore, to reduce the required number of touch pads, a multiplexer DEMUX can also be provided, which is used to selectively apply the input signals provided to at least two sensing electrodes TE and the output signals output from the sensing electrodes TE to the substrate driving chip 35.

[0102] The multiplexer contact line MCL, electrically connected in a one-to-one correspondence to the sensing signal line TL, can extend from the contact unit CP to the multiplexer unit MUXP. The multiplexer contact line MCL can be electrically connected to the multiplexer DEMUX located in the multiplexer unit MUXP. For example, the multiplexer contact line MCL can be electrically connected to the drain electrode 143 of the multiplexer DEMUX (see...). Figure 11 ).

[0103] Reference Figure 6 The multiplexer DEMUX includes a first multiplexer transistor T. DM1 Second multiplexer transistor T DM2 Although the first multiplexer transistor T is shown in the figure. DM1 Second multiplexer transistor T DM2 Both are PMOS transistors, but the embodiments according to the present invention are not limited thereto. The first multiplexer transistor T DM1 Second multiplexer transistor T DM2 Each of them includes a source electrode, a drain electrode, and a gate electrode.

[0104] The pad multiplexer connection line PML can be electrically connected to the first multiplexer transistor T. DM1 The source electrode. A multiplexer contact line MCL can be connected to the first multiplexer transistor T. DM1 The drain electrode. The first multiplexer selection signal CL1 can be provided to the first multiplexer transistor T. DM1 The gate electrode. When a low-level first multiplexer select signal CL1 is applied to the first multiplexer transistor T DM1 When the gate electrode is reached, the first multiplexer transistor T DM1 It is conductive, and therefore, any multiplexer contact line MCL and pad multiplexer connection line PML can be electrically connected to each other.

[0105] The pad multiplexer connection line PML can be electrically connected to the second multiplexer transistor T.DM2 The source electrode. The second multiplexer transistor T. DM2 The drain electrode can be connected to transistor T, which is not connected to the first multiplexer. DM1 Another multiplexer contact line, MCL.

[0106] The second multiplexer selection signal CL2 can be provided to the second multiplexer transistor T. DM2 The gate electrode. When a low-level second multiplexer select signal CL2 is applied to the second multiplexer transistor T DM2 When the gate electrode is reached, the second multiplexer transistor T DM2 It is conductive, and therefore another multiplexer contact line MCL and pad multiplexer connection line PML can be electrically connected to each other.

[0107] When the first multiplexer transistor T DM1 Second multiplexer transistor T DM2 When the first multiplexer selection signal CL1 and the second multiplexer selection signal CL2 are selectively turned on, a pad multiplexer connection line PML can be selectively connected to two multiplexer contact lines MCL. According to some exemplary embodiments, time-division driving can be performed when the first multiplexer selection signal CL1 and the second multiplexer selection signal CL2 have different timing sequences.

[0108] Furthermore, although the embodiment shows that the pad multiplexer connection line PML is selectively connected to two multiplexer contact lines MCL, according to some exemplary embodiments, the pad multiplexer connection line PML can be connected to three or four multiplexer contact lines MCL. When a multiplexer DEMUX selects and connects to three or more multiplexer contact lines MCL, the number of multiplexer transistors included in the multiplexer DEMUX can also be three or more.

[0109] The pad multiplexer connection line PML can be electrically connected to the touch pad TPAD located in the pad area PA. For example... Figure 5 As shown, the pad multiplexer connection line PML can extend from the multiplexer DEMUX and can extend along the first direction DR1 to connect to each touch pad TPAD.

[0110] An input signal having an input voltage (e.g., a predetermined input voltage) provided from the substrate driver chip 35 can be provided to the sensing electrode TE via the touch pad TPAD, the pad multiplexer connection line PML, the source and drain electrodes of the multiplexer DEMUX, the multiplexer contact line MCL, and the sensing signal line TL. An output signal (touch input signal) sensed from the sensing electrode TE can be provided to the substrate driver chip 35 via the sensing signal line TL, the multiplexer contact line MCL, the drain and source electrodes of the multiplexer DEMUX, the pad multiplexer connection line PML, and the touch pad TPAD.

[0111] A ground line GL can also be positioned between the pad multiplexer connection line PML and the external drive circuit unit OCP. Each of the ground lines GL can be electrically connected to the ground pad GPAD located in the pad area PA. The substrate driver chip 35 can apply a ground voltage to each of the ground lines GL through the ground pad GPAD.

[0112] Simultaneously, the external drive circuit unit OCP can be positioned adjacent to the pad multiplexer connection line PML. For example... Figure 5 As shown, since the external drive circuit unit OCP is positioned adjacent to the pad multiplexer connection line PML, the external drive circuit unit OCP may affect the touch signal passing through the pad multiplexer connection line PML. To reduce the lateral electric field interference of the external drive circuit unit OCP, which is positioned adjacent to the pad multiplexer connection line PML, on the touch signal passing through the pad multiplexer connection line PML, the lateral electric field blocking pattern FPP can also be located on the lower portion of the pad multiplexer connection line PML.

[0113] The lateral electric field barrier pattern (FPP) can overlap with the multiplexer unit (MUXP) and the pad multiplexer connection line (PML). The FPP can also overlap with the adjacent ground line (GL). That is, the FPP can cover a portion of the multiplexer unit (MUXP), the pad multiplexer connection line (PML), and the ground line (GL). The FPP may not overlap with the external drive circuit unit (OCP).

[0114] A lateral electric field blocking pattern (FPP) is arranged to overlap the lower portion of a pad multiplexer connection line (PML) to block the lateral electric field between the PML and the external drive circuit unit (OCP) adjacent to the PML. In this case, an electric field can also be formed between the FPP and the PML. Due to the electric field formed between the FPP and the PML, input and output signals transmitted through the PML may be interfered with. Therefore, a voltage (e.g., a predetermined voltage) can be applied to the FPP. As a method of applying a voltage (e.g., a predetermined voltage) to the FPP, a method is shown to further provide a lateral electric field blocking pattern line (FPPL) connected to the FPP and to further provide a lateral electric field blocking pattern pad (FPPAD) in the pad region (PA). For example, when an input signal is applied from the substrate driver chip 35 to the touch pad TPAD, a first voltage with the same magnitude as the input signal can be applied to the lateral electric field barrier pattern pad FPPAD. Similarly, when an output signal is provided from the touch pad TPAD to the substrate driver chip 35, a second voltage with the same magnitude as the output signal can be applied to the lateral electric field barrier pattern pad FPPAD. Therefore, the lateral electric field barrier pattern FPP receives a voltage at the same level as the pad multiplexer connection line PML arranged in the thickness direction, preventing interference to the input and output signals transmitted through the pad multiplexer connection line PML due to the electric field formed between the lateral electric field barrier pattern FPP and the pad multiplexer connection line PML.

[0115] Reference Figure 7 and Figure 8 As described above, each sensing electrode TE can be formed as a grid pattern. When each sensing electrode TE has a rhomboid shape in the figure, the grid pattern constituting each sensing electrode TE can be formed by a first line extending along the inclined direction of the first direction DR1 and a second line intersecting the first line.

[0116] Each sensing electrode TE and the sensing signal line TL electrically connected to each sensing electrode TE can be directly disposed on the encapsulation layer ENL. The sensing electrodes TE and the sensing signal line TL can be disposed on the same layer and can be made of the same material.

[0117] Each sensing electrode TE and the sensing signal line TL electrically connected to each sensing electrode TE may include a metallic conductive layer or a transparent conductive layer. The metallic conductive layer may include aluminum, titanium, copper, molybdenum, silver, or alloys thereof.

[0118] The transparent conductive layer can include transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO), conductive polymers such as PEDOT, metal nanowires, or graphene. As described above, since each sensing electrode TE is arranged in a non-light-emitting region, each sensing electrode TE can remain unaffected by the light-emitting process even when it is made of a low-resistance opaque metal.

[0119] Each sensing electrode TE and the sensing signal line TL electrically connected to each sensing electrode TE may include a conductive layer with a multilayer structure. For example, each sensing electrode TE and the sensing signal line TL electrically connected to each sensing electrode TE may include a conductive layer with a three-layer structure of titanium / aluminum / titanium.

[0120] Reference Figure 9 and Figure 10 The effective display area AAR comprises multiple pixels. Each pixel includes a light-emitting area EMA. The light-emitting area EMA may overlap with and be defined by an opening in the embankment layer PDL. A non-light-emitting area NEM is located between the light-emitting areas EMA of each pixel. The non-light-emitting area NEM may overlap with and be defined by the embankment layer PDL. The non-light-emitting area NEM may surround the light-emitting area EMA. When viewed in a plan view, the non-light-emitting area NEM has a grid shape or mesh shape arranged along a diagonal direction intersecting a first direction DR1 and a second direction DR2. A mesh pattern MSP may be arranged within the non-light-emitting area NEM.

[0121] A pixel may include a first color pixel R (e.g., a red pixel), a second color pixel B (e.g., a blue pixel), and a third color pixel G (e.g., a green pixel). The first color typically has a wavelength band in the range of about 640 nm to about 750 nm and is considered red; the second color typically has a wavelength band in the range of about 450 nm to about 480 nm and is considered blue; and the third color typically has a wavelength band in the range of about 492 nm to about 600 nm and is considered green.

[0122] The shape of the luminous area EMA of each color pixel can typically be an octagon, quadrilateral, or rhombus with rounded corners. However, embodiments of the present invention are not limited to this, and the shape of each luminous area EMA can be a circle, rhombus, polygon, or polygon with rounded corners.

[0123] According to some exemplary embodiments, the shape of the light-emitting region EMA_R of the first color pixel R and the shape of the light-emitting region EMA_B of the second color pixel B can have similar shapes to each other, that is, rhombuses with rounded corners. The light-emitting region EMA_B of the second color pixel B can be larger than the light-emitting region EMA_R of the first color pixel R.

[0124] The luminous area EMA_G of the third color pixel G can be smaller than the luminous area EMA_R of the first color pixel R. The luminous area EMA_G of the third color pixel G can be tilted in the diagonal direction and can have an octagonal shape with the maximum width in the tilting direction. The third color pixel G may include a third color pixel G in which the luminous area EMA_G1 is tilted in the first diagonal direction and a third color pixel G in which the luminous area EMA_G2 is tilted in the second diagonal direction.

[0125] Color pixels can be arranged in various ways. According to some exemplary embodiments, a first color pixel R (e.g., a red pixel) and a second color pixel B (e.g., a blue pixel) are alternately arranged in a first row along a second direction DR2, and a third color pixel G (e.g., a green pixel) can be arranged in a second row adjacent to the first row along the second direction DR2. Pixels belonging to the second row (third color pixels G) can be alternately arranged in the second direction DR2 relative to pixels belonging to the first row. In the second row, third color pixels G tilted in the first diagonal direction (refer to EMA_G2) and third color pixels G tilted in the second diagonal direction (refer to EMA_G1) can be alternately arranged along the second direction DR2. The number of third color pixels G belonging to the second row can be twice the number of first color pixels R or second color pixels B belonging to the first row.

[0126] The third row has the same arrangement of color pixels as the first row, but the arrangement order can be reversed. That is, the second color pixel B can be arranged in the third row in the same column as the first color pixel R in the first row, and the first color pixel R can be arranged in the third row in the same column as the second color pixel B in the first row. The fourth row has the same arrangement of third color pixels G as the second row, but the arrangement order can be reversed based on the shape that is sloping in the diagonal direction. That is, the third color pixel G that is sloping in the second diagonal direction can be arranged in the fourth row in the same column as the third color pixel G that is sloping in the first diagonal direction in the second row, and the third color pixel G that is sloping in the first diagonal direction can be arranged in the fourth row in the same column as the third color pixel G that is sloping in the second diagonal direction in the second row.

[0127] The arrangement of the first to fourth rows can be repeated along the first direction DR1. However, the arrangement of pixels is of course not limited to the above description.

[0128] The mesh pattern MSP can be arranged along the pixel boundaries within the non-emissive region NEM. The mesh pattern MSP may not overlap with the emissive region EMA. The width of the mesh pattern MSP can be smaller than the width of the non-emissive region NEM. According to some exemplary embodiments, the mesh aperture MHL exposed by the mesh pattern MSP can have a generally rhomboid shape.

[0129] Although the size of the mesh apertures MHL can be the same, they can differ from one another depending on the size of the luminous area EMA exposed by the mesh aperture MHL, or they can differ from one another regardless of the size of the luminous area EMA. Although the figure shows one mesh aperture MHL corresponding to one luminous area EMA, the embodiments according to the invention are not limited thereto, and one mesh aperture MHL can correspond to two or more luminous areas EMA.

[0130] exist Figure 10 In the cross-sectional view, most of the layers below the anode electrode 161 are omitted, and the structure on the organic light-emitting diode is shown.

[0131] Reference Figure 10 The substrate 101 of the display device 1 can be made of an insulating material such as a polymer resin. Examples of polymer resins may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl compounds, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), and combinations thereof. The substrate 101 can be a flexible substrate capable of being bent, folded, rolled up, etc. Examples of materials forming a flexible substrate may include, but are not limited to, polyimide (PI).

[0132] The anode electrode 161 is located on the substrate 101. In the figures, for ease of illustration, the anode electrode 161 is shown directly on the substrate 101. However, as is known in the art, multiple thin-film transistors and multiple signal lines are arranged between the substrate 101 and the anode electrode 161.

[0133] The anode electrode 161 can be a pixel electrode arranged for each pixel. The anode electrode 161 can have a laminated film structure in which a material layer having a high work function, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3), and a reflective material layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or mixtures thereof, are laminated. The material layer with a higher work function can be formed on top of the reflective material layer and thus closer to the light-emitting layer. The anode electrode 161 can have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, or ITO / Ag / ITO, but its structure is not limited to these.

[0134] A barrier layer PDL can be formed on substrate 101. The barrier layer PDL can be formed on or located on anode electrode 161 and can include openings exposing anode electrode 161. The luminescent region (EMA) and the non-luminescent region (NEM) can be defined by the barrier layer PDL and its openings. The barrier layer PDL can include organic insulating materials such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The barrier layer PDL can also include inorganic materials.

[0135] A light-emitting layer is formed on or located on the anode electrode 161 exposed by the dam layer PDL. The light-emitting layer may include an organic layer OL. The organic layer OL may include an organic light-emitting layer, and may also include a hole injection layer / hole transport layer and / or an electron injection layer / electron transport layer.

[0136] For each color pixel, the wavelength of light emitted by the emissive layer can be different. For example, the emissive layer may include a first color emissive layer located in the emissive region EMA_R of the first color pixel R, a second color emissive layer located in the emissive region EMA_B of the second color pixel B, and a third color emissive layer located in the emissive region EMA_G of the third color pixel G. The first color emissive layer may emit light in the red wavelength band, the second color emissive layer may emit light in the blue wavelength band, and the third color emissive layer may emit light in the green wavelength band.

[0137] The cathode electrode 170 can be disposed on or located on the light-emitting layer. The cathode electrode 170 can be a common electrode that is integrally disposed on the light-emitting layer without distinguishing pixels. The anode electrode 161, the light-emitting layer, and the cathode electrode 170 can constitute an organic light-emitting element.

[0138] The cathode electrode 170 can contact not only the light-emitting layer but also the upper surface of the embankment layer PDL. The cathode electrode 170 can be conformally formed relative to the underlying structure to reflect the steps of the underlying structure.

[0139] The cathode electrode 170 may include a material layer having a low work function, including Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or compounds or mixtures thereof (e.g., a mixture of Ag and Mg). The cathode electrode 170 may also include a transparent metal oxide layer situated on the material layer having a low work function.

[0140] A thin-film encapsulation layer 180, comprising a first inorganic film 181, an organic film 182, and a second inorganic film 183, is located on the cathode electrode 170. Each of the first inorganic film 181 and the second inorganic film 183 may comprise silicon nitride, silicon oxide, or silicon oxynitride. The organic film 182 may comprise an organic insulating material, such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0141] The sensing electrode TE may be located on the thin-film encapsulation layer 180, and its redundant description will be omitted. Figure 10 This is a cross-sectional view of the sensor unit, and therefore, the sensing signal line TL is not shown in the cross-sectional view.

[0142] The sensing electrode TE can overlap with the embankment layer PDL and can be located in the non-emitting region NEM. Because the grid pattern MSP forming the sensing electrode TE does not overlap with the emitting region EMA, the grid pattern MSP does not interfere with light emission and is not visible to the user.

[0143] Reference Figure 11 The substrate 101 can be arranged or positioned to cover the effective region AAR and the ineffective region NAR. The substrate 101 may include multiple laminated films. The substrate 101 may include a first laminated film 102, a second laminated film 103 located on the first laminated film 102, and a substrate bonding layer 104 located between the first laminated film 102 and the second laminated film 103. Each of the laminated films 102 and 103 may include a flexible organic insulating material. The substrate bonding layer 104 may include an adhesive layer.

[0144] However, the structure of substrate 101 is not limited to this, and substrate 101 may have a structure in which a second laminate 103 and a substrate bonding layer 104 other than the first laminate 102 may be omitted, and a barrier layer 111, which will be described later, may be located on the first laminate 102.

[0145] The barrier layer 111 may be located on the substrate 101. The barrier layer 111 may include an inorganic material. Figure 11 As shown in the examples, the barrier layer 111 may include multiple laminated films. According to some exemplary embodiments, the buffer layer may also be located between the barrier layer 111 and the substrate 101 or between the barrier layer 111 and the semiconductor layers ACT1, ACT2 and ACT3, which will be described later.

[0146] Semiconductor layers ACT1, ACT2, and ACT3 may be located on barrier layer 111. The first semiconductor layer ACT1 may be located in the active region AAR, the second semiconductor layer ACT2 may be located in the multiplexer unit MUXP, and the third semiconductor layer ACT3 may be located in the external drive circuit unit OCP.

[0147] A first gate insulating layer 112 may be located on semiconductor layers ACT1, ACT2, and ACT3. The first gate insulating layer 112 may perform an insulating function between semiconductor layers ACT1, ACT2, and ACT3 and gate electrodes GE1, GE2, and GE3, which will be described later. The first gate insulating layer 112 may include an inorganic material.

[0148] The first conductive layer 110 may be located on the first gate insulating layer 112. The first conductive layer 110 may include a first gate electrode GE1 located in the effective region AAR, a third gate electrode GE3 located in the external drive circuit unit OCP, and a lateral electric field blocking pattern FPP located between the multiplexer unit MUXP and the external drive circuit unit OCP. The first gate electrode GE1 may be the gate electrode of the thin-film transistor located in the effective region AAR, and the third gate electrode GE3 may be the gate electrode of the thin-film transistor located in the external drive circuit unit OCP.

[0149] The first conductive layer 110 may comprise at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 110 may be a monolayer film made of any suitable conductive material (including the exemplary materials listed above). However, embodiments of the present invention are not limited thereto, and the first conductive layer 110 may be a laminated film.

[0150] The second gate insulating layer 113 may be located on the first conductive layer 110. The second gate insulating layer 113 may be used to insulate the first conductive layer 110 from the second conductive layer 120, which will be described later. The second gate insulating layer 113 may include an inorganic material.

[0151] The second conductive layer 120 may be located on the second gate insulating layer 113. The second conductive layer 120 may include a second gate electrode GE2 located in the multiplexer unit MUXP. The second gate electrode GE2 may be a multiplexer DEMUX located in the multiplexer unit MUXP (see [link to DEMUX]). Figure 6 The second conductive layer 120 may comprise at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second conductive layer 120 may be a monolayer film made of any suitable conductive material (e.g., the materials listed above). However, embodiments of the invention are not limited thereto, and the second conductive layer 120 may be a laminated film.

[0152] The first interlayer insulating film 114 may be located on the second conductive layer 120. The first interlayer insulating film 114 may serve to insulate the second conductive layer 120 from the third conductive layer 130, which will be described later. The first interlayer insulating film 114 may include inorganic materials.

[0153] The third conductive layer 130 may be located on the first interlayer insulating film 114. The third conductive layer 130 may include a first connection electrode CE1 or a gate connection electrode positioned throughout the contact unit CP, the multiplexer unit MUXP, and the region between the contact unit CP and the multiplexer unit MUXP. The first connection electrode CE1 may be electrically connected to the second connection electrode CE2 and the drain electrode 143 of the thin-film transistor of the multiplexer DEMUX located in the multiplexer unit MUXP. The third conductive layer 130 may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer 130 may be a monolayer film made of any suitable conductive material (e.g., the exemplary materials listed above). However, embodiments of the invention are not limited thereto, and the third conductive layer 130 may be a laminated film.

[0154] The second interlayer insulating film 115 may be located on or formed on the third conductive layer 130. The second interlayer insulating film 115 may include inorganic or organic materials. The second interlayer insulating film 115 may serve to insulate the third conductive layer 130 and the fourth conductive layer 140, which will be described in more detail below.

[0155] The fourth conductive layer 140 may be located on the second interlayer insulating film 115. The fourth conductive layer 140 may include the drain electrode 141 and source electrode 142 of the thin film transistor of the pixel located in the effective region AAR, the drain electrode 143 and source electrode 144 of the thin film transistor of the multiplexer DEMUX located in the multiplexer unit MUXP, the selection signal line 145 electrically connected to the second gate electrode GE2 of the thin film transistor of the multiplexer DEMUX, the drain electrode 146 and source electrode 147 of the thin film transistor of the external drive circuit unit OCP, the second connection electrode CE2 or the source connection electrode located in the contact unit CP, the pad multiplexer connection line PML, and the low-voltage power line ELVSS located in the region between the contact unit CP and the multiplexer unit MUXP.

[0156] The drain electrode 141 and source electrode 142 of the thin-film transistor of the pixel can be electrically connected to the first semiconductor layer ACT1 through contact holes CNT1 and CNT2, respectively. The drain electrode 143 and source electrode 144 of the thin-film transistor of the multiplexer DEMUX can be electrically connected to the second semiconductor layer ACT2 through contact holes CNT5 and CNT6, respectively. The drain electrode 146 and source electrode 147 of the thin-film transistor of the external drive circuit unit OCP can be electrically connected to the third semiconductor layer ACT3 through contact holes CNT8 and CNT9, respectively. In addition, the second connection electrode CE2 can be electrically connected to the first connection electrode CE1 through the third contact hole CNT3, the drain electrode 143 of the thin-film transistor of the multiplexer DEMUX can be electrically connected to the first connection electrode CE1 through the fourth contact hole CNT4, and the select signal line 145 can be electrically connected to the second gate electrode GE2 through the seventh contact hole CNT7. Meanwhile, the fourth conductive layer 140 may also include an external drive circuit control signal line 148 (hereinafter referred to as the input signal line) that is electrically connected to the third gate electrode GE3 of the thin film transistor of the external drive circuit unit OCP through the tenth contact hole CNT10.

[0157] In addition, the fourth conductive layer 140 may also include a ground line GL in the region between the multiplexer unit MUXP and the external drive circuit unit OCP.

[0158] The first insulating layer 150 may be located on the fourth conductive layer 140. The first insulating layer 150 may include: a first insulating pattern 151 located on the drain electrode 141 and source electrode 142 of the thin-film transistors of the pixels positioned in the effective region AAR, and the drain electrode 146 and source electrode 147 of the thin-film transistors of the external drive circuit unit OCP, to cover these components; a second insulating pattern 152 located on the drain electrode 143 and source electrode 144 of the thin-film transistors of the multiplexer DEMUX located in the multiplexer unit MUXP, and the pad multiplexer connection line PML, to cover these components; a third insulating pattern 153 located on the second connection electrode CE2 to partially expose the upper surface of the second connection electrode CE2; and a fourth insulating pattern 154 located on the ground line GL to cover the ground line GL. The first insulating layer 150 may include an organic insulating material.

[0159] The insulating patterns 151 to 154 may be spaced apart from each other.

[0160] The fifth conductive layer 160 can be located on the first insulating layer 150. This is because the material of the fifth conductive layer 160 is similar to that described above. Figure 10 The anode electrode 161 described is made of the same material, so its redundant description will be omitted.

[0161] The fifth conductive layer 160 may include: an anode electrode 161 located in the region between the effective region AAR, the external drive circuit unit OCP, and the region between the external drive circuit unit OCP and the effective region AAR; and a third connection electrode 162 physically spaced apart from the anode electrode 161 and located in the region between the multiplexer unit MUXP and the contact unit CP. The anode electrode 161 and the third connection electrode 162 may not overlap with the pad multiplexer connection line PML, respectively. That is, the space between the anode electrode 161 and the third connection electrode 162 may overlap with the pad multiplexer connection line PML in the thickness direction. Therefore, parasitic capacitance can be prevented from forming between the pad multiplexer connection line PML and the fifth conductive layer 160, which is electrically connected to the low-voltage power line ELVSS, which will be described later.

[0162] The second insulating pattern 152 of the first insulating layer 150 exposes the upper surface of the low-voltage power line ELVSS, and the third connecting electrode 162 can directly contact the low-voltage power line ELVSS having the exposed upper surface.

[0163] The fifth insulating pattern 191 and the sixth insulating pattern 192, located between the contact unit CP and the multiplexer unit MUXP, can be situated on the fifth conductive layer 160. Each of the fifth insulating pattern 191 and the sixth insulating pattern 192 may comprise an organic insulating material. The fifth insulating pattern 191 is positioned closer to the multiplexer unit MUXP than the sixth insulating pattern 192 and can be directly situated on the third connection electrode 162. The sixth insulating pattern 192 can be in direct contact with the upper surface of the second insulating pattern 152 exposed through the third connection electrode 162 and with the third connection electrode 162. The sixth insulating pattern 192, the second insulating pattern 152 overlapping the sixth insulating pattern 192 in the thickness direction, and the fifth insulating pattern 191 can function as dams. That is, the sixth insulating pattern 192 and the second insulating pattern 152 overlapping the sixth insulating pattern 192 in the thickness direction can serve as a second dam, and the fifth insulating pattern 191 can serve as a first dam.

[0164] The cathode electrode 170 may be located on the fifth insulating pattern 191 and the sixth insulating pattern 192. The cathode electrode 170 may be positioned throughout the active area AAR, the external drive circuit unit OCP, and the multiplexer unit MUXP, and may be in direct contact with the anode electrode 161 in the active area AAR and the external drive circuit unit OCP for electrical connection to the anode electrode 161. It may also be in direct contact with the third connection electrode 162 located below it in the multiplexer unit MUXP for electrical connection to the third connection electrode 162, and thus may be electrically connected to the low-voltage power line ELVSS.

[0165] A thin-film encapsulation layer 180 may be located on the cathode electrode 170. A first inorganic film 181 and a second inorganic film 183 may extend from the effective region AAR to the first dam and the second dam, respectively. The first inorganic film 181 may be in direct contact with the first dam and the second dam. An organic film 182 may extend from the effective region AAR to the multiplexer unit MUXP and may have a smaller extension length than the inorganic films 181 and 182.

[0166] The sensing electrode TE can be located on the thin-film encapsulation layer 180. The sensing electrode TE can be located directly on the thin-film encapsulation layer 180.

[0167] Reference Figure 12 The lateral electric field barrier pattern line FPPL can be electrically connected to the lateral electric field barrier pattern FPP through the eleventh contact hole CNT11. The lateral electric field barrier pattern line FPPL can be physically connected to the lateral electric field barrier pattern pad FPPAD located in the pad area PA.

[0168] Figure 13 This is a plan view showing the arrangement of the pad multiplexer connection lines and the input signal lines of the external drive circuit. Figure 14 yes Figure 13 A schematic cross-sectional view.

[0169] Reference Figure 13 and Figure 14 The input signal line 148 of the thin-film transistor connected to the external drive circuit unit OCP can extend parallel to the pad multiplexer connection line PML. That is, the input signal line 148 of the thin-film transistor connected to the external drive circuit unit OCP can extend along the first direction DR1. The cathode electrode 170 can be located on the input signal line 148 and the pad multiplexer connection line PML, and the lateral electric field blocking pattern FPP can be located on the lower portion of the pad multiplexer connection line PML. The cathode electrode 170 can completely cover the input signal line 148 and the pad multiplexer connection line PML in a plan view, and the lateral electric field blocking pattern FPP can cover the pad multiplexer connection line PML and the adjacent ground line GL. The lateral electric field blocking pattern FPP can not overlap with the input signal line 148.

[0170] like Figure 14 As shown, a transverse electric field can be generated between the input signal line 148 and the pad multiplexer connection line PML. Figure 13 and Figure 14 As shown, when multiple pad multiplexer connection lines (PMLs) and multiple input signal lines 148 are arranged, a transverse electric field can be generated between the PMLs and the input signal lines 148, which are at the same or similar distance from the ground line GL. The transverse electric field can include a first transverse electric field drawn with a convex parabola toward the cathode electrode 170 and a second transverse electric field drawn with a convex parabola toward the transverse electric field blocking pattern FPP. The transverse electric field generated between the PMLs and the input signal lines 148 can produce signal noise in the PMLs.

[0171] The first lateral electric field can be blocked by the cathode electrode 170 located above the input signal line 148 and the pad multiplexer connection line PML. Furthermore, the second lateral electric field can overlap with the pad multiplexer connection line PML in the thickness direction, so as to be blocked by the lateral electric field blocking pattern FPP covering the pad multiplexer connection line PML. Therefore, signal aging of the pad multiplexer connection line PML that may be caused by the lateral electric field generated between the pad multiplexer connection line PML and the external drive circuit unit OCP can be reduced or prevented.

[0172] Other embodiments will be described below. In the following embodiments, components that are the same as those in the already described embodiments are indicated by the same reference numerals, and their descriptions will be omitted or simplified.

[0173] Figure 15 This is a cross-sectional view of a display panel according to another embodiment.

[0174] Reference Figure 15 The difference between the transverse electric field blocking pattern FPP_1 according to this embodiment and the transverse electric field blocking pattern FPP mentioned above according to the embodiment is that the transverse electric field blocking pattern FPP_1 is located in the second conductive layer 120_1.

[0175] For example, the lateral electric field blocking pattern FPP_1 according to this embodiment may be located in the second conductive layer 120_1. In other words, the second conductive layer 120_1 may also include the lateral electric field blocking pattern FPP_1. The first conductive layer 110_1 may include a first gate electrode GE1 and a third gate electrode GE3.

[0176] Figure 16 This is a cross-sectional view of a display panel according to another embodiment.

[0177] Reference Figure 16 The difference between the transverse electric field blocking pattern FPP_2 according to this embodiment and the transverse electric field blocking pattern FPP mentioned above according to the embodiment is that the transverse electric field blocking pattern FPP_2 is located in the third conductive layer 130_1.

[0178] For example, the lateral electric field blocking pattern FPP_2 according to this embodiment may be located in the third conductive layer 130_1. In other words, the third conductive layer 130_1 may also include the lateral electric field blocking pattern FPP_1. The first conductive layer 110_1 may include a first gate electrode GE1 and a third gate electrode GE3.

[0179] Figure 17 This is a cross-sectional view of a display panel according to another embodiment.

[0180] Reference Figure 17 The difference between the transverse electric field blocking pattern FPP_3 according to this embodiment and the transverse electric field blocking pattern FPP mentioned above according to the embodiment is that the transverse electric field blocking pattern FPP_3 does not overlap with the grounding line GL in the thickness direction.

[0181] For example, the lateral electric field blocking pattern FPP_3 according to this embodiment may not overlap with the ground line GL in the thickness direction. Therefore, the first conductive layer 110_2 may include the first gate electrode GE1, the third gate electrode GE3, and the aforementioned lateral electric field blocking pattern FPP_3.

[0182] Figure 18 This is a cross-sectional view of a display panel according to another embodiment.

[0183] Reference Figure 18 According to the transverse electric field blocking pattern FPP_4 of this embodiment and Figure 11 The difference in the implementation method is that the transverse electric field blocking pattern FPP_4 is electrically connected to the ground wire GL.

[0184] For example, the lateral electric field blocking pattern FPP_4 according to this embodiment can be electrically connected to the ground line GL. The lateral electric field blocking pattern FPP_4 can be electrically connected to the ground line GL through contact holes penetrating the second interlayer insulating film 115, the first interlayer insulating film 114, and the second gate insulating layer 113.

[0185] Because the lateral electric field blocking pattern FPP_4 is electrically connected to the ground line GL, the ground voltage applied from the ground pad GPAD can be applied equally to the lateral electric field blocking pattern FPP_4. That is, the ground voltage can be applied to the lateral electric field blocking pattern FPP_4. Although the embodiments according to the present invention are not limited thereto, the ground voltage can be substantially about 0V. Therefore, the lateral electric field blocking pattern line FPPL and the lateral electric field blocking pattern pad FPPAD connected to the lateral electric field blocking pattern FPP_4 can be omitted.

[0186] Therefore, the first conductive layer 110_3 may include a first gate electrode GE1, a third gate electrode GE3, and the aforementioned lateral electric field blocking pattern FPP_4.

[0187] Figure 19 This is a schematic plan view of a display panel according to another embodiment.

[0188] Reference Figure 19 The display panel according to this embodiment and Figure 5 The difference in the implementation method is that the transverse electric field blocking pattern FPP_5 is formed as a floating electrode.

[0189] For example, in the display panel according to this embodiment, the lateral electric field blocking pattern FPP_5 is formed as a floating electrode. That is, the display panel according to this embodiment and Figure 5 The difference in the implementation is that the lateral electric field blocking pattern line FPPL, which connects to the lateral electric field blocking pattern FPP_5 and the lateral electric field blocking pattern pad FPPAD, is omitted.

[0190] Figure 20 This is a plan view illustrating the arrangement of pad multiplexer connection lines and input signal lines of external drive circuitry according to some exemplary embodiments.Figure 21 It is along Figure 20 The sectional view taken from line III-III'.

[0191] Reference Figure 20 and Figure 21 According to the transverse electric field blocking pattern FPP_6 of this embodiment and Figure 13 The difference in the implementation is that the lateral electric field blocking pattern FPP_6 is electrically connected to the cathode electrode 170 through the twelfth contact hole CNT12 that penetrates the second insulating pattern 152, the second interlayer insulating film 115, the first interlayer insulating film 114, and the second gate insulating layer 113.

[0192] For example, the lateral electric field blocking pattern FPP_6 can be electrically connected to the cathode electrode 170 through the twelfth contact hole CNT12 that penetrates the second insulating pattern 152, the second interlayer insulating film 115, the first interlayer insulating film 114, and the second gate insulating layer 113. According to some exemplary embodiments, because the lateral electric field blocking pattern FPP_6 is electrically connected to the cathode electrode 170 and the cathode electrode 170 is electrically connected to the low-voltage power line ELVSS, the voltage supplied from the low-voltage power line ELVSS can be applied to the lateral electric field blocking pattern FPP_6. Therefore, features such as... Figure 19 The lateral electric field blocking pattern line FPPL is shown connecting the lateral electric field blocking pattern FPP_5 and the lateral electric field blocking pattern pad FPPAD.

[0193] The effects of this invention are not limited to the foregoing, and various other effects are contemplated herein.

[0194] Although some exemplary embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions may be made without departing from the scope and spirit of the invention as disclosed in the appended claims and their equivalents.

Claims

1. A display device, including: A substrate, comprising an effective region and an ineffective region, the ineffective region surrounding the effective region and including a pad region in which a plurality of touch pads are disposed; Multiple sensing electrodes are located in the effective region of the substrate; Multiple sensing signal lines are connected to each of the sensing electrodes; A multiplexer is connected to the multiple sensing signal lines; A pad multiplexer connection cable connects the multiplexer and the touch pad; as well as A lateral electric field blocking pattern is positioned between the pad multiplexer connection and the substrate. The lateral electric field barrier pattern covers the multiplexer connection lines of the pads. The display device further includes: a driving circuit, adjacent to the multiplexer connection line of the pads. The lateral electric field blocking pattern is configured to block the lateral electric field between the drive circuit and the pad multiplexer connection line.

2. The display device according to claim 1, in, Each of the multiple sensing signal lines is connected in a one-to-one correspondence to each of the sensing electrodes.

3. The display device according to claim 2, further comprising: The cathode electrode is located between the pad multiplexer connection line and the sensing electrode. The cathode electrode covers the pad multiplexer connection line and the drive circuit.

4. The display device according to claim 3, in, The driving circuit includes a light-emitting control driving circuit or a scanning driving circuit.

5. The display device according to claim 3, in, The driving circuit includes thin-film transistors, and The pad multiplexer connection line extends parallel to the input signal line of the gate electrode of the thin-film transistor connected to the driving circuit.

6. The display device according to claim 5, further comprising: The grounding wire is located between the pad multiplexer connection line and the input signal line.

7. The display device according to claim 6, in, The transverse electric field blocking pattern is electrically connected to the grounding wire.

8. The display device according to claim 3, in, The multiplexer includes thin-film transistors, and The thin-film transistor of the multiplexer includes a drain electrode connected to the sensing signal line, a source electrode connected to the pad multiplexer connection line, and a gate electrode located below the drain electrode and the source electrode.

9. The display device according to claim 8, in, The sensing signal line is electrically connected to the source connection electrode below the sensing signal line, and The source electrode is electrically connected to the drain electrode.

10. The display device according to claim 9, in, The source connection electrode is electrically connected to the gate connection electrode below the source connection electrode, and The gate connection electrode is electrically connected to the drain electrode.

11. The display device according to claim 8, in, The gate electrode is electrically connected to the select signal line of the multiplexer.

12. The display device according to claim 8, further comprising: The driving substrate is attached to the pad area. The driving substrate is configured to apply an input signal to the sensing electrode and apply an output signal output from the sensing electrode.

13. The display device according to claim 12, further comprising: A lateral electric field barrier pattern pad is located in the pad area and is electrically connected to the lateral electric field barrier pattern. The voltage is applied to the lateral electric field barrier pattern through the lateral electric field barrier pattern pad.

14. The display device according to claim 13, in, The voltage applied to the transverse electric field blocking pattern is equal to at least one of the voltage of the input signal and the voltage of the output signal.

15. The display device according to claim 3, in, The cathode electrode overlaps with and is electrically connected to the transverse electric field blocking pattern.

16. A display device, including: A substrate, comprising an effective region and an ineffective region, the ineffective region surrounding the effective region and including a pad region in which a plurality of touch pads are disposed; Multiple light-emitting elements are arranged in the effective region of the substrate; An encapsulation layer is applied to the plurality of light-emitting elements and extends over both the effective and ineffective regions. A touch sensor, on the encapsulation layer, includes a plurality of sensing electrodes disposed on the encapsulation layer in the effective area and a plurality of sensing signal lines connected to each of the sensing electrodes; A multiplexer is connected to the multiple sensing signal lines; A pad multiplexer connection cable connects the multiplexer and the touch pad; as well as A lateral electric field blocking pattern is positioned between the pad multiplexer connection and the substrate. The lateral electric field barrier pattern covers the multiplexer connection lines of the pads. The display device further includes: a driving circuit, adjacent to the multiplexer connection line of the pads. The lateral electric field blocking pattern is configured to block the lateral electric field between the drive circuit and the pad multiplexer connection line.

17. The display device according to claim 16, in, Each of the multiple sensing signal lines is connected in a one-to-one correspondence to each of the sensing electrodes.

18. The display device according to claim 17, further comprising: The cathode electrode is located between the pad multiplexer connection line and the sensing electrode. The cathode electrode covers the pad multiplexer connection line and the drive circuit, and The driving circuit includes a light-emitting control driving circuit or a scanning driving circuit.

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