A multi-core processor and a control method thereof

Abstract

The application provides a multi-core processor and a control method thereof, which are simple in structure, reasonable in design, conflict-free in memory access, do not need to yield or arbitrate, and can maintain high speed and high performance. The multi-core processor comprises a pair of processor cores A and processor cores B arranged in pairs, a shared memory for connecting the processor cores A and the processor cores B arranged in pairs respectively, a clock generation circuit configured to generate a clock signal, the clock signal being input into the processor core A and serving as a working timing of the processor core A to control interaction with the shared memory, an inverter connected to an output end of the clock generation circuit and configured to invert the clock signal to generate an inverted clock signal, and the inverted clock signal being input into the processor core B and serving as a working timing of the processor core B to control interaction with the shared memory.

Description

TECHNICAL FIELD

[0001] The present application relates to multi-core processor architecture, in particular to a multi-core processor and a control method thereof. BACKGROUND

[0002] Multi-core processor architecture is widely used in current electronic systems; for example, 4G / 5G cellular communication devices, in which each processing unit (i.e., each processor core) is used to control certain hardware acceleration modules in real time, such as channel codec acceleration dedicated hardware modules in 4G / 5G communication devices. The processing units (computer cores) used in these electronic systems usually face high performance requirements. First, high speed frequency is usually required. Second, strong logical derivation is required, thus avoiding performance delay caused by deep pipeline. Finally, and most importantly and most challenging, the interrupt application from the controlled hardware acceleration module must be responded in time.

[0003] The common architecture of traditional multi-core processors is to use the same shared memory, and each processor core sees consistent content in the same memory. This brings the problem that the speed of data operation (reading, writing back) is seriously slowed down because everyone shares each other's courtesy and necessary arbitration mechanism, and often causes traffic jams at intersections. As shown in Figure 1 The arbitration mechanism of the multi-core processor when reading the shared main memory will seriously restrict system performance.

[0004] Another common architecture of traditional multi-core processors is shown in Figure 2 based on data cache multi-core data instant sharing; each processor core uses its own data cache, and each core can read and write back its own data cache at high speed, while the data cache system ensures that the content in each data cache is always synchronized with the shared main memory. However, when an interrupt occurs, if the data cache is mismatched, to ensure that the data content in the data cache is consistent with the main memory, the interrupt response speed will be significantly affected, and the interrupt response time will be prolonged - which is a fatal impact on the real-time performance of the processor. Although the simplest and most straightforward acceleration method is to increase the CPU frequency, which can usually be achieved by increasing the depth of the processor pipeline. However, increasing the depth of the processor pipeline will slow down the response to interrupts (because it needs to clean up a deeper and more complex processor pipeline), and at the same time affect the logical processing ability during normal work (longer data dependency delay caused by deeper pipeline) - all of which are contrary to the demand for improving system performance. SUMMARY

[0005] In view of the problems in the prior art, the application provides a multi-core processor and a control method thereof, which are simple in structure, reasonable in design, do not conflict when accessing memory, do not need to yield and do not need to be arbitrated, and can maintain high speed and high performance.

[0006] The application is realized by the following technical solutions.

[0007] A multi-core processor comprises,

[0008] A processor core A and a processor core B arranged in pairs;

[0009] A shared memory for connecting the processor core A and the processor core B arranged in pairs respectively;

[0010] A clock generation circuit configured to generate a clock signal; the clock signal is input into the processor core A and serves as a working timing of the processor core A to control interaction with the shared memory;

[0011] An inverter connected to an output end of the clock generation circuit and configured to invert the clock signal to generate an inverted clock signal; the inverted clock signal is input into the processor core B and serves as a working timing of the processor core B to control interaction with the shared memory.

[0012] Preferably, the processor core A works at a rising edge of the clock signal, and the processor core B works at a rising edge of the inverted clock signal.

[0013] Preferably, the application further comprises a plurality of groups of the processor core A and the processor core B arranged in pairs, and each group of the processor core A and the processor core B arranged in pairs is connected to one shared memory.

[0014] Further, one processor core A or one processor core B is shared by the plurality of groups of the processor core A and the processor core B arranged in pairs.

[0015] Preferably, the processor core A is connected to the corresponding shared memory through a processor core A bus, and the processor core B arranged in pairs with the processor core A is connected to the same shared memory through a processor core B bus.

[0016] Preferably, the processor core A and the processor core B work to perform at least one of read / write control, address decoding and read / write data on the same shared memory.

[0017] A control method of a multi-core processor comprises,

[0018] Generating a clock signal for controlling the multi-core processor;

[0019] Providing the generated clock signal as input to a processor core A of the multi-core processor to control the processor core A to access a shared memory;

[0020] The clock signal is inverted to obtain an inverted clock signal as input provided to the processor core B of the multi-core processor, and the processor core B is controlled to access the same shared memory;

[0021] The processor core A and the processor core B are arranged in pairs and access the same shared memory.

[0022] Preferably, the processor core A is controlled to access the shared memory through the rising edge of the clock signal, and the processor core B is controlled to access the shared memory through the rising edge of the inverted clock signal.

[0023] Preferably, the clock signal controls a plurality of processor cores A, and the inverted clock signal controls a plurality of processor cores B.

[0024] Preferably, the clock signal is provided as input to a plurality of processor cores A of the multi-core processor, and the plurality of processor cores A are controlled to access a plurality of shared memories, respectively.

[0025] The inverted clock signal is provided as input to a plurality of processor cores B of the multi-core processor, and the plurality of processor cores B are controlled to access a plurality of shared memories, respectively.

[0026] The same shared memory is accessed only by a group of processor cores A and processor cores B arranged in pairs.

[0027] Compared with the prior art, the present application has the following beneficial technical effects:

[0028] The multi-core processor of the present application is arranged in pairs by two processor cores using the shared memory together, and the shared memory can update, synchronize and read and write data in real time through the complementarity of the clock signal and the inverted clock signal. Meanwhile, the two multi-core processors arranged in pairs can keep high-speed operation without waiting for each other, and access the shared memory alternately, like independent operation, and can fully communicate data with each other. The performance of the cellular communication system is significantly improved, and the present application is very suitable for systems sensitive to interruption response requirements.

[0029] Further, the overall performance of the multi-core processor system is greatly improved by a plurality of groups of processor cores arranged in pairs in the multi-core processor. The two processor cores arranged in pairs are arranged corresponding to the corresponding shared memory, and a two-dimensional multi-core processor architecture can be formed for large-scale complex computing systems. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 It is an architecture of the multi-core processor in the prior art.

[0031] Figure 2 It is another architecture of the multi-core processor in the prior art.

[0032] Figure 3 This refers to the architecture of the multi-core processor described in the embodiments of the present invention.

[0033] Figure 4 This is a timing control diagram of paired processor cores in the multi-core processor described in the embodiment of the present invention.

[0034] Figure 5 This refers to the architecture of multiple paired processor cores in the multi-core processor described in the embodiments of the present invention.

[0035] Figure 6 This is a flowchart of the multi-core processor control method described in an example of the present invention. Detailed Implementation

[0036] The present invention will be further described in detail below with reference to specific embodiments. These descriptions are for explanation purposes only and are not intended to limit the scope of the invention.

[0037] This invention provides a multi-core processor, comprising:

[0038] A pair of processor cores A and B;

[0039] Shared memory is used to connect paired processor cores A and B respectively;

[0040] A clock generation circuit is configured to generate a clock signal; the clock signal is input to processor core A and serves as the operating timing of processor core A, controlling its interaction with shared memory;

[0041] An inverter, connected to the output of a clock generation circuit, is configured to invert the clock signal to generate an inverted clock signal; the inverted clock signal is input to processor core B and serves as the operating timing of processor core B, controlling its interaction with shared memory.

[0042] Specifically, such as Figure 3 As shown, the processor cores are configured in a paired architecture. In this preferred embodiment, processor core 1 and processor core 2 are described as processor core A and processor core B, respectively. Two identical processor cores are used, but they use opposite clocks and exchange data through a shared memory. Generally, processor core 1 and processor core 2 are completely identical and belong to the same type of processor. In some embodiments, processor core 1 and processor core 2 can be configured to be different from each other, but both access the same shared memory.

[0043] The same shared memory is connected to both processor cores 1 and 2 via separate processor core 1 bus and processor core 2 bus, respectively, to allow independent access to the data stored therein. Typically, this is accomplished by way of a wire running between each processor core and its respective bus. The shared memory can be a random access memory (RAM) mounted on a circuit board. As shown in Figure 3 Access to the shared memory can be governed by a clock signal CLK generated by a clock generation circuit. The clock generation circuit can also be referred to as a clock module. For example, the clock generation circuit can be an electronic oscillator mounted on a circuit board.

[0044] Because the two processor cores are each operating at different clock phases, they do not conflict when accessing the shared memory, do not need to yield, and do not need to be arbitrated, all while maintaining high speed and high performance with respect to each other. As shown in Figure 4 The clock signal CLK is input to processor core 1, and the inverse (inverted) clock signal CLK INV is input to processor core 2.

[0045] The processor cores paired in the manner described herein are able to independently access the shared memory in a seemingly exclusive manner. Because the processor cores alternate in accessing the shared memory, the processor cores can not access each other even though they can access each other via the shared memory. From the perspective of each processor core, the shared memory belongs only to that processor core, thereby making this method of accessing the shared memory ensure that there is no conflict between the processor cores and, thus, no need for arbitration.

[0046] In the preferred embodiment, both processor cores, processor core 1 and processor core 2, operate on the rising edge of the corresponding clock, thereby synchronizing the access of both paired processor cores 1 and 2 via the clock signal. The inverse of the clock signal is controlled by an inverter when the clock signal enters processor core 2.

[0047] Specifically, as shown in Figure 4 The clock signal CLK provided as input to processor core 1 includes a series of "on" and "off" periods. Likewise, the inverse clock signal CLK INV provided as input to processor core 2 includes a series of "on" and "off" periods. As shown in Figure 4 The beginning of each "on" period can correspond to the rising edge of the signal, and the end of each "on" period can correspond to the falling edge of the signal. Thus, processor core 1 operates on the rising edge of the clock signal, and processor core 2 operates on the rising edge of the inverse clock signal. For convenience, the period in which processor core 1 operates can be referred to as the "odd period," and the period in which processor core 2 operates can be referred to as the "even period."

[0048] Processor core A and processor core B work on at least one of read / write control, address decoding, and read / write data of the same shared memory. Specifically, the activities of the multi-core processor can be classified into two categories, i.e., write operation and read operation. As will be discussed further below, the write operation can be considered as a single-cycle operation, while the read operation can be considered as a double-cycle operation.

[0049] In each odd cycle, processor core 1 can send a control signal to the shared memory, which indicates to the shared memory the type of access requested by processor core 1. In other words, the control signal can indicate whether processor core 1 is requesting read or write permission from the shared memory. If processor core 1 is interested in reading data from the shared memory, the control signal can be accompanied by an address corresponding to the data to be read. As shown in FIG. 2, the shared memory can provide the requested data to processor core 1 in the next even cycle. If processor core 1 is interested in writing data to the shared memory, the control signal can be accompanied by an address specifying where the data is to be written and the data itself. The write operation can be performed by processor core 1 in one cycle, as no "response" from the shared memory is needed. Figure 4

[0050] In each even cycle, processor core 2 can send a control signal to the shared memory, which indicates to the shared memory the type of access required by processor core 2. In other words, the control signal can indicate whether processor core 2 is requesting read or write permission from the shared memory. If processor core 2 is interested in reading data from the shared memory, the control signal can be accompanied by an address corresponding to the data to be read. As shown in FIG. 3, the shared memory can provide the requested data to processor core 2 in the next odd cycle. If processor core 2 is interested in writing data to the shared memory, the control signal can be accompanied by an address specifying where the data is to be written and the data itself. The write operation can be performed by processor core 2 in one cycle, as no "response" from the shared memory is needed. Figure 4

[0051] Thus, by the paired processor core architecture proposed by the present invention, the performance of a cellular communication system is significantly improved, such that the multi-core system can ensure each processor core to run at high speed (without yielding and waiting), as if each processor core is running independently, and at the same time, the processor cores can fully communicate with each other. Such a multi-core system is suitable for use in a system sensitive to interruption response requirement.

[0052] ​​Paired-core architectures can significantly improve the performance of computing devices equipped with microcontrollers containing one or more multi-core processors. For example, a dual-core architecture can help improve the efficiency of models communicating over broadband cellular networks. A multi-core processor with a paired-core architecture can potentially maintain high performance for each core while still allowing efficient communication between the cores. In short, a multi-core processor with a paired-core architecture can support data sharing between multiple cores without compromising performance.

[0053] The architecture described in this invention can also be extended to multi-core systems with more than two processor cores. For example, expanding from a pair of processor cores with out-of-clocked operation to multiple processor cores with out-of-clocked operation, multiple sets of paired processor cores A and B are configured, with each set of paired processor cores A and B connected to a shared memory module. Specifically, the way they share memory is as follows... Figure 5 As shown.

[0054] Taking processor cores 1, 2, 3, and 4 as examples, as described above, processor cores 1 and 3, controlled by clock signals, belong to type A, while processor cores 2 and 4, controlled by inverted clock signals, belong to type B. These two types of processor cores can be paired. In this preferred embodiment, four processor cores form three pairs: processor core 1 and processor core 2, processor core 2 and processor core 3, and processor core 3 and processor core 4, respectively accessing shared memory 1, 2, and 3. In the paired configuration, the middle processor cores 2 and 3 are actually shared, achieving a multi-processor core architecture configuration. It can be reasonably inferred that each processor core can actually be paired with several shared memory cores and processor cores with inverted control clock signals, each managed by a single clock signal for type A and by its inversion for type B, allowing each processor core corresponding to a shared memory to access it alternately.

[0055] by Figure 5 Using the one-dimensional CPU array shown as a foundation, this invention proposes a low-cost and practically efficient computer architecture capable of constructing a two-dimensional "CPU ocean." Such a multi-core system can be widely used in large-scale complex computing systems.

[0056] The present invention also provides a control method for a multi-core processor, comprising generating a clock signal for controlling the multi-core processor;

[0057] The generated clock signal is provided as input to processor core A of the multi-core processor to control processor core A to access a shared memory.

[0058] The clock signal is inverted to obtain an inverted clock signal as input provided to the processor core B of the multi-core processor, to control the processor core B to access the same shared memory;

[0059] The processor core A and the processor core B are arranged in pairs, and respectively access the same shared memory.

[0060] The multi-core processor system described above can be executed, or the multi-core processor can be configured independently, and specifically, as shown in Figure 6 .

[0061] The clock generation circuit can generate a clock signal, which is provided as input to the processor core A. This clock signal can control the access of the processor core A to the shared memory. This clock signal can also be provided as input to an inverter. The inverter can invert the clock signal to generate an inverted clock signal having an opposite phase to the clock signal, and the inverted clock signal is provided to the processor core B to control the access of the processor core B to the shared memory. In other words, the clock signal and the inverted clock signal can be complementary to each other, the clock signal can have an "on" period, and the inverted clock signal can have an "off" period, and vice versa. Thus, the opposite phases of the clock signal and the inverted clock signal enable the shared memory to be accessed by the processor core A or the processor core B in each period.

[0062] For the multi-core processor with more than two processor cores, the same control mode can be used to control the pairs of processor cores respectively, to realize the alternate access and read-write control of the shared content.

[0063] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the system, device and unit described above can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0064] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0065] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flow or blocks Figure 1 one or more flow or blocks

[0066] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flow or blocks Figure 1 one or more flow or blocks

[0067] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flow or blocks Figure 1 one or more flow or blocks

[0068] Finally, it should be noted that the above-mentioned embodiments are merely used to illustrate the technical solutions of the present application, rather than limit the technical solutions of the present application. Although the present application is described in detail with reference to the above embodiments, those skilled in the art should understand that the specific embodiments of the present application can be modified or replaced, and any modification or replacement without departing from the spirit and scope of the present application should be covered in the protection scope of the claims of the present application.

Claims

1. A multi-core processor, characterized in that, include, A pair of processor cores A and B; Shared memory is used to connect processor cores A and B, which are configured in pairs, respectively; processor core A is connected to the corresponding shared memory through processor core A bus, and processor core B, which is configured in pairs with it, is connected to the same shared memory through processor core B bus. Used for alternating access to the same shared memory; A clock generation circuit is configured to generate a clock signal; the clock signal is input to processor core A and serves as the operating timing of processor core A, controlling its interaction with shared memory; An inverter, connected to the output of a clock generation circuit, is configured to invert the clock signal to generate an inverted clock signal. The inverted clock signal is input to processor core B and serves as the working timing of processor core B, controlling its interaction with shared memory. Processor core A operates on the rising edge of the clock signal, controlling processor core A to access shared memory; processor core B operates on the rising edge of the inverted clock signal, controlling processor core B to access shared memory; ensuring no conflicts between processor cores and eliminating the need for arbitration; It also includes multiple sets of paired processor cores A and B, with each set of paired processor cores A and B connected to a shared memory. When processor core A and processor core B are working, they perform at least one of the following accesses to the same shared memory: read / write control, address decoding, and read / write data.

2. A multi-core processor according to claim 1, characterized in that, In a multi-pair configuration of processor cores, a single processor core A or processor core B is shared.

3. A control method for a multi-core processor, characterized in that, include, Generate clock signals for controlling multi-core processors; The generated clock signal is provided as input to processor core A of the multi-core processor to control processor core A to access a shared memory. The clock signal is inverted to obtain an inverted clock signal, which is then provided as input to processor core B of the multi-core processor to control processor core B to access the same shared memory. The processor core A and processor core B are configured in pairs and each accesses the same shared memory. The clock signal controls multiple processor cores A, and the inverted clock signal controls multiple processor cores B. The clock signal is provided as input to multiple processor cores A of the multi-core processor, and each processor core A controls access to multiple shared memory. The inverted clock signal is provided as input to multiple processor cores B of the multi-core processor, and each processor core B controls access to multiple shared memory. The same shared memory can only be accessed by a pair of processor cores A and B.

4. The control method for a multi-core processor according to claim 3, characterized in that, The rising edge of the clock signal controls processor core A to access shared memory, while the rising edge of the inverted clock signal controls processor core B to access shared memory.

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