Memory device including data lines at multiple device levels

Abstract

The present application relates to memory devices including data lines on multiple device levels. Some embodiments include apparatus and methods of forming the apparatus. One of the apparatuses includes: a first column of a first memory cell string; a second column of a second memory cell string; a first conductive structure extending in a first direction, the first conductive structure being positioned above and in electrical contact with the first column; a second conductive structure extending in the first direction, the second conductive structure being positioned above and in electrical contact with the second column; a select gate coupled to the first and second memory cell strings; a first data line positioned on a first level of the apparatus and extending in a second direction, the first data line being positioned above and in electrical contact with the first conductive structure; and a second data line positioned on a second level of the apparatus and extending in the second direction, the second data line being positioned above and in electrical contact with the second conductive structure.

Description

Technical Field

[0001] The present application relates generally to memory devices. Background Art

[0002] Memory devices are widely used in computers and many electronic items. Memory devices typically have many memory cells for storing information and data lines (e.g., bit lines) for carrying information (in the form of signals) to and from the memory cells. The data lines are typically formed one by one in a single level (e.g., layer) of the memory device. As the demand for memory cell density increases for a given device size, the number of data lines may also increase to accommodate the increased memory cell capacity. In some applications, a smaller device size may be desired, resulting in a reduced distance between adjacent data lines. An increase in the number of data lines in a given area or a reduction in the distance between adjacent data lines may result in an increase in the bad coupling capacitance between adjacent data lines. An increase in the bad coupling capacitance may degrade device performance. Summary of the invention

[0003] In one aspect, the present application provides a device comprising: a first pillar of a first memory cell string; a second pillar of a second memory cell string; a first conductive structure extending in a first direction, the first conductive structure being positioned above the first pillar and being electrically contacted therewith; a second conductive structure extending in the first direction, the second conductive structure being positioned above the second pillar and being electrically contacted therewith; a selection gate coupled to the first and second memory cell strings; a first data line positioned on a first level of the device and extending in a second direction, the first data line being positioned above the first conductive structure and being electrically contacted therewith; and a second data line positioned on a second level of the device and extending in the second direction, the second data line being positioned above the second conductive structure and being electrically contacted therewith.

[0004] In another aspect, the present application provides an apparatus comprising: a first data line positioned on a first level of a memory device; a second data line positioned on a second level of the memory device; a first memory cell string, each of which is coupled to a corresponding data line in the first data line and the second data line; a second memory cell string, each of which is coupled to a corresponding data line in the first data line and the second data line; a first selection gate coupled to the first memory cell string; a second selection gate coupled to the second memory cell string and electrically separated from the first selection gate; and an access line shared by the first memory cell string and the second memory cell string.

[0005] In another aspect, the present application provides a method comprising: forming a conductive structure over a first column of a first memory cell string of a memory device and electrically contacting it with corresponding columns in the first column, the first memory cell string including memory cells positioned on different levels of the memory device; forming a second conductive structure over a second column of a second memory cell string of the memory device after forming the first conductive structure, so that the second conductive structure is electrically contacting with corresponding columns in the second column, the second memory cell string including memory cells positioned on the different levels of the memory device; forming a first data line on the first level of the memory device and electrically contacting it with corresponding conductive structures in the first conductive structure; and forming a second data line on the second level of the memory device and electrically contacting it with corresponding conductive structures in the second conductive structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A block diagram of an apparatus in the form of a memory device including a data line is shown according to some embodiments described herein.

[0007] Figure 2 A schematic diagram of a portion of a memory device including a memory array (eg, an area of ​​memory cells) and data lines is shown according to some embodiments described herein.

[0008] Figure 3 According to some embodiments described herein, Figure 2 A top view of the structure of a memory device.

[0009] Figure 4 According to some embodiments described herein, a method including data lines positioned on (e.g., formed on) multiple levels of a memory device is shown. Figure 3 An isometric view (eg, perspective view) of a portion of a memory device.

[0010] Figure 5 According to some embodiments described herein, the method along line 5-5 is shown. Figure 3 A side view (eg, a cross-sectional view) of the structure of a memory device.

[0011] Figure 6 According to some embodiments described herein, the method along line 6-6 is shown. Figure 3 A side view (eg, a cross-sectional view) of the structure of a memory device.

[0012] Fig. 7A A structure including a memory cell string having a pillar is shown according to some embodiments described herein. Figure 3A side view (eg, a cross section relative to an XZ direction) of a portion of the structure of a memory device.

[0013] Figure 7B Show along Fig. 7A A top view (e.g., a cross-section relative to the XY plane) of a portion of the column along line 7B-7B.

[0014] Figure 7C Show along Fig. 7A A top view (e.g., a cross-section relative to the XY plane) of a portion of the column along line 7C-7C.

[0015] Figure 8 According to some embodiments described herein, Figures 2 to 7C 0014] A side view (eg, a cross-sectional view) of the structure of a portion of a memory device of a variation of the memory device shown in FIG.

[0016] Fig.9A According to some embodiments described herein, a structure including two memory cell strings and a pillar is shown. Figure 8 A side view (eg, a cross section relative to the XZ direction) of another portion of the structure of the memory device.

[0017] Fig. 9B Show along Fig.9A A top view (e.g., a cross-section relative to the XY plane) of a portion of the column along line 9B-9B.

[0018] Fig. 9C Show along Fig.9A A top view (e.g., a cross-section relative to the XY plane) of a portion of the column along line 9C-9C.

[0019] Fig.10 According to some embodiments described herein, a Figures 2 to 7C An isometric view (eg, a perspective view) of a portion of the structure of a memory device showing variations of the data lines of the memory device in FIG.

[0020] Fig.11 According to some embodiments described herein, Fig.10 A side view (eg, a cross-sectional view) of the structure of a memory device.

[0021] Fig.12 According to some embodiments described herein, Fig.11 A side view (eg, a cross-sectional view) of a structure of a memory device in a variation of a memory device.

[0022] Fig.13A top view of the structure of a memory device including multiple rows of pillars of memory cell strings and data lines is shown according to some embodiments described herein.

[0023] Fig.14 According to some embodiments described herein, Fig.13 A side view (e.g., a cross-sectional view) of the structure of the memory of line 13-13.

[0024] Fig.15 Flowchart showing a process of forming data lines in different levels (multiple physical levels) of a memory device according to some embodiments described herein. DETAILED DESCRIPTION

[0025] The technology described herein includes a memory device having data lines formed in multiple levels of the memory device. The structure and formation of the data lines described herein can maintain the coupling capacitance between adjacent data lines at an acceptable value for an increase in the number of data lines or for a decrease in the distance between adjacent data lines. This can maintain or improve the performance of the memory device described herein. Figures 1 to 15 Other improvements and benefits of the described techniques are discussed in detail.

[0026] Figure 1 A block diagram of an apparatus in the form of a memory device 100 including data lines 170 is shown according to some embodiments described herein. The memory device 100 may include a memory array (or multiple memory arrays) 101 containing memory cells 110. In the physical structure of the memory device 100, the memory cells 110 may be arranged vertically above a substrate (e.g., a semiconductor substrate) of the memory device 100 (e.g., stacked on top of each other). The memory cells 110 may include floating gate memory cells, charge trap memory cells, or other types of memory cells. The memory cells 110 may include nonvolatile memory cells.

[0027] Memory device 100 may include access lines 150, which include word lines of memory device 100. Access lines 150 may carry signals (eg, word line signals) WL0 to WLm. Memory device 100 may selectively access memory cells 110 using access lines 150.

[0028] Data lines 170 may include local data lines (eg, local bit lines) of memory device 100 . Data lines 170 may carry signals (eg, bit line signals) BL0 to BLn. Memory device 100 may use data lines 170 to exchange information (eg, data) with memory cells 110 .

[0029] The memory device 100 may include an address register 107 to receive address information (e.g., address signals) ADDR on lines (e.g., address lines) 103. The memory device 100 may include row access circuitry 108 and column access circuitry 109 (e.g., part of a decoder circuitry of the memory device 100) that may decode the address information from the address register 107. Based on the decoded address information, the memory device 100 may determine which memory cells 110 will be accessed during a memory operation. The memory device 100 may perform a read operation to read (e.g., sense) information (e.g., previously stored information) in the memory cells 110, or perform a write (e.g., program) operation to store (e.g., program) information in the memory cells 110. The memory device 100 may use data lines 170 associated with signals BL0 to BLn to provide information to be stored in the memory cells 110, or to obtain information to be read (e.g., sensed) from the memory cells 110. Memory device 100 may also perform an erase operation to erase some or all of the information from memory cells 110 .

[0030] The memory device 100 may include a control unit 118, which may be configured (e.g., may include components) to control memory operations of the memory device 100 based on control signals on line 104. Examples of control signals on line 104 include one or more clock signals and other signals (e.g., chip enable signal CE#, write enable signal WE#) to indicate which memory operation (e.g., read, write, or erase operation) the memory device 100 may perform. The control unit 118 may include components, such as firmware, hardware, or software, or any combination of firmware, hardware, and software, to control memory operations of the memory device 100. An external device may provide a command on line 104 to cause the memory device 100 to perform a memory operation (e.g., read, write, or erase operation). The external device includes a processor, a memory controller, other types of external devices.

[0031] Memory device 100 may include buffer circuitry 120, which may include sense amplifiers and page buffer circuits (e.g., data latches), among other circuit components. Buffer circuitry 120 may be responsive to signals BL_SEL0 to BL_SELn from column access circuitry 109. Buffer circuitry 120 may be configured to determine (e.g., by sensing) the value of information read from memory cell 110 (e.g., during a read operation) and provide the value of the information to line (e.g., global data line) 175. Buffer circuitry 120 may also be configured to use the signal on line 175 to determine the value of information to be stored (e.g., programmed) in memory cell 110 (e.g., during a write operation) based on the value (e.g., voltage value) of the signal on line 175 (e.g., during a write operation).

[0032] Memory device 100 may include input / output (I / O) circuitry 117 to exchange information between memory cells 110 and lines (e.g., I / O lines) 105. Signals DQ0 through DQN on lines 105 may represent information read from or stored in memory cells 110. Lines 105 may include conductive nodes within memory device 100 or pins (or solder balls) on a package containing memory device 100. Other devices external to memory device 100, such as a memory controller or processor, may communicate with memory device 100 through lines 103, 104, and 105.

[0033] The memory device 100 may receive supply voltages, including supply voltages Vcc and Vss. The supply voltage Vss may operate at ground potential (e.g., having a value of approximately zero volts). The supply voltage Vcc may include an external voltage supplied to the memory device 100 from an external power source (e.g., a battery or alternating current to direct current (AC-DC) converter circuitry).

[0034] Each of the memory cells 110 may be programmed to store information representing a value of up to a single bit, or information representing a value of multiple bits (e.g., two, three, four, or another number of bits). For example, each of the memory cells 110 may be programmed to store information representing a binary value of "0" or "1" for a single bit. Memory cells that store a single bit per cell are sometimes referred to as single-level cells. In another example, each of the memory cells 110 may be programmed to store information representing a value of multiple bits, such as one of four possible values ​​"00", "01", "10", and "11" for two bits, one of eight possible values ​​"000", "001", "010", "011", "100", "101", "110", and "111" for three bits, or one of other values ​​of another number of multiple bits. Memory cells that can store multiple bits are sometimes referred to as multi-level cells (or multi-state cells).

[0035] The memory device 100 may include a nonvolatile memory device such that the memory cell 110 may retain information stored thereon when power (e.g., voltages Vcc, Vss, or both) is disconnected from the memory device 100. For example, the memory device 100 may be a flash memory device such as a NAND flash memory (e.g., a 3-way (3-D) NAND) or a NOR flash memory device, or another memory device such as a variable resistance memory device (e.g., a phase change memory device or a resistive RAM (random access memory) device). Those skilled in the art may recognize that the memory device 100 may include other components, several of which are not described in detail. Figure 1 , so as not to obscure the example embodiments described herein.

[0036] At least a portion of the memory device 100 may include the following reference Figures 2 to 15 The structure of any memory device described may be similar to (or identical to) the structure of any memory device described.

[0037] Figure 2 A schematic diagram of a portion of a memory device including a memory array (eg, a memory cell region) 201 and data lines 271, 272, 273, 274, 275, and 276 (271-276) is shown according to some embodiments described herein. The memory device 200 may correspond to Figure 2 For example, the memory array 201 may correspond to Figure 1 The data lines 271 to 276 may correspond to the memory array 101. Figure 1 In another example, the memory device 200 may include a data line 170 that may correspond to Figure 1The control unit of the memory device 200 may be configured to allow the memory device 200 to perform read, write, and erase operations, as well as other operations of the memory device 200.

[0038] Figure 2 The X, Y, and Z directions are shown, which may be relative to physical directions (e.g., dimensions) of the structure of memory device 200. For example, the Z direction may be a direction perpendicular to (e.g., relative to a perpendicular direction of) a substrate (e.g., a semiconductor substrate) of memory device 200. The Z direction is perpendicular to the X and Y directions (e.g., the Z direction is perpendicular to an XY plane of memory device 200).

[0039] As in Figure 2 2 , data lines 271, 272, 273, 274, 275, and 276 may carry signals (e.g., bit line signals) BL1, BL2, BL3, BL4, BL5, and BL6, respectively. In the physical structure of the memory device 200, the data lines 271 to 276 may be structured as conductive lines and have respective lengths extending along the Y direction. As described in more detail below, the data lines (e.g., data lines 271 to 276) of the memory device 200 may be formed on different levels (e.g., layers) in the physical structure of the memory device 200. For example, the data lines 271, 273, and 275 may be formed on one level (e.g., a lower level) of the memory device 200, and the data lines 272, 274, and 276 may be formed on another level (e.g., an upper level) of the memory device 200. Figure 2 An example is shown where the memory device 200 includes six data lines, such as data lines 271-276. However, the memory device 200 may include many data lines, such as more than six data lines.

[0040] As in Figure 2 As shown in FIG. 1 , a memory array (e.g., a memory cell region) 201 may include memory cells 210, 211, 212, and 213, which may be included in (e.g., may be formed in) corresponding memory cell strings 231, 232, 233, 234, 235, and 236 (231 to 236), and memory cell strings 231′, 232′, 233′, 234′, 235′, and 236′ (231′ to 236′) of the memory device 200. Memory cell strings 231-236 and 231'-236' may be coupled to data lines 271-276 through conductive connections 241, 242, 243, 244, 245, and 246 (241-246) and 241', 242', 243', 244', 245', and 246' (241'-246'), respectively. As an example, Figure 2Twelve memory cell strings are shown for memory device 200. However, memory device 200 may include many memory cell strings (e.g., more than twelve memory cell strings). As an example, Figure 2 Specific connections are shown between memory cell strings 231-236 and 231'-236' and data lines 271-276. However, memory cell strings 231-236 and 231'-236' may be coupled to data lines 271-276 with different connections. For example, instead of coupling to both lower and upper data lines, memory cell strings 231-236 may be coupled to one set of data lines similar to data lines 271, 273, and 275 (e.g., data lines at a lower physical level of memory device 200), and memory cell strings 231'-236' may be coupled to another set of data lines similar to data lines 272, 274, and 276 (e.g., data lines at an upper physical level of memory device 200).

[0041] As in Figure 2 , each memory cell string (e.g., memory cell string 231) of the memory device 200 may have serially connected memory cells (e.g., four serially connected memory cells), wherein the serially connected memory cells may include one of the memory cells 210, one of the memory cells 211, one of the memory cells 212, and one of the memory cells 213. In the physical structure of the memory device 200, each of the memory cell strings 231 to 236 and 231′ to 236′ may be formed (e.g., vertically formed) in a direction outward (e.g., Z direction) from a substrate of the memory device 200. In the physical structure of the memory device 200, the memory cells 210, 211, 212, and 213 may be formed (e.g., vertically formed) in different levels (e.g., four different layers) along the Z direction of the memory device 200 and below the structure of the data lines (e.g., data lines 271 to 276) of the memory device 200. Figure 2 An example of four memory cells in each memory cell string is shown (eg, memory cells 210, 211, 212, and 213 in memory cell string 231). However, the number of memory cells in each memory cell string of memory device 200 may vary.

[0042] like Figure 2, memory device 200 may include control gates 250, 251, 252, and 253, which may carry corresponding signals (e.g., word line signals) WL0, WL1, WL2, and WL3. Control gates 250, 251, 252, and 253 may include (or may be a portion of) access lines (which may include word lines) of memory device 200. Each of control gates 250, 251, 252, and 253 may be part of a structure (e.g., a level) of conductive material (e.g., a layer of conductive material) located in a single level of memory device 200. Memory device 200 may use signals WL0, WL1, WL2, and WL3 to control access to memory cells 210, 211, 212, and 213, respectively, during a memory operation (e.g., a read, write, or erase operation). For example, during a read operation, the memory device 200 may use signals WL0, WL1, WL2, and WL3 to control access to the memory cells 210, 211, 212, and 213 to read (e.g., sense) information (e.g., previously stored information) from the memory cells 210, 211, 212, and 213. In another example, during a write operation, the memory device 200 may use signals WL0, WL1, WL2, and WL3 to control access to the memory cells 210, 211, 212, and 213 to store information in the memory cells 210, 211, 212, and 213.

[0043] As in Figure 2 , memory cells in different memory cell strings can share the same control gate (e.g., share the same physical control gate). For example, memory cell 210 can share control gate 250, memory cell 211 can share control gate 251, memory cell 212 can share control gate 252, and memory cell 213 can share control gate 253.

[0044] As an example, Figure 2 Four control gates (eg, control gates 250, 251, 252, and 253) of memory device 200 are shown. The number of control gates of memory device 200 can vary (eg, can be more than four).

[0045] As in Figure 2 , memory device 200 may include a line (e.g., source line or source plate) 298 that may carry a signal (e.g., source line signal) SRC. Line 298 may be structured as a conductive line or conductive plate of memory device 200. Line 298 may be a common conductive line (e.g., a common source line or a common source plate). Line 298 may be coupled to a ground connection of memory device 200.

[0046] Memory device 200 may include select gates (e.g., drain select gates) 281 and 282. Select gates 281 and 282 may carry signals (e.g., drain select gate signals) SGD1 and SGD2, respectively. Select gates 281 and 282 are electrically separated from each other. Select gate 281 may be coupled to memory cell strings 231 to 236. Select gate 282 may be coupled to memory cell strings 231' to 236'.

[0047] Memory device 200 may include transistors (e.g., drain select transistors) 261 and 262. Each of memory cell strings 231-236 may include one of transistors 261. Each of memory cell strings 231'-236' may include one of transistors 262. Transistors 261 may share (e.g., may be coupled to) the same select gate 281. Transistors 262 may share (e.g., may be coupled to) the same select gate 282.

[0048] Transistors 261 and 262 may be controlled (e.g., turned on or off) by signals SGD1 and SGD2, respectively. During a memory operation (e.g., a read or write operation), transistors 261 and transistor 262 may be turned on one at a time (e.g., by activating signals SGD1 and SGD2 one at a time). For example, transistor 261 may be turned on (e.g., by activating signal SGD1) during a memory operation (e.g., a read or write operation) of memory device 200 to couple memory cell strings 231 to 236 to data lines 271 to 276, respectively. Transistor 261 may be turned off (e.g., by deactivating signal SGD1) to decouple memory cell strings 231 to 236 from data lines 271 to 276. In another example, the transistor 262 can be turned on (e.g., by activating the signal SGD2) during a memory operation (e.g., a read or write operation) of the memory device 200 to couple the memory cell strings 231′ to −236′ to the data lines 271 to 276, respectively. The transistor 262 can be turned off (e.g., by deactivating the signal SGD2) to decouple the memory cell strings 231′ to 236′ from the data lines 271 to 276.

[0049] Memory device 200 can include a select gate (eg, source select gate) 280. Select gate 280 can carry a signal (eg, source select gate signal) SGS. Select gate 280 can be coupled to memory cell strings 231-236 and 231'-236'.

[0050] The memory device 200 may include a transistor (e.g., a source select transistor) 260. Each of the memory cell strings 231 to 236 and 231' to 236' may include one of the transistors 262. The transistors 260 may share (e.g., may be coupled to) the same select gate 280. The transistors 260 may be controlled (e.g., turned on or off) by the same signal (e.g., an SGS signal). During a memory operation (e.g., a read or write operation) of the memory device 200, the transistor 260 may be turned on (e.g., by activating the SGS signal) to couple the memory cell strings 231 to 236 and 231' to 236' to the line 298. The transistor 260 may be turned off (e.g., by deactivating the SGS signal) to decouple the memory cell strings 231 to 236 and 231' to 236' from the line 298.

[0051] Memory device 200 includes other components not shown in Figure 2 , so as not to obscure the example embodiments described herein. Figures 3 to 7C Some of the structures of the memory device 200 are described.

[0052] Figure 3 A schematic diagram including the locations of memory cell strings 231-236 and 231'-236' and data lines 271-276 is shown according to some embodiments described herein. Figure 2 For simplicity, some elements of the structure of the memory device 200 may be omitted from a particular figure in the drawings so as not to obscure the description of the element (or elements) described in the particular figure. For example, Figures 3 to 14 Dielectric materials (e.g., silicon dioxide) between elements of memory device 200 are omitted. Additionally, cross-sectional lines (e.g., hatching) are omitted from some of the elements shown in the described figures. The dimensions (e.g., physical structures) of the elements shown in the figures described herein are not to scale.

[0053] Figure 3 Example locations of memory cell strings 231 to 236 and 231 ' to 236' are shown (from a top view). However, the locations of memory cell strings 231 to 236 and 231 ' to 236' may be different from Figure 3 The following references Figure 5 , Figure 6 and Fig. 7A Show and describe along Figure 3 5 - 5 , line 6 - 6 , and line 7A- 7A in different views (eg, side views) of memory device 200 .

[0054] As in Figure 3, the memory device 200 may include conductive contacts 331, 332, 333, 334, 335, and 336 (331-336) and 331', 332', 333', 334', 335', ​​and 336' (331'-336') coupled to pillars (described below) of respective memory cell strings 231-236 and 231'-236'. The memory device 200 may include conductive structures (in the form of conductive contacts) formed below respective data lines 271-276 and above respective conductive contacts 331-336 and 331'-336'. Figure 4 (shown in the).

[0055] As in Figure 3 , data lines 271-276 may have respective lengths extending in the Y direction and may be positioned (eg, formed) above the memory array 201. Each of the data lines 271-276 may be positioned on a respective conductive structure (in Figure 4 , Figure 5 and Figure 6 ) and above corresponding conductive contacts among the conductive contacts 331 to 336 and 331 ' to 336'. For example, the data line 271 can be positioned above (e.g., directly above) the conductive contacts 331 and 331'. In another example, the data line 272 can be positioned above (e.g., directly above) the conductive contacts 332 and 332'.

[0056] Figure 3 The outlines of select gates (e.g., drain select gates) 281 and 282 are also shown. As described above, select gates 281 and 282 are electrically separated from each other. Each of select gates 281 and 282 can have a length along the X direction. Select gate 281 can be shared by memory cell strings 231 to 236. For example, select gate 281 spans a portion of memory cell strings 231 to 236. Select gate 281 can be shared by memory cell strings 231' to 236'. For example, select gate 282 spans a portion of memory cell strings 231' to 236'.

[0057] Figure 4 A memory device 200 including data lines positioned on (eg, formed on) multiple levels 461 and 462 is shown according to some embodiments described herein. Figure 3 An isometric view (eg, a perspective view) of a portion of a memory device 200. Figure 4 , memory device 200 may include different levels (eg, physical layers) 459, 460, 461, and 462 along the Z direction. A substrate (not shown) of memory device 200 is positioned below level 459. Figure 4, data lines 271 , 273 , and 275 may be located at (eg, formed at) level 461 (eg, located on the same level). Data lines 272 , 274 , and 276 may be located at (eg, formed at) level 462 .

[0058] The data lines 271 to 276 may be positioned side by side along the X direction such that adjacent data lines (two data lines are positioned immediately adjacent to each other) among the data lines 271 to 276 may be separated from each other by a distance (e.g., a gap) along the X direction. Thus, the data lines on the same level (e.g., level 461 or level 462) may be separated from each other by a distance (e.g., a gap) along the X direction. For example, the data lines 271, 273, and 275 may be positioned side by side along the X direction such that the data lines 271, 273, and 275 may be separated from each other by a distance (e.g., a gap) along the X direction. In another example, the data lines 272, 274, and 276 may be positioned side by side along the X direction such that the data lines 272, 274, and 276 may be separated from each other by a distance (e.g., a gap) along the X direction. The distance along the X direction between two adjacent data lines on one level (e.g., level 461) (e.g., data lines 271 and 273) and the distance along the X direction between two adjacent data lines on another level (e.g., level 462) (e.g., data lines 272 and 274) may be the same (e.g., equal distances), or may be different (e.g., unequal distances).

[0059] For simplicity, Figure 4 Display Figure 3 Only some of the conductive contacts (e.g., conductive contacts 331-336) among the conductive contacts 331-336 and 331'-336' in the memory device 200. The conductive contacts 331-336 may be located at (e.g., formed at) corresponding locations of the memory device 200 and on the same level (e.g., level 460). As an example, Figure 4 The conductive contacts 331 to 336 are shown in a specific shape (eg, cylindrical). However, the conductive contacts 331 to 336 and 331 ' to 336 ' ( Figure 3 and Figure 4 ) may have different shapes (eg, a square frame shape, a rectangular frame shape, or other shapes).

[0060] Figure 4 Display Figure 3 Only some of the memory cell strings (eg, memory cell strings 231 to 236) among the memory cell strings 231 to 236 and 231' to 236' of the memory array 201. The memory cell strings 231 to 236 may be located at (eg, formed on) corresponding locations of the memory array 201. For simplicity, Figure 4Details of memory cell strings 231-236 are omitted. Memory cell strings 231-236 may include pillars (dashed lines and unlabeled) having pillar contacts (dashed lines and unlabeled) positioned on level 459. The pillar contacts are positioned below respective conductive contacts 331-336 and may be coupled to (electrically contact) respective conductive contacts 331-336.

[0061] As in Figure 4 , the memory device 200 may include conductive structures (e.g., vertical conductive structures) 431, 432, 433, 434, 435, and 436 (431-436) that are coupled to data lines 271-276 and conductive contacts 331-336, respectively. For simplicity, Figure 4 Other conductive structures (eg, data lines 271 to 276 and Figure 3 The conductive structure between the corresponding conductive contacts 331' to 336' in FIG.

[0062] exist Figure 4 , each of the conductive structures 431 to 436 may include a length extending along the Z direction. The length of each of the conductive structures 431, 433, and 435 may be less than the length of each of the conductive structures 432, 434, and 436. Each of the conductive structures 431 to 436 may include (e.g., may be formed of) a conductive material extending along the Z direction. Examples of conductive materials include metals, conductively doped polysilicon, or other conductive materials. Although Figure 4 4. Although not shown in FIG. 4, memory device 200 may include a dielectric material (e.g., silicon dioxide) formed between levels 459 and 462. The dielectric material may be formed before conductive structures 431-436. Then, openings (e.g., holes (e.g., vertical vias) may be formed in the dielectric material. The material of each of conductive structures 431-436 may be formed (e.g., deposited) inside a respective one of the openings.

[0063] As in Figure 4 As shown in , each of the conductive structures 431-436 can be coupled to (e.g., electrically contacted with) a corresponding conductive contact among the conductive contacts 331-336, and coupled to (e.g., electrically coupled with) a corresponding data line among the data lines 271-276. For example, the conductive structure 431 can include an end (e.g., a bottom end) coupled to (e.g., directly contacting) the conductive contact 331, and another end (e.g., a top end) coupled to (e.g., directly contacting) the data line 271. In another example, the conductive structure 432 can include an end (e.g., a bottom end) coupled to (e.g., directly contacting) the conductive contact 332, and another end (e.g., a top end) coupled to (e.g., directly contacting) the data line 272. Figure 4The corresponding data lines 271-276 of the memory device 200 and other conductive contacts (eg, Figure 3 Other conductive structures between the conductive contacts 331' to 336) shown in FIG.

[0064] exist Figure 4 In the embodiment, the conductive structure 431 and the conductive contact 331 may be a conductive connection 241 ( Figure 2 ). Similarly, the conductive structure 432 and the conductive contact 332 may be part of the conductive connection 242 ( Figure 2 ). The conductive structure 433 and the conductive contact 333 may be part of the conductive connection 243 ( Figure 2 ). The conductive structure 434 and the conductive contact 334 may be part of the conductive connection 244 ( Figure 2 ). The conductive structure 435 and the conductive contact 335 may be part of the conductive connection 245 ( Figure 2 ). The conductive structure 436 and the conductive contact 336 may be part of the conductive connection 246 ( Figure 2 ).

[0065] Figure 5 According to some embodiments described herein, Figure 3 Line 5-5 Figure 2 2 is a side view (eg, a cross-sectional view) of the structure of the memory device 200. Figure 6 According to some embodiments described herein, Figure 3 Line 6-6 Figure 2 A side view (eg, a cross-sectional view) of the structure of the memory device 200 is shown. Figure 5 and Figure 6 , data lines 271, 273, and 275 may be positioned on (eg, formed on) level 461 of memory device 200. Data lines 272, 274, and 276 may be positioned on (eg, formed on) another level of memory device 200 (eg, level 462).

[0066] As in Figure 5 and Figure 6 , memory cell strings 231-236 may include pillars (e.g., vertical pillars) 541, 542, 543, 544, 545, and 546 (541-546), respectively. Pillars 541-546 may include pillar contacts 541C-546C, respectively, positioned on the same level (e.g., level 459) of memory device 200. Pillars 541-546 may be positioned (e.g., directly) below respective conductive contacts 331-336, and below (e.g., directly below) respective conductive structures 431-436.

[0067] Conductive structures 431-436 may be coupled to (eg, electrically contact) pillars 541-546 via conductive contacts 331-336 of pillars 541-546, respectively. Figure 5 and Figure 6 , data lines 271-276 can be coupled to (eg, electrically coupled to) pillars 541-546, respectively, through respective conductive structures 431-436 and respective conductive contacts 331-336.

[0068] As in Figures 3 to 6 , memory cell strings 231, 233, 235, 231', 233', and 235' may include different rows of columns coupled to data lines 271, 273, and 275. For example, memory cell strings 231, 233, and 235 ( Figure 4 and Figure 5 ) may include a row of pillars 541, 543, and 545 (along the X direction) coupled to data lines 271, 273, and 275. Memory cell strings 232, 234, 236, 232', 234', and 236' may include different rows of pillars coupled to recessed data lines 272, 274, and 276. For example, memory cell strings 232, 234, and 236 ( Figure 4 and Figure 5 ) may include a row of pillars 542, 544, and 546 coupled to data lines 272, 274, and 276 (along the X direction, adjacent to a row of pillars 541, 543, and 545).

[0069] As in Figure 5 and Figure 6 As shown in , the distance (e.g., vertical distance) between data lines 271, 273 and 275 and corresponding pillar contacts 541C, 543C and 545C may be smaller than the distance (e.g., vertical distance) between lines 272, 274 and 276 and corresponding pillar contacts 542C, 544C and 546C.

[0070] In an alternative structure of memory device 200, the conductive contacts (e.g., conductive contacts 331-336) of memory device 200 may be omitted. Thus, in an alternative structure of memory device 200, conductive structures 431-436 may be directly coupled to (e.g., in direct electrical contact with) pillars 541-546, respectively.

[0071] Fig. 7A A structure including a memory cell string 231 having a pillar 541 is shown according to some embodiments described herein. Figure 2 and Figure 3 2 is a side view (eg, a cross section relative to an XZ direction) of a portion of the structure of the memory device 200 . Fig. 7AThe structure of one memory cell string (e.g., memory cell string 231) of the memory device 200 is shown. However, other memory cell strings (e.g., Figure 2 The memory cell strings 232 to 236 and 231' to 236') may have Fig. 7A The structure is similar or identical to the memory cell string 231 shown in FIG.

[0072] exist Fig. 7A In the embodiment, data lines 271 and 272, conductive structures 431 and 432, conductive contacts 331 and 332, and pillars 541 and 542 are connected to Figure 4 , Figure 5 and Figure 6 are the same as those shown in Fig. 7A As shown in , each of the data lines 271 and 272 may have a thickness along the Z direction and a width along the X direction. Each of the thickness (along the Z direction) and the width (along the X direction) is smaller than the length (along the Y direction). The thickness may be smaller than, equal to, or greater than the width.

[0073] As in Fig. 7A , data lines 271 and 272 are positioned in levels 461 and 462, respectively. Levels 461 and 462 are located in a portion of the memory device 200 above the memory array 201 relative to the Z direction. The memory array 201 is positioned above the substrate 790 of the memory device 200. As described above with reference to Figure 2 As depicted, memory array 201 is the location where strings of memory cells (one of which is shown as memory cell string 231) of memory device 200 can be formed.

[0074] As in Fig. 7A , a pillar (e.g., a vertical pillar) 541 may be part of a memory cell string 231 and may have a length extending in the Z direction (e.g., extending vertically relative to the substrate 790). The pillar 541 may extend through the memory cells 210, 211, 212, and 213 of the memory cell string 231. The pillar 541 may include (e.g., may be formed of) a conductive material (e.g., conductively doped polysilicon). Each of the memory cells 210, 211, 212, and 213 may include the structure of a transistor (e.g., a memory cell transistor). A portion of the pillar 541 may form a channel region (e.g., conduct current) of the transistor of each memory cell 210, 211, 212, and 213.

[0075] Pillar contact 541C may be formed of conductively doped polysilicon, metal, or other conductive materials. Pillar 541 may include portion 744. Pillar contact 541C and portion 744 of pillar 541 may include the same conductive material or different conductive materials.

[0076] Conductive structure 431, conductive contact 331, and pillar 541 may be part of a circuit path (eg, a conductive channel of memory cell string 231) between data line 271 and conductive region 798 (associated with signal SRC). Conductive region 798 may be Figure 2 A portion of a line (eg, source line or source plate) 298 in the conductive structure 431 and the pillar 541 may have the same material or different materials. The conductive structure 431 and the pillar 541 may have the same diameter or different diameters. Fig. 7A In the present invention, during a memory operation (e.g., a read or write operation) of the memory device 200, a circuit path (e.g., a current path) can be formed between the data line 271 and the conductive region 798 through the conductive structure 431, the conductive contact 331 and the pillar 541 (which includes the pillar contact 541C and a portion 744 of the pillar 541).

[0077] The substrate 790 of the memory device 200 may include a semiconductor substrate (eg, a silicon-based substrate). For example, the substrate 790 may include a p-type silicon substrate or an n-type silicon substrate. Fig. 7A , memory cells 210, 211, 212, and 213 of memory cell 231 may be positioned in different levels (along the Z direction) of memory device 200 along respective portions of (e.g., adjacent) pillars 541. For example, memory cells 210, 211, 212, and holes 213 may be positioned up and down (e.g., formed vertically) in levels 750, 751, 752, and 753 of memory device 200, respectively. Other memory cell strings (e.g., Figure 2 Memory cells 210, 211, 212, and 213 of memory cell strings 232 to 236 and 231' to 236' in the memory cell string 231 may also be located on corresponding levels 750, 751, 752, and 753, as memory cells 210, 211, 212, and 213 of memory cell string 231 ( Fig. 7A ).

[0078] The control gates 250, 251, 252, and 253 of the memory device 200 may be positioned in the same level (e.g., level 750, 751, 752, and 753, respectively) where the memory cells 210, 211, 212, and 213 are positioned along respective portions (in the Z direction) of (e.g., adjacent) pillars 541. The control gates 250, 251, 252, and 253 may include (e.g., may be formed of) a conductive material (or materials). Example materials for the control gates 250, 251, 252, and 253 include metals, doped polysilicon, and other conductive materials.

[0079] exist Fig. 7AIn the embodiment, the selection gate (e.g., drain selection gate) 281 may have a length extending along the X direction (e.g., perpendicular to the length of the data lines 271 and 272 (along the Y direction). The material of the selection gate 281 may include a conductive material (e.g., conductively doped polysilicon, metal, other conductive materials).

[0080] Fig. 7A An example is shown in which select gate (e.g., source select gate) 280 may have a structure (e.g., shape, material, or both) similar to (or the same as) that of select gate 281. However, select gate 280 may have a structure (e.g., shape, material, or both) similar to (or the same as) that of each of control gates 250, 251, 252, and 253.

[0081] As in Fig. 7A , transistor (e.g., source select transistor) 260 and transistor (e.g., drain select transistor) 261 may be positioned along respective portions of (e.g., adjacent) pillars 541 along the Z direction. Memory cells 210, 211, 212, and 213 of memory cell string 231 may be positioned along portions of pillar 541 between transistors 260 and 261.

[0082] Memory cell string 231 may include materials 703, 704, 705 formed between portion 744 of pillar 541 and a corresponding control gate among control gates 250, 251, 252, and 253. Material 703 may also be formed between pillar 541 and each of select gates 280 and 281. Materials 703, 704, and 705 located at a particular memory cell (among memory cells 210, 211, 212, and 213) may be a portion (e.g., a memory element) of that particular memory cell. As shown in Fig. 7A , the combination of materials 703, 704, and 705 of a memory cell (among memory cells 210, 211, 212, and 213) can be separated (along the Z direction) from the combination of materials 703, 704, and 705 of another memory cell (among memory cells 210, 211, 212, and 213).

[0083] Material 703 may include a charge blocking material (or multiple charge blocking materials), such as a dielectric material (eg, silicon nitride) capable of blocking the tunneling of charges.

[0084] Material 704 may include a charge storage material (or multiple charge storage materials) that can provide a charge storage function to represent the value of the information stored in memory cells 210, 211, 212, and 213. For example, material 704 may include polysilicon (e.g., conductively doped polysilicon), which may be p-type polysilicon or n-type polysilicon. The polysilicon may be configured to operate as a floating gate (e.g., to store charge) in a memory cell (e.g., memory cell 210, 211, 212, or 213). In another example, material 704 may include a dielectric material (e.g., a silicon nitride-based material or other dielectric material) that can capture charge in a memory cell (e.g., memory cell 210, 211, 212, or 213).

[0085] Material 705 may include a tunnel dielectric material (or tunnel dielectric material) capable of allowing tunneling of charges (eg, electrons), such as silicon dioxide.

[0086] As in Fig. 7A , memory device 200 may include circuitry 795 positioned (e.g., formed) below memory array 201 (e.g., positioned directly below memory cell string 231). Circuitry 795 may include circuit elements (e.g., transistors T) coupled to other circuit elements of memory device 200 (e.g., coupled to data lines 271 to 276). Circuit elements (e.g., transistors T) of circuitry 795 may be configured to perform a portion of the function of a memory device (e.g., memory device 200). For example, circuitry 795 may include decoder circuits, driver circuits, buffers (e.g., page buffers), sense amplifiers, charge pumps, and other circuitry of memory device 200. In an alternative structure of memory device 200, circuitry 795 may be positioned (e.g., formed) above memory array 201 (rather than below memory array 201). For example, in an alternative structure of memory device 200, circuitry 795 can be positioned above memory array 201 and below data lines 271 and 272 (e.g., circuitry 795 is positioned between data lines 271 and 272 of memory array 201 along the Z direction). In another example, in an alternative structure of memory device 200, circuitry 795 can be positioned above memory array 201 and above data lines 271 and 272 (e.g., data lines 271 and 272 are positioned between circuitry 795 and memory array 201 along the Z direction).

[0087] Figure 7B and Figure 7C Different views of column 541 are shown along 7B-7B and 7C-7C, respectively. Figure 7B Show along Fig. 7AA top view (eg, a cross section relative to the XY plane) of portion 744 of column 541 taken along line 7B-7B. Figure 7C Show along Fig. 7A A top view (eg, a cross section relative to the XY plane) of the column contact 740 of the column 541 along line 7C-7C.

[0088] As in Figure 7B , portion 744 may include material 744A and material 744B surrounded by material 744A. Material 744A may be (or may include) a portion of a conductive structure (e.g., a conductive channel) of pillar 541. Material 744B may include a dielectric material. In an alternative structure of pillar 541, material 744B may be omitted from pillar 541 so that the entire portion 744 of pillar 541 may include material 744A (without material 744B).

[0089] As in Figure 7C , the shape of the post contact 740 (e.g., from a top view) can be relatively circular. Figure 7C , the shape of portion 744 (eg, in a top view) may be relatively circular. Other memory cell strings (in Figure 2 Other pillar contacts (shown in ) may have shapes similar to that of pillar contact 740.

[0090] Figure 8 According to some embodiments described herein, Figures 2 to 7C 800 is a side view (e.g., a cross-sectional view) of the structure of a portion of a memory device 800 that is a variation of the memory device 200 shown in . Memory device 800 may include elements that are similar to (or identical to) the elements of memory device 200. Therefore, for simplicity, similar and identical elements between memory devices 200 and 800 are given the same labels, and their descriptions are not repeated.

[0091] Memory device 800 ( Figure 8 ) and a memory device 200 (e.g., Figure 5 and Figure 6 ) include the difference between Figure 8 The memory device 800 in omits the conductive contacts 331 to 336. Figure 8 As shown in , conductive structures 431-436 can be directly coupled to pillar contacts 541C-546C of pillars 541-546, respectively.

[0092] Fig.9A A structure including a memory cell string 231 and a pillar 541 is shown according to some embodiments described herein. Figure 8800 is a side view of another portion of the structure of the memory device 800 (eg, a cross section with respect to the XZ direction). Figure 8 ) and a memory device 200 (eg, Fig. 7A ) include omitting conductive contacts (e.g., conductive contacts 331 and 332) from memory device 800. Fig.9A , the conductive structure 431 can be directly coupled to the pillar contact 541C. Similarly, the conductive structure 432 and other conductive structures (not shown) of the memory device 800 can be directly coupled to the respective pillar contacts of the respective pillars of the memory device 800.

[0093] Fig.10 According to some embodiments described herein, a Figures 2 to 7C 1000 is an isometric view (e.g., a perspective view) of a portion of the structure of memory device 1000 that includes data lines 271-276 of a variation of data lines 271-276 of memory device 200 shown in FIG. Memory device 1000 may include elements that are similar to (or identical to) elements of memory device 200. Therefore, for simplicity, similar and identical elements between memory devices 200 and 1000 are given the same labels, and their descriptions are not repeated. Differences between memory devices 200 and 1000 include Fig.10 The shapes of the data lines 271 to 276 of the memory device 1000 are shown in FIG. Fig.10 As shown in , each of the data lines 271 to 276 may include a thickness (along the Z direction) and a width (along the X direction) greater than the thickness.

[0094] Fig.11 According to some embodiments described herein, Fig.10 1 is a side view (eg, a cross-sectional view) of the structure of the memory device 1000. Fig.11 An example is shown where data lines 271, 273, and 275 overlap (in the X direction) data lines 272, 274, and 276. However, in alternative structures of memory device 1000, data lines 271, 273, and 275 may not overlap (eg, the X direction) data lines 272, 274, and 276.

[0095] Fig.12 According to some embodiments described herein, Fig.11 1000 is a side view (eg, a cross-sectional view) of a structure of a memory device 1200 of a variation of the memory device 1000. Fig.10 ) and the memory device 1200 include the following differences: Fig.12 The memory device 1200 in omits the conductive contacts 331 to 336. Fig.12, the conductive structures 431 - 436 can be directly coupled to pillar contacts 541 - 546C of pillars 541 - 546 of the memory device 1200 , respectively.

[0096] Fig.13 A top view of the structure of a memory device 1300 including multiple rows of pillars of memory cell strings 231-236 and 231'-236' and data lines 271-276 and 1371'-1376' is shown according to some embodiments described herein. Fig.14 According to some embodiments described herein, Fig.13 Line 14-14 Fig.13 1300 is a side view (eg, a cross-sectional view) of a structure of a memory device 1300. Fig.13 and Fig.14 ) can be Figures 2 to 7C Therefore, for simplicity, similar and identical elements between memory devices 200 and 1300 are given the same labels and their descriptions are not repeated. The differences between memory devices 200 and 1300 include Fig.13 The formation (eg, arrangement) of the data lines 1371 to 1376 and 1371 ′ to 1376 ′, and the formation (eg, arrangement) of the memory cell strings 231 to 236 and 231 ′ to 236 ′.

[0097] As in Fig.13 , a select gate (eg, source select gate) 281 associated with signal SGD1 may be coupled to memory cell strings 231 to 236. A select gate (eg, source select gate) 282 associated with signal SGD2 may be coupled to memory cell strings 231' to 236'.

[0098] As in Fig.13 and Fig.14 , data lines 1371-1376 may be positioned on level 461 of memory device 1300. Data lines 1371-1376 may carry BL1, BL2, BL3, BL4, BL5, and BL6 signals (e.g., bit line signals), respectively. Data lines 1371′-1376′ may be positioned on level 462 of memory device 1300 (which is above level 461). Data lines 1371′-1376′ may carry signals (e.g., bit line signals) BL1′, BL2′, BL3′, BL4′, BL5′, and BL6′, respectively.

[0099] The data lines 1371 to 1376 may include a group of data lines 1371, 1373, and 1375, and a group of data lines 1372, 1374, and 1376 interlaced with the group of data lines 1371, 1373, and 1375. The memory cell strings 231 to 236 may include a row of pillars 1351, 1353, and 1355 and a row of pillar lines 1352, 1354, and 1356 (immediately adjacent to (e.g., adjacent to) the row of pillars 1351, 1353, and 1355). The row of pillars 1351, 1353, and 1355 may be coupled to the data lines 1371, 1373, and 1375, respectively. The row of pillars 1352, 1354, and 1356 may be coupled to the data lines 1372, 1374, and 1376, respectively.

[0100] The data lines 1371' to 1376' may include a group of data lines 1371', 1373', and 1375', and a group of data lines 1372', 1374', and 1376' interlaced with the group of data lines 1371', 1373', and 1375'. The memory cell strings 231' to 236' may include a row of pillars 1351', 1353', and 1355' and a row of pillar lines 1352', 1354', and 1356' (immediately adjacent to (e.g., adjacent to) the row of pillars 1351', 1353', and 1355'). The row of pillars 1351', 1353', and 1355' may be coupled to the data lines 1371', 1373', and 1375', respectively. The row pillars 1352', 1354', and 1356' may be coupled to data lines 1372', 1374', and 1376', respectively.

[0101] Memory device 1300 may include conductive structures 1341-1346 and 1341'-1346', and conductive contacts 1331-1336 and 1331'-1336'. Conductive structures 1341-1346 may be coupled to data lines 1371-1376, respectively, and to conductive contacts 1331-1336, respectively. Conductive structures 1341'-1346' may be coupled to data lines 1371'-1376', respectively, and to conductive contacts 1331'-1336', respectively.

[0102] The conductive contacts 1331-1336 may be respectively coupled to the pillar contacts 1351C-1356C of the pillars 1351-1356. The conductive contacts 1331'-1336' may be respectively coupled to the pillar contacts 1351C'-1356C' of the pillars 1351'-1356'.

[0103] In an alternative structure of memory device 1300, conductive contacts 1331-1336 and 1331'-1336' may be omitted. Thus, in an alternative structure of memory device 1300, conductive structures 1341-1346 may be directly coupled to pillar contacts 1351C-1356C, respectively. In an alternative structure of memory device 1300, conductive structures 1341'-1346' may be directly coupled to pillar contacts 1351C'-1356C', respectively.

[0104] Fig.15 1 is a flow chart showing a method 1500 for forming data lines in different levels (multiple physical levels) of a memory device according to some embodiments described herein. The method 1500 may be used to form at least a portion of the memory devices described herein. For example, the method 1500 may be used to form the data lines of the memory devices 100, 200, 800, 1000, 1200, and 1300. As described in Fig.15 As shown in , method 1500 may include activities 1510 , 1520 , 1530 , and 1540 .

[0105] Activity 1510 can include forming a conductive structure over and electrically contacting a first pillar of a first memory cell string of a memory device, the first memory cell string including memory cells positioned on a different level of the memory device.

[0106] Forming the first conductive structure may include depositing a first conductive material in the first hole. Prior to forming the conductive material (which forms the conductive structure), the first hole may be formed over a respective one of the first pillars.

[0107] The conductive structures in activity 1510 may include conductive structures 431, 433, and 435 ( Figure 4 and Figure 5 ). The first pillar and first memory cell string in activity 1510 may include pillars 541, 543, and 545 of memory cell strings 231, 233, and 235, respectively ( Figure 5 ). Alternatively, the conductive structures in activity 1510 may include conductive structures 1341 to 1346 ( Fig.13 ). Alternatively, the first pillar and the first memory cell string in activity 1510 may include pillars 1351-1356 of memory cell strings 231-236, respectively ( Fig.14 ).

[0108] Fig.15 Activity 1520 in can include, after forming the first conductive structure, forming a second conductive structure over a second pillar of a second memory cell string of the memory device. The second conductive structure can make electrical contact with a corresponding pillar of the second pillars.

[0109] Forming the second conductive structure may include depositing the second conductive material in the second hole.The second hole may be formed over a corresponding one of the second pillars after the first material is deposited in the first hole.

[0110] The conductive structures in activity 1520 may include conductive structures 432, 434, and 436 ( Figure 4 and Figure 5 The second pillar and second memory cell string in activity 1520 may include pillars 542, 544, and 546 of memory cell strings 232, 234, and 236, respectively ( Figure 5 ). Alternatively, the conductive structures in activity 1520 may include conductive structures 1341' to 1346' ( Fig.14 ). Alternatively, the second pillar and the second memory cell string in activity 1520 may include pillars 1351' to 1356' of memory cell strings 231' to 236', respectively ( Fig.14 ).

[0111] Fig.15 Activity 1530 in can include forming a first data line on a first level of the memory device and making electrical contact with a corresponding conductive structure in the first conductive structure (in activity 1510). The first data line can be formed before forming the second conductive structure (in activity 1520).

[0112] The first data line in activity 1530 may include data lines 271, 273, and 275 ( Figures 3 to 6 ). Alternatively, the first data line in activity 1530 may include data lines 1371 to 1376 ( Fig.13 and Fig.14 ).

[0113] Fig.15 Activity 1540 in can include forming a second data line on a second level of the memory device and making electrical contact with a corresponding conductive structure in the second conductive structures (formed in activity 1520). The second data line can be formed after forming the second data line (in activity 1520).

[0114] The second data lines in activity 1540 may include data lines 272, 274, and 276 ( Figures 3 to 6 ). Alternatively, the first data line in activity 1530 may include data lines 1371' to 1376' ( Fig.13 and Fig.14 ).

[0115] Method 1500 may include additional activities ( Fig.151500 may include forming first conductive contacts (in activity 1510) over the first pillars and before forming the first conductive structures. The first conductive contacts may be formed such that respective ones of the first conductive contacts may be positioned between and contact respective ones of the first conductive structures and respective ones of the first pillars.

[0116] In another example, method 1500 may include forming second conductive contacts on the second pillars and before forming the second conductive structures. The second conductive contacts may be formed such that respective ones of the second conductive contacts may be positioned between and contact respective ones of the second conductive structures and respective ones of the second pillars.

[0117] Method 1500 may include additional activities that are omitted from method 1500 so as not to obscure Fig.15 For example, method 1500 may include forming a memory cell string (including forming pillars and pillar contacts) before forming conductive contacts, conductive structures, and data lines.

[0118] In the above reference Figures 1 to 15 Providing data lines (e.g., data lines 271-276, 271'-276', 1371-1376, and 1371'-1376') in the described memory device can allow the memory device to have the improvements and benefits mentioned above. For example, the structure and formation of the data lines described herein can keep the coupling capacitance between adjacent data lines at an acceptable value for an increase in the number of data lines or for a decrease in the distance between adjacent data lines. This can maintain or improve the performance of the memory device described herein.

[0119] The description of apparatus (e.g., memory devices 100, 200, 800, 1000, 1200, and 1300) and methods (e.g., method (e.g., process) 1500 of forming at least a portion of a memory device) is intended to provide a general understanding of the structure of various embodiments, but is not intended to provide a complete description of all elements and features that may utilize the structure described herein. For example, an apparatus herein refers to a device (e.g., any of memory devices 100, 200, 800, 1000, 1200, and 1300) or a system (e.g., a computer, cellular phone, or other electronic system) that includes the device of any of memory devices 100, 200, 800, 1000, 1200, and 1300.

[0120] References Figures 1 to 15Any of the components described may be implemented in a variety of ways, including simulation via software. Thus, the apparatus described above (e.g., memory devices 100 and 200 or a portion of each of these memory devices, including a control unit in these memory devices, such as control unit 118 ( Figure 1 )) may all be characterized herein as "modules" (or "modules"). Such modules may include hardware circuit systems, single-processor and / or multi-processor circuits, memory circuits, software program modules and objects, and / or firmware, as necessary or appropriate for the specific implementation of the various embodiments, and combinations thereof. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and range simulation package, a capacitance and inductance simulation package, a power / heat dissipation simulation package, a signal transmission reception simulation package, and / or a combination of software and hardware for operating or simulating the operation of various potential embodiments.

[0121] Memory devices 100, 200, 800, 1000, 1200, and 1300 may be included in devices (e.g., electronic circuit systems) such as high-speed computers, communication and signal processing circuit systems, single or multi-processor modules, single or multiple embedded processors, multi-core processors, message information switches, and application-specific modules including multi-layer, multi-chip modules. Such devices may further be included as subcomponents in various other devices (e.g., electronic systems), such as televisions, cellular phones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Moving Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitors, blood pressure monitors, etc.), set-top boxes, and others.

[0122] References Figures 1 to 15The described embodiments include devices and methods of forming the devices. One of the devices includes: a first column of a first memory cell string; a second column of a second memory cell string; a first conductive structure extending in a first direction, the first conductive structure positioned above and in electrical contact with the first column; a second conductive structure extending in the first direction, the second conductive structure positioned above and in electrical contact with the second column; a select gate coupled to the first and second memory cell strings; a first data line positioned on a first level of the device and extending in a second direction, the first data line positioned above and in electrical contact with the first conductive structure; and a second data line positioned on a second level of the device and extending in the second direction, the second data line positioned above and in electrical contact with the second conductive structure. Other embodiments are described, including additional devices and methods.

[0123] In the detailed description and claims, the term "on..." used with respect to two or more elements (e.g., materials) one "on" another means at least some contact between the elements (e.g., between the materials). The term "over..." means that the elements (e.g., materials) are in close proximity, but may be with one or more additional intermediate elements (e.g., materials) such that contact is possible but not required. Unless otherwise specified, as used herein, "on..." or "over..." do not imply any directionality.

[0124] In the detailed description and claims, a list of items connected by the term "at least one of" may mean any combination of the listed items. For example, if items A and B are listed, the phrase "at least one of A and B" means only A; only B; or A and B. In another example, if items A, B, and C are listed, the phrase "at least one of A, B, and C" means only A; only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all of A, B, and C. Item A may include a single element or multiple elements. Item B may include a single element or multiple elements. Item C may include a single element or multiple elements.

[0125] In the detailed description and claims, a list of items connected by the term "one of" may mean only one of the listed items. For example, if items A and B are listed, the phrase "one of A and B" means only A (excluding B); only B (excluding A). In another example, if items A, B, and C are listed, the phrase "one of A, B, and C" means only A; only B; or only C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements. In the detailed description and claims, a list of items connected by the term "at least one of" may mean any combination of the listed items. For example, if items A and B are listed, the phrase "at least one of A and B" means only A; only B; or A and B. In another example, if items A, B, and C are listed, the phrase “at least one of A, B, and C” may mean only A; only B; only C; A and B (without C); A and C (without B); B and C (without A); or A, B, and C. Each of items A, B, and C may include a single element (e.g., a circuit element) or multiple elements (e.g., multiple circuit elements).

[0126] The above description and drawings illustrate some embodiments of the present invention, enabling those skilled in the art to practice the embodiments of the present invention. Other embodiments may incorporate structural, logical, electrical, process and other changes. Examples represent possible variations only. Portions and features of some embodiments may be included in or replace those of other embodiments. After reading and understanding the above description, many other embodiments will be apparent to those skilled in the art.

Claims

1. A memory device, comprising: a first column of a first memory cell string; a second column of a second memory cell string; a first conductive structure extending along a first direction, the first conductive structure being positioned above and in electrical contact with the first pillar; a second conductive structure extending along the first direction, the second conductive structure being positioned above and in electrical contact with the second pillar; a select gate coupled to the first and second memory cell strings; a first data line positioned on a first level of the memory device and extending in a second direction, the first data line being positioned above and in electrical contact with the first conductive structure; a second data line positioned on a second level of the memory device and extending in the second direction, the second data line positioned over and in electrical contact with the second conductive structure, wherein the first pillar comprises a first pillar contact, the first pillar contact is located at a first distance from the first data line, and the second pillar comprises a second pillar contact, the second pillar contact is located at a second distance from the second data line, and the first distance is less than the second distance; a first conductive contact positioned between and contacting the first conductive structure and the first pillar contact; and A second conductive contact is positioned between and contacts the second conductive structure and the second post contact.

2. The memory device of claim 1 , wherein the select gate is positioned on a third level of the memory device, the third level of the memory device being between memory cells in the first and second memory cell strings and the first level of the memory device, and wherein the memory cells are positioned on multiple levels of the memory device, and the third level being between the multiple levels and the first level. 3 . The memory device of claim 1 , wherein the first data line comprises a thickness along the first direction, a width along a third direction, and the width is smaller than the thickness. 4 . The memory device of claim 1 , wherein the first data line comprises a thickness along the first direction, a width along a third direction, and the width is greater than the thickness.

5. The memory device of claim 1 , further comprising: a first additional column of a first additional string of memory cells; a second additional column of a second additional string of memory cells; a first additional conductive structure extending along the first direction and electrically contacting the first additional pillar; a second additional conductive structure extending along the first direction and electrically contacting the second additional pillar, wherein: The first data line is positioned over and in electrical contact with the first additional conductive structure; and The second data line is positioned over and in electrical contact with the second additional conductive structure.

6. A memory device comprising: a first data line positioned on a first level of the memory device; a second data line positioned on a second level of the memory device; a first memory cell string, each of the first memory cell strings being coupled to a corresponding data line of the first data line and the second data line; a second memory cell string, each of the second memory cell strings being coupled to a corresponding data line of the first data line and the second data line; a first select gate coupled to the first memory cell string; a second select gate coupled to the second memory cell string and electrically separated from the first select gate; and an access line shared by the first memory cell string and the second memory cell string, in: The first data lines include a first group of data lines, and a second group of data lines interlaced with the first group of data lines; The first memory cell string includes a first row column and a second row column immediately adjacent to the first row column; The first row of columns is coupled to the first set of data lines; and The second row of columns is coupled to the second set of data lines.

7. The memory device of claim 6, further comprising a third select gate coupled to the first and second memory cell strings.

8. The memory device of claim 6, further comprising: a first conductive structure extending in a direction between the first data line and the first memory cell string; and A second conductive structure extends in a direction between the second data line and the second memory cell string, wherein each of the first conductive structures has a length smaller than a length of each of the second conductive structures.

9. The memory device according to claim 8 further includes conductive contacts, wherein the first memory cell string and the second memory cell include pillars, the pillars include pillar contacts, and each of the conductive contacts is positioned between and contacts a corresponding pillar contact among the pillar contacts and a corresponding conductive structure among the first conductive structures.

10. The memory device of claim 6, wherein: The second data lines include a third group of data lines and a fourth group of data lines interlaced with the third group of data lines; The second memory cell string includes a third row column immediately adjacent to the second row column and a fourth row column immediately adjacent to the third row column; The third row of columns is coupled to the third set of data lines; and The fourth row of columns is coupled to the fourth set of data lines.

11. A method for forming a memory device, comprising: forming a conductive structure over and in electrical contact with a respective one of first pillars of a first memory cell string of a memory device, the first memory cell string comprising memory cells positioned on a different level of the memory device, wherein the first memory cell string comprises a first row of pillars and a second row of pillars immediately adjacent to the first row of pillars; forming a second conductive structure over a second pillar of a second memory cell string of the memory device after forming the first conductive structure, such that the second conductive structure is in electrical contact with a corresponding one of the second pillars, the second memory cell string including memory cells positioned on the different level of the memory device; forming first data lines on a first level of the memory device and in electrical contact with the corresponding ones of the first conductive structures, and wherein forming the first data lines comprises: forming a first set of data lines and a second set of data lines interleaved with the first set of data lines such that the first row of pillars is coupled to the first set of data lines and the second row of pillars is coupled to the second set of data lines; and Second data lines are formed on a second level of the memory device and are in electrical contact with corresponding ones of the second conductive structures. 12 . The method of claim 11 , wherein the first data line is formed before forming the second conductive structure. 13 . The method of claim 11 , wherein the second data line is formed before forming the second conductive structure.

14. The method according to claim 11, further comprising: forming first conductive contacts over the first pillars and before forming the first conductive structures, such that respective ones of the first conductive contacts are positioned between and contact respective ones of the first conductive structures and respective ones of the first pillars; and A second conductive contact is formed above the second column of the second memory cell string and before forming the second conductive structure, so that a corresponding conductive contact in the second conductive contacts is positioned between and contacts a corresponding conductive structure in the second conductive structure and a corresponding column in the second column.

15. The method of claim 11, wherein: Forming the first conductive structure includes depositing a first conductive material in a first hole; and Forming the second conductive structure includes depositing a second conductive material in a second hole after depositing the first conductive material in the first hole.

16. The method of claim 11, wherein the second memory cell string includes a third row column and a fourth row column immediately adjacent to the third row column, and forming the second data line includes: A third set of data lines and a fourth set of data lines interleaved with the third set of data lines are formed such that the third row of columns are coupled to the third set of data lines and the fourth row of columns are coupled to the fourth set of data lines.

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