Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a package substrate, a logic chip stacked on the package substrate and including at least one logic element, and a stack structure. The stack structure includes an integrated voltage regulator (IVR) chip including a voltage regulation circuit regulating a voltage of the at least one logic element, and a passive element chip stacked on the IVR chip and including an inductor.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0171034, filed on December 19, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the present invention relate to semiconductor packages and methods of manufacturing the semiconductor package, and more specifically, to semiconductor packages including logic chips and integrated voltage regulator (IVR) chips and methods of manufacturing the semiconductor package. Background Technology

[0004] Voltage regulators are widely used to regulate voltage in electronic devices such as computers, servers, and smartphones. In such devices, and similar devices, requirements such as regulated voltage levels and current consumption may vary. Typically, specific voltage regulators are designed for small systems based on the system's input current requirements. Because manufacturing such voltage regulators in semiconductor chips is difficult and / or expensive, they are usually manufactured separately and used on a system board. Inductors are used for the operation of voltage regulators. Because inductors are large in size, the arrangement of the voltage regulator and inductors is a factor in improving the operating characteristics of the voltage regulator. Summary of the Invention

[0005] An exemplary embodiment of the present invention provides a semiconductor package comprising an integrated voltage regulator (IVR) chip with a voltage regulator (VR) and a logic chip with logic elements, which improves the operating characteristics of the IVR chip and minimizes or reduces the package size.

[0006] According to an exemplary embodiment, a semiconductor package includes: a package substrate; a logic chip stacked on the package substrate and including at least one logic element; and a stacked structure. The stacked structure includes: an integrated voltage regulator (IVR) chip, the IVR including a voltage regulation circuit for regulating the voltage of the at least one logic element; and a passive component chip stacked on the IVR chip and including an inductor.

[0007] According to an exemplary embodiment, a semiconductor package includes: a package substrate; a logic chip mounted on the package substrate and including at least one logic element; a first integrated voltage regulator (IVR) chip stacked on the logic chip and including voltage regulation circuitry for regulating the voltage of the at least one logic element; and a first passive component chip stacked on the first IVR chip and including an inductor. The first passive component chip is stacked on the first IVR chip in a front-to-front bonding configuration, wherein the active surfaces of the first passive component chip and the active surfaces of the first IVR chip face each other. The pitch between the pads of the first passive component chip or the first IVR chip is approximately 10 μm or less.

[0008] According to an exemplary embodiment, a method of manufacturing a semiconductor package includes forming a plurality of voltage regulators (VRs) on a first wafer and forming a plurality of passive components on a second wafer. Each of the passive components includes an inductor. The method further includes: forming a plurality of logic elements on a third wafer; forming a stacked wafer by stacking the second wafer on the first wafer in a front-to-front bonding configuration, wherein the active surfaces of the first wafer and the second wafer face each other; forming a first stacked structure by sawing the stacked wafers, the first stacked structure including an integrated voltage regulator (IVR) chip located at the bottom of the first stacked structure and a passive component chip located at the top of the first stacked structure; stacking the first stacked structure on the third wafer; forming a second stacked structure by sawing the third wafer, the second stacked structure including a logic chip located at the bottom of the second stacked structure and the first stacked structure located at the top of the second stacked structure; and stacking the second stacked structure on a package substrate.

[0009] According to an exemplary embodiment, a method of manufacturing a semiconductor package includes: forming a plurality of voltage regulators (VRs) on a first wafer; forming a plurality of passive components on a second wafer, wherein each of the passive components includes an inductor; forming a plurality of logic components on a third wafer; forming a first stacked wafer by stacking the second wafer on the first wafer; forming a second stacked wafer by stacking the first stacked wafer on the third wafer; forming a stacked structure in which logic chips, integrated voltage regulator (IVR) chips and passive component chips are stacked sequentially from bottom to top by sawing the second stacked wafer; and stacking the stacked structure on a package substrate. Attached Figure Description

[0010] The above and other features of the present invention will become more readily understood by referring to the accompanying drawings, which describe exemplary embodiments of the invention in detail.

[0011] Figure 1 This is a cross-sectional view of a semiconductor package according to an exemplary embodiment.

[0012] Figure 2 It shows Figure 1 A cross-sectional view of a stacked structure of integrated voltage regulator (IVR) chips and passive component chips in a semiconductor package.

[0013] Figures 3A to 3C This illustrates an embodiment of the invention. Figure 1 A cross-sectional view of a structure in a semiconductor package where stacked structures are stacked on a logic chip in various bonding methods.

[0014] Figure 4 and Figure 5 This is a cross-sectional view of a semiconductor package according to an exemplary embodiment.

[0015] Figure 6 , Figures 7A to 7C , Figures 8A to 8B , Figure 9 and Figure 10 This schematically illustrates the manufacturing process according to an exemplary embodiment. Figure 1 Top view, perspective view and cross-sectional view of the process of semiconductor packaging.

[0016] Figure 11 and Figure 12 It schematically illustrates the manufacturing process. Figure 4 A top view of the process of a semiconductor packaging method.

[0017] Figure 13A and Figure 13B It schematically illustrates the manufacturing process. Figure 5 A perspective view of the process of a semiconductor packaging method.

[0018] Figure 14 , Figures 15A to 15C and Figure 16 This schematically illustrates the manufacturing process according to an exemplary embodiment. Figure 1 Perspective views, cross-sectional views, and top views of the process for semiconductor packaging. Detailed Implementation

[0019] Exemplary embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings. The same reference numerals may refer to the same elements throughout the drawings, and redundant descriptions may be omitted.

[0020] Figure 1This is a cross-sectional view of a semiconductor package 1000 according to an exemplary embodiment. Figure 2 It shows Figure 1 A cross-sectional view of a stacked structure SS comprising an integrated voltage regulator (IVR) chip 100 and a passive component chip 200 in a semiconductor package 1000. The term "chip" can refer to a semiconductor chip.

[0021] Reference Figure 1 and Figure 2 According to an exemplary embodiment, the semiconductor package 1000 may include a logic chip 300, a stacked structure SS, a package substrate 400, and a sealing material 500.

[0022] like Figure 1 As shown, in an exemplary embodiment, the stacked structure SS can be stacked on the package substrate 400 in a configuration where the stacked structure SS, the logic chip 300, and the package substrate 400 overlap each other in a cross-sectional view. For example, the stacked structure SS can be stacked adjacent to the logic chip 300 on the package substrate 400, wherein the logic chip 300 is disposed between the stacked structure SS and the package substrate 400. For example, in an exemplary embodiment, in a cross-sectional view, the stacked structure SS, the logic chip 300, and the package substrate 400 can be aligned with each other.

[0023] The logic chip 300 can be mounted on the package substrate 400 via the connecting member 330 and the underfill 350. The underfill 350 can fill the area between the logic chip 300 and the package substrate 400. According to an exemplary embodiment, when the sealing material 500 is formed by a process such as molded underfill (MUF), the underfill 350 can be omitted. Furthermore, according to an exemplary embodiment, the underfill 350 can be replaced with an adhesive film.

[0024] The logic chip 300 may include multiple logic elements. A logic element can refer to an element that performs various signal processing operations, including logic circuits such as AND gates, OR gates, NOT gates, and flip-flops. For example, a logic element may be an element that performs signal processing such as analog signal processing, analog-to-digital (A / D) conversion, and control. A logic element may also be referred to herein as a logic circuit element. The logic chip 300 may be referred to as, for example, a control chip, a processing chip, a CPU chip, etc., depending on its function.

[0025] The logic chip 300 may include a body 301, a through electrode 310, and a wiring layer 320. The body 301 may include a semiconductor substrate, an integrated circuit layer, and an interlayer insulating film. The semiconductor substrate may refer to a silicon substrate. The integrated circuit layer may include the logic circuits described above. The wiring layer 320 may include an insulating layer and multilayer wiring located within the insulating layer.

[0026] Because the through electrode 310 has a structure in which the through electrode 310 passes through the silicon portion of the body 301 constituting the logic chip 300, the through electrode 310 can also be referred to as a through silicon via (TSV). For example, in the semiconductor package 1000 of the exemplary embodiment, the through electrode 310 can be formed in a via-middle structure. However, the inventive concept is not limited thereto. For example, in the exemplary embodiment, the through electrode 310 can also be formed in a via-first or via-last structure. A via-first structure refers to a structure in which the through electrode is formed before the integrated circuit layer is formed; a via-middle structure refers to a structure in which the through electrode is formed after the integrated circuit layer is formed but before the wiring layer is formed; and a via-last structure refers to a structure in which the through electrode is formed after the wiring layer is formed. In the semiconductor package 1000 of the exemplary embodiment, the through electrode 310 can be obtained from a via-middle structure and extend through the body 301 to the wiring layer 320.

[0027] The through electrode 310 can be connected to the lower pad 305 on the lower surface and can be connected to the chip pad on the upper surface (see [reference]). Figure 3A (322 in the example). In an exemplary embodiment, the through electrode 310 can be connected to the chip pad via a wiring layer. In an exemplary embodiment, the through electrode 310 can be directly connected to the chip pad.

[0028] A lower protective layer 303 and a lower pad 305 can be disposed on the lower surface of the logic chip 300. The lower pad 305 has a structure connecting to a through electrode 310, can be disposed on the lower surface of the logic chip 300, and can be exposed from the lower protective layer 303. A connecting member 330 can be disposed on the lower pad 305. The through electrode 310 can be connected to the connecting member 330 through the lower pad 305.

[0029] The interconnect 330 may include conductive materials, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), solder, etc. However, the material of the interconnect 330 is not limited to these. The interconnect 330 may be formed as multiple layers or a single layer. For example, when the interconnect 330 is formed as multiple layers, the interconnect 330 may include copper pillars and solder. When the interconnect 330 is formed as a single layer, the interconnect 330 may include tin-silver solder or copper. The interconnect 330 is commonly referred to as a bump, and the process of attaching bumps to a chip in wafer state is called a bumping process.

[0030] The stacked structure SS can be stacked on the logic chip 300 via bonding member B. The structure of the stacked structure SS bonded and stacked on the logic chip 300 via bonding member B can be varied. For example, depending on the shape or material of bonding member B, the bonding and stacking structure between the stacked structure SS and the logic chip 300 can be different. (See reference...) Figures 3A to 3C The stacked structure SS is described in more detail on the logic chip 300 via bonding member B.

[0031] The stacked structure SS may include an IVR chip 100 located at its bottom and a passive component chip 200 located at its top, such as Figure 2 As shown.

[0032] IVR chip 100 may include circuitry for regulating the voltage of logic elements in the logic chip, i.e., a voltage regulator (VR). VR may also be referred to as a voltage regulation circuit. VR may include control circuitry and switching logic circuitry. The control circuitry may include a plurality of transistors for voltage regulation, and the switching logic circuitry may include at least two transistors for selecting current paths. The switching logic circuitry may be connected to passive elements such as inductors and capacitors disposed on passive element chip 200. That is, passive element chip 200 may include passive elements, and the passive elements may be, for example, inductors or capacitors. Passive elements may also be referred to herein as passive circuit elements. For example, the control circuitry, switching logic circuitry, inductors, and capacitors may be configured to function as a buck regulator. The voltage regulation circuitry may regulate the voltage of one or more logic elements of the logic chip 300.

[0033] In the semiconductor package 1000 of the exemplary embodiment, the IVR chip 100 can be implemented as a silicon wafer-based semiconductor chip. Alternatively, the IVR chip 100 can be implemented with a structure that integrates control circuitry and switching logic circuitry within a single semiconductor chip. The IVR chip 100 can be manufactured in a compact structure using silicon wafer-based semiconductor processes.

[0034] For example, the IVR chip 100 may include a body 101, a through electrode 110, and a wiring layer 120. The body 101 may include a semiconductor substrate, an integrated circuit layer, and an interlayer insulating film. The semiconductor substrate may refer to a silicon substrate. Additionally, the integrated circuit layer may include the control circuitry and switching logic circuitry described above. The wiring layer 120 may include an insulating layer and multilayer wiring located within the insulating layer.

[0035] The through electrode 110 can pass through the body 101 and connect to the wiring layer 120. According to an exemplary embodiment, the through electrode 110 can be formed with a structure having the through electrode 110 passing through the wiring layer 120. Because the through electrode 110 passes through the silicon body 101, the through electrode 110 can also be referred to as a TSV. The control circuitry and switching logic circuitry of the IVR chip 100 can be connected to the passive elements of the passive element chip 200 via the through electrode 110 and / or the wiring layer 120, and can also be connected to the logic elements of the logic chip 300 via the through electrode 110.

[0036] like Figure 2 As shown, the lower pad 105 can be disposed on the lower surface of the IVR chip 100, and the chip pad 122 can be disposed on the upper surface of the IVR chip 100. The lower pad 105 can be connected to the through electrode 110 and can be exposed from the protective layer 103 formed on the lower surface of the IVR chip 100. The chip pad 122 can be connected to the through electrode 110 through wiring in the wiring layer 120.

[0037] The passive component chip 200 may include multiple passive components. These passive components may include, for example, inductors and capacitors. The passive component chip 200 may also be implemented as a silicon wafer-based semiconductor chip. For example, the passive component chip 200 may be implemented with a structure that integrates passive components such as inductors and capacitors into a single semiconductor chip.

[0038] The passive component chip 200 may include a body 201 and a wiring layer 220. The passive component may be disposed on the body 201. The wiring layer 220 may include an insulating layer and multilayer wiring located within the insulating layer. Chip pads 222 may be disposed on the lower surface of the wiring layer 220. The passive component can be connected to the chip pads 222 through the wiring of the wiring layer 220.

[0039] In the semiconductor package 1000 of the exemplary embodiment, the stacked structure SS may have a structure in which passive component chips 200 are stacked on IVR chip 100 in a front-to-front bonding configuration. A front-to-front bonding configuration may refer to a configuration in which two chips or two wafers are bonded such that their active surfaces face each other. The front surface refers to an active surface, and an active surface is a surface on which components are formed in a wafer state, and may be a surface on which chip pads are formed.

[0040] In the figure, components stacked in a front-to-back configuration can be indicated by "F2B", and components stacked in a front-to-front configuration can be indicated by "F2F". Additionally, in the figure, ASivr can indicate the active surface of IVR chip 100, NASivr can indicate the passive surface of IVR chip 100, and ASpas can indicate the active surface of passive component chip 200.

[0041] In the stacked structure SS, passive component chips 200 are stacked on IVR chips 100 in a front-to-front bonding configuration. Front-to-front bonding can be achieved using pad-to-pad bonding, where the chip pads 122 of the IVR chip 100 are in one-to-one contact with the corresponding chip pads 222 of the passive component chip 200. That is, the chip pads 122 and 222 of the IVR chip 100 can be formed in a one-to-one correspondence. In this case, chip pads 122 and 222 can be copper pads. The passive component chip 200 can be stacked on the IVR chip 100 in a front-to-front bonding configuration, such that the active surface ASpas of the passive component chip 200 faces the active surface ASivr of the IVR chip 100. Chip pads 122 and 222 can include copper (Cu), therefore, a pad-to-pad bonding where chip pads 122 and 222 are in direct contact with each other can also be referred to as a Cu-to-Cu bonding.

[0042] In the semiconductor package 1000 of the exemplary embodiment, the type of bonding of the stacked structure SS is not limited to pad-to-pad bonding. For example, the stacked structure SS may have a stacked structure that uses an anisotropic conductive film (ACF) instead of pad-to-pad bonding for bonding. That is, front-to-front bonding can be achieved using ACF. ACF refers to an anisotropic conductive film in which fine conductive particles are mixed with an adhesive resin to form a film and conduct electricity only in one direction. One direction may refer to the direction in which the two chip pads to be bonded face each other. For example, nickel (Ni), carbon, solder, etc. can be used as fine conductive particles. Even when the passive component chip 200 is stacked on the IVR chip 100 using bonding with ACF, it can correspond to a front-to-front bonding form because the chip pad 122 of the IVR chip 100 faces the chip pad 222 of the passive component chip 200.

[0043] Front-to-front bonding can be performed at the wafer level. As mentioned above, the technology or corresponding structure for performing front-to-front bonding at the wafer level is called wafer-on-wafer (WoW) technology or WoW structure (hereinafter collectively referred to as "WoW structure"). When chips or wafers are stacked in a WoW structure via front-to-front bonding, the pitch of the chip pads used for bonding can be very small. For example, chip pad 122 of IVR chip 100 or chip pad 222 of passive component chip 200 can have a first pitch P1, and the first pitch P1 can be, for example, about 10 μm or less. However, the first pitch P1 is not limited to the above values.

[0044] The through electrode 110 or lower pad 105 of the IVR chip 100 may have a second pitch P2, and the second pitch P2 may vary depending on the bonding method used to stack the stacked structure SS on the logic chip 300 below it. The bonding method of the stacked structure SS stacked on the logic chip 300 may vary depending on the second pitch P2.

[0045] For example, when the stacked structure SS is stacked on the logic chip 300 using die-to-wafer (D2W) technology or structure (hereinafter referred to as "D2W structure"), the second pitch P2 can be similar to the first pitch P1. For example, the second pitch P2 can be approximately 5 μm to approximately 10 μm. In the D2W structure, the second pitch P2 is not limited to the above values. When the stacked structure SS is stacked on the logic chip 300 using chip-on-wafer (CoW) technology or structure (hereinafter referred to as "CoW structure"), the second pitch P2 can be larger than the first pitch P1. For example, the second pitch P2 can be approximately 50 μm or smaller. In an exemplary embodiment, the second pitch P2 can be approximately 30 μm. In the CoW structure, the second pitch P2 is not limited to the above values. D2W structure can refer to a structure where chips are stacked on a wafer but are stacked via bonding between chip pads (e.g., pad-to-pad bonding or bonding using ACF), and CoW structure can refer to a structure where chips are stacked on a wafer but are stacked via bonding using interconnecting members such as bumps or solder balls. When bonding is performed using interconnecting members, sufficient distance can be ensured between adjacent pads to prevent short circuits due to reflow during the bonding process.

[0046] The package substrate 400 is a support substrate on which logic chips 300 and stacked structures SS are mounted, and may include at least one wiring layer. When wiring is formed as multiple layers, different wiring layers can be connected to each other by vertical contact. According to an exemplary embodiment, the package substrate 400 may include through electrodes that directly connect pads on the upper and lower surfaces. However, since the package substrate 400 is not typically formed from a silicon wafer, the through electrodes may not correspond to TSVs. A protective layer, such as solder resist, may be formed on the upper and lower surfaces of the package substrate 400. Pads may connect to wiring in the wiring layers and be exposed from the protective layer. The package substrate 400 may be formed based on, for example, a ceramic substrate, a printed circuit board (PCB), an organic substrate, or an interposer substrate. According to an exemplary embodiment, the package substrate 400 may be formed from an active wafer, such as a silicon wafer.

[0047] like Figure 1 As shown, external connection members 420, such as bumps or solder balls, can be disposed on the lower surface of the package substrate 400. The external connection members 420 can serve to mount the semiconductor package 1000 onto an external system board or motherboard. The external connection members 420 can be larger than the connection members 330 of the logic chip 300. Furthermore, the pitch of the external connection members 420 can be larger than the pitch of the connection members 330 of the logic chip 300. The material or structure of the external connection members 420 is the same as that described above regarding the connection members 330 of the logic chip 300.

[0048] Sealing material 500 can cover and seal the logic chip 300, the stacked structure SS, and the underfill 350 on the packaging substrate 400. Sealing material 500 can seal and protect the logic chip 300 and the stacked structure SS from external physical and chemical damage. Sealing material 500 can be formed from, for example, epoxy, thermosetting, thermoplastic, or UV-curable materials. Alternatively, sealing material 500 can be formed from resin and may include fillers. Sealing material 500 can be formed using a MUF process, in which case the underfill 350 can be omitted.

[0049] like Figure 1 As shown, the sealing material 500 may have a structure that covers the upper surface of the stacked structure SS. However, the inventive concept is not limited thereto. For example, in an exemplary embodiment, the sealing material 500 may have a structure that does not cover the upper surface of the stacked structure SS. That is, the upper surface of the stacked structure SS may be exposed from the sealing material 500.

[0050] The semiconductor package 1000 of the exemplary embodiment may have a structure in which a stacked structure SS is stacked on the logic chip 300, and the stacked structure SS may have a structure in which passive component chips 200 are stacked on the IVR chip 100. The structure of the stacked structure SS can minimize or reduce resistance by minimizing or reducing the path between the voltage regulator of the IVR chip 100 and the passive components (e.g., inductors) in the passive component chips 200, thereby improving the operating characteristics of the IVR chip 100. Furthermore, because the stacked structure SS including the IVR chip 100 is directly stacked on the logic chip 300, the operating characteristics of the logic chip 300 can be improved, and the size of the package can be minimized or reduced.

[0051] Referring to the comparative example, voltage regulators and inductors are typically manufactured together as a single chip. However, in this case, because the inductor occupies a large area, this method cannot reduce the chip size. Furthermore, when the voltage regulator is separately mounted on the system board, the path to the logic chip or inductor increases, which leads to a deterioration in the operating characteristics of both the voltage regulator and the logic chip. Moreover, when the voltage regulator and passive components such as inductors are separately mounted on the package substrate, the package size increases. However, in the semiconductor package 1000 according to the exemplary embodiment, the stacked structure SS is formed with passive component chips 200 stacked on the IVR chip 100, and the stacked structure SS is stacked on the logic chip 300. Therefore, the above-mentioned problems can be solved according to the exemplary embodiment conceived in this invention.

[0052] Figures 3A to 3C This illustrates an embodiment of the invention. Figure 1 A cross-sectional view of the structure in the semiconductor package 1000 where the stacked structure SS is stacked on the logic chip 300 in various bonding configurations. For ease of illustration, further descriptions of the previously described components and technical aspects may be provided only briefly or omitted.

[0053] Reference Figure 3AIn the semiconductor package 1000 of the exemplary embodiment, the stacked structure SS can be stacked on the logic chip 300 in a front-to-back bonding configuration. The back surface refers to the surface opposite the passive surface and the active surface. Therefore, the front-to-back bonding configuration can refer to the form in which two chips or two wafers are bonded so that the active surface and the passive surface face each other. For example, the stacked structure SS can be bonded and stacked on the logic chip 300 with the active surface ASlo of the logic chip 300 and the passive surface NASivr of the IVR chip 100 facing each other. Therefore, in the semiconductor package 1000 of the exemplary embodiment, the logic chip 300 can have an upper side as the active surface ASlo and a lower side as the passive surface NASlo (wherein NASlo indicates the passive surface of the logic chip 300). Additionally, the IVR chip 100 at the lower part of the stacked structure SS can have an upper side as the active surface ASivr (wherein ASiivr indicates the active surface of the IVR chip 100) and a lower side as the passive surface NASivr.

[0054] In the semiconductor package 1000 of the exemplary embodiment, the stacked structure SS can be stacked on the logic chip 300 via pad-to-pad bonding, wherein the chip pad 322 of the logic chip 300 and the lower pad 105 of the IVR chip 100 are in direct contact with each other. Furthermore, the stacked structure SS located on the logic chip 300 via pad-to-pad bonding can be obtained from a WoW structure or a D2W structure.

[0055] As described above, the chip pads 122 of the IVR chip 100 and the chip pads 222 of the passive component chip 200 that contact the chip pads 122 in the stacked structure SS have a first pitch P1. Additionally, the through electrode 110 of the IVR chip 100, the lower pad 105 connected to the through electrode 110, and the chip pad 322 of the logic chip 300 that contacts the lower pad 105 via pad-to-pad bonding can have a second pitch P2. The second pitch P2 can be similar to the first pitch P1. For example, the second pitch P2 can be approximately 10 μm or less. In an exemplary embodiment, the second pitch P2 can be approximately 5 μm. In an exemplary embodiment, the second pitch P2 can be approximately 10 μm.

[0056] The through electrode 310 of the logic chip 300 and the lower pad 305 connected to the through electrode 310 may have a third pitch P3. Considering that the logic chip 300 is stacked on the package substrate 400 via connection members 330, in a CoW structure, the third pitch P3 may be similar to or larger than the pad pitch. For example, the third pitch P3 may be approximately 50 μm or larger. However, the third pitch P3 is not limited to the above values.

[0057] Reference Figure 3BIn the semiconductor package 1000' of the exemplary embodiment, the stacked structure SS can be stacked on the logic chip 300 in a front-to-back bonding configuration. For example, similar to Figure 3A The semiconductor package 1000 has a stacked structure SS that can be bonded and stacked on the logic chip 300, such that the active surface ASlo of the logic chip 300 and the passive surface NASivr of the IVR chip 100 face each other. Therefore, the logic chip 300 can have an upper side as the active surface ASlo and a lower side as the passive surface NASivr, and the IVR chip 100 of the stacked structure SS can have an upper side as the active surface ASivr and a lower side as the passive surface NASivr.

[0058] However, in semiconductor package 1000', the stacked structure SS can be stacked on logic chip 300 using ACF 150 bonding instead of pad-to-pad bonding. The stacked structure of logic chip 300 and stacked structure SS using ACF 150 bonding can be obtained from WoW structure or D2W structure.

[0059] In the stacked structure SS, the chip pad 122 of the IVR chip 100 and the chip pad 222 of the passive component chip can have a first pitch P1. Furthermore, the through electrode 110 of the IVR chip 100, the lower pad 105 connected to the through electrode 110, and the chip pad 322 of the logic chip 300 corresponding to the lower pad 105 through bonding with the ACF 150 can have a second pitch P2. Furthermore, the through electrode 310 of the logic chip 300 and the lower pad 305 connected to the through electrode 310 can have a third pitch P3. The dimensions of the first pitch P1, the second pitch P2, and the third pitch P3 are consistent with those described above. Figure 3A The semiconductor package 1000 is described in the same way.

[0060] Reference Figure 3C In the semiconductor package 1000 of the exemplary embodiment, the stacked structure SS can be stacked on the logic chip 300a in a back-to-back bonding configuration. The back-to-back bonding configuration can refer to the form in which two chips or two wafers are bonded so that the passive surfaces face each other.

[0061] For example, the stacked structure SS can be bonded and stacked on the logic chip 300a with the passive surface NASlo of the logic chip 300a and the passive surface NASivr of the IVR chip 100 facing each other. Therefore, in the semiconductor package 1000", the logic chip 300a can have an upper side as the passive surface NASlo and a lower side as the active surface ASlo. As for the stacked structure SS, it is designed to be compatible with... Figure 3AIn the same manner as in the semiconductor package 1000, the IVR chip 100 can have an upper side as an active surface ASiVr and a lower side as a passive surface NaSiVr. The semiconductor package 1000 can be considered as a semiconductor package that, with... Figure 3A Semiconductor package 1000 and Figure 3B Compared to the semiconductor package 1000', the logic chip 300a is upside down and its upper and lower surfaces are altered.

[0062] In the semiconductor package 1000", the stacked structure SS can be stacked on the logic chip 300a via a connection member 130. The connection member 130 is connected to the... Figure 1 The connection member 330 for the logic chip 300 is described in the semiconductor package 1000. The logic chip 300a and the stacked structure SS can be obtained from the CoW structure by means of the connection member 130. When using the connection member 130 for bonding, the adhesive film 160 can be disposed between the IVR chip 100 and the logic chip 300a.

[0063] In the semiconductor package 1000", the chip pads 122 of the IVR chip 100 in the stacked structure SS and the chip pads 222 of the passive component chip 200 that contact the chip pads 122 may have a first pitch P1. Additionally, the through electrode 110 of the IVR chip 100 and the lower pad 105 connected to the through electrode 110, as well as the lower pad 305 of the logic chip 300a connected to the lower pad 105 by means of a connection member 330 and the through electrode 310 connected to the lower pad 305, may have a second pitch P2'. However, the second pitch P2' may be, for example, about 50 μm or less. In an exemplary embodiment, based on a CoW structure, the second pitch P2' may be about 30 μm. However, the second pitch P2' is not limited to the above values.

[0064] The chip pad 322 of logic chip 300a can have a third pitch P3. The third pitch P3 is related to the above... Figure 3A The description of the third pitch P3 in the semiconductor package 1000 is the same. That is, considering that the logic chip 300a is stacked on the package substrate 400 via the connection member 330, in the CoW structure, the third pitch P3 can be similar to or larger than the pad pitch. For example, the third pitch P3 can be approximately 50 μm or larger. However, the third pitch P3 is not limited to the above values. In addition, considering that the second pitch P2' is also obtained from the CoW structure, as... Figure 3C As shown, the third pitch P3 can be substantially the same as the second pitch P2'. However, the inventive concept is not limited thereto. For example, according to an exemplary embodiment, the third pitch P3 can be larger than the second pitch P2'.

[0065] In addition, Figure 3C Although a stacked structure SS is shown stacked on the passive surface NASlo of the logic chip 300a by means of the connection member 130, the stacked structure of the semiconductor package 1000" is not limited to this. For example, in the semiconductor package 1000" of the exemplary embodiment, the stacked structure SS can be stacked on the active surface ASlo of the logic chip 300a by means of the connection member 130.

[0066] In addition, Figure 3C Although back-to-back bonding is shown to be achieved by using the bonding of connecting members, the inventive concept is not limited thereto. For example, in an exemplary embodiment, back-to-back bonding can be achieved by using pad-to-pad bonding or bonding using anisotropic conductive films, and the specific implementation is similar to that of front-to-back bonding using pad-to-pad bonding or bonding using anisotropic conductive films, and will not be described in detail here.

[0067] Figure 4 and Figure 5 These are cross-sectional views of semiconductor packages 1000a and 1000b according to exemplary embodiments. For ease of explanation, further descriptions of the previously described elements and techniques may be provided only briefly or omitted.

[0068] Reference Figure 4 The semiconductor package 1000a of the exemplary embodiment and Figure 1 The difference in the semiconductor package 1000 lies in the fact that two stacked structures, SS1 and SS2, are stacked on the logic chip 300. For example, in the semiconductor package 1000a, the first stacked structure SS1 can be stacked on the upper left side of the logic chip 300, and the second stacked structure SS2 can be stacked on the upper right side of the logic chip 300. Therefore, in a cross-sectional view, the first stacked structure SS1 and the second stacked structure SS2 can be stacked adjacent to each other on the logic chip 300.

[0069] Both stacked structures SS1 and SS2 can include the same components and have the same construction as the stacked structure SS described above. Therefore, in an exemplary embodiment, the first IVR chip 100 can be stacked on the logic chip 300, and the second IVR chip 100 can be stacked on the logic chip 300. Furthermore, the first passive component chip 200 can be stacked on the first IVR chip 100, and the second passive component chip 200 can be stacked on the second IVR chip 100.

[0070] The first stacked structure SS1 and the second stacked structure SS2 can be stacked on the logic chip 300 in various bonding configurations. For example, the first stacked structure SS1 and the second stacked structure SS2 can be stacked on the logic chip 300 in a front-to-back bonding configuration or a back-to-back bonding configuration. Furthermore, the stacked structure of the first stacked structure SS1 and the second stacked structure SS2 on the logic chip 300 through such front-to-back or back-to-back bonding can be obtained from D2W or CoW structures. However, since the two stacked structures SS1 and SS2 are stacked on one logic chip 300, a WoW structure where wafers are stacked on a wafer can be excluded.

[0071] exist Figure 4 The diagram illustrates a structure where two stacked structures, SS1 and SS2, are stacked on a logic chip 300. However, the structure of the semiconductor package 1000a is not limited to this. For example, in an exemplary embodiment, the semiconductor package 1000a may include a structure where three or more stacked structures are stacked on the logic chip 300.

[0072] The logic chip 300 may include at least one logic element. In an exemplary embodiment, the logic chip 300 may include multiple logic elements. Furthermore, the logic elements may use at least two different voltages. For example, different logic elements may use different voltages to operate appropriately. In this case, a stacked structure of IVR chips capable of adjusting the corresponding voltages and passive component chips relative to the IVR chips is arranged on the logic chip 300, thus optimizing or improving the operating characteristics of the logic chip 300. Additionally, as... Figure 4 As shown, when all stacked structures SS1 and SS2 are disposed within the upper surface of the logic chip 300, the overall size of the semiconductor package 1000a can be compared with... Figure 1 The dimensions of the semiconductor package 1000 are basically the same.

[0073] Reference Figure 5 The difference between the semiconductor package 1000b of the exemplary embodiment and the previously described semiconductor packages 1000, 1000', 1000" and 1000a is that the stacked structure SS3 is not stacked on the logic chip 300. For example, in the semiconductor package 1000b, the stacked structure SS3 can be directly stacked on the package substrate 400 via the connecting member 130. The structure of the stacked structure SS3 can be similar to that of the referenced... Figure 2 The described stacked structure SS is essentially the same. However, in terms of size, the stacked structure SS3 can be smaller than that included in [the previous section]. Figure 1 The semiconductor package 1000 contains a stacked structure SS. Additionally, according to an exemplary embodiment, the stacked structure SS3 may have a similar structure to... Figure 4The stacked structure of the semiconductor package 1000a has similar dimensions to SS1 and SS2.

[0074] The stacked structure SS3 can be stacked on the package substrate 400 via the connecting member 130, and the bottom filler 160a can fill the area between the stacked structure SS3 and the package substrate 400. When the sealing material 500 is formed by the MUF process, the bottom filler 160a can be omitted. Because the stacked structure SS3 is stacked via the connecting member 130, the pitch of the through electrode 110 and the lower pad 105 can be similar to the pitch of the pads in the CoW structure.

[0075] The voltage regulator of the IVR chip 100 in the stacked structure SS3 can be connected to the logic element of the logic chip 300b via wiring in the package substrate 400. In the exemplary embodiment, because the stacked structure SS3 is not stacked on top of the logic chip 300b, a direct connection between the IVR chip 100 and the logic chip 300b via a through electrode is not implemented; therefore, the logic chip 300b does not include a through electrode.

[0076] Because the semiconductor package 1000b includes a stacked structure SS3 on which passive component chips 200 are stacked on the IVR chip 100, the operating characteristics of the IVR chip 100 can be improved. Furthermore, while the size of the package substrate 400 remains constant, the size of the logic chip 300b is reduced, and the stacked structure SS3 is disposed on the remaining portion of the package substrate 400; therefore, the overall height of the semiconductor package 1000b can be reduced. Moreover, because the logic chip 300b can be formed without forming through electrodes, the efficiency of manufacturing the logic chip 300b can be improved, which increases yield; therefore, mass production of the semiconductor package 1000b can be increased.

[0077] Figure 6 , Figures 7A to 7C , Figures 8A to 8B , Figure 9 and Figure 10 This schematically illustrates the manufacturing process according to an exemplary embodiment. Figure 1 Top view, perspective view and cross-sectional view of the process of semiconductor packaging. Figure 7B and Figure 7C According to an exemplary embodiment, along Figure 7A The cross-sectional view taken from line I-I'. Figure 8A and Figure 8B Corresponding to Figure 7B and Figure 7C . will refer to Figure 1 , Figure 2 and Figures 3A to 3C Give Figure 6 , Figures 7A to 7C , Figures 8A to 8B , Figure 9 and Figure 10 The description is as follows. For ease of explanation, further descriptions of the previously described components and technical aspects may be provided briefly or omitted.

[0078] Reference Figure 6 In a method for manufacturing semiconductor packages, firstly, corresponding devices are formed on each wafer. For example, a voltage regulator can be formed on a first wafer 100S, a passive component (e.g., an inductor) can be formed on a second wafer 200S, and a logic element can be formed on a third wafer 300S. Figure 6 In this context, the solid-lined rectangles can correspond to individual chips separated by subsequent sawing processes. For example, an IVR chip 100 can be formed on a first wafer 100S, a passive component chip 200 can be formed on a second wafer 200S, and a logic chip 300 can be formed on a third wafer 300S.

[0079] The IVR chip 100, passive component chip 200, and logic chip 300 can be respectively connected to... Figure 1 The IVR chip 100, passive component chip 200, and logic chip 300 of the semiconductor package 1000 are substantially identical. However, in an exemplary embodiment, because the IVR chip 100, passive component chip 200, and logic chip 300 are in a wafer state before bonding and sawing processes are performed, connecting members or ACF are not included. In an exemplary embodiment, the IVR chip 100 and logic chip 300 in the wafer state may include through electrodes, and the passive component chip 200 in the wafer state does not include through electrodes.

[0080] Reference Figures 7A to 7C The second wafer 200S is stacked on top of the first wafer 100S in a WoW (Work of Wo) structure to form a stacked wafer SW or SW'. For example, in... Figure 7B and Figure 7C As seen in the diagram, the second wafer 200S can be stacked on the first wafer 100S in a front-to-front bonding configuration. Furthermore, the second wafer 200S can be stacked on the first wafer 100S via pad-to-pad bonding. Therefore, the chip pads 122 of the first wafer 100S and the corresponding chip pads 222 of the second wafer 200S can contact each other (e.g., directly contact each other).

[0081] Figure 7C Stacked wafers SW' and Figure 7B The difference between the stacked wafers SW and the stacked wafers SW is that the connecting member 130 is further disposed on the lower surface of the first wafer 100S. For example, Figure 7B The stacked wafers (SW) can be a stacked structure formed by sawing. Figure 8AThe SS) was then stacked on the logic chip 300 in a D2W structure. In contrast, Figure 7C The stacked wafers SW' can be a stacked structure formed by sawing. Figure 8B The SS') is then stacked on the logic chip 300 in a CoW structure. In the formation Figure 7B After stacking the wafers SW, a bump process can be used to attach the connection members 130 to the lower surface of the first wafer 100S. Figure 7C Stacked wafers SW'.

[0082] The chip pads 122 of the first wafer 100S and the chip pads 222 of the second wafer 200S may have a first pitch P1. Additionally, the through electrode 110 and the lower pad 105 of the first wafer 100S may have a second pitch P2 or P2'. The second pitch P2 or P2' may vary depending on whether the stacking structure is a D2W structure or a CoW structure on the logic chip, as described above. For example, when the stacking structure is a D2W structure, the through electrode 110 and the lower pad 105 of the first wafer 100S may have a second pitch P2. The second pitch P2 may be related to... Figure 3A or Figure 3B The second pitch P2 of the through electrode 110 and the lower pad 105 in the semiconductor package 1000 or 1000' is the same as described. When the stacked structure is stacked in a CoW structure, the through electrode 110 and the lower pad 105 of the first wafer 100S may have a second pitch P2'. The second pitch P2' is related to the second pitch P2' of the through electrode 110 and the lower pad 105 in the semiconductor package 1000 or 1000'. Figure 3C The through electrode 110 and the second pitch P2' of the lower pad 105 of the IVR chip 100 in the semiconductor package 1000" are the same as described.

[0083] Reference Figure 8A and Figure 8B The stacked wafers SW and SW' are separated individually using a sawing process to form stacked structures SS and SS'. For example, the sawing process can be used to separate the stacked wafers SW and SW'. Figure 7B The stacked wafers SW are separated individually to form Figure 8A The stacked structure SS can be cut using a sawing process. Figure 7C The stacked wafers SW' are separated individually to form Figure 8B The stacked structure SS'. As mentioned above, Figure 8A The through electrode 110 and lower pad 105 of the stacked structure SS IVR chip 100 can have a second pitch P2, and Figure 8B The through electrode 110 and lower pad 105 of the IVR chip 100 in the stacked structure SS' can have a second pitch P2'.

[0084] Reference Figure 9 Each stacked structure SS or SS' is stacked on the logic chip 300 of the third wafer 300S. For example, Figure 8A The stacked structure SS can be stacked on the logic chip 300 of the third wafer 300S in a D2W structure. Additionally, Figure 8A The stacked structure of SS can utilize pad-to-pad bonding or ACF bonding. Additionally, Figure 8A The stacked structure SS can be stacked in a front-to-back bonding configuration. In the front-to-back bonding configuration, the passive surface of the IVR chip 100 of the stacked structure SS is bonded to the active surface of the logic chip 300, as shown in... Figure 3A or Figure 3B As in semiconductor packages 1000 or 1000'. However, according to an exemplary embodiment, Figure 8A The stacked structure SS can have a back-to-back bonding configuration, in which the passive surface of the IVR chip 100 of the stacked structure SS is bonded to the passive surface of the logic chip 300.

[0085] Figure 8B The stacked structure SS' can be stacked on the logic chip 300 of the third wafer 300S in a CoW structure. Additionally, Figure 8B The stacking of the stacked structure SS' can be achieved by using the joint of connecting member 130. Additionally, Figure 8B The stacking structure SS' can have a back-to-back joining form, such as in Figure 3C As in the semiconductor package 1000". However, the inventive concept is not limited thereto. For example, according to an exemplary embodiment, Figure 8B The stacking structure SS' can have a front-to-back joining form.

[0086] Reference Figure 10 After stacking the stacked structures SS or SS' onto the logic chip 300, a bumping process can be performed to attach the connection members 330 to the lower surface of the third wafer 300S. Subsequently, the logic chip 300 and the stacked structures SS or SS' are individually separated by a sawing process, thereby forming a structure where the stacked structures SS or SS' are stacked on the logic chip 300. Then, the logic chip 300 and the stacked structures SS or SS' are stacked on the packaging substrate 400 using the connection members 330 and underfill 350, and sealed with a sealing material 500, thus enabling the fabrication of... Figure 1 Semiconductor package 1000. For example, when... Figure 8A When the stacked structure SS is stacked on the logic chip 300, manufacturing... Figure 3A or Figure 3B The semiconductor package 1000 or 1000' shown includes this structure, and when... Figure 8BWhen the stacked structure SS' is stacked on the logic chip 300, it can be manufactured Figure 3C The semiconductor package 1000 shown includes this structure.

[0087] Figure 11 and Figure 12 It schematically illustrates the manufacturing process. Figure 4 A top view of the process of the semiconductor package 1000a. (Refer to...) Figure 4 describe Figure 11 and Figure 12 For ease of explanation, further descriptions of the previously described components and technical aspects may be provided briefly or omitted.

[0088] Reference Figure 11 In an exemplary embodiment of the method for manufacturing a semiconductor package, firstly, a corresponding element is formed on each of a plurality of wafers. For example, a voltage regulator may be formed on a first wafer 100S1, a passive element may be formed on a second wafer 200S1, and a logic element may be formed on a third wafer 300S1. Figure 11 In this context, the solid-lined rectangles can correspond to individual chips separated by a subsequent sawing process. For example, an IVR chip 100' can be formed on a first wafer 100S1, a passive component chip 200' can be formed on a second wafer 200S1, and a logic chip 300' can be formed on a third wafer 300S1.

[0089] In the method of manufacturing a semiconductor package according to an exemplary embodiment, the IVR chip 100' of the first wafer 100S1 and the passive component chip 200' of the second wafer 200S1 may have substantially the same size, but the logic chip 300' of the third wafer 300S1 may be larger than the IVR chip 100' and the passive component chip 200'. Additionally, as... Figure 11 As shown, the logic chip 300' can have an elongated shape in one direction. However, the inventive concept is not limited thereto. For example, according to an exemplary embodiment, the logic chip 300' can also have a square structure similar to the IVR chip 100' and the passive component chip 200', but can have a larger size.

[0090] Then, execution and reference. Figures 7A to 8B The process described is the same as the process used to form such a... Figure 8A or Figure 8B The stacked structure SS or SS' shown.

[0091] Reference Figure 12Each stacked structure SS or SS' is stacked on logic chip 300' of the third wafer 300S1, and the stacked structures SS or SS' are stacked two at a time on logic chip 300'. The stacked structures SS or SS' can be stacked two at a time on logic chip 300' in a D2W or CoW structure. For example, in Figure 8A In the case of the stacked structure SS, the stacked structure SS can be stacked on the logic chip 300' in a D2W structure, and... Figure 8B In the case of the stacked structure SS', the stacked structure SS' can be stacked on logic chip 300' in a CoW structure, with each pair stacked on top of the other.

[0092] Next, a bumping process is performed to attach the connecting member 330 to the lower surface of the third wafer 300S1, and a sawing process is performed to separate them individually, thus forming a structure in which two stacked structures SS or SS' are stacked on a logic chip 300. Subsequently, the logic chip 300' and the two stacked structures SS or SS' are stacked on the package substrate 400 using the connecting member 330 and underfill 350, and sealed with a sealing material, thus enabling the fabrication of... Figure 4 1000a semiconductor package.

[0093] Figure 13A and Figure 13B It schematically illustrates the manufacturing process. Figure 5 A perspective view of the process of the semiconductor package 1000b. (Refer to...) Figure 5 describe Figure 13A and Figure 13B For ease of explanation, further descriptions of the previously described components and technical aspects may be provided briefly or omitted.

[0094] Reference Figure 13A and Figure 13B In the method of manufacturing a semiconductor package according to an exemplary embodiment, such as Figure 6 As shown, corresponding components are formed on each wafer. However, through electrodes are not formed on the logic chip 300b of the third wafer 300S2. Then, in the formation... Figure 7B After stacking the wafers (SW), such as Figure 13A As shown, the connecting member 130 is attached to the lower surface of the first wafer 100S using a bumping process to form a connection. Figure 7C The stacked wafer SW'. Additionally, as... Figure 13B As shown, the connecting member 330 can be attached to the lower surface of the third wafer 300S2 by a bumping process.

[0095] Subsequently, the stacked wafer SW' and the third wafer 300S2 are individually separated using a sawing process to form a stacked structure (see...). Figure 8BThe stacked structure SS' and logic chip 300b are then stacked on a packaging substrate 400 via connecting members 130 and 330 and bottom fillers 160a and 350, and a sealing material is formed on the packaging substrate 400. Therefore, a packaging structure SS' and logic chip 300b can be manufactured. Figure 5 1000b semiconductor package.

[0096] Figure 14 , Figures 15A to 15C and Figure 16 This schematically illustrates the manufacturing process according to an exemplary embodiment. Figure 1 Perspective, cross-sectional and top views of the process of a semiconductor package 1000. Figures 15A to 15C It is along Figure 14 The cross-sectional view taken from line II-II'. Refer to... Figures 1 to 3C describe Figure 14 , Figures 15A to 15C and Figure 16 For ease of explanation, further descriptions of the previously described components and technical aspects may be provided briefly or omitted.

[0097] Reference Figure 14 In the method of manufacturing a semiconductor package according to an exemplary embodiment, such as Figure 6 As shown, corresponding components are formed on each of the multiple wafers. Then, a second wafer 200S is stacked on top of the first wafer 100S in a WoW (Work-in-Way) structure to form a stacked wafer SW or SW'. Next, the stacked wafer SW or SW' is stacked on top of a third wafer 300S in a WoW structure to form a complete stacked wafer SWT with a three-layer structure. The stacking structure of the entire stacked wafer SWT can have various structures, such as... Figures 15A to 15C As seen in [the text] and described below.

[0098] Reference Figure 15A In the first complete stacked wafer SWT1, the stacked wafer SW can have a front-to-front bonding stacked structure. Alternatively, the stacked wafer SW can have a pad-to-pad bonding stacked structure, in which the chip pads 122 of the first wafer 100S directly contact the corresponding chip pads 222 of the second wafer 200S. However, the stacked structure of the stacked wafer SW is not limited to a pad-to-pad bonding stacked structure. For example, according to an exemplary embodiment, the stacked wafer SW can have a bonding stacked structure using an ACF (Acoustic Coding Facility).

[0099] In the stacked wafer SW, the chip pads 122 of the first wafer 100S and the chip pads 222 of the second wafer 200S may have a first pitch P1. Additionally, the through electrode 110 and the lower pad 105 of the first wafer 100S may have a second pitch P2. As described below, since the stacked wafer SW is stacked on the third wafer 300S via pad-to-pad bonding, the second pitch P2 may be substantially the same as the first pitch P1.

[0100] The stacked wafer SW can be stacked on the third wafer 300S in a front-to-back bonding configuration. For example, the stacked wafer SW can be stacked on the third wafer 300S such that the passive surface of the first wafer 100S faces the active surface of the third wafer 300S. Furthermore, the stacked wafer SW can be stacked on the third wafer 300S via pad-to-pad bonding. Therefore, the lower pad 105 of the first wafer 100S can directly contact the corresponding chip pad 322 of the third wafer 300S. The through electrode 310 and the lower pad 305 of the third wafer 300S can have a third pitch P3. After the sawing process, the first complete stacked wafer SWT1 can correspond to... Figure 3A The structure shown in the figure.

[0101] Reference Figure 15B In the second complete stacked wafer SWT2, the stacked wafer SW can have a front-to-front bonding stacked structure and a pad-to-pad bonding stacked structure. However, according to an exemplary embodiment, the stacked wafer SW can have a stacked structure with bonding using an ACF (Acceptable Connective Cell). In the stacked wafer SW, the chip pads 122 of the first wafer 100S and the chip pads 222 of the second wafer 200S can have a first pitch P1, and the through electrode 110 and the lower pad 105 of the first wafer 100S can have a second pitch P2. As described below, because the stacked wafer SW is stacked on the third wafer 300S using bonding using an ACF, the second pitch P2 can be substantially the same as the first pitch P1.

[0102] The stacked wafers SW can be stacked on the third wafer 300S in a front-to-back bonding configuration. Alternatively, the stacked wafers SW can be stacked on the third wafer 300S using ACF 150 bonding. Therefore, the lower pad 105 of the first wafer 100S and the chip pad 322 of the third wafer 300S can be positioned corresponding to each other. The through electrode 310 and the lower pad 305 of the third wafer 300S can have a third pitch P3. After the sawing process, the second complete stacked wafer SWT2 can correspond to... Figure 3B The structure shown in the figure.

[0103] Reference Figure 15CIn the third entire stacked wafer SWT3, the stacked wafer SW' can have a front-to-front bonding stacked structure and a pad-to-pad bonding stacked structure. However, according to an exemplary embodiment, the stacked wafer SW' can have a stacked structure with bonding via ACF.

[0104] In the stacked wafer SW', the chip pads 122 of the first wafer 100S and the chip pads 222 of the second wafer 200S may have a first pitch P1. Furthermore, the through electrode 110 and the lower pad 105 of the first wafer 100S may have a second pitch P2'. As described below, because the stacked wafer SW' is stacked on the third wafer 300S by bonding using the connecting member 130, the second pitch P2' may be larger than the first pitch P1. Before stacking the stacked wafer SW' on the third wafer 300S, the connecting member 130 may be attached to the lower surface of the stacked wafer SW' using a bumping process.

[0105] Stacked wafers SW' can be stacked on the third wafer 300S in a back-to-back bonding configuration. For example, stacked wafers SW' can be stacked on the third wafer 300S such that the passive surface of the first wafer 100S faces the passive surface of the third wafer 300S. An adhesive film 160 can be disposed between the first wafer 100S and the third wafer 300S. Alternatively, stacked wafers SW' can be stacked on the third wafer 300S by bonding using a connecting member 130. Therefore, the lower pad 105 of the first wafer 100S of stacked wafers SW' can be connected to the corresponding lower pad 305 of the third wafer 300S using the connecting member 130 as a medium. The through electrode 310 and the lower pad 305 of the third wafer 300S can have a third pitch P3. The third pitch P3 can be substantially the same as the second pitch P2'. After the sawing process, the third complete stacked wafer SWT3 can correspond to Figure 3C The structure shown in the figure.

[0106] Reference Figure 16After the entire stacked wafer SWT is formed, a connecting member 330 is formed on the lower surface of the third wafer 300S using a bumping process. The lower surface of the third wafer 300S can vary depending on whether the entire stacked wafer SWT has a first entire stacked wafer SWT1, a second entire stacked wafer SWT2, or a third entire stacked wafer SWT3 structure. For example, when the entire stacked wafer SWT has a first entire stacked wafer SWT1 or a second entire stacked wafer SWT2 structure, the connecting member 330 can be attached to the passive surface of the third wafer 300S because the stacked wafers SW' are stacked on the third wafer 300S in a front-to-back bonding configuration. When the entire stacked wafer SWT has a third entire stacked wafer SWT3 structure, the connecting member 330 can be attached to the active surface of the third wafer 300S because the stacked wafers SW' are stacked on the third wafer 300S in a back-to-back bonding configuration.

[0107] Subsequently, the entire stacked wafer SWT is individually separated using a sawing process to form a three-layer stacked structure of logic chip 300 or 300a and stacked structure SS. The three-layer stacked structure can correspond to, for example... Figures 3A to 3C The structure is shown in the figure. Subsequently, the three-layer stacked structure is stacked on the packaging substrate 400 via the connecting member 330 and the bottom filler 350, and a sealing material is formed on the packaging substrate 400. Therefore, it is possible to manufacture... Figure 1 1000 semiconductor packages.

[0108] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made herein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor package comprising: a package substrate; a logic chip stacked on the package substrate and including at least one logic element; and a stacked structure, wherein the stacked structure includes: an integrated voltage regulator chip including a voltage regulating circuit that regulates a voltage of the at least one logic element; and a passive element chip stacked on the integrated voltage regulator chip and including an inductor. The stacked structure is stacked on the logic chip.

2. The semiconductor package of claim 1, wherein, The logic chip includes a plurality of logic elements that use at least two different voltages, 3. The semiconductor package of claim 2, wherein, wherein at least two stacked structures are stacked on the logic chip, wherein the plurality of logic elements includes the at least one logic element and the stacked structure is one of the at least two stacked structures. The stacked structure is stacked on the package substrate, and the stacked structure, the logic chip, and the package substrate overlap each other in a cross-sectional view of the semiconductor package.

4. The semiconductor package of claim 1, wherein, In the stacked structure, the passive element chip is stacked on the integrated voltage regulator chip in a front-to-front bonding form in which active surfaces of the passive element chip and the integrated voltage regulator chip face each other.

5. The semiconductor package of claim 1, wherein, The front-to-front bonding is achieved by a pad-to-pad bonding using copper pads to bond to each other, or by a bonding using anisotropic conductive film.

6. The semiconductor package of claim 5, wherein, At least one of the integrated voltage regulator chip and the logic chip includes a through electrode, 7. The semiconductor package of claim 1, wherein, wherein the stacked structure is stacked on the logic chip in a front-to-back bonding form in which a passive surface of the integrated voltage regulator chip faces an active surface of the logic chip, or in a back-to-back bonding form in which the passive surface of the integrated voltage regulator chip faces a passive surface of the logic chip. Both the front-to-back bonding and the back-to-back bonding are achieved by any one of a pad-to-pad bonding, a bonding using anisotropic conductive film, and a bonding using a connection member.

8. The semiconductor package of claim 7, wherein, When the stacked structure is stacked on the logic chip, the logic chip includes a through electrode, 9. The semiconductor package of claim 1, wherein, when the stacked structure is not stacked on the logic chip, the logic chip does not include the through electrode, and the logic chip is stacked on the package substrate using a connection member.

10. A semiconductor package comprising: a package substrate; a logic chip mounted on the package substrate and including at least one logic element; a first integrated voltage regulator chip stacked on the logic chip and including a voltage regulating circuit that regulates a voltage of the at least one logic element; and a first passive element chip stacked on the first integrated voltage regulator chip and including an inductor, ​ ​ wherein the first passive element chip is stacked on the first integrated voltage regulator chip in a front-to-front bonding form in which an active surface of the first passive element chip and an active surface of the first integrated voltage regulator chip face each other, wherein a pitch between pads of the first integrated voltage regulator chip or the first passive element chip is 10 pm or less.

11. The semiconductor package of claim 10, wherein, at least one of the first integrated voltage regulator chip and the logic chip includes a through electrode, wherein the first integrated voltage regulator chip is stacked on the logic chip in a front-to-back bonding form in which an active surface of the first integrated voltage regulator chip faces an active surface of the logic chip or in a back-to-back bonding form in which the active surface of the first integrated voltage regulator chip faces an active surface of the logic chip.

12. The semiconductor package of claim 11, wherein, The front-to-back bonding and the back-to-back bonding are each achieved by any one of a pad-to-pad bonding, a bonding using anisotropic conductive film, and a bonding using a connection member.

13. The semiconductor package of claim 11, wherein, when the first integrated voltage regulator chip is stacked on the logic chip in a form in which pads of the first integrated voltage regulator chip contact corresponding pads of the logic chip, a pitch between the pads is 5 pm to 10 pm, and when the first integrated voltage regulator chip is stacked on the logic chip using a connection member, a pitch between the connection members is 50 pm or less.

14. The semiconductor package of claim 10, further comprising: at least one second integrated voltage regulator chip stacked on the logic chip adjacent to the first integrated voltage regulator chip; and a second passive element chip stacked on the at least one second integrated voltage regulator chip.

15. A method of manufacturing a semiconductor package, the method comprising: forming a plurality of voltage regulators on a first wafer; forming a plurality of passive elements on a second wafer, wherein each of the passive elements includes an inductor; forming a plurality of logic elements on a third wafer; forming a stacked wafer by stacking the second wafer on the first wafer in a front-to-front bonding form in which an active surface of the first wafer and an active surface of the second wafer face each other; forming a first stacked structure including an integrated voltage regulator chip at a lower portion of the first stacked structure and a passive element chip at an upper portion of the first stacked structure by sawing the stacked wafer; stacking the first stacked structure on the third wafer; forming a second stacked structure including a logic chip at a lower portion of the second stacked structure and the first stacked structure at an upper portion of the second stacked structure by sawing the third wafer; and stacking the second stacked structure on a package substrate.

16. The method of claim 15, wherein, forming the plurality of logic elements on the third wafer includes forming through electrodes on the third wafer, wherein stacking the first stacked structure on the third wafer includes stacking the first stacked structure on the third wafer in a front-to-back bonding form in which a passive surface of the integrated voltage regulator chip faces an active surface of the logic chip or a back-to-back bonding form in which the passive surface of the integrated voltage regulator chip faces a passive surface of the logic chip.

17. The method of claim 16, wherein, stacking the first stacked structure on the third wafer includes stacking the first stacked structure on the logic chip in a form in which pads of the integrated voltage regulator chip contact corresponding pads of the logic chip or stacking the first stacked structure on the logic chip using connection members.

18. The method of claim 15, wherein, stacking the first stacked structure on the third wafer includes stacking at least two of the first stacked structures on a corresponding logic chip.

19. A method of manufacturing a semiconductor package, the method comprising: forming a plurality of voltage regulators on a first wafer; forming a plurality of passive elements on a second wafer, wherein each of the passive elements includes an inductor; forming a plurality of logic elements on a third wafer; forming a first stacked wafer by stacking the second wafer on the first wafer; forming a second stacked wafer by stacking the first stacked wafer on the third wafer; forming a stacked structure having a logic chip, an integrated voltage regulator chip, and a passive element chip sequentially stacked from a lower portion by sawing the second stacked wafer; and stacking the stacked structure on a package substrate.

20. The method of claim 19, wherein, forming the plurality of logic elements on the third wafer includes forming through electrodes on the third wafer, wherein forming the first stacked wafer includes stacking the second wafer on the first wafer in a front-to-front bonding form in which an active surface of the first wafer and an active surface of the second wafer face each other.

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