Semiconductor device

Abstract

A semiconductor device includes a substrate including a first region and a second region; a first transistor on the first region and including a first semiconductor pattern protruding from the first region, a first gate structure covering an upper surface and a sidewall of the first semiconductor pattern, a first source / drain layer on the first semiconductor pattern at an opposite side of the first gate structure, an upper surface of the first source / drain layer being closer to the substrate than an uppermost surface of the first gate structure; and a second transistor on the second region and including a second semiconductor pattern protruding from the second region, a second gate structure covering a sidewall of the second semiconductor pattern, a second source / drain layer under the second semiconductor pattern, and a third source / drain layer on the second semiconductor pattern, wherein an upper surface of the first region is lower than an upper surface of the second region.

Description

TECHNICAL FIELD

[0001] Embodiments relate to semiconductor devices. BACKGROUND

[0002] When forming a fin-type field effect transistor (finFET) and a vertical channel field effect transistor (vFET) on the same substrate, the gate of the vFET can expose an upper portion of the semiconductor pattern. An insulating interlayer covering the finFET and the vFET can be etched to expose a hard mask on the semiconductor pattern, and the gate can be etched. SUMMARY

[0003] Embodiments can be implemented by providing a semiconductor device including a substrate having a first region and a second region, a first transistor on the first region of the substrate, the first transistor including a first semiconductor pattern protruding in a vertical direction from an upper surface of the first region of the substrate, a first gate structure covering an upper surface and sidewalls of the first semiconductor pattern, and a first source / drain layer on respective portions of the first semiconductor pattern at opposite sides of the first gate structure, an upper surface of the first source / drain layer being closer to the substrate in the vertical direction than an uppermost surface of the first gate structure, and a second transistor on the second region of the substrate, the second transistor including a second semiconductor pattern protruding in the vertical direction from an upper surface of the second region of the substrate, a second gate structure covering sidewalls of the second semiconductor pattern, a second source / drain layer at an upper portion of the second region of the substrate and under the second semiconductor pattern, and a third source / drain layer on the second semiconductor pattern, wherein the upper surface of the first region of the substrate is lower than the upper surface of the second region of the substrate.

[0004] Embodiments can be realized by providing a semiconductor device including a substrate including a first region and a second region; a first transistor over the first region of the substrate; and a second transistor over the second region of the substrate. The first transistor includes a first semiconductor pattern protruding in a vertical direction from an upper surface of the first region of the substrate and extending longitudinally in a first direction parallel to the upper surface of the substrate; a first gate structure over the first semiconductor pattern, the first gate structure extending longitudinally in a second direction parallel to the upper surface of the substrate and intersecting the first direction; second semiconductor patterns spaced apart from each other in the vertical direction, each of the second semiconductor patterns extending longitudinally in the first direction across the first gate structure; and a first source / drain layer on respective portions of the first semiconductor pattern at opposite sides of the first gate structure in the first direction. The second transistor includes a third semiconductor pattern protruding in the vertical direction from an upper surface of the second region of the substrate; a second gate structure covering sidewalls of the third semiconductor pattern; a second source / drain layer at an upper portion of the second region of the substrate and under the third semiconductor pattern; and a third source / drain layer over the third semiconductor pattern. Wherein the upper surface of the first region of the substrate is lower than the upper surface of the second region of the substrate.

[0005] Embodiments can be realized by providing a semiconductor device including a substrate including a first region, a second region, and a third region; a first transistor over the first region of the substrate; a second transistor over the second region of the substrate; and a third transistor over the third region of the substrate. The first transistor includes a first semiconductor pattern protruding in a vertical direction from an upper surface of the first region of the substrate and extending longitudinally in a first direction parallel to the upper surface of the substrate; a first gate structure covering an upper surface and sidewalls of the first semiconductor pattern in a second direction parallel to the upper surface of the substrate and intersecting the first direction; and a first source / drain layer on respective portions of the first semiconductor pattern at opposite sides of the first gate structure in the first direction. The second transistor includes a second semiconductor pattern protruding in the vertical direction from an upper surface of the second region of the substrate and extending longitudinally in the first direction; a second gate structure surrounding sidewalls of the second semiconductor pattern; a second source / drain layer at an upper portion of the second region of the substrate and under the second semiconductor pattern; and a third source / drain layer on the second semiconductor pattern. The third transistor includes a third semiconductor pattern protruding in the vertical direction from an upper surface of the third region of the substrate and extending longitudinally in the first direction; a third gate structure on the third semiconductor pattern; fourth semiconductor patterns spaced apart from each other in the vertical direction, each of the fourth semiconductor patterns extending longitudinally in the first direction across the third gate structure; and a fourth source / drain layer on respective portions of the third semiconductor structure at opposite sides of the third gate structure in the first direction. Wherein the upper surface of the first region of the substrate is lower than the upper surface of the second region of the substrate, and the upper surface of the third region of the substrate is lower than the upper surface of the first region of the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0006] The features will become apparent to one skilled in the art upon examination of the detailed description of the exemplary embodiments, taken in conjunction with the accompanying drawings, in which:

[0007] Figures 1 to 21 are plan and sectional views of multiple stages in a method of manufacturing a semiconductor device according to example embodiments.

[0008] Figures 22 to 31 are sectional views of multiple stages in a method of manufacturing a semiconductor device according to example embodiments.

[0009] Figures 32 to 45 are plan and sectional views of multiple stages in a method of manufacturing a semiconductor device according to example embodiments.

[0010] Figure 46 is a sectional view of a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0011] Hereinafter, in the specification (not necessarily in the claims), two directions substantially parallel to the upper surface of the substrate and intersecting each other can be defined as a first direction and a second direction, respectively, and a direction substantially perpendicular to the upper surface of the substrate can be defined as a third direction or a vertical direction. In an example embodiment, the first direction and the second direction can be substantially perpendicular to each other.

[0012] Figures 1 to 21 are plan views and sectional views of a plurality of stages in a method of manufacturing a semiconductor device according to an example embodiment. Specifically, Figure 1 , Figure 3 , Figure 8 , Figure 11 and Figure 19 are plan views, Figure 2 , Figure 4 , Figures 6-7 , Figure 9 , Figure 12 , Figure 14 , Figure 16 and Figure 20 are sectional views taken along line A-A' of the respective plan views, Figure 5 , Figure 10 , Figure 13 , Figure 15 , Figures 17-18 and Figure 21 are sectional views taken along line B-B' and C-C' of the respective plan views, respectively.

[0013] Referring to Figure 1 and Figure 2 , a first impurity region 110 can be formed at a portion of the second region II of the substrate 100 (including the first region I and the second region II). An upper portion of the first region I of the substrate 100 can be removed to form a first recess 120.

[0014] The substrate 100 can include a semiconductor material such as silicon, germanium, silicon germanium, etc., or a III-V semiconductor compound such as GaP, GaAs, GaSb, etc. In an implementation, the substrate 100 can be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0015] The first impurity region 110 can be formed by implanting an impurity onto the substrate 100 through, for example, an ion implantation process, and the impurity can include, for example, an n-type impurity or a p-type impurity. In an implementation, as shown in the drawings, the first impurity region 110 can extend longitudinally in the first direction in the second region II of the substrate 100. In an implementation, the first impurity region 110 can be formed in an entire portion of the second region II of the substrate 100, or a plurality of first impurity regions 110 can be formed to be spaced apart from each other in the second direction.

[0016] When the first recess 120 is formed on the first region I of the substrate 100, the upper surface of the first region I of the substrate 100 can have a first height H1 (e.g., in the third or vertical direction) that is less than a second height H2 of the upper surface of the second region II of the substrate 100.

[0017] Referring to Figures 3 to 5 , the first hard mask 132 and the second hard mask 134 can be formed on the first region I and the second region II of the substrate 100, respectively, and the upper portion of the substrate 100 can be etched using the first hard mask 132 and the second hard mask 134 as etching masks to form the first semiconductor pattern 102 and the second semiconductor pattern 104 protruding upward from the substrate 100 in the third direction on the first region I and the second region II of the substrate 100, respectively. A portion of the upper surface of the first impurity region 110 on the second region II of the substrate 100 can be exposed.

[0018] In an implementation, each of the first hard mask 132 and the second hard mask 134 can extend in the first direction (e.g., longitudinally). In an implementation, the second hard mask 134 can overlap the first impurity region 110 in a plan view. In an implementation, as shown in the drawings, one first hard mask 132 and one second hard mask 134 can be on the first region I and the second region II of the substrate 100, respectively. In an implementation, a plurality of first hard masks 132 can be formed to be spaced apart from each other in the second direction and / or in the first direction on the first region I of the substrate 100, and a plurality of second hard masks 134 can be formed to be spaced apart from each other in the second direction and / or in the first direction on the second region II of the substrate 100. In an implementation, a plurality of first semiconductor patterns 102 can be formed to be spaced apart from each other on the first region I of the substrate 100, and a plurality of second semiconductor patterns 104 can be formed to be spaced apart from each other on the second region II of the substrate 100.

[0019] Each of the first hard mask 132 and the second hard mask 134 can include a nitride, such as silicon nitride.

[0020] When the first semiconductor pattern 102 and the second semiconductor pattern 104 are formed, the upper surfaces of the first region I and the second region II of the substrate 100 (on which or at which the first semiconductor pattern 102 and the second semiconductor pattern 104 are not formed) can have a third height H3 and a fourth height H4 (in the vertical direction), respectively, and the third height H3 can be less than the fourth height H4. In an implementation, the thickness of the first region I of the substrate 100 in the third direction (e.g., corresponding to H3) can be less than the thickness of the second region II of the substrate 100 in the third direction (e.g., corresponding to H4).

[0021] Referring toFigure 6 A first spacer layer can be formed on the substrate 100 with the first semiconductor pattern 102 and the second semiconductor pattern 104 and the first hard mask 132 and the second hard mask 134, and an upper portion of the first spacer layer can be etched to form a first spacer 142 and a second spacer 144 covering lower sidewalls of the first semiconductor pattern 102 and the second semiconductor pattern 104, respectively.

[0022] The first spacer 142 and the second spacer 144 can include an oxide, such as silicon oxide.

[0023] A first sacrificial layer 150 can be formed to cover the first semiconductor pattern 102 and the second semiconductor pattern 104 and the first hard mask 132 and the second hard mask 134. A portion of the first sacrificial layer 150 on the first region I of the substrate 100 can expose an upper surface of the first hard mask 132.

[0024] The first sacrificial layer 150 can include, for example, silicon on hard mask (SOH), amorphous carbon layer (ACL), etc. The exposed first hard mask 132 can be removed to expose an upper surface of the first semiconductor pattern 102, and the first sacrificial layer 150 can be removed.

[0025] Referring to Figure 7 A gate structure layer can be conformally formed on the first spacer 142 and the second spacer 144, the first semiconductor pattern 102 and the second semiconductor pattern 104, and the second hard mask 134.

[0026] In an implementation, the gate structure layer 190 can include an interface layer 160, a gate insulating layer 170, and a gate electrode layer 180 stacked in sequence. The interface layer 160, the gate insulating layer 170, and the gate electrode layer 180 can include, for example, silicon oxide, metal oxide, and metal, respectively.

[0027] Referring to Figures 8 to 10 The gate structure layer 190 can be etched by an etching process using an etching mask to form a first gate structure 192 and a second gate structure 194 on the first region I and the second region II of the substrate 100, respectively.

[0028] In one embodiment, the first gate structure 192 can extend in the second direction and can cover a portion of the first semiconductor pattern 102, for example, a central portion in the first direction. When a plurality of first semiconductor patterns 102 are formed to be spaced apart from each other in the second direction, the first gate structure 192 can cover one or some of the plurality of first semiconductor patterns 102. In one embodiment, one first gate structure 192 can be used as shown in the drawing. In one embodiment, a plurality of first gate structures 192 can be formed to be spaced apart from each other in the first direction, and each of the plurality of first gate structures 192 can cover a portion of each first semiconductor pattern 102. The first gate structure 192 can include the first interface pattern 162, the first gate insulating pattern 172, and the first gate electrode 182 which are sequentially stacked.

[0029] The second gate structure 194 can extend in the first direction and can completely cover the second semiconductor pattern 104. In a plan view, the second gate structure 194 can have an area greater than that of the second semiconductor pattern 104. When a plurality of second semiconductor patterns 104 are formed to be spaced apart from each other in the second direction, a plurality of second gate structures 194 can be formed to be spaced apart from each other in the second direction to cover the second semiconductor patterns 104, respectively. In one embodiment, a plurality of second gate structures 194 can be formed to be spaced apart from each other in the first direction. The second gate structure 194 can include the second interface pattern 164, the second gate insulating pattern 174, and the second gate electrode 184 which are sequentially stacked.

[0030] Referring to Figures 11 to 13 A second spacer layer can be formed on the first gate structure 192 and the second gate structure 194, the first and second spacers 142 and 144, and the first semiconductor pattern 102, and the second spacer layer can be anisotropically etched.

[0031] The fourth spacer 202 can be formed on the sidewall of the first gate structure 192, the fifth spacer 203 can be formed on the sidewall of a portion of the first semiconductor pattern 102 (not covered by the first gate structure 192), and the seventh spacer 205 can be formed on the sidewall of the second gate structure 194.

[0032] The portion of the first gate structure 192 on the first semiconductor pattern 102 and the portion of the first gate structure 192 on the first spacer 142 can have different heights, and thus the third spacer 201 can be further formed on the portion of the first gate structure 192 on each of the opposite sidewalls of the first semiconductor pattern 102 along the second direction. In an implementation, the portion of the second gate structure 194 on the second semiconductor pattern 104 and the portion of the second gate structure 194 on the second spacer 144 can have different heights, and thus the sixth spacer 204 can be further formed on the portion of the second gate structure 194 on each of the opposite sidewalls of the second semiconductor pattern 104 along the second direction.

[0033] The portion of the first semiconductor pattern 102 not covered by the first gate structure 192 and the fourth spacer 202 can be etched to form a second recess, and a selective epitaxial growth (SEG) process can be performed using the portion of the first semiconductor pattern 102 exposed by the second recess as a seed to form a second impurity region 210 in the second recess.

[0034] In an implementation, the SEG process can be performed using a silicon source gas, a germanium source gas, an etching gas, and a carrier gas to form a monocrystalline silicon germanium layer. The SEG process can be performed using a p-type impurity source gas to form a silicon germanium layer doped with a p-type impurity.

[0035] In an implementation, the SEG process can be performed using a silicon source gas, a carbon source gas, an etching gas, and a carrier gas to form a monocrystalline silicon carbide layer. The SEG process can be performed using an n-type impurity source gas to form a monocrystalline silicon carbide layer doped with an n-type impurity. In an implementation, the SEG process can be performed using a silicon source gas, an etching gas, and a carrier gas to form a monocrystalline silicon layer. The SEG process can be performed using an n-type impurity source gas to form a monocrystalline silicon layer doped with an n-type impurity.

[0036] The second impurity region 210 can grow not only in a vertical direction but also in a horizontal direction, and can contact the sidewall of the fourth spacer 202. In an implementation, the second impurity region 210 can have a cross section taken along the second direction, which has a polygonal shape, such as a pentagonal shape, for example.

[0037] Referring to Figure 14 and Figure 15 , a first insulating interlayer 220 can be formed on the first spacer 142 and the second spacer 144 to cover the first gate structure 192 and the second gate structure 194, the third to seventh spacers 201, 202, 203, 204, and 205, and the second impurity region 210, and can be planarized until the upper surface of the second hard mask 134 is exposed.

[0038] In an implementation, the planarization process can be performed by a chemical mechanical polishing (CMP) process. As described above, the third height H3 of the upper surface of the first region I of the substrate 100 can be less than the fourth height H4 of the second region II of the substrate 100, and during the planarization process, the upper surface of the first gate structure 192 on the first region I of the substrate 100 can not be exposed.

[0039] In the planarization process, portions of the second gate structure 194 on the upper surface of the second hard mask 134 can also be removed.

[0040] The upper portion of the exposed second gate structure 194, the second hard mask 134, and the upper portion of the sixth spacer 204 can be removed, and a third recess 230 exposing the upper surface of the second semiconductor pattern 104 can be formed.

[0041] Referring to Figure 16 and Figure 17 Impurities can be implanted into the upper portion of the exposed second semiconductor pattern 104 by, for example, an ion implantation process to form a third impurity region 240. In an implementation, the third impurity region 240 can include impurities having the same conductivity type as the first impurity region 110.

[0042] In an implementation, referring to Figure 18 after the exposed upper portion of the second semiconductor pattern 104 is removed, a SEG process can be performed to form the third impurity region 240 using the second semiconductor pattern 104 as a seed. In this case, the third impurity region 240 can have a cross-section taken along the second direction having a shape like a polygon, such as a shape like a pentagon.

[0043] Referring to Figures 19 to 21 , a second insulating interlayer 250 can be formed on the first insulating interlayer 220, the third impurity region 240, the second gate structure 194, and the sixth and seventh spacers 204 and 205 to fill the third recess 230, a first contact plug 261 and a second contact plug 262 can be formed through the first and second insulating interlayers 220 and 250 on the first region I of the substrate 100, and a third to fifth contact plugs 264 to 266 can be formed through the second insulating interlayer 250 and / or the first insulating interlayer 220 on the second region II of the substrate 100.

[0044] The first contact plug 261 can contact an upper surface (e.g., a surface facing away from the substrate 100 in the third direction) of the first gate structure 192, the second contact plug 262 can contact an upper surface of the second impurity region 210, the third contact plug 264 can contact an upper surface of the second gate structure 194, the fourth contact plug 265 can contact an upper surface of the third impurity region 240, and the fifth contact plug 266 can contact an upper surface of the first impurity region 110 through the second spacer 144.

[0045] Each of the first to fifth contact plugs 261, 262, 264, 265, and 266 can include a metal, a metal nitride, a metal silicide, doped polysilicon, etc. A metal silicide pattern can be further formed between the first to third impurity regions 110, 210, and 240 and the fifth, second, and fourth contact plugs 266, 262, and 265, respectively.

[0046] The semiconductor device can be manufactured by the above processes. As described above, the first recess 120 can be formed on the first region I of the substrate 100 such that a third height H3 of an upper surface of the first region I of the substrate 100 on which the first semiconductor pattern 102 is not formed can be less than a fourth height H4 of an upper surface of the second region II of the substrate 100 on which the second semiconductor pattern 104 is not formed. In an implementation, to expose an upper portion of the second semiconductor pattern 104 on the second region II of the substrate 100 to form the third impurity region 240, a CMP process can be performed to remove an upper portion of the first insulating interlayer 220 instead of an etching process.

[0047] In an implementation, when the plurality of second semiconductor patterns 104 are formed, portions of the second gate structure 194 on the plurality of second semiconductor patterns 104, respectively, can be removed by a CMP process such that other portions can remain at a constant height and can be etched to a given thickness by an etching process to expose the upper portion of the second semiconductor pattern 104. In an implementation, a distribution (e.g., variation) of lengths of the second gate structure in the third direction around the sidewalls of the second semiconductor pattern 104 can be reduced (e.g., when compared to removing portions of the second gate structure on the second semiconductor pattern, respectively, by an etching process and then removing other portions of the second gate structure by another etching process).

[0048] By the above processes, a semiconductor device can be formed that includes fin-type field effect transistors (finFETs) and vertical channel field effect transistors (vFETs) on the first region I and the second region II of the substrate 100, respectively, and that can have the following structural features.

[0049] The first transistor can be formed on the first region I of the substrate 100, and can include a first semiconductor pattern 102 extending in the first direction and protruding upward in the third direction from an upper surface of the first region I of the substrate 100, a first gate structure 192 extending in the second direction to cover an upper surface and sidewalls in the second direction of the first semiconductor pattern 102, and a second impurity region 210 on respective portions of the first semiconductor pattern 102 at opposite sides of the first gate structure 192 in the first direction. The first semiconductor pattern 102 can function as a channel of the first transistor, and the second impurity region 210 can include impurities having the same conductivity type to respectively function as source / drain layers of the first transistor. Accordingly, the first transistor can be a finFET.

[0050] In an implementation, an upper surface of the second impurity region 210 can be lower (e.g., closer to the substrate 100 in the third direction) than an uppermost surface (e.g., a surface farthest from the substrate 100 in the third direction) of the first gate structure 192.

[0051] The second transistor can be formed on the second region II of the substrate 100, and can include a second semiconductor pattern 104 extending in the first direction and protruding upward in the third direction from an upper surface of the second region II of the substrate 100, a second gate structure 194 extending in the first direction to cover sidewalls of the second semiconductor pattern 104, a first impurity region 110 under the second semiconductor pattern 104 (at an upper portion of the second region II of the substrate 100), and a third impurity region 240 on the second semiconductor pattern 104. The second semiconductor pattern 104 can function as a channel of the second transistor, and the first impurity region 110 and the third impurity region 240 can include impurities having the same conductivity type to respectively function as source / drain layers of the second transistor. Accordingly, the second transistor can be a vFET.

[0052] In an implementation, a third height H3 of an upper surface of the first region I of the substrate 100 can be less than a fourth height H4 of an upper surface of the second region II of the substrate 100. In an implementation, an uppermost surface of the first gate structure 192 can be lower than an upper surface of the third impurity region 240.

[0053] In an implementation, the first gate structure 192 and the second gate structure 194 can be formed on the first spacer 142 and the second spacer 144, respectively.

[0054] In one implementation, the third spacers 201 can be formed on portions of the first gate structure 192 on opposite sidewalls of the first semiconductor pattern 102 along the second direction, the fourth spacers 202 can cover the sidewalls of the first gate structure 192, and the fifth spacers 203 can cover the sidewalls of the second impurity region 210. The sixth spacers 204 can be formed on corresponding portions of the second gate structure 194 on opposite sidewalls of the second semiconductor pattern 104 along the first direction, and the seventh spacers 205 can cover the sidewalls of the second gate structure 194.

[0055] In one implementation, the first gate structure 192 can include the first interface pattern 162, the first gate insulating pattern 172, and the first gate electrode 182 stacked in this order on a surface of the first semiconductor pattern 102 and an upper surface of the first spacer 142, and the second gate structure 194 can include the second interface pattern 164, the second gate insulating pattern 174, and the second gate electrode 184 stacked in this order on a sidewall of the second semiconductor pattern 104 and an upper surface of the second spacer 144.

[0056] In one implementation, the first contact plug 261 can be electrically connected to the first gate structure 192, and the second contact plug 262 can be electrically connected to the second impurity region 210, respectively. The third contact plug 264 can be electrically connected to the second gate structure 194, the fourth contact plug 265 can be electrically connected to the third impurity region 240, and the fifth contact plug 266 can be electrically connected to the first impurity region 110.

[0057] Figures 22 to 31 are cross-sectional views of a plurality of stages in a method of manufacturing a semiconductor device according to example implementations. Specifically, Figure 22 、 Figure 24 、 Figure 26 、 Figure 28 and Figure 30 are cross-sectional views taken along lines A-A' of the respective plan views, Figure 23 、 Figure 25 、 Figure 27 、 Figure 29 and Figure 31 are cross-sectional views taken along lines B-B' and C-C' of the respective plan views, respectively.

[0058] This method can include processes substantially the same as or similar to those shown with reference to Figures 1 to 21 , and thus repetitive description thereof can be omitted here.

[0059] With reference to Figure 22 and Figure 23 , the processes performed with reference to Figures 1 to 6After substantially the same or similar processes as those shown, dummy gate structure layers can be formed on the first and second spacers 142 and 144, the first and second semiconductor patterns 102 and 104, and the second hard mask 134, and can be patterned to form first and second dummy gate structures 342 and 344 on the first and second regions I and II of the substrate 100, respectively.

[0060] The first and second dummy gate structures 342 and 344 can have uppermost surfaces substantially coplanar with each other in the third direction (e.g., substantially the same distance from the substrate 100 in the third direction), which can be different from the conformally formed first and second gate structures 192 and 194 as shown with reference to Figure 8 and Figure 9 In an implementation, the first and second dummy gate structures 342 and 344 can have the same layout as the first and second gate structures 192 and 194.

[0061] The first dummy gate structure 342 can include a first dummy gate insulating pattern 312, a first dummy gate electrode 322, and a first dummy gate mask 332 stacked in the third direction in that order, and the second dummy gate structure 344 can include a second dummy gate insulating pattern 314, a second dummy gate electrode 324, and a second dummy gate mask 334 stacked in the third direction in that order.

[0062] Each of the first and second dummy gate insulating patterns 312 and 314 can include an oxide such as silicon oxide, each of the first and second dummy gate electrodes 322 and 324 can include, for example, polysilicon, and the first and second dummy gate masks 332 and 334 can include a nitride such as silicon nitride.

[0063] Referring to Figure 24 and Figure 25 substantially the same or similar processes as those shown with reference to Figures 11 to 13 may be performed.

[0064] In an implementation, a fourth spacer 202 can be formed on sidewalls of the first dummy gate structure 342, a fifth spacer 203 can be formed on sidewalls of a portion of the first semiconductor pattern 102 not covered by the first dummy gate structure 342, and a seventh spacer 205 can be formed on sidewalls of the second dummy gate structure 344.

[0065] In an implementation, unlike the first and second gate structures 192 and 194, the first and second dummy gate structures 342 and 344 can be formed non-conformally, so that the portions of the first and second dummy gate structures 342 and 344 on the first and second semiconductor patterns 102 and 104 and on the first and second spacers 142 and 144 can not have height differences, so that the third and sixth spacers 201 and 204 can not be formed.

[0066] The portion of the first semiconductor pattern 102 not covered by the first dummy gate structure 342 and the fourth spacer 202 can be etched to form a second recess, and an SEG process can be performed using the portion of the first semiconductor pattern 102 exposed by the second recess as a seed to form a second impurity region 210 in the second recess.

[0067] Referring to Figure 26 and Figure 27 , a first insulating interlayer 220 can be formed on the first and second spacers 142 and 144 to cover the first and second dummy gate structures 342 and 344, the fourth, fifth, and seventh spacers 202, 203, and 205, and the second impurity region 210, and can be planarized until the upper surfaces of the first and second dummy gate masks 332 and 334 are exposed.

[0068] The exposed first and second dummy gate masks 332 and 334 and the first and second dummy gate electrodes 322 and 324 and the first and second dummy gate insulating patterns 312 and 314 thereunder can be removed to form a fourth recess exposing the upper surface and sidewalls of the first semiconductor pattern 102, the upper surface of the first spacer 142, and the inner sidewall of the fourth spacer 202 on the first region I of the substrate 100 and a fifth recess exposing the upper surface and sidewalls of the second hard mask 134, the sidewall of the second semiconductor pattern 104, the upper surface of the second spacer 144, and the inner sidewall of the seventh spacer 205 on the second region II of the substrate 100.

[0069] Third and fourth interface patterns 352 and 354 can be formed on the upper surfaces and sidewalls of the first and second semiconductor patterns 102 and 104 exposed by the fourth and fifth recesses, respectively, a gate insulating layer and a work function control layer can be sequentially stacked on the surfaces of the third and fourth interface patterns 352 and 354, the upper surface and sidewalls of the second hard mask 134, the upper surfaces of the first and second spacers 142 and 144, and the inner sidewalls of the fourth and seventh spacers 202 and 205, and a gate electrode layer can be formed on the work function control layer to fill the fourth and fifth recesses.

[0070] The gate electrode layer, the work function control layer, and the gate insulating layer can be planarized until an upper surface of the first insulating interlayer 220 is exposed to form a third gate structure 392 in the fourth recess on the first region I of the substrate 100 and a fourth gate structure 394 in the fifth recess on the second region II of the substrate 100. The third gate structure 392 can include the third interface pattern 352, the third gate insulating pattern 362, the first work function control pattern 372, and the third gate electrode 382, and the fourth gate structure 394 can include the fourth interface pattern 354, the fourth gate insulating pattern 364, the second work function control pattern 374, and the fourth gate electrode 384.

[0071] Each of the first work function control pattern 372 and the second work function control pattern 374 can include, for example, a metal, a metal nitride, a metal silicide, a metal alloy, etc.

[0072] Referring to Figure 28 and Figure 29 substantially the same or similar processes as those shown in Referring to Figure 14 and Figure 15 substantially the same or similar processes as those shown in Referring to

[0073] In an implementation, the first insulating interlayer 220 can be planarized until an upper surface of the second hard mask 134 is exposed, and during the planarization process, a portion of the fourth gate structure 394 on the upper surface of the second hard mask 134 can be removed on the second region II of the substrate 100, and a portion of the third gate structure 392 having a thickness corresponding to the removed portion of the fourth gate structure 394 can be removed on the first region I of the substrate 100. In an implementation, the planarization process can be performed by a CMP process.

[0074] An upper portion of the fourth gate structure 394, the second hard mask 134, and an upper portion of the seventh spacer 205 can be removed by an etching process, and thus a seventh recess 234 can be formed to expose an upper portion of the second semiconductor pattern 104. During the etching process, an upper portion of the third gate structure 392 and an upper portion of the fourth spacer 202 can also be removed to form a sixth recess 232.

[0075] In one implementation, after the CMP process for exposing the upper surface of the second hard mask 134, a process for forming a seventh recess 234 on the second region II of the substrate 100 to expose the upper portion of the second semiconductor pattern 104 can be performed only once, simultaneously with the process for forming a sixth recess 232 on the first region I of the substrate 100. This is feasible because the third height H3 of the upper surface of the first region I of the substrate 100 is less than the fourth height H4 of the second region II of the substrate 100. If the third height H3 of the upper surface of the first region I of the substrate 100 is equal to the fourth height H4 of the second region II of the substrate 100, the etching process for the fourth gate structure 394 will be performed twice to expose the upper portion of the second semiconductor pattern 104 on the second region II of the substrate 100, which may result in a distribution of the length of the fourth gate structure 394 covering the second semiconductor pattern 104 in the third direction. Only when an additional etching mask is used can the etching process for exposing the upper portion of the second semiconductor pattern 104 on the second region II of the substrate 100 be performed only once.

[0076] In one implementation, the upper surface of the first region I of the substrate 100 may be lower than the upper surface of the second region II of the substrate 100. Therefore, after performing CMP on the third gate structure 392 and the fourth gate structure 394 until the upper surface of the second hard mask 134 is exposed, an etching process can be performed on the third gate structure 392 and the fourth gate structure 394 together, so that the upper part of the second semiconductor pattern 104 on the second region II of the substrate 100 can be exposed.

[0077] Reference Figure 30 and Figure 31 It can be executed and referenced. Figures 16 to 21 The processes shown are essentially the same or similar processes for manufacturing semiconductor devices.

[0078] The first contact plug 261 can contact the upper surface of the third gate structure 392, and the second contact plug 262 can contact the upper surface of the second impurity region 210. The third contact plug 264 can contact the upper surface of the fourth gate structure 394, the fourth contact plug 265 can contact the upper surface of the third impurity region 240, and the fifth contact plug 266 can pass through the second spacer 144 to contact the upper surface of the first impurity region 110.

[0079] Semiconductor devices can be similar to Figures 19 to 21 Semiconductor devices, and may have the following additional features.

[0080] In an implementation, the third gate structure 392 can include the third interface pattern 352 on the surface of the first semiconductor pattern 102, and the third gate insulating pattern 362, the first work function control pattern 372, and the third gate electrode 382 stacked in sequence from the third interface pattern 352, the upper surface of the first spacer 142, and the inner sidewall of the fourth spacer 202. The fourth gate structure 394 can include the fourth interface pattern 354 on the surface of the second semiconductor pattern 104, and the fourth gate insulating pattern 364, the second work function control pattern 374, and the fourth gate electrode 384 stacked in sequence from the fourth interface pattern 354, the upper surface of the second spacer 144, and the inner sidewall of the seventh spacer 205.

[0081] Figures 32 to 45 are plan views and sectional views of a plurality of stages in a method of manufacturing a semiconductor device according to example embodiments. Figure 33 、 Figure 36 and Figure 39 are plan views, Figure 32 、 Figure 34 、 Figure 37 、 Figure 40 、 Figure 42 and Figure 44 are sectional views taken along lines A-A' of the respective plan views, Figure 35 、 Figure 38 、 Figure 41 、 Figure 43 and Figure 45 are sectional views taken along lines B-B' and C-C' of the respective plan views.

[0082] The method can include substantially the same or similar processes to those shown with reference to Figures 1 to 21 or Figures 22 to 31 , and thus repeated description thereof can be omitted here.

[0083] With reference to Figure 32 , the substrate 100 including the second region II and the third region III can be subjected to substantially the same or similar processes to those shown with reference to Figure 1 and Figure 2 .

[0084] In an implementation, after the first impurity region 110 is formed at a portion of the second region II of the substrate 100, an upper portion of the third region III of the substrate 100 can be removed to form an eighth recess. When the eighth recess is formed on the third region III of the substrate 100, a fifth height of an upper surface of the third region III of the substrate 100 can be less than the second height H2 of the upper surface of the second region II of the substrate 100.

[0085] The second sacrificial layer 410 and the semiconductor layer 420 can be stacked alternately and repeatedly on the second region II and the third region III of the substrate 100.

[0086] In one implementation, the second sacrificial layer 410 and the semiconductor layer 420 can be formed using a SEG process that uses the upper part of the substrate 100 as a seed. In another implementation, the second sacrificial layer 410 can be formed using a SEG process employing a silicon source gas (e.g., dichlorosilane (SiH2Cl2) gas) or a germanium source gas (e.g., germanane (GeH4) gas), thus forming a single-crystal silicon-germanium layer. In yet another implementation, the semiconductor layer 420 can be formed using a SEG process employing a silicon source gas (e.g., dichlorosilane (Si2H6) gas), thus forming a single-crystal silicon layer.

[0087] Reference Figures 33 to 35 The second sacrificial layer 410 and semiconductor layer 420, which are alternately and repeatedly stacked on the second region II of the substrate 100, can be removed to expose the upper surface of the second region II of the substrate 100, and can be performed in accordance with reference to Figures 3 to 5 The processes shown are essentially the same or similar.

[0088] In one implementation, the second hard mask 134 and the third hard mask 136 may be formed on the exposed upper surface of the second region II of the substrate 100 and on the uppermost surface of the semiconductor layer 420 on the third region III of the substrate 100, respectively. The upper part of the second region II of the substrate 100 and the second sacrificial layer 410 and semiconductor layer 420, which are alternately and repeatedly stacked on the upper part of the third region III of the substrate 100, may be etched using the second hard mask 134 and the third hard mask 136 as etching masks, respectively.

[0089] In one implementation, a second semiconductor pattern 104 may be formed on a second region II of the substrate 100 to protrude upward therefrom (e.g., upward in a third region), and a second hard mask 134 may be formed on the second semiconductor pattern 104. A third semiconductor pattern 106, along with a second sacrificial pattern 412 and a fourth semiconductor pattern 422 alternately and repeatedly stacked on the third semiconductor pattern 106, may be formed on a third region III of the substrate 100, and a third hard mask 136 may be formed on the uppermost of the fourth semiconductor patterns 422.

[0090] When the second semiconductor pattern 104 and the third semiconductor pattern 106 are formed, the upper surfaces of the second region III and the third region III of the substrate 100 (on which the second semiconductor pattern 104 and the third semiconductor pattern 106 are not formed, respectively) may have a fourth height H4 and a sixth height H6, respectively, and the sixth height H6 may be smaller than the fourth height H4.

[0091] Referring to Figures 36 to 39 , substantially the same or similar processes to those shown in Figure 22 and Figure 23 may be performed.

[0092] In an implementation, the second dummy gate structure 344 and the third dummy gate structure 346 can be formed on the second region II and the third region III of the substrate 100, and the second spacer 144 and the eighth spacer 146 can be formed to cover lower sidewalls of the second dummy gate structure 344 and the third dummy gate structure 346, respectively.

[0093] The third dummy gate structure 346 can include a third dummy gate insulating pattern 316, a third dummy gate electrode 326, and a third dummy gate mask 336 stacked in the third direction in that order.

[0094] Referring to Figures 39 to 41 , substantially the same or similar processes to those shown in Figure 24 and Figure 25 may be performed, such that the seventh spacer 205 can be formed on sidewalls of the second dummy gate structure 344, the ninth spacer 207 can be formed on sidewalls of the third dummy gate structure 346, and the tenth spacer 208 can be formed on sidewalls of the third semiconductor pattern 106.

[0095] A portion of the third semiconductor pattern 106 that is not covered by the third dummy gate structure 346 and the tenth spacer 208 can be etched to form a ninth recess, a laterally exposed portion of each of the second sacrificial patterns 412 exposed by the ninth recess can be removed to form a gap, and an eleventh spacer 430 can be formed in the gap.

[0096] The eleventh spacer 430 can have a concave shape at a central portion in the third direction. In an implementation, the eleventh spacer 430 can have a cross-section taken along the first direction, the cross-section having a horseshoe shape or a semi-circular shape with concave sidewalls. In an implementation, the eleventh spacer 430 can have a rectangular shape with concave sidewalls and rounded corners. The eleventh spacer 430 can include nitride, such as silicon nitride.

[0097] An SEG process can be performed using the portion of the third semiconductor pattern 106 exposed by the ninth recess and sidewalls of the fourth semiconductor pattern 422 exposed by the ninth recess as seeds to form a fourth impurity region 215 in the ninth recess.

[0098] Referring to Figure 42 and Figure 43 , substantially the same or similar processes to those shown in Figure 26 andFigure 27 substantially the same or similar processes as those shown.

[0099] In one implementation, a first insulating interlayer 220 can be formed on the second spacer 144 and the eighth spacer 146 to cover the second and third gate structures 344 and 346, the seventh, ninth and tenth spacers 205, 207 and 208, and the fourth impurity region 215, and can be planarized until the upper surfaces of the second dummy gate mask 334 and the third dummy gate mask 336 are exposed.

[0100] The exposed second dummy gate mask 334 and the second dummy gate electrode 324 and the second dummy gate insulating pattern 314 thereunder can be removed to form a tenth recess exposing the upper surface and the sidewall of the second hard mask 134, the sidewall of the second semiconductor pattern 104, the upper surface of the second spacer 144 and the inner sidewall of the seventh spacer 205. In one implementation, the exposed third dummy gate mask 336 and the third dummy gate electrode 326, the third dummy gate insulating pattern 316 and the second sacrificial pattern 412 thereunder can be removed to form an eleventh recess exposing the upper surface and the sidewall of the third semiconductor pattern 106, the upper surface of the eighth spacer 146 and the inner sidewall of the ninth spacer 207.

[0101] A fourth interface pattern 354 can be formed on the upper surface and the sidewall of the second semiconductor pattern 104 exposed by the tenth recess, and a fifth interface pattern 356 can be formed on the upper surface and the sidewall of the third semiconductor pattern 106 exposed by the eleventh recess. A gate insulating layer, a work function control layer and a gate electrode layer can be sequentially formed in the tenth recess and the eleventh recess.

[0102] The gate electrode layer, the work function control layer and the gate insulating layer can be planarized until the upper surface of the first insulating interlayer 220 is exposed to form a fourth gate structure 394 in the tenth recess on the second region II of the substrate 100 and a fifth gate structure 396 in the eleventh recess on the third region III of the substrate 100. The fifth gate structure 396 can include the fifth interface pattern 356, a fifth gate insulating pattern 366, a third work function control pattern 376 and a fifth gate electrode 386.

[0103] Referring to Figure 44 Figure 45 substantially the same or similar processes as those shown in FIGS. 1A to 1H can be performed to complete the fabrication of the semiconductor device. Figures 28 to 31

[0104] ​​In an implementation, the third to fifth contact plugs 264, 265, and 266 can be formed on the second region II of the substrate 100, and the sixth contact plug 267 can be formed through the first insulating interlayer 220 and the second insulating interlayer 250 to contact the upper surface of the fourth impurity region 215 on the third region III of the substrate 100.

[0105] Through the above processes, a vFET and a multi-bridge channel field effect transistor (MBCFET) can be formed on the second region II and the third region III of the substrate 100, respectively, and the semiconductor device can have the following structural features.

[0106] In an implementation, the second transistor can be formed on the second region II of the substrate 100 and can include the fourth gate structure 394, the second semiconductor pattern 104 serving as a channel, and the first impurity region 110 and the third impurity region 240 serving as source / drain layers, respectively.

[0107] In an implementation, the third transistor can be formed on the third region III of the substrate 100 and can include the third semiconductor pattern 106 extending in the first direction (e.g., longitudinally) and protruding upward in the third direction from the upper surface of the third region III of the substrate 100, the fifth gate structure 396 extending on the third semiconductor pattern 106 in the second direction, the fourth semiconductor pattern 422 spaced apart from each other in the third direction, each fourth semiconductor pattern 422 can extend in the first direction through the fifth gate structure 396, and the fourth impurity region 215 on the respective portions of the third semiconductor pattern 106 at opposite sides of the fifth gate structure 396 in the first direction.

[0108] Each fourth semiconductor pattern 422 can serve as a channel of the third transistor, and the fourth impurity region 215 can include impurities having the same conductivity type and serve as source / drain layers, respectively. In an implementation, the third transistor can be a MBCFET.

[0109] In an implementation, the upper surface of the third region III of the substrate 100 can be lower than the upper surface of the second region II of the substrate 100. In an implementation, the upper surface of the fifth gate structure 396 can be substantially coplanar with the upper surface of the fourth gate structure 394.

[0110] In an implementation, the fourth gate structure 394 and the fifth gate structure 396 can be formed on the second spacer 144 and the eighth spacer 146, respectively.

[0111] In an implementation, a ninth spacer 207 covering a portion of the sidewall of the fifth gate structure 396 and a tenth spacer 208 covering the sidewall of the fourth impurity region 215 can be formed on the third region III of the substrate 100. In an implementation, an eleventh spacer 430 can be further formed between the fourth semiconductor patterns 422 and between the third semiconductor pattern 106 and the fourth semiconductor pattern 422 on the third region III of the substrate 100. The eleventh spacer 430 can be formed between the fifth gate structure 396 and each of the fourth impurity regions 215.

[0112] In an implementation, the fifth gate structure 396 can include a fifth interface pattern 356 on the surface of the third semiconductor pattern 106 and the surface of each of the fourth semiconductor patterns 422 and a fifth gate insulating pattern 366, a third work function control pattern 376, and a fifth gate electrode 386 stacked in sequence from the surface of the fifth interface pattern 356, the upper surface of the eighth spacer 146, and the inner sidewalls of the ninth spacer 207 and the eleventh spacer 430.

[0113] Figure 46 is a cross-sectional view of a semiconductor device according to an example implementation.

[0114] This semiconductor device can include a finFET, a vFET, and a MBCFET on the first to third regions I, II, and III of the substrate 100, respectively. The finFET and the vFET can be substantially the same as or similar to those of Figure 30 and Figure 31 The MBCFET can be substantially the same as or similar to those of Figure 44 and Figure 45 .

[0115] The third height H3 of the upper surface of the first region I of the substrate 100 can be less than the fourth height H4 of the upper surface of the second region II of the substrate 100, and the sixth height H6 of the upper surface of the third region III of the substrate 100 can be less than the third height H3 of the upper surface of the first region I of the substrate 100. In an implementation, the thickness of the first region I of the substrate 100 in the third direction (e.g., corresponding to H3) can be less than the thickness of the second region II of the substrate 100 in the third direction (e.g., corresponding to H4). In an implementation, the thickness of the third region III of the substrate 100 in the third direction (e.g., corresponding to H6) can be less than the thickness of the first region I of the substrate 100 in the third direction (e.g., corresponding to H3).

[0116] By summarizing and reviewing, when the vFET includes multiple gates, the gates can be etched by performing two etching processes, which can result in a distribution (variation) of the length of the gates in the vertical direction.

[0117] One or more embodiments can provide a semiconductor device including both a finFET and a vFET.

[0118] One or more embodiments can provide a semiconductor device having good characteristics.

[0119] The semiconductor device can include a finFET and / or an MBCFET as well as a vFET, and a gate structure of the vFET can have a small distribution or variation in length in a vertical direction, thereby having improved electrical characteristics.

[0120] Example embodiments have been disclosed herein and, although the use of certain terms can imply a certain terminology, these are used herein only in a generic and descriptive sense and not for limitation purposes. In some instances, features, characteristics, and / or elements described in association with a particular embodiment can be used singularly, in combination with or in isolation, unless otherwise specifically stated as such, or to the context suggests otherwise. Thus, one of ordinary skill in the art would understand that various changes can be made to the form and details of the application described without departing from the spirit and scope of the application as set forth in the following claims.

[0121] Korean Patent Application No. 10-2019-0169763, filed on December 18, 2019, in the Korean Intellectual Property Office and entitled "Semiconductor Device," is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device comprising: a substrate including a first region and a second region, a first transistor over the first region of the substrate, the first transistor including: a first semiconductor pattern protruding in a vertical direction from an upper surface of the first region of the substrate; a first gate structure covering an upper surface and a sidewall of the first semiconductor pattern; and a first source / drain layer on respective portions of the first semiconductor pattern at opposite sides of the first gate structure, an upper surface of the first source / drain layer being closer to the substrate in the vertical direction than an uppermost surface of the first gate structure is to the substrate; and a second transistor over the second region of the substrate, the second transistor including: a second semiconductor pattern protruding in the vertical direction from an upper surface of the second region of the substrate; a second gate structure covering a sidewall of the second semiconductor pattern; a second source / drain layer at an upper portion of the second region of the substrate and under the second semiconductor pattern; and a third source / drain layer over the second semiconductor pattern, wherein the upper surface of the first region of the substrate is lower than the upper surface of the second region of the substrate.

2. The semiconductor device according to claim 1, wherein the uppermost surface of the first gate structure is closer to the substrate in the vertical direction than an upper surface of the third source / drain layer is to the substrate.

3. The semiconductor device according to claim 1, wherein each of the first semiconductor pattern and the second semiconductor pattern includes a material that is the same as a material of the substrate.

4. The semiconductor device according to claim 1, further comprising a first spacer over the first region of the substrate and a second spacer over the second region of the substrate, wherein the first gate structure is over the first spacer and the second gate structure is over the second spacer.

5. The semiconductor device according to claim 4, further comprising: a third spacer covering a sidewall of the first gate structure; a fourth spacer covering a sidewall of the first source / drain layer; and a fifth spacer covering a sidewall of the second gate structure, wherein the third spacer and the fourth spacer are over the first spacer and the fifth spacer is over the second spacer.

6. The semiconductor device according to claim 5, wherein: the first gate structure extends longitudinally in a second direction parallel to an upper surface of the substrate, the first source / drain layer respectively at opposite sides of the first gate structure in a first direction parallel to the upper surface of the substrate and crossing the second direction, the second gate structure extends longitudinally in the first direction and covers the sidewall of the second semiconductor pattern, and the semiconductor device further comprises: a sixth spacer over respective portions of the first gate structure at opposite sides of the first semiconductor pattern along the second direction. ​ a seventh spacer on respective portions of the second gate structure at opposite sides of the second semiconductor pattern in the first direction.

7. The semiconductor device according to claim 6, wherein: the first gate structure includes a first interface pattern, a first gate insulating pattern, and a first gate electrode, which are stacked in order from a surface of the first semiconductor pattern and an upper surface of the first spacer, and the second gate structure includes a second interface pattern, a second gate insulating pattern, and a second gate electrode, which are stacked in order from a sidewall of the second semiconductor pattern and an upper surface of the second spacer.

8. The semiconductor device according to claim 5, wherein: the first gate structure includes a first interface pattern on a surface of the first semiconductor pattern, and a first gate insulating pattern, a first work function control pattern, and a first gate electrode, which are stacked in order from a surface of the first interface pattern, an upper surface of the first spacer, and an inner sidewall of the third spacer, and the second gate structure includes a second interface pattern on a surface of the second semiconductor pattern, and a second gate insulating pattern, a second work function control pattern, and a second gate electrode, which are stacked in order from a surface of the second interface pattern, an upper surface of the second spacer, and an inner sidewall of the fifth spacer.

9. The semiconductor device according to claim 1, further comprising: a first contact plug electrically connected to the first gate structure; second contact plugs respectively electrically connected to the first source / drain layers; a third contact plug electrically connected to the second gate structure; a fourth contact plug electrically connected to the third source / drain layers; and a fifth contact plug electrically connected to the second source / drain layers.

10. The semiconductor device according to claim 1, wherein: the first source / drain layers include impurities having the same conductivity type, the second source / drain layers and the third source / drain layers include impurities having the same conductivity type, the first transistor is a fin-type field effect transistor, and the second transistor is a vertical channel field effect transistor.

11. A semiconductor device comprising: a substrate including a first region and a second region; a first transistor on the first region of the substrate, the first transistor including: a first semiconductor pattern protruding in a vertical direction from an upper surface of the first region of the substrate and extending longitudinally in a first direction parallel to the upper surface of the substrate; a first gate structure on the first semiconductor pattern, the first gate structure extending longitudinally in a second direction parallel to the upper surface of the substrate and intersecting the first direction; second semiconductor patterns spaced apart from each other in the vertical direction, each of the second semiconductor patterns extending longitudinally in the first direction across the first gate structure; and first source / drain layers on respective portions of the first semiconductor pattern at opposite sides of the first gate structure in the first direction; and a second transistor on the second region of the substrate, the second transistor including: a second semiconductor pattern protruding in the vertical direction from an upper surface of the second region of the substrate and extending longitudinally in the first direction, and a second gate structure on the second semiconductor pattern, the second gate structure extending longitudinally in the second direction. a third semiconductor pattern protruding from an upper surface of the second region of the substrate in the vertical direction; a second gate structure covering a sidewall of the third semiconductor pattern; a second source / drain layer on an upper portion of the second region of the substrate and under the third semiconductor pattern; and a third source / drain layer on the third semiconductor pattern, wherein the upper surface of the first region of the substrate is lower than the upper surface of the second region of the substrate.

12. The semiconductor device of claim 11, wherein an upper surface of the first gate structure is coplanar with an upper surface of the second gate structure.

13. The semiconductor device of claim 11, wherein each of the first semiconductor pattern and the second semiconductor pattern comprises a material that is the same as a material of the substrate.

14. The semiconductor device of claim 11, further comprising a first spacer on the first region of the substrate and a second spacer on the second region of the substrate, wherein the first gate structure is on the first spacer and the second gate structure is on the second spacer.

15. The semiconductor device of claim 14, further comprising: a third spacer covering a sidewall of the first gate structure; a fourth spacer covering a sidewall of the first source / drain layer; and a fifth spacer covering a sidewall of the second gate structure, wherein the third spacer and the fourth spacer are on the first spacer and the fifth spacer is on the second spacer.

16. The semiconductor device of claim 15, further comprising a sixth spacer between the second semiconductor patterns and between the first semiconductor pattern and the second semiconductor pattern, the sixth spacer being between the first gate structure and each of the first source / drain layers.

17. The semiconductor device of claim 16, wherein: the first gate structure comprises a first interface pattern on a surface of the first semiconductor pattern and a surface of each of the second semiconductor patterns and a first gate insulating pattern, a first work function control pattern, and a first gate electrode stacked in order from a surface of the first interface pattern, an upper surface of the first spacer, and an inner sidewall of the third spacer and an inner sidewall of the sixth spacer, and the second gate structure comprises a second interface pattern on a surface of the third semiconductor pattern and a second gate insulating pattern, a second work function control pattern, and a second gate electrode stacked in order from a surface of the second interface pattern, an upper surface of the second spacer, and an inner sidewall of the fifth spacer.

18. The semiconductor device of claim 11, wherein: the first source / drain layer comprises impurities of a same conductivity type, the second source / drain layer and the third source / drain layer comprise impurities of a same conductivity type, the first transistor is a multi-bridge channel field effect transistor, and the second transistor is a vertical channel field effect transistor.

19. A semiconductor device, comprising: ​ A substrate including a first region, a second region, and a third region; A first transistor over the first region of the substrate, the first transistor including: a first semiconductor pattern protruding in a vertical direction from an upper surface of the first region of the substrate and extending longitudinally in a first direction parallel to the upper surface of the substrate; a first gate structure covering an upper surface and sidewalls of the first semiconductor pattern in a second direction parallel to the upper surface of the substrate and intersecting the first direction; and a first source / drain layer on respective portions of the first semiconductor pattern at opposite sides of the first gate structure in the first direction; A second transistor over the second region of the substrate, the second transistor including: a second semiconductor pattern protruding in the vertical direction from an upper surface of the second region of the substrate and extending longitudinally in the first direction; a second gate structure surrounding sidewalls of the second semiconductor pattern; a second source / drain layer on an upper portion of the second region of the substrate and under the second semiconductor pattern; and a third source / drain layer over the second semiconductor pattern; and A third transistor over the third region of the substrate, the third transistor including: a third semiconductor pattern protruding in the vertical direction from an upper surface of the third region of the substrate and extending longitudinally in the first direction; a third gate structure over the third semiconductor pattern; fourth semiconductor patterns spaced apart from each other in the vertical direction, each of the fourth semiconductor patterns extending longitudinally in the first direction across the third gate structure; and a fourth source / drain layer on respective portions of the third semiconductor pattern at opposite sides of the third gate structure in the first direction, wherein: the upper surface of the first region of the substrate is lower than the upper surface of the second region of the substrate, and the upper surface of the third region of the substrate is lower than the upper surface of the first region of the substrate.

20. The semiconductor device according to claim 19, wherein: the first source / drain layer includes impurities of the same conductivity type, the second source / drain layer and the third source / drain layer include impurities of the same conductivity type, the fourth source / drain layer includes impurities of the same conductivity type, the first transistor is a fin-type field-effect transistor, the second transistor is a vertical channel field-effect transistor, and the third transistor is a multi-bridge-channel field-effect transistor.

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