Secondary controlled ac-dc converter and method for low frequency operation

Abstract

A secondary controlled AC-DC converter and method for low frequency operation are disclosed. A secondary controlled AC-DC converter including an oscillator in a primary side controller (PSC) and a method for operating it to enable soft start and low frequency operation are provided. Generally, the method includes driving a power switch coupled between an AC input and a primary side of the converter with a gate drive (GD) signal. At start up and after an automatic restart, the GD signal is generated using an oscillator signal from the oscillator. After receiving a start-stop pulse from a secondary side controller, the oscillator signal is decoupled from the GD signal using a controller in the PSC and the PSC begins generating the GD signal with a pulse width modulation (PWM) generated using the start-stop pulse. The oscillator operates at a first frequency independent of the PWM signal. The PWM signal includes one of a plurality of frequencies selected based on power drawn from the converter and can be less than the first frequency in low power applications.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority benefit under 35 U.S.C. 119(e) of U.S. Provisional Patent Application Serial No. 62 / 950,430, filed December 19, 2019, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates generally to AC-DC converters, and more particularly to secondary side controlled AC-DC converters including a primary side oscillator and methods for operating the same to achieve low frequency operation. BACKGROUND

[0004] AC-DC converters convert power from an alternating current (AC) source to direct current (DC) at a specified voltage level. For a given size and weight, AC-DC converters using secondary side control can deliver power more efficiently, and thus are widely used in portable electronic devices. Typically, an AC-DC converter transfers power from an AC input connected or coupled to a primary side of a transformer to a DC output coupled to a secondary side of the transformer.

[0005] A simplified schematic block diagram of one such AC-DC converter including a synchronous rectifier (SR) sensing architecture is shown in Figure 1 Referring to Figure 1 , an AC-DC converter 100 generally includes a rectification circuit, e.g., a bridge rectifier 101, coupled to a transformer 102 to rectify an AC input voltage, an active rectification element or power switch (PS), e.g., a PS field effect transistor (PS_FET 104) on the primary side of the transformer, a synchronous rectifier (SR), e.g., a SR field effect transistor (SR_FET 106) on the secondary side of the transformer, and an output filter or capacitor 108. In operation, the PS_FET 104 switches power to the primary side on or off in response to a signal from a primary side controller 110. In a secondary side controlled converter, a secondary side controller 112 coupled to a drain node (SR_DRAIN 114) and gate of the SR_FET 106 senses a voltage on the SR_DRAIN and turns the SR_FET on and off in response to a sensed voltage peak and negative and zero crossing points.

[0006] During regular operation after start-up, the AC-DC converter 100 is considered to operate in flyback mode and a magnetic field is established in the transformer 102 while the current on the primary side increases linearly. When the PS_FET 104 is off or open and the SR_FET 106 is on or closed, the AC-DC converter 100 transfers power to the secondary side where the magnetic field starts to decay and the secondary side current steadily decreases, but gradually, as power is supplied to the capacitor 108 connected to the output, until a point is reached where essentially zero current is flowing in the secondary. When operating in flyback mode, the primary side controller 110 receives modulated pulses or signals from the secondary side controller 112 through the PWM transformer 116 to drive the PS_FET 104 using pulse width modulation (PWM). This feedback enables the frequency and / or duration of the pulses used to drive the PS_FET 104 to be determined by the secondary side controller 112 based on the power drawn from the secondary side.

[0007] During power-up of the AC-DC converter 100, the primary side controller 110 receives power directly from the bridge through the VDD pin 118, the secondary side controller 112, which receives power from the secondary side of the transformer 102, has not yet been powered up and therefore cannot generate signals or pulses to drive the PS_FET 104 to enable power to be transferred to the secondary side of the transformer 102. Referring to Figure 2 To address this problem, previous generations of flyback AC-DC converters 100 included a dedicated primary side or gate drive (GD) oscillator 120 and other pulse generating circuitry in the primary side controller 110 for the sole purpose of generating signals or pulses 202 to drive the PS_FET 104 at a predetermined fixed frequency and pulse duration during a soft start 204 period or mode of operation. The soft start 204 period lasts until the secondary side controller 112 is powered up and starts generating modulated pulses 206, the secondary side controller 112 and the primary side controller 110 being coupled through the PWM transformer 116. As indicated by arrow 208, the circuitry in the primary side controller 110 synchronizes the pulses 202 from the primary side oscillator 120 with the pulses 206 received from the secondary side controller 112 and generates a gate driver output 210 to drive the PS_FET 104.

[0008] One problem with the above architecture arises when the frequency of the pulses 206 received from the secondary side controller 112 is lower than the fixed frequency of the primary side oscillator 120 due to low demand for power on the secondary side as indicated by the ellipse 212. This can occur, for example, when the AC-DC converter 100 is in a standby mode. Note that in a conventional flyback AC-DC converter 100, the gate driver output 210 always follows the pulses 202 from the primary side oscillator 120. Thus, the AC-DC converter 100 will operate with the gate driver output 210 at a higher frequency and lower efficiency than required.

[0009] Another problem with the above architecture is that the GD oscillator 120 is dedicated only for the purpose of generating the signal or pulses 202 to drive the PS_FET 104, and the primary side controller 110 must also include a separate oscillator or clock / oscillator 122 for generating a clock signal at a fixed frequency to operate the logic elements in the primary side controller.

[0010] Thus, there is a need for an AC-DC converter that can operate efficiently in flyback mode at a lower frequency that is not limited by the predetermined frequency of a dedicated oscillator in the primary controller. There is also a need for an AC-DC converter that does not require a dedicated primary side oscillator for soft start operation. SUMMARY

[0011] A secondary controlled AC-DC converter with a standalone oscillator in the primary side controller (PSC) and a method for operating it to achieve soft start and low frequency operation to improve efficiency are provided. Typically, the oscillator signal from the oscillator is also used as a clock signal to operate the controller in the PSC, thereby reducing the cost, complexity and size of the converter while further improving the efficiency.

[0012] In one embodiment, the method includes driving a power switch (PS) coupled between an AC input and a primary side of the converter with a gate drive (GD) signal. At start up and after an automatic restart, the GD signal is generated using an oscillator signal from an oscillator. After receiving a pulse width modulation (PWM) signal from a secondary side controller in the PSC, the oscillator signal is decoupled from the GD signal using a controller in the PSC and the PWM signal is used to generate the GD signal. The oscillator operates at a first frequency that is independent of the PWM signal. The PWM signal includes one of a plurality of frequencies selected based on power drawn from the converter and can be less than the first frequency in low power applications.

[0013] Other features and advantages of embodiments of the present application will be apparent from the following detailed description, taken in conjunction with the accompanying drawings in which like reference numerals refer to like elements. It will be apparent that the application is not limited to the specific embodiments described herein. The embodiments are presented as examples of the application only. Based on the teachings provided herein, additional embodiments will be apparent to those skilled in the relevant art. BRIEF DESCRIPTION OF DRAWINGS

[0014] Embodiments of the present application will now be described, by way of example only, with reference to the illustrative drawings in which like reference numerals refer to like elements. In addition, the drawings are incorporated in and form part of the specification to illustrate embodiments of the present application and, along with the description, further serve to explain the principles of the application and to enable a person skilled in the relevant art to make and use the application.

[0015] Figure 1 is a schematic block diagram illustrating a conventional secondary controlled AC-DC converter;

[0016] Figure 2 is a timing diagram illustrating typical waveforms of key signals in a primary side controller (PSC) of a conventional secondary controlled AC-DC converter controlled by pulse width modulation (PWM) using pulses from a secondary side controller (SSC);

[0017] Figure 3 is a schematic block diagram illustrating a secondary controlled AC-DC converter including an embodiment of a PSC having an independent oscillator;

[0018] Figure 4 is a schematic block diagram depicting an embodiment of a PSC of Figure 3 ;

[0019] Figure 5 is a timing diagram illustrating waveforms of key signals of a PSC of Figure 4 operating in an open loop mode using signals originating from an independent oscillator and in a closed loop mode using signals from a SSC;

[0020] Figure 6 is a flow chart illustrating an embodiment of a method for operating a secondary controlled AC-DC converter in an open loop mode using signals originating from an independent oscillator in the PSC and in a closed loop mode using signals from a SSC;

[0021] Figure 7 is a logic gate diagram of a portion of a PSC illustrating an embodiment of a logic circuit for determining whether the PSC should operate in an open loop mode or in a closed loop mode; and

[0022] Figure 8is a logic gate diagram that is part of the PSC showing an embodiment for gate drive output (GDO) control. DETAILED DESCRIPTION

[0023] Disclosed is a secondary controlled AC-DC converter having a primary side controller (PSC) including an independent oscillator and controller for switching between an open loop mode of operation using a gate drive signal originating from the oscillator and a closed loop mode using a pulse width modulated (PWM) signal or pulses from a secondary side controller (SSC) and a method for operating the same. The systems and methods of the present disclosure are particularly useful in or with flyback AC-DC converters to reduce the cost, complexity, and size of the converter while improving soft start and low frequency operation to improve efficiency.

[0024] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application can be practiced without these specific details. In other instances, well-known structures and techniques have not been shown in detail in order to avoid unnecessarily obscuring the understanding of this description.

[0025] Reference in the description to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment. The term "coupled" as used herein can include both a direct electrical connection between two or more components or elements and an indirect electrical connection through one or more intermediate components.

[0026] Embodiments of a secondary controlled AC-DC converter including a PSC having an independent oscillator will now be described with reference to Figure 3 and Figure 4 Figure 3 is a schematic block diagram showing substantially the entire secondary controlled AC-DC converter 300 including a primary side controller (PSC 302) having an independent oscillator 304. Figure 4 is a more detailed schematic block diagram of the PSC 400 depicting an embodiment of the independent oscillator in the secondary controlled AC-DC converter 300 suitable for use in Figure 3

[0027] Reference is made to Figure 3 ​​The AC-DC converter 300 generally includes a flyback transformer 306 having a primary winding (NP) on a primary side 308 electrically connected or coupled to an AC input and a secondary winding (NS) on a secondary side 310 coupled to a DC output.

[0028] On the primary side 308, one or more input filters and rectifier circuits, such as a bridge rectifier 312, coupled to the primary winding of the transformer 306, rectify and filter the AC input voltage to supply input power to the primary winding of the transformer. The input filter can include a first input filter 314 having a capacitor (Cl) coupled to or across the output of the rectifier 312 and a second RC filter or buffer 316 including a resistor or resistive element (R2) and a capacitor (C2) coupled in parallel between a first terminal of the primary winding of the transformer 306 and a cathode of a diode or rectifier (D2) having an anode coupled to a second terminal of the primary winding of the transformer. The AC-DC converter 300 also includes a power switch (PS 318), such as a primary field effect transistor (PR_FET), having a first or drain node coupled to the second terminal of the primary winding of the transformer 306, a second or gate node coupled to a gate drive output (GDO) pin in the PSC 302, and a third or source node coupled to a current sense (CS) pin in the PSC, and the power switch (PS 318) is grounded through a resistive current sense (RCS) circuit 320 to sense a primary side current (I_primary) flowing through the primary winding when the PS 318 is closed or turned on.

[0029] Generally, the PSC 302 is also coupled to the output of the bridge rectifier 312 through a resistive element (Rin) to provide power to the PSC during a start-up phase. Once the start-up phase is complete and the line voltage (V IN ) is within a normal operating range, and the PS 318 is operated to enable power to be transferred through the flyback transformer 306, an optional / auxiliary regulator 322 is coupled to an auxiliary winding of the flyback transformer 306 for supplying power to the PSC 302.

[0030] On the secondary side 310, the AC-DC converter 300 includes a filter capacitor 324 and an output capacitor 326 coupled between a first terminal of the secondary winding of the transformer 306 and electrical ground to provide a DC output voltage to an output interface or connector 328. Typically, as shown in the implementation, the output connector 328 is also coupled to a secondary side controller (SSC) 330 through a plurality of communication channels 332 to support various charging protocols. Suitable output connectors 328 can include those compatible and supporting the following standard and proprietary charging protocols: including Universal Serial Bus Power Delivery (USB PD) 2.0 and USB PD 3 with Programmable Power Supply (PPS), Quick Charge charging protocols, AFC charging protocols, and charging protocols. For example, the connector 328 can include a Universal Serial Bus Type-C (USB-C) compatible connector, where the AC-DC converter 300 complies with the USB protocol to provide a DC output voltage of about 3.3 V DC to about 21.5 V DC at a current of about 0 milliampere (mA) to about 5000 mA.

[0031] The AC-DC converter 300 also includes a synchronous rectifier (SR 334), e.g., a synchronous rectifier field effect transistor (SR FET), on the secondary side 310 coupled between a second terminal of the secondary winding of the transformer 306 and a ground terminal of the DC output. The SR 334 includes a first or drain node coupled to the transformer 306 and an SRS pin in the SSC 330 to sense a voltage on the drain of the SR, a second or gate node coupled to an SR gate drive pin to drive or control the SR, and a third or source node coupled to the SSC and the ground terminal of the DC output.

[0032] Optionally, as shown in the implementation, the secondary side 310 also includes an additional or secondary switch (SS) 336, e.g., an NFET, coupled between the transformer 306 and the DC output to enable the SSC 330 to turn off the DC output to prevent overvoltage and / or undervoltage conditions. The SS 336 includes a source node coupled to a voltage bus input pin (V BUS _ IN ) of the SSC to drive or control the SS, and a drain node coupled to a voltage bus output pin (V BUS _ CTRL ) and to the DC output. BUS _ OUT

[0033] As​Figure 3 As shown, the AC-DC converter 300 also includes an isolation circuit or barrier 344 for electrically isolating the secondary side 310 from the high AC input voltage appearing on the primary side 308. Because transformer 306 is a step-down transformer, it is typically considered part of the isolation barrier 344. Additionally, where, as shown in the embodiment, the AC-DC converter 300 is a flyback converter in which SSC 330 provides feedback or a PWM signal from a pulse width modulation (PWM) pin in SSC to PSC 302, the isolation barrier 344 also includes a pulse edge transformer (PET 346) for coupling the PWM signal to a pulse input pin in PSC. Refer below... Figure 4 This describes the details of these additional circuits or components according to various implementation methods.

[0034] Figure 4 It is a description Figure 3 A schematic block diagram illustrating the implementation of the PSC. (Refer to...) Figure 4 The PSC 400 includes a gate driver 402 for driving an external primary FET or power switch (PS404) via a gate drive output (GDO) to control the current flowing through the primary side of the flyback transformer 406.

[0035] PSC 400 V DD Pins such as Figure 3 The circuit shown is connected to the line voltage (V) via a bridge rectifier. IN Alternatively, a high-voltage (HV) startup circuit 408 can be directly coupled to the AC input. Either implementation will provide power to the PSC400 during the startup phase. When V... IN When the line voltage is low and PS 404 is kept off, UVLO block 410 prevents erroneous startup. When the line voltage exceeds a predetermined voltage, OVP block 412 turns off PS 404. Once the line voltage is within the normal operating range, gate driver 402 begins switching PS 404, and after the startup phase, optional / auxiliary regulator 414, coupled to the auxiliary winding of flyback transformer 406, supplies power to PSC 400, and after the startup phase, there is no power source from V DD The pin current. The voltage on the auxiliary winding is a scaled voltage of the secondary side voltage. When the power or voltage supplied by the optional / auxiliary regulator 414 is low, the auxiliary power on the reset (POR) block 416 keeps PS 404 off, and when the voltage exceeds a predetermined voltage, the auxiliary OVP block 418 turns PS 404 off.

[0036] PSC 400 also includes an oscillator and receiver (Rx) sub-circuit or block 420 for generating a free-running PWM signal and providing the free-running PWM signal to the gate driver 402 to turn on the PS 404 at soft start when the SSC (not shown in this figure) is not active, and once the SSC becomes active the oscillator and receiver (Rx) sub-circuit or block 420 receives PWM signals from the secondary side and couples these signals to the gate driver while decoupling the free-running PWM signal from the gate driver.

[0037] The oscillator and Rx block 420 includes an independent oscillator 422 for providing an oscillator signal to a pulse width modulation (PWM) generator 424 to generate a free-running PWM signal and provide the free-running PWM signal to the gate driver 402, a controller 426 for selecting which PWM signals to couple to the gate driver, and first and second comparators 428a and 428b through which positive and negative edges of PWM signals from the secondary side are passed to the controller. The oscillator and Rx block 420 also includes a plurality of internal voltage sources (shown in Figure 4 as exemplary 7.5 V sources) and first and second current supplies 430a and 430b that provide reference voltages to the oscillator 422 and comparators 428a, 428b, and an auto-restart timer 432 coupled to and synchronized with the oscillator or receiving the oscillator and coupled to the controller 426 to set a predetermined or predefined time for which the PSC 400 is to operate in open loop mode before checking for PWM signals from the SSC and switching to a closed loop mode of operation.

[0038] The oscillator and Rx block 420 supports soft start operation by gradually increasing the duty cycle from DCmin to DCmax using an external capacitor 434 connected to the SS pin of the PSC 400 and charged by the internal current source 430b. The duration of the soft start operation is set by the external capacitor 434 and will depend on the current from the internal current source 430b. A suitable current can include, for example, a current of about 5 μΑ. Similarly, for Figure 4In the illustrated embodiment, the maximum amplitude of the soft-start ramp is limited to about half of the internal voltage source voltage or about 3.75V. The oscillator 422 has a frequency (Fosc) set by an external resistor 436 connected to the resistor timing (RT) pin of the PSC. Typically, as illustrated in the embodiment, the oscillator and Rx block 420 includes a discharge path and switch 438 that discharges the external capacitor 434 prior to the soft-start operation or after the soft-start operation.

[0039] Additionally, to generate a free-running PWM signal during soft-start and couple the free-running PWM signal to the gate driver 402, the oscillator and Rx block 420 receives a pulse or PWM signal from the secondary side controller (SSC) through the PULSE IN pin when the secondary side is active. A pulse edge transformer (PET 440) is used to couple the PWM signal from the secondary side to the primary side. The PET 440 ensures proper frequency response and is selected to have sufficient Q-factor to avoid excessive overshoot. The first comparator 428a detects the positive edge of the pulse from the secondary side indicating the start of the pulse of the PWM signal, while the second comparator 428b detects the negative edge of the pulse from the secondary side indicating the stop or end of the pulse of the PWM signal. In response to these start and stop signals received from the first and second comparators 428a, 428b, the controller 426 couples the PWM signal from the secondary side to the gate driver 402 while simultaneously or concurrently decoupling the free-running PWM signal from the gate driver, thereby placing the AC-DC converter in a closed-loop mode of operation.

[0040] In some embodiments, such as illustrated, the PSC 400 can also include a current sense block 442 for detecting an overcurrent condition due to large currents flowing from the flyback transformer 406. The current sense block 442 provides pulse-by-pulse protection when the voltage on the current sense (CS) pin exceeds a voltage threshold (V CSTH ) sensed using an external resistive current sense (RCS) circuit 444 coupled to the primary side of the flyback transformer 406, and the current sense block 442 limits the current on the primary side by turning off the PS 404. In open-loop mode, if the voltage CS pin exceeds V CSTH , the PSC 400 can restart in soft-start mode after the auto-restart timer 432 times out. In closed-loop mode, the PS 404 is turned on again when the next pulse is received from the secondary side.

[0041] Figure 5 illustrates a diagram of the free-running PWM signal from the oscillator and Rx block 420 Figure 4a timing diagram of the waveforms of the key signals of the PSC operating in open loop mode using a signal originating from a free running independent oscillator 422. Referring to Figure 5 , the waveforms show a signal or pulses 502 generated from a free running independent oscillator 422 in the PSC 400. Note that these pulses have a substantially uniform or constant frequency. In some embodiments, using the signal or pulses 502 from the oscillator signal, the frequency of the pulses 502 is selected to enable operation of the elements in the PSC 400 including the controller. During a soft start period 504 or mode of operation, the pulses 502 generated from the oscillator are used to operate the gate driver (GD) 402 to generate a gate driver output (GDO 506) to drive the power switch (PS 404) to enable the secondary controlled AC-DC converter to start generating power on the secondary side and power up the SSC in open loop mode. Once the SSC is powered up and starts generating a feedback (FB) signal or a series of start and stop pulses, the leading and trailing edges of the PWM signal 508, from the SSC indicating that the AC-DC converter should start PWM using the start and stop pulses from the SSC to start and end each PWM pulse, the controller in the PSC 400 decouples the pulses 502 generated from the oscillator signal from the gate driver 402 and couples the FB or PWM signal to the gate driver to generate the GD signal to drive the PS in closed loop mode. As mentioned above, an advantage of this PSC 400 is that the independent oscillator 422 in the PSC continues to operate at a fixed frequency generating a clock signal to operate the logic elements in the PSC, for example, the controller 426.

[0042] Another advantage of the PSC 400 is that, as indicated by the ellipse 510, even when the frequency of the pulses 508 received from the SSC is lower than the fixed frequency of the independent oscillator 422 due to low demand for power on the secondary side of the AC-DC converter 300, the GDO 506 continues to follow the lower frequency pulses 508 from the SSC enabling the gate driver 402 to operate at a lower frequency than the fixed frequency of the independent oscillator and to operate more efficiently. This saves a significant amount of power, in particular when the AC-DC converter 300 is in standby mode of operation.

[0043] Embodiments of a method for operating a secondary controlled AC-DC converter in open loop mode using a signal originating from an independent oscillator in the PSC and in closed loop mode using a signal from the SSC will now be described with reference to the flowchart of Figure 6 Referring to Figure 6The method begins with soft start of the AC-DC converter using the oscillator signal from the free running independent oscillator in the PSC to control the gate driver (602). As described above, generally this step includes using the oscillator signal as a clock signal to operate elements in the PSC including logic elements or logic gates in the controller. This open loop mode of operation continues for a predetermined duration (604). The predetermined duration is based on both: the time required for the SSC to be powered up and begin generating a pulse width modulated (PWM) signal; and a minimum duration or time set by a timer or a plurality of elements having a predetermined fixed delay, for example, a plurality of buffers included in the logic elements or logic gates of the PSC. Once the predetermined duration has elapsed, the logic elements or logic gates of the PSC check to determine if a feedback (FB) or PWM signal is received from the SSC in the PSC (606). If the FB or PWM signal has been received, the GD is controlled or operated in a closed loop mode using the signal from the SSC (608). Additionally, the oscillator signal is decoupled from the GD signal using the controller in the PSC. If the FB or PWM signal is not received, the GD continues to be controlled or operated in the open loop mode using the signal from the independent oscillator in the PSC (610). Next, a fault check is performed to determine if any signal has been detected in the operation of the AC-DC converter that indicates one of a plurality of predefined faults (612). If no fault is detected, and the FB or PWM signal continues to be received from the SSC (step 606), the secondary controlled AC-DC converter continues to operate in the closed loop, post soft start mode using the signal from the SSC (step 608). If no fault is detected, and the FB or PWM signal is not received from the SSC (step 606), the secondary controlled AC-DC converter continues to operate in the open loop, soft start mode using the signal from the independent oscillator in the PSC (step 610). However, if a fault has been detected, the PSD consults a fault table (614) and determines if an automatic restart or auto restart is indicated (616). Table I below summarizes the fault conditions that indicate an automatic restart. If a restart is indicated, the open loop mode of operation is resumed for the predetermined duration (step 604). However, if a restart is not indicated, that is, the restart will not clear the fault condition, the GDO signal to the GD is withdrawn, and power conversion is terminated (618).

[0044] Table I

[0045]

[0046] Figure 7is a logic gate diagram that is part of the PSC that shows an embodiment of a logic circuit 700 for determining whether the PSC should operate in open loop mode or closed loop mode. The purpose of this logic circuit is to determine whether the PSC should be in closed loop mode or open loop mode.

[0047] Upon reset or detection of any fault, the logic will cause the PSC to operate in open loop mode. When all faults are removed and the FB or PWM signal is received from the SSC, the logic circuit will only transition the PSC to closed loop mode. The setting and resetting of this loop controller circuit are asynchronous. That is, any fault will prevent the latch 702 from being set. Therefore, the reset condition and removal of the FB or PWM signal can create a short glitch to the clock input of the latch 702. To create a wider pulse and prevent the latch 702 from latching on the glitch, a stack of buffers 704 is included as input to a first or NOT gate 706 that is coupled to the input of the latch 702. Referring to Figure 7 In operation, the logic circuit 700 receives a signal on the FB loop control input 708 as having received the FB or PWM signal from the SSC in the PSC. This signal is coupled to a second or NOT gate 710 in the logic circuit 700. The logic circuit 700 simultaneously or concurrently checks or determines that no reset signal 712, fault detection signal 714, or line under voltage (UV) detection signal 716 is received on a third or NOT gate 718. If any of these three signals have been received, the third or NOT gate 718 passes the signal to the latch 702, preventing the AC-DC converter from operating in closed loop mode, and thereby placing the PSC in open loop mode.

[0048] If none of the three signals are received, the third or NOT gate 718 passes the signal through an inverter 720 to the second or NOT gate 710, and if the appropriate signal has been received from the FB loop control input 708, the second or NOT gate passes the signal to the first or NOT gate 706, causing the latch 702 to latch the close signal to the closed loop output 722. However, if the FB signal is not received on the FB loop control input 708, the latch 702 outputs the open loop signal through an inverter 726 to the open loop output 724, and through one or more buffers 730 to the open loop delay output 728.

[0049] Figure 8 is a logic gate diagram that is part of the PSC that shows an embodiment of a gate drive output (GDO) control circuit 800. Referring to Figure 8When in open loop mode, a high oscillator input (osc_input 802) is applied to an AND gate 804 to set a flip-flop or latch 806, and a GDO (GDO_output 814) is provided through an inverter 808 and NOR gates 810 and 812 to drive a power switch or primary FET (not shown in this figure). When a PWM signal from the SSC is detected on sspwm-input 816, the signal is applied through a NOR gate 818 to reset the latch 806, and through a buffer 820 to the AND gate 804 to decouple the osc_input 802 from the GDO_output 814. When in closed loop mode, a high feedback turn-on input (fb_on 822) is applied through an inverter 824 to set a second flip-flop or latch 826, and the GDO_output 814 is provided through NOR gates 828, 810 and 812. When a high feedback turn-off signal (fb_off 830) is applied through a NOR gate 832, the latch 826 resets, removing the fb_on 822 from the GDO_output 814. Any fault such as an over current input (over_current 834), a shutdown signal (shutdown_on 836), a reset signal 838 applied through a buffer 839, or any other fault 840 such as one of those listed in Table I applied through a NOR gate 842 and an inverter 844 will reset the latch 826, removing the fb_on 822 from the GDO_output 814. Additionally, a line under voltage signal (line_uv 846) applied through a NOR gate 812 will turn off the GDO_output 814 32 milliseconds (ms) after the falling edge of the from signal, and in closed loop mode, if the secondary side detection signal (ssdet 848) falls and is coupled through an inverter 849 to the NOR gate 828, the GDO_output 814 will turn off. Finally, a signal from an open loop input 850 or a closed loop input 852 from a user or other logic element in the PSC will cause the PSC to operate in open loop mode or closed loop mode, respectively. Finally, a signal applied to a discharge input (discharge_n 854) prior to or after a soft start operation will indicate that the external capacitor 434 (not shown) has been discharged and the soft start period has begun. Conversely, a high input on the discharge_n 854 will indicate that the duration set for the soft start operation is complete.

[0050] Thus, a secondary controlled AC-DC converter comprising an independent oscillator and a controller for switching between an open loop mode of operation using a gate drive signal originating from the independent oscillator and a closed loop mode using pulse width modulation (PWM) from the secondary side controller and a method for operating the same have been disclosed. Embodiments of the present application have been described above by means of functional and schematic block diagrams illustrating the implementation of specified functions and their relationships. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternative boundaries can be defined so long as the specified functions and their relationships are appropriately performed.

[0051] The foregoing description of specific implementations will so fully reveal the general nature of the application that others can modify and / or adapt for various applications such specific implementations without undue experimentation without departing from the general concept thereof. Consequently, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in technical art in light of the teachings and guidance.

[0052] It is to be understood that the detailed description of the specific implementation is intended to be illustrative, rather than limiting, of the disclosure. The disclosure is not limited to the specific implementation described herein, but rather, the goal is to include all implementations falling within the scope of the appended claims and their equivalents. It will be apparent to those skilled in the art that various modifications and variations can be made in the present implementation without departing from the spirit or scope of the disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of this implementation provided they come within the scope of the appended claims and their equivalents.

[0053] The breadth and scope of the present application should not be limited by any of the above-described exemplary implementations, but should be defined in accordance with the following claims and their equivalents.

Claims

1. A method of operating an AC-DC converter, the method comprising: driving a power switch (PS) coupled between an AC input and a primary side of a flyback transformer with a gate drive (GD) signal generated using an oscillator signal from an oscillator in a primary side controller; receiving in the primary side controller a pulse width modulated (PWM) signal from a secondary side controller coupled to a secondary side of the AC-DC converter; and decoupling the oscillator signal from the GD signal using a controller in the primary side controller and using the PWM signal to generate the GD signal that drives the PS, wherein the oscillator operates at a first frequency independent of the PWM signal, and wherein the PWM signal is generated at one of a plurality of second frequencies selected by the secondary side controller based on power drawn from the secondary side of the AC-DC converter.

2. The method of claim 1, further comprising operating elements in the primary side controller using the oscillator signal as a clock signal.

3. The method of claim 2, wherein, the first frequency is constant based on the elements in the primary side controller that use the oscillator signal as the clock signal.

4. The method of claim 1, wherein, the second frequency is lower than the first frequency.

5. A method of operating a primary side controller of an AC-DC converter, the method comprising: operating the AC-DC converter in an open loop mode by driving a power switch (PS) coupled between an AC input and a primary side of the AC-DC converter with a gate drive (GD) signal generated using an oscillator signal from an oscillator in the primary side controller; receiving in the primary side controller a feedback (FB) signal from a secondary side controller coupled to a secondary side of the AC-DC converter; and operating the AC-DC converter in a closed loop mode by decoupling the oscillator signal from the GD signal using a controller in the primary side controller and using the FB signal to generate the GD signal that drives the PS, wherein the oscillator operates at a first frequency independent of the FB signal, wherein the FB signal is generated by the secondary side controller at a second frequency independent of the first frequency, and wherein the second frequency comprises one of a plurality of frequencies selected by the secondary side controller based on power drawn from the secondary side of the AC-DC converter.

6. The method of claim 5, further comprising automatically restarting the AC-DC converter by operating the AC-DC converter in the open loop mode until the FB signal is received in the primary side controller and then operating the AC-DC converter in the closed loop mode after detecting one of a plurality of predefined faults in operation of the AC-DC converter.

7. The method of claim 6, wherein, the plurality of predefined faults comprises: a line voltage exceeds a predetermined high voltage or a predetermined low voltage; the GD signal is below a predetermined minimum voltage; a voltage from an auxiliary regulator on the primary side exceeds an overvoltage protection threshold in open loop mode; the current on the primary side exceeds a current sense threshold; a stop command is received from a secondary side controller SSC; no start or stop pulses are received from the SSC after a predetermined time; and a start pulse is received from the SSC without a stop pulse.

8. The method of claim 5, wherein, Further comprising operating elements in the primary side controller using the oscillator signal as a clock signal.

9. The method of claim 8, wherein, the first frequency is a constant frequency based on the elements in the primary side controller using the oscillator signal as the clock signal.

10. The method of claim 5, wherein, the second frequency is lower than the first frequency.

11. A primary side controller for an AC-DC converter, the primary side controller comprising: an oscillator for supplying an oscillator signal to a gate driver in the AC-DC converter, the gate driver for generating a gate drive GD signal to drive a power switch PS coupled between an AC input and a primary side of the AC-DC converter; and a controller in the primary side controller coupled to receive a feedback FB signal from a secondary side controller in a secondary side of the AC-DC converter, the controller configured to decouple the oscillator signal from the gate driver and couple the FB signal to the gate driver to generate the GD signal to drive the PS upon receiving the FB signal, wherein the oscillator operates at a first frequency independent of the FB signal, wherein the FB signal is generated at a second frequency comprising one of a plurality of frequencies selected automatically based on power drawn from the secondary side of the AC-DC converter, and wherein the first frequency on which the oscillator operates is independent of the second frequency of the FB signal.

12. The primary side controller of claim 11, wherein, the oscillator further supplies the oscillator signal as a clock signal to elements in the controller to operate the elements.

13. The primary side controller of claim 12, wherein, the first frequency is a constant frequency based on the elements in the controller using the oscillator signal as the clock signal.

14. The primary side controller of claim 11, wherein, the second frequency is lower than the first frequency.

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