Reduced bubble defects

Abstract

In some examples, a method of processing a substrate includes applying a photoresist (PR) on a surface of the substrate, pre-exposing the PR to ultraviolet (UV) light before depositing or etching a metal oxide (MO) layer on the PR, and then depositing or etching the MO layer on the PR after pre-exposing the PR to the UV light.

Description

[0001] Priority claim

[0002] This application claims priority to U.S. Patent Application No. 62 / 768,641, filed on November 16, 2018, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to bubble defect reduction in depositing and / or etching a metal oxide (MO) layer on a photoresist on a substrate. Background Art

[0004] The background description provided here is for the purpose of generally presenting the context of the present disclosure. No admission is made, either explicitly or implicitly, that the work of the presently designated inventors is prior art to the present disclosure to the extent that it is described in this background section and in aspects of the specification that were not determined to be prior art at the time the application was filed.

[0005] Atomic layer deposition (ALD) is a deposition method that has the ability to control the thickness of thin films formed on semiconductor substrates to the order of one atomic monolayer. Plasma-enhanced ALD (PEALD) is a further enhancement that enables improved film properties at lower temperatures. PEALD uses chemical precursors (such as ALD) in an RF-induced plasma to produce the necessary chemical reactions to form thin films in a highly controlled manner. PEALD has many advantages, including low-temperature processing, excellent deposited layer conformality and thickness control, and the ability to perform pre-deposition and post-deposition in-situ processing.

[0006] Multi-patterning is a technique used to increase the feature density of integrated circuits (ICs) beyond the limits of photolithography. Such multi-patterning techniques include, for example, pitch segmentation, sidewall image transfer, self-aligned contacts, via patterning, layout segmentation, and self-aligned double or quadruple patterning. Multi-patterning is expected to become essential for 10nm and 7nm node semiconductor processes and beyond.

[0007] Self-aligned quadruple patterning (SAQP) is essentially two cycles of a double patterning technique, often referred to as self-aligned double patterning (SADP). Both SAQP and SADP require a substrate with multiple layers formed on it. For example, the layers on the substrate may include, starting from the bottom layer upwards, a first carbon film called an ashing hard mask (AHM) or spin-on carbon layer (SOC), a silicon oxide (SiO2) layer, a second carbon (AHM / SOC) layer, and an antireflective layer (ARL).

[0008] SADP uses a photolithography step and an additional etching step to define spacer-like features on a substrate. In the SADP process, the first step is to deposit a resist material (also called a photoresist or photoresist layer, referred to as PR in this article), and then use photolithography to pattern the "mandrels" on the top ARL layer on the substrate. The mandrels typically have a spacing equal to or close to the lithographic limit. Next, the mandrels are covered with a deposited layer, such as silicon oxide (SiO2). A "spacer etch" is then performed, removing (a) the horizontal surfaces of the SiO2 layer and (b) the PR. As a result, only the vertical surfaces of the SiO2 remain on the ARL layer. These vertical surfaces define "spacers" with a spacing finer than that achievable by conventional photolithography.

[0009] SAQP is a continuation of the double patterning process. With SAQP, the SiO2 spacers are used as a mask in the etching step to remove the underlying ARL layer and the second AHM layer, except for the masked areas. Afterwards, the SiO2 spacers are removed, forming the second mandrels in the AHM layer. Another SiO2 layer is then deposited, followed by another "spacer etch" to remove (a) the horizontal portion of the SiO2 layer and (b) the second mandrels. The result is a structure with SiO2 spacers formed on the underlying SiO2 layer. With the SAQP process, the pitch of the second SiO2 spacers is finer than the first spacers and far exceeds the limits of traditional photolithography.

[0010] While multi-patterning offers significant benefits and helps expand the use of conventional photolithography techniques into next-generation integrated circuits, each process has its limitations. In particular, multi-patterning requires numerous deposition, photolithography, and etching steps to form spacers. The finer the spacer pitch, the more photolithography and etch cycles typically involved. These additional steps significantly increase the cost and complexity of semiconductor manufacturing.

[0011] As semiconductor manufacturers increasingly seek to employ SAQP and SADP to further shrink nodes, they are also looking for ways to reduce the cost of adopting the technology. One possible approach is to form the spacer using MO and deposit it directly on top of the PR layer. MO is harder and has a higher modulus than conventional silicon dioxide, and enables the creation and use of thinner spacers, and also has a secondary role of being able to act as a second mandrel. This approach of using MO spacers as spacers first and then using them as mandrels is called spacer-on-spacer technology. Certain approaches to spacer-on-spacer technology that achieve the necessary SAQP performance can be very cost-effective because they can eliminate many deposition, lithography, and etching steps and can therefore be used to offset the cost advantages of the technology.

[0012] As part of this spacer-by-spacer technique, certain MOs can be used as spacer materials to be deposited directly on top of the PR layer. Some examples show that this can be done without damaging the PR material. However, in some cases, particularly when performing spacer etching on certain wafers, significant defects can occur. One issue involves the generation of unwanted bubble defects. The present disclosure attempts to at least address this issue. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In the figures of the accompanying drawings, some embodiments are shown by way of example and not limitation:

[0014] Figure 1 is a schematic diagram illustrating bubble defects according to some examples.

[0015] Figure 2 is a block diagram illustrating operations in a method, according to an example embodiment. DETAILED DESCRIPTION

[0016] The following description includes systems, methods and techniques that embody the illustrative embodiments of the present disclosure. In the following description, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of the exemplary embodiments. However, it will be apparent to those skilled in the art that the subject matter of the present invention may be practiced without these specific details.

[0017] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. The following notice applies to the software and data described below and in the drawings, which form a part of this document: Copyright © LAM Research Corporation, 2018-2019. All rights reserved.

[0018] As mentioned above, the formation of bubble defects can be a problem in certain semiconductor manufacturing operations. Current manufacturing techniques using silicon oxide (SiO2) spacers are sometimes limited when scaling down to accommodate shrinking technology nodes. In some examples, other techniques involving MO spacers allow for scalability, but there are still issues related to the formation of bubble defects that occur in the PR layer during the etching of the MO downstream of the deposition stage. During the etching process, the presence of such defects can limit or prevent otherwise useful MO (such as tin oxide (SnO2)) from being used in smaller-scale operations or serving a secondary role as a mandrel on the PR layer.

[0019] Without wishing to be bound by theory, it is believed that the formation of bubble defects may be caused by the interaction of ultraviolet (UV) light or radiation present in the plasma gas during the dry etching chemistry with electrons emitted by the MO layer at the interface between the MO layer and the PR. In some cases, the PR layer may be a positive PR that softens when UV is applied during the curing process. When MO is present on the PR layer, it is believed that the secondary electron emission from the MO layer interacts with the positive PR and softens it under the action of the applied UV. The formation of bubble defects may be particularly significant when a highly emissive MO such as tin oxide is used because this material has a very high secondary electron emission coefficient. It is believed that the softening of the PR layer results in outgassing of the material when it breaks, thereby forming bubble defects during curing. In the accompanying drawings Figure 1 A schematic diagram of bubble defects appearing in three example panes 100 can be seen in FIG.

[0020] In some examples, a UV pre-curing or pre-exposure operation is performed. Figure 2 , the exemplary method 200 includes performing a pre-cure or pre-exposure operation on a substrate such as a silicon wafer (Si) including PR. The wafer including PR is exposed to UV before depositing the MO layer onto the PR. In some examples, the pre-cure or pre-exposure operation can be performed during or in addition to the SAQP process, SADP process, or spacer-by-spacer process as described above. In some examples, the PR is exposed to UV light or radiation before depositing the MO layer onto the PR, and the PR is not affected by the plasma UV exposure during or after the deposition of the MO layer. Figure 2 As shown in the exemplary image 202, some test examples using this method completely or at least substantially eliminated the formation of bubble defects.

[0021] For example, preliminary or pre-curing UV exposure can be performed in an existing tool with a UV source, in an external chamber equipped with a UV source, or in a wafer processing chamber with a plasma source. Other arrangements are also possible. Suitable plasma sources can include helium, argon, or nitrogen in an amount sufficient to generate UV for pre-curing purposes.

[0022] The above examples are merely illustrative and should not be considered limiting. Thus, in other examples, bubble defect reduction can be performed during or relative to other stages in semiconductor manufacturing operations. In some examples, bubble defect reduction, including pre-curing or pre-exposure operations, can be performed during or relative to a deposition stage, photolithography stage, etch stage, or other wafer processing stage involving the use of plasma. In some examples, bubble defect reduction, including pre-curing or pre-exposure operations, can be performed during or relative to a combination of stages.

[0023] Furthermore, although some of the examples discussed above mention tin oxide as an exemplary MO layer, the present disclosure can be used with other types of films or layers, some of which may include MO, metal nitrides, metal carbides, metals, and the like. Further exemplary layers or films also include dielectric materials of metallic or non-metallic materials. Figure 2 The exemplary wafer depicted includes a silicon material (Si) layer or film. Other compositions or materials that constitute or are included in the illustrated Si, PR, and MO layers are also possible.

[0024] Accordingly, some embodiments may include one or more of the following examples.

[0025] 1. A method for processing a substrate, the method comprising: applying a photoresist (PR) on a surface of the substrate; pre-exposing the PR to ultraviolet (UV) light before depositing or etching a metal oxide (MO) layer on the PR; and depositing or etching the MO layer on the PR after pre-exposing the PR to UV light.

[0026] 2. The method of example 1, wherein immediately after the pre-exposure to UV light: depositing or etching an MO layer on the PR.

[0027] 3. The method of Example 1 or 2, wherein the substrate comprises a silicon wafer.

[0028] 4. The method of any one of examples 1-3, wherein pre-exposing the PR to UV light is performed during or in addition to a self-aligned quadruple patterning (SAQP) process.

[0029] 5. The method of any one of Examples 1-4, wherein pre-exposing the PR to UV light is performed during or in addition to a self-aligned double patterning (SADP) process.

[0030] 6. The method of any one of examples 1-5, wherein pre-exposing the PR to UV light is performed during or in addition to a spacer-by-spacer process.

[0031] 7. The method according to any one of examples 1-6, further comprising protecting the PR from UV exposure during or after depositing or etching the MO layer on the PR.

[0032] 8. The method of any of examples 1-7, wherein shielding the PR from UV exposure comprises shielding the PR from plasma UV exposure.

[0033] 9. The method of any one of Examples 1-8, wherein pre-exposing the PR to UV light before depositing or etching a MO layer (later) on the PR is performed in an existing substrate processing tool having a UV light source.

[0034] 10. The method of any one of examples 1-9, wherein pre-exposing the PR to ultraviolet (UV) light before depositing or etching the MO layer on the PR is performed in an external chamber equipped with a UV light source.

[0035] 11. The method of any one of Examples 1-10, wherein the substrate is processed in a substrate processing tool comprising a plasma source for generating a plasma comprising a component in an amount sufficient to generate UV light to pre-expose the PR to the UV light.

[0036] 12. The method of example 11, wherein the plasma composition comprises one or more components comprising helium, argon, and nitrogen.

[0037] 13. The method of any one of Examples 1-12, wherein the MO layer comprises tin oxide.

[0038] 14. A method for processing a substrate, the method comprising: applying PR on a surface of the substrate; pre-exposing the PR to ultraviolet (UV) light before depositing or etching a layer on the PR; and depositing or etching a layer on the PR after pre-exposing the PR to UV light.

[0039] 15. The method of Example 14, wherein the layer comprises one or more of an MO layer, a metal nitride layer, a metal carbide layer, and a metal layer.

[0040] Although various embodiments and examples have been described with reference to specific exemplary embodiments and examples, it is apparent that various modifications and changes may be made to these embodiments without departing from the broader scope of the present disclosure. Therefore, the description and drawings should be considered illustrative rather than restrictive. The drawings forming a part thereof show specific embodiments in which the present subject matter may be practiced in an illustrative and non-limiting manner. The embodiments shown are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized and derived therefrom so that structural and logical replacements and changes may be made without departing from the scope of the present disclosure. Therefore, this detailed description should not be understood in a limiting sense, and the scope of the various embodiments is limited only by the appended claims and the full scope of equivalents to which these claims are assigned.

[0041] Here, for convenience only, these embodiments of the subject matter of the present invention may be referred to individually and / or collectively by the term "invention", and it is not intended to voluntarily limit the scope of this application to any single invention or inventive concept (if a plurality of inventions are actually disclosed). Therefore, although specific embodiments have been illustrated and described herein, it should be understood that any arrangement calculated to achieve the same purpose can replace the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of the various embodiments. By reading the above description, the combination of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art.

Claims

1. A method for processing a substrate, the method comprising: applying a positive photoresist PR on the surface of the substrate; pre-exposing the PR to ultraviolet light before depositing or etching a metal oxide layer on the PR, wherein the pre-exposing the PR reduces bubble defects; and After pre-exposing the PR to ultraviolet light, a metal oxide layer is deposited or etched on the PR to form spacers. 2 . The method of claim 1 , wherein depositing or etching a metal oxide layer on the PR is performed immediately after the pre-exposure to ultraviolet light.

3. The method according to claim 1, wherein The substrate includes a silicon wafer.

4. The method according to claim 1, wherein Pre-exposing the PR to ultraviolet light is performed during or in addition to a self-aligned quadruple patterning (SAQP) process.

5. The method according to claim 1, wherein Pre-exposing the PR to ultraviolet light is performed during or in addition to a self-aligned double patterning (SADP) process.

6. The method according to claim 1, wherein Pre-exposing the PR to ultraviolet light is performed during or in addition to the spacer-by-spacer process. 7 . The method of claim 1 , further comprising protecting the PR from ultraviolet light exposure during or after depositing or etching a metal oxide layer on the PR. 8 . The method of claim 7 , wherein shielding the PR from UV exposure comprises shielding the PR from plasma UV exposure.

9. The method according to claim 1, wherein: Pre-exposing the PR to UV light before depositing or etching a metal oxide layer on the PR is performed in existing substrate processing tools having a UV light source.

10. The method according to claim 1, wherein Pre-exposing the PR to UV light before depositing or etching a metal oxide layer on the PR is performed in an external chamber equipped with a UV light source.

11. The method according to claim 1, wherein The substrate is processed in a substrate processing tool including a plasma source for generating a plasma including a component in an amount sufficient to generate ultraviolet light to pre-expose the PR to the ultraviolet light.

12. The method of claim 11, wherein the plasma composition comprises one or more components including helium, argon, and nitrogen.

13. The method according to claim 1, wherein The metal oxide layer includes tin oxide.

14. A method for processing a substrate, the method comprising: applying a positive PR on the surface of the substrate; pre-exposing the PR to ultraviolet light before depositing or etching a layer on the PR, wherein the pre-exposing the PR reduces bubble defects; and After pre-exposing the PR to ultraviolet light, a layer is deposited or etched on the PR to form spacers.

15. The method according to claim 14, wherein The layer includes one or more of a metal nitride layer, a metal carbide layer, and a metal layer.

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