Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a capacitor including a lower electrode, an upper electrode, and a dielectric layer between the lower electrode and the upper electrode. The lower electrode includes ABO3, where "A" is a first metal element and "B" is a second metal element having a work function greater than a work function of the first metal element. The dielectric layer includes CDO3, where "C" is a third metal element and "D" is a fourth metal element. The lower electrode includes first layers and second layers alternately and repeatedly stacked. The first layers include the first metal element and oxygen. The second layers include the second metal element and oxygen. The dielectric layer is in contact with the lower electrode at a first contact surface corresponding to the second layers.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application claims priority from Korean Patent Application No. 10-2019-0174171, filed on December 24, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0003] Some example embodiments relate to a semiconductor, and more particularly, to a semiconductor device and / or a method of manufacturing the same. BACKGROUND

[0004] Semiconductor devices are widely used in the electronic industry due to their small size, multi-functional characteristics, and / or low manufacturing cost. As the electronic industry develops, semiconductor devices have been highly integrated. The width of patterns included in semiconductor devices has been reduced to increase the integration density of semiconductor devices. In particular, as the design rule of a semiconductor memory device such as a dynamic random access memory (DRAM) decreases, the oxidation of a lower electrode of a capacitor can increase the capacitance range (e.g., a standard deviation and / or an interquartile range and / or a difference between a maximum value and a minimum value of capacitance). Accordingly, there is a need for a structure and method of a semiconductor memory device capable of reducing the capacitance difference. SUMMARY

[0005] Some example embodiments of the inventive concept can provide a semiconductor device capable of reducing the leakage current of a capacitor and / or a method of manufacturing the same.

[0006] Alternatively or additionally, some example embodiments of the inventive concept can also provide a semiconductor device capable of improving reliability and / or a method of manufacturing the same.

[0007] According to some example embodiments, a semiconductor device can include a capacitor including a lower electrode, an upper electrode, and a dielectric layer between the lower electrode and the upper electrode. The lower electrode includes ABO3, where “A” is a first metal element and “B” is a second metal element having a work function greater than that of the first metal element. The dielectric layer includes CDO3, where “C” is a third metal element and “D” is a fourth metal element. The lower electrode includes first layers and second layers alternately and repeatedly stacked. The first layers include the first metal element and oxygen. The second layers include the second metal element and oxygen. The dielectric layer is in contact with the lower electrode at a first contact surface corresponding to the second layers.

[0008] According to some example embodiments, a semiconductor device can include a capacitor including a lower electrode, an upper electrode, and a dielectric layer between the lower electrode and the upper electrode. The lower electrode includes a first metal element, a second metal element, and oxygen. The dielectric layer includes a third metal element, a fourth metal element, and oxygen. The lower electrode includes first layers and second layers alternately and repeatedly stacked; the first layers include the first metal element and oxygen. The second layers include the second metal element and oxygen. The first metal element is at least one of Sr, Ba, La, or Ca, and the second metal element is at least one of Ru, Mo, Ir, Co, or Ni. The dielectric layer is in contact with the lower electrode at a first contact surface, the first contact surface corresponding to the second layers.

[0009] According to some example embodiments, a semiconductor device can include a first wire buried in an upper portion of a substrate, the first wire extending in a first direction; an active portion in the upper portion of the substrate, the active portion defined by a device isolation pattern, the active portion including first and second doped regions spaced apart from each other, and the first wire interposed between the first and second doped regions; a second wire on the substrate, the second wire extending in a second direction intersecting the first direction, the second wire connected to the first doped region; a contact connected to the second doped region; and a capacitor connected to the second doped region through the contact. The capacitor includes a lower electrode, an upper electrode, and a dielectric layer between the lower electrode and the upper electrode. The lower electrode includes ABO3, where "A" is a first metal element, "B" is a second metal element, a work function of the second metal element is greater than a work function of the first metal element, the dielectric layer includes CDO3, where "C" is a third metal element, "D" is a fourth metal element. The lower electrode includes first layers and second layers alternately and repeatedly stacked, the first layers including the first metal element and oxygen, the second layers including the second metal element and oxygen. The dielectric layer is in contact with the lower electrode at a first contact surface of the lower electrode, the first contact surface corresponding to the second layers.

[0010] According to some example embodiments, a method of manufacturing a semiconductor device can include forming a lower electrode on a substrate; forming a dielectric layer on the lower electrode; and forming an upper electrode on the dielectric layer. Forming the lower electrode includes performing a lower electrode formation cycle a plurality of times, the lower electrode formation cycle including a process of depositing a first layer and a process of depositing a second layer. The process of depositing the first layer includes supplying a first metal element source and supplying an oxygen source. The process of depositing the second layer includes supplying a second metal element source and supplying the oxygen source. The process of depositing the second layer ends forming the lower electrode. BRIEF DESCRIPTION OF DRAWINGS

[0011] Example embodiments will become more fully understood from the detailed description and accompanying drawings.

[0012] Figure 1 is a cross-sectional view illustrating a capacitor according to some example embodiments of the inventive concept.

[0013] Figure 2 is an enlarged view of the region "Q". Figure 1

[0014] Figure 3 is a plan view of the first layer.

[0015] Figure 4 is a plan view of the second layer.

[0016] Figure 5 is a plan view of the third layer.

[0017] Figure 6 is a plan view of the fourth layer.

[0018] Figure 7 is a conceptual view showing an interface between a lower electrode and a dielectric layer according to a comparative example.

[0019] Figure 8 is a process flow diagram showing a method of forming a capacitor according to some example embodiments of the inventive concept.

[0020] Figure 9 is a conceptual view showing a deposition apparatus for forming a layer according to some example embodiments of the inventive concept.

[0021] Figure 10 is a timing diagram showing a supply cycle of process gases for forming a lower electrode according to some example embodiments of the inventive concept.

[0022] Figure 11 is a timing diagram showing a supply cycle of process gases for forming a dielectric layer according to some example embodiments of the inventive concept.

[0023] Figure 12 is a plan view of a semiconductor memory device including a capacitor according to some example embodiments of the inventive concept.

[0024] Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 19 are cross-sectional views taken along lines A1-A2 and B1-B2 of Figure 12 showing a method of manufacturing a semiconductor memory device including a capacitor according to some example embodiments of the inventive concept. DETAILED DESCRIPTION

[0025] Semiconductor devices and methods of manufacturing the same according to some example embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings.​

[0026] Figure 1 is a cross-sectional view showing a capacitor according to some example embodiments of inventive concepts. Figure 2 is Figure 1 is a magnified view of a region “Q” of Figure 3 is a plan view of the first layer. Figure 4 is a plan view of the second layer. Figure 5 is a plan view of the third layer. Figure 6 is a plan view of the fourth layer.

[0027] Referring to Figure 1 and Figure 2 , the capacitor CAP can include a lower electrode 10, an upper electrode 50, and a dielectric layer 30 between the lower electrode 10 and the upper electrode 50. The upper electrode 50 can be spaced apart from the lower electrode 10 in a Z direction. For example, the capacitor CAP can be disposed on a substrate (not shown), the lower electrode 10 can be adjacent to the substrate, and the upper electrode 50 can be spaced apart from the substrate with the lower electrode 10 therebetween. For example, the lower electrode 10, the dielectric layer 30, and the upper electrode 50 can be sequentially stacked on the substrate in the Z direction. As used herein, the X direction, the Y direction, and the Z direction can correspond to different directions relative to each other, and the use of the X direction, the Y direction, and the Z direction does not necessarily indicate a relationship to the ground, such as a plane relative to the Earth. For example, the Z direction can extend in a direction that is perpendicular or parallel to a plane relative to the Earth. As another example, the lower electrode 10 can be conformal to another surface (e.g., a base electrode).

[0028] Referring to Figure 2 , the lower electrode 10 can include a first compound including a first metal element M1, a second metal element M2, and at least one oxygen atom OA. For example, the lower electrode 10 can be a ternary compound represented by the chemical formula ABO3. Here, “A” can correspond to the first metal element M1, and “B” can correspond to the second metal element M2. The first compound can have a perovskite crystal structure, such as a structure having two different sizes of cations (e.g., “A” and “B”) and anions (e.g., O3). For example, the first metal element M1 can be disposed at each of eight corners of a unit cell, and the second metal element M2 can be disposed at a center of the unit cell. The oxygen atom OA can be disposed at each center of six faces of the unit cell. A ratio of the first metal element M1:the second metal element M2:the oxygen atom OA in the unit cell can be 1:1:3. The lower electrode 10 can have ferromagnetic properties. A thickness of the lower electrode 10 can be in a range of about to about .

[0029] The lower electrode 10 can include atomic layers stacked alternately and repeatedly in the Z direction, such as a first layer L1 and a second layer L2. As shown in FIG. 1A, the first layer L1 can be parallel to the XY plane, and can be formed of a first metal element M1 and an oxygen atom OA. The first layer L1 can correspond to a {100} plane of the lower electrode 10. The first metal element M1 can be disposed at each lattice point, and the oxygen atom OA can be disposed at the center of a face of a unit cell formed of four first metal elements M1. The ratio of the first metal element M1 to the oxygen atom OA in the first layer L1 can be 1:1. Figure 3

[0030] As shown in FIG. 1B, the second layer L2 can be parallel to the XY plane, and can be formed of a second metal element M2 and the oxygen atom OA. The second layer L2 can correspond to the {100} plane of the lower electrode 10. The second metal element M2 can be disposed at the center of the unit cell. The oxygen atom OA can be disposed at each center of a face included in / constituted by / corresponding to the unit cell (or at each center of an edge of the unit cell in a plan view). The ratio of the second metal element M2 to the oxygen atom OA in the second layer L2 can be 1:2. Figure 4

[0031] The work function of the second metal element M2 can be greater than the work function of the first metal element M1. For example, the work function of the first metal element M1 can be less than 4 eV. The work function of the second metal element M2 can be greater than 4.5 eV and less than 6 eV. For example, the first metal element M1 can be at least one of Sr, Ba, La, or Ca. The second metal element M2 can be at least one of Ru, Mo, Ir, Co, or Ni. For example, the first compound can be, but is not limited to, SrRu03, SrCo03, SrMo03, CaRu03, BaRu03, or (Ba,Sr)Ru03.

[0032] The dielectric layer 30 can include a second compound including a third metal element M3, a fourth metal element M4, and the oxygen atom OA. For example, the dielectric layer 30 can be or include a ternary compound represented by a chemical formula CDO3. Here, “C” can correspond to the third metal element M3, and “D” can correspond to the fourth metal element M4. The second compound can have a perovskite crystal structure. For example, the third metal element M3 can be disposed at each of eight corners of a unit cell, and the fourth metal element M4 can be disposed at the center of the unit cell. The oxygen atom OA can be disposed at each center of six faces of the unit cell. The ratio of the third metal element M3:the fourth metal element M4:the oxygen atom OA in the unit cell can be 1:1:3. The dielectric layer 30 can have paraelectric and / or ferroelectric properties. The thickness of the dielectric layer 30 can be in a range of approximately 1 nm to approximately 100 nm. The dielectric layer 30 can include a second compound including a third metal element M3, a fourth metal element M4, and the oxygen atom OA. For example, the dielectric layer 30 can be or include a ternary compound represented by a chemical formula CDO3. Here, “C” can correspond to the third metal element M3, and “D” can correspond to the fourth metal element M4. The second compound can have a perovskite crystal structure. For example, the third metal element M3 can be disposed at each of eight corners of a unit cell, and the fourth metal element M4 can be disposed at the center of the unit cell. The oxygen atom OA can be disposed at each center of six faces of the unit cell. The ratio of the third metal element M3:the fourth metal element M4:the oxygen atom OA in the unit cell can be 1:1:3. The dielectric layer 30 can have paraelectric and / or ferroelectric properties. The thickness of the dielectric layer 30 can be in a range of approximately 1 nm to approximately 100 nm.​​​

[0033] The dielectric layer 30 can include third layers L3 and fourth layers L4 which are alternately and repeatedly stacked in the Z direction. As shown, the third layers L3 can be parallel to the XY plane, and can be formed of third metal elements M3 and oxygen atoms OA. The third layers L3 can correspond to the {100} plane of the dielectric layer 30. The third metal elements M3 can be disposed at each lattice point (e.g., each lattice point of a unit cell), and the oxygen atoms OA can be disposed at the center of a face of a unit cell formed of four third metal elements M3. The ratio of the third metal elements M3 to the oxygen atoms OA in the third layers L3 can be 1:1. Figure 5

[0034] As shown, the fourth layers L4 can be parallel to the XY plane, and can be formed of fourth metal elements M4 and oxygen atoms OA. The fourth layers L4 can correspond to the {100} plane of the dielectric layer 30. The fourth metal elements M4 can be disposed at the center of a unit cell. The oxygen atoms OA can be disposed at each center of a face included / constituted / corresponding to a unit cell (or at each center of an edge of a unit cell in a plan view). The ratio of the fourth metal elements M4 to the oxygen atoms OA in the fourth layers L4 can be 1:2. Figure 6

[0035] The work function of the fourth metal elements M4 can be greater than the work function of the third metal elements M3. For example, the work function of the third metal elements M3 can be less than 4 eV. The work function of the fourth metal elements M4 can be greater than 4.0 eV and less than 4.5 eV. For example, the third metal elements M3 can be at least one of Ba, Sr, or Ca. The fourth metal elements M4 can be at least one of Ti, Zr, or Hf. For example, the second compound can be, but is not limited to, BaTiO3, (Ba,Sr)TiO3(BST), SrTiO3, (Ba,Sr)(Zr,Ti)O3(BSZTO), Sr(Zr,Ti)O3(SZTO), Ba(Zr,Ti)O3(BZTO), (Ba,Sr)ZrO3(BSZO), SrZrO3, or BaZrO3. Alternatively or additionally, the third metal elements M3 can be an element (e.g., Pb) whose work function is greater than 4 eV and less than the work function of the fourth metal elements M4. In this case, the second compound can be or include Pb(Zr,Ti)O3(PZT) or (Pb,La)(Zr,Ti)O3(PLZT).

[0036] ​​The work function of the fourth layer L4, corresponding to the oxide layer of the fourth metal element M4, can be greater than the work function of the third layer L3, corresponding to the oxide layer of the third metal element M3. For example, when the fourth layer L4 is TiO2 and the third layer L3 is SrO, the work function of the fourth layer L4 (approximately 6.33 eV) can be greater than the work function of the third layer L3 (approximately 3.18 eV). For instance, the work function of the fourth layer L4 can be in the range of approximately 5.0 eV to approximately 6.5 eV.

[0037] The upper electrode 50 may include a metal layer comprising at least one of a noble metal (e.g., Pt, Ir, or Ru), Ti, or W. In some example embodiments, the upper electrode 50 may be formed of the same ternary compound as the lower electrode 10. In some example embodiments, the upper electrode 50 may include a heterosemiconductor material such as silicon-germanium.

[0038] An interface IF may exist between the lower electrode 10 and the dielectric layer 30. The interface IF may be or correspond to a region in which a first contact surface CS1 corresponding to the top surface of the lower electrode 10 contacts (e.g., directly and / or atomically) and a second contact surface CS2 corresponding to the bottom surface of the dielectric layer 30. From a lattice perspective, the first contact surface CS1 and the second contact surface CS2 may be spaced apart from each other, but from a macroscopic scale perspective, the first contact surface CS1 and the second contact surface CS2 may be in contact with each other.

[0039] The first contact surface CS1 of the lower electrode 10 can be a {100} plane. The first contact surface CS1 can be one of the layers L1 and L2 that has a larger work function. For example... Figure 2 As shown, the first contact surface CS1 can be or corresponds to the second layer L2. The second layer L2 can be composed of a second metal element M2 and oxygen atoms OA (or substantially composed of the second metal element M2 and oxygen atoms OA, or including the second metal element M2 and oxygen atoms OA), and can be represented by BO2. The first layer L1 can be composed of a first metal element M1 and oxygen atoms OA (or substantially composed of the first metal element M1 and oxygen atoms OA, or including the first metal element M1 and oxygen atoms OA), and can be represented by AO. The work function of the oxide of the second metal element M2 (e.g., BO2) can be greater than the work function of the oxide of the first metal element M1 (e.g., AO).

[0040] For example, the work function of the second layer L2 corresponding to the oxide layer of the second metal element M2 can be greater than the work function of the first layer L1 corresponding to the oxide layer of the first metal element M1. For example, when the second layer L2 is RuO2 and the first layer L1 is SrO, the work function of the second layer L2 (approximately 5.16 eV) can be greater than the work function of the first layer L1 (approximately 2.55 eV). The second contact surface CS2 of the dielectric layer 30 can be the one of the third layer L3 and the fourth layer L4 having the smaller work function. For example, the second contact surface CS2 can be or correspond to the third layer L3.

[0041] Figure 7 is a conceptual diagram illustrating an interface between a lower electrode and a dielectric layer according to a comparative example. Referring to Figure 7 In the comparative example, the first contact surface CS1 of the lower electrode 10 can be or correspond to the first layer L1.

[0042] When the dielectric layer 30 is formed of a ternary compound having a perovskite crystal structure, the dielectric constant of the dielectric layer 30 can increase compared to a binary compound such as ZrO2. As a result, the capacitance of the capacitor can increase. If the lower electrode 10 is formed of a binary compound, the lattice mismatch between the lower electrode 10 and the dielectric layer 30 formed of a ternary compound can reduce the crystallinity of the dielectric layer 30, and thus the dielectric constant of the dielectric layer 30 can deteriorate. The work function of the ternary compound dielectric layer can be smaller than that of the binary compound dielectric layer, and thus the conduction band offset (CBO) value between the ternary compound dielectric layer and the lower electrode can be smaller than approximately 1.0 eV. Accordingly, the leakage current of the capacitor can increase. However, according to some example embodiments of the inventive concept, the first contact surface CS1 of the lower electrode 10 can be the second layer L2 having a work function greater than that of the first layer L1, and thus the CBO value can increase to approximately 2.0 eV or more. As a result, the leakage current of the capacitor according to some example embodiments of the inventive concept can decrease compared to the case where the first contact surface CS1 is the first layer L1 as in the comparative example of Figure 7 The leakage current of the capacitor according to some example embodiments of the inventive concept can decrease compared to the case where the first contact surface CS1 is the first layer L1 as in the comparative example of

[0043] Figure 8 is a process flow diagram illustrating a method of forming a capacitor according to some example embodiments of the inventive concept. Figure 9 is a conceptual diagram illustrating a deposition apparatus for forming a layer according to some example embodiments of the inventive concept. Figure 10 is a timing diagram illustrating a supply cycle of process gases for forming a lower electrode according to some example embodiments of the inventive concept. Figure 11 is a timing diagram illustrating a supply cycle of process gases for forming a dielectric layer according to some example embodiments of the inventive concept.

[0044] Referring to Figure 8 and Figure 9 The deposition apparatus 1000 can include a deposition chamber 21. For example, the deposition apparatus 1000 can be or include an atomic layer deposition (ALD) apparatus. The deposition apparatus 1000 can further include a chuck / platen / platform 22 disposed in the deposition chamber 21 and on which a substrate WF is loaded, and a showerhead 23 for supplying a gas such as a reaction gas into the deposition chamber 21. The platform 22 can include a heater 25 therein to maintain the substrate WF at a desired and / or specified temperature. A high radio frequency (HRF) power 28 of 13.56 MHz and / or 27 MHz can be applied to the showerhead 23 (and / or a top electrode connected to the showerhead 23), and the platform 22 can be grounded, thus a plasma can be formed between the showerhead 23 and the platform 22. In some example embodiments, when the plasma is formed, a low radio frequency (LRF) power 29 of 5 MHz or less (e.g., 400 kHz to 500 kHz) can additionally be applied to the showerhead 23 and / or the top electrode as desired / needed.

[0045] A gas such as a reaction gas can be supplied into the deposition chamber 21 through the showerhead 23. In some example embodiments, the showerhead 23 can be connected to the first metal element source 11, the second metal element source 12, the third metal element source 13, the fourth metal element source 14, and the oxygen source 16 through one or more supply lines. The carrier gas supply unit 15 can be connected to the showerhead 23. The first metal element source 11, the second metal element source 12, the third metal element source 13, the fourth metal element source 14, and the oxygen source 16 can be fed to the showerhead 23 through separate supply lines separated from each other. Alternatively, at least part of the separate supply lines can overlap with each other, for example, be shared. The first metal element source 11 to the fourth metal element source 14 can be or include sources of elements different from each other. Alternatively, when the kinds of at least some of the above-mentioned first metal element to the fourth metal element are the same as each other, at least some of the first metal element source 11 to the fourth metal element source 14 can be sources of substantially the same element. For example, when the first metal element M1 is the same as the third metal element M3, the first metal element source 11 and the third metal element source 13 can be substantially the same source.

[0046] The carrier gas supplied from the carrier gas supply unit 15 can carry other sources and / or precursors into the deposition chamber 21. The carrier gas makes it possible to purge unreacted materials and / or reaction by-products in the deposition chamber 21 to the outside of the deposition chamber 21 by using a vacuum pump. The carrier gas can be or include an inert gas (e.g., helium (He) or neon (Ne)), and / or can be a gas having very low reactivity (e.g., nitrogen (N2) or carbon dioxide (CO2)). However, example embodiments of the present inventive concept are not limited thereto. At least a portion of the supply line of the carrier gas supply unit 15 can overlap with the supply lines of the first metal element source 11, the second metal element source 12, the third metal element source 13, the fourth metal element source 14, and the oxygen source 16. Alternatively, the supply line of the carrier gas supply unit 15 can be separate from the supply lines of the first metal element source 11, the second metal element source 12, the third metal element source 13, the fourth metal element source 14, and the oxygen source 16.

[0047] A substrate WF can be loaded on a stage 22 in the deposition chamber 21 (S100). The substrate WF can be a wafer, for example, a wafer having a diameter of 200 mm or 300 mm. A plurality of sources can be supplied into the deposition chamber 21 to form a lower electrode on the substrate WF (S200). The process of forming the lower electrode can be completed after forming the lower electrode to have a certain and / or desired thickness, and then a first heat treatment process can be performed (S300). The process of forming the lower electrode will be described in more detail below.

[0048] Referring to Figures 1 to 4 and Figures 8 to 10 , a lower electrode 10 can be formed on a substrate WF (e.g., a wafer) (S200). The formation of the lower electrode 10 can be performed similarly to and / or according to the timing chart of Figure 10 . The formation of the lower electrode 10 can include a plurality of first cycles CL1. The first cycle CL1 can include a process SC1 of forming a first layer L1 (hereinafter referred to as a first process SC1) and a process SC2 of forming a second layer L2 (hereinafter referred to as a second process SC2).

[0049] The first process SC1 can include a process S101 of supplying a first metal element source 11, a first purge process P1, a first process S102 of supplying an oxygen source 16, and a second purge process P2, which are sequentially performed. A first layer L1 composed of (or substantially composed of or including) a first metal element M1 and oxygen atoms OA (e.g., in a gas phase) and substantially corresponding to an (atomic) monolayer can be formed by the first process SC1. As disclosed herein, a monolayer can mean a layer of a structure having an atomic two-dimensional arrangement. The second process SC2 can include a process S103 of supplying a second metal element source 12, a third purge process P3, a second process S104 of supplying an oxygen source 16, and a fourth purge process P4, which are sequentially performed. A second layer L2 composed of (or substantially composed of or including) a second metal element M2 and oxygen atoms OA (e.g., in a gas phase) and substantially corresponding to an (atomic) monolayer can be formed by the second process SC2. Source gases not reacted with the wafer in the processes immediately before each of the first to fourth purge processes P1-P4 can be exhausted to the outside of the deposition chamber 21 by each or at least some of the first to fourth purge processes P1-P4. The first cycle CL1 can be performed a plurality of times to form the lower electrode 10 in which the first and second layers L1 and L2 are alternately and repeatedly stacked.

[0050] The first metal element source 11 can include at least one of Sr, Ba, La, or Ca. For example, the first metal element source 11 can be a strontium (Sr) source. The strontium source can include a cyclopentadienyl ligand and / or a ketimine ligand. The second metal element source 12 can include at least one of Ru, Mo, Ir, Co, or Ni. For example, the second metal element source 12 can be a ruthenium (Ru) source. The ruthenium source can include a β-diketonate ligand. For example, the oxygen source 16 can include O2 and / or O3.

[0051] In the first process SC1, the process S101 of supplying the first metal element source 11 can be performed over a time t01. For example, the time t01 can be in a range of about 7 seconds to about 15 seconds. In the second process SC2, the process S103 of supplying the second metal element source 12 can be performed over a time t03. For example, the time t03 can be in a range of about 3 seconds to about 7 seconds. For example, the process S101 of supplying the first metal element source 11 can be longer than the process S103 of supplying the second metal element source 12. Each of the first purge process P1 to the fourth purge process P4 can be performed over a time of about 15 seconds to about 25 seconds. The first supply process S102 of the oxygen source 16 can be performed over a time t02. For example, the time t02 can be in a range of about 15 seconds to about 25 seconds. The second supply process S104 of the oxygen source 16 can be performed over a time t04. For example, the time t04 can be in a range of about 15 seconds to about 25 seconds. During the first cycle CL1 for forming the lower electrode 10, a chamber temperature can be maintained at a temperature of about 300 degrees Celsius to about 500 degrees Celsius. During the first cycle CL1 for forming the lower electrode 10, a pressure in the chamber can be in a range of about 1 Torr (133 Pascal) to about 3 Torr (400 Pascal).

[0052] The formation of the lower electrode 10 can start at a start ts1 of an initial first cycle CL1s and can end at an end te1 of a final first cycle CL1e. Figure 10 The initial first cycle CL1s including the start ts1 can start from the first process SC1 of the first process SC1 and the second process SC2. Alternatively, the initial first cycle CL1s can start from the second process SC2. In the final first cycle CL1e including the end te1, the last supplied metal element source can be the second metal element source 12. For example, the final first cycle CL1e can end by the second process SC2 of the first process SC1 and the second process SC2. Thereby, with reference to Figure 1 and Figure 2 The first contact surface CS1 of the lower electrode 10 described can be or correspond to the second layer L2.

[0053] After the end te1, a first heat treatment process (S300) can be performed. The first heat treatment process (S300) can be performed in situ in the deposition chamber 21. However, some example embodiments of the inventive concept are not limited thereto; for example, the substrate WF can be heat treated in other chambers. No metal element source can be supplied during the first heat treatment process (S300). The first heat treatment process (S300) can be performed at a temperature of about 300 degrees Celsius to about 600 degrees Celsius. The crystallinity of the lower electrode 10 can be increased by the first heat treatment process (S300).

[0054] A dielectric layer 30 (S400) can be formed on the lower electrode 10. This can be similar to... Figure 11 Timing diagram or with Figure 11 The formation of dielectric layer 30 is performed in a manner corresponding to the timing diagram. The formation of dielectric layer 30 may include multiple second cycles CL2. The second cycle CL2 may include a process SC3 (hereinafter referred to as the third process SC3) for forming the third layer L3 and a process SC4 (hereinafter referred to as the fourth process SC4) for forming the fourth layer L4.

[0055] The third process SC3 may include the sequentially executed processes of supplying the third metal element source 13 (S201), the fifth scavenging process (P5), the third supply process of the oxygen source 16 (S202), and the sixth scavenging process (P6). A third layer L3, consisting of (or substantially consisting of) the third metal element M3 and oxygen atoms OA and substantially corresponding to a single layer, can be formed through the third process SC3. The fourth process SC4 may include the sequentially executed processes of supplying the fourth metal element source 14 (S203), the seventh scavenging process (P7), the fourth supply process of the oxygen source 16 (S204), and the eighth scavenging process (P8). A fourth layer L4, consisting of (or substantially consisting of) the fourth metal element M4 and oxygen atoms OA and substantially corresponding to a single layer, can be formed through the fourth process SC4. The second cycle CL2 may be performed multiple times to form a dielectric layer 30 in which the third layer L3 and the fourth layer L4 are stacked alternately and repeatedly. The third metal element source 13 may include at least one of Sr, Ba, La, or Ca. The fourth metal element source 14 may include at least one of Ti, Zr, or Hf. For example, the fourth metal element source 14 may include TiCl4.

[0056] In the third process SC3, the process S201 of supplying the third metal element source 13 can be performed at a time t05. For example, the time t05 can be in a range from about 7 seconds to about 15 seconds. In the fourth process SC4, the process S203 of supplying the fourth metal element source 14 can be performed at a time t07. For example, the time t07 can be in a range from about 3 seconds to about 7 seconds. In other words, the process S201 of supplying the third metal element source 13 can be longer than the process S203 of supplying the fourth metal element source 14. Each of the fifth purge process P5 to the eighth purge process P8 can be performed for a time of about 15 seconds to about 25 seconds. The third supply process S202 of the oxygen source 16 can be performed at a time t06. For example, the time t06 can be in a range from about 15 seconds to about 25 seconds. The fourth supply process S204 of the oxygen source 16 can be performed at a time t08. For example, the time t08 can be in a range from about 15 seconds to about 25 seconds. During the second cycle CL2 for forming the dielectric layer 30, the chamber temperature can be maintained at a temperature of about 300 degrees Celsius to about 500 degrees Celsius. During the second cycle CL2 for forming the dielectric layer 30, the pressure in the chamber can be in a range from about 1 Torr (133 Pascal) to about 3 Torr (400 Pascal).

[0057] The formation of the dielectric layer 30 can start at a start ts2 of an initial second cycle CL2s and can end at an end of a last second cycle. The initial second cycle CL2s including the start ts2 can start with the third process SC3 of the third process SC3 and the fourth process SC4. For example, in the initial second cycle CL2s including the start ts2, the initially supplied metal element source can be the third metal element source 13. Thereby, with reference to Figure 1 and Figure 2 The second contact surface CS2 of the dielectric layer 30 described can be or correspond to the third layer L3. Alternatively, the initial second cycle CL2s including the start ts2 can start with the fourth process SC4 of the third process SC3 and the fourth process SC4. Thereby, the second contact surface CS2 can be or correspond to the fourth layer L4.

[0058] After the formation of the dielectric layer 30 is completed, a second heat treatment process (S500) can be performed. The second heat treatment process (S500) can be performed in situ in the deposition chamber 21. However, some example embodiments of the present inventive concept are not limited thereto. No metal element source can be supplied during the second heat treatment process (S500). The second heat treatment process (S500) can be performed at a temperature of about 300 degrees Celsius to about 600 degrees Celsius. Alternatively, the second heat treatment process (S500) can be omitted. Thereafter, a process of forming the upper electrode 50 can be performed.

[0059] Figure 12is a plan view showing a semiconductor memory device including a capacitor according to some example embodiments of the inventive concepts. Figures 13 to 19 is a cross-sectional view taken along lines A1-A2 and B1-B2 of Figure 12 is a plan view showing a semiconductor memory device including a capacitor according to some example embodiments of the inventive concepts.

[0060] In the following example embodiments, a capacitor used as a storage portion of a semiconductor memory device is described as an example. However, the capacitor according to some example embodiments of the inventive concepts is not limited to the storage portion of the semiconductor memory device, but can be used as a non-storage element such as a decoupling structure.

[0061] Referring to Figure 12 and Figure 13 A device isolation pattern 302 can be provided in the substrate 301 to define active portions ACT. The substrate 301 can be or include a semiconductor substrate, such as a single crystalline silicon wafer that has been lightly doped (e.g., lightly doped with boron). Each of the active portions ACT can have an isolated shape when viewed in plan view. Each of the active portions ACT can have a strip shape extending along a third direction D3 when viewed in plan view. Each of the active portions ACT can correspond to a portion of the substrate 301 that is surrounded by the device isolation pattern 302 when viewed in plan view.

[0062] Word lines WL can intersect the active portions ACT. The word lines WL can be respectively provided in recesses formed in the device isolation pattern 302 and the active portions ACT. The word lines WL can be parallel to a first direction D1 that intersects the third direction D3. The word lines WL can include an electrically conductive material. A gate dielectric layer 307 can be provided between the word lines WL and inner surfaces of the recesses. The gate dielectric layer 307 can include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material.

[0063] A first doped region 312a can be provided in each of the active portions ACT between a pair of the word lines WL, and a pair of second doped regions 312b can be respectively provided in two edge regions of each of the active portions ACT. The first doped regions 312a and the second doped regions 312b can be doped with, for example, N-type dopants (e.g., phosphorus and / or arsenic). The first doped regions 312a can correspond to common drain regions, and the second doped regions 312b can correspond to source regions. Each of the word lines WL and the first doped regions 312a and the second doped regions 312b adjacent thereto can constitute (e.g., correspond to) a transistor, and can be used as, be, or correspond to an access transistor for accessing a storage element of a DRAM cell; however, example embodiments are not limited thereto.

[0064] A top surface of the word line WL can be lower than a top surface of the active portion ACT. A word line cover pattern 310 can be provided on each word line WL. The word line cover pattern 310 can have a linear shape extending in a longitudinal direction of the word line WL, and can cover a top surface of the word line WL. The word line cover pattern 310 can include, for example, silicon nitride.

[0065] An interlayer insulating pattern 305 can be provided on the substrate 301. The interlayer insulating pattern 305 can be formed of a single layer or multiple layers including at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0066] An upper portion of the substrate 301, the device isolation pattern 302, and the word line cover pattern 310 can be partially recessed to form a first recessed region R1. Bit lines BL can be provided on the interlayer insulating pattern 305. The bit lines BL can intersect the word line cover pattern 310 and the word line WL. As Figure 12 indicated, the bit lines BL can extend in a second direction D2 intersecting the first direction D1 and the third direction D3. Each bit line BL can include a polysilicon pattern 330, an ohmic pattern 331, and a metal-containing pattern 332 sequentially stacked. The polysilicon pattern 330 can include polysilicon doped with or not doped with a dopant. The ohmic pattern 331 can include a metal silicide. The metal-containing pattern 332 can include at least one of a metal (e.g., tungsten, titanium, and / or tantalum) or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and / or tungsten nitride). A bit line cover pattern 337 can be provided on each bit line BL. The bit line cover pattern 337 can include an insulating material (e.g., silicon nitride). The bit line cover pattern 337 can include the same or different material as the word line cover pattern 310.

[0067] A bit line contact DC can be provided in the first recessed region R1 intersecting the bit line BL. The bit line contact DC can include polysilicon doped with or not doped with a dopant (e.g., boron). The bit line contact DC can be electrically connected to the first doped region 312a, and can electrically connect the first doped region 312a to the bit line BL.

[0068] A fill insulating pattern 341 can be provided in the first recessed region R1 in which the bit line contact DC is not provided. The fill insulating pattern 341 can have a single layer or a multiple layer structure including at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0069] As Figure 12 indicated, a storage node contact BC can be provided between a pair of bit lines BL adjacent to each other. The storage node contacts BC can be spaced apart from each other. The storage node contact BC can include polysilicon doped with (e.g., doped with boron) or not doped with a dopant.

[0070] A bit line spacer can be provided between the bit line BL and the storage node contact BC, the bit line spacer including a first spacer 321 and a second spacer 325 spaced apart from each other by an air gap AG. The first spacer 321 can cover sidewalls of the bit line BL and sidewalls of a bit line cover pattern 337. The second spacer 325 can be adjacent to the storage node contact BC. The first spacer 321 can extend to cover sidewalls of the bit line contact DC and sidewalls and a bottom surface of the first recessed region R1. The first spacer 321 and the second spacer 325 can include the same material. For example, the first spacer 321 and the second spacer 325 can include silicon nitride. Alternatively, the air gap AG can not be provided, and a third spacer can be provided between the first spacer 321 and the second spacer 325.

[0071] A storage node ohmic layer 309 can be provided on the storage node contact BC. The storage node ohmic layer 309 can include a metal silicide, such as tungsten silicide (WSi x ) The diffusion barrier pattern 311a can cover the storage node ohmic layer 309, the first spacer 321 and the second spacer 325, and the bit line cover pattern 337. The diffusion barrier pattern 311a can include a metal nitride such as titanium nitride and / or tantalum nitride. A landing pad LP can be provided on the diffusion barrier pattern 311a. The landing pad LP can include a metal-containing material such as tungsten. An upper portion of the landing pad LP can cover a top surface of the bit line cover pattern 337 and can have a width greater than a width of the storage node contact BC. As shown, a center of the landing pad LP can be offset from a center of the storage node contact BC in the first direction D1. One upper sidewall of the bit line cover pattern 337 can overlap with the landing pad LP and can be covered by a third spacer 327. A second recessed region R2 can be formed at another upper sidewall of the bit line cover pattern 337. Figure 12

[0072] A first cover pattern 358a can be provided between adjacent landing pads LP. The first cover pattern 358a can have an inner lining shape so that a space surrounded thereby can be filled with a second cover pattern 360a. Each of the first cover pattern 358a and the second cover pattern 360a can include a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or a porous layer. The first cover pattern 358a and the second cover pattern 360a can fill the second recessed region R2.

[0073] ​An etch stop layer 370 can be formed on the landing pad LP, the first cover pattern 358a, and the second cover pattern 360a. A first mold layer 372, a support layer 374, and a second mold layer 376 can be formed on the etch stop layer 370. For example, each of the etch stop layer 370 and the support layer 374 can be formed of a silicon nitride layer. Each of the first mold layer 372 and the second mold layer 376 can be formed of a material having etch selectivity with respect to the support layer 374. For example, each of the first mold layer 372 and the second mold layer 376 can be formed of a silicon oxide layer.

[0074] Referring to Figure 12 and Figure 14 The second mold layer 376, the support layer 374, the first mold layer 372, and the etch stop layer 370 can be sequentially patterned to form electrode holes EH exposing the landing pad LP, respectively. A conductive layer can be formed to fill the electrode holes EH, and an etch-back process and / or a chemical mechanical polishing (CMP) process can be performed on the conductive layer to remove the conductive layer disposed on the second mold layer 376 and form base electrodes SE in the electrode holes EH, respectively. The base electrodes SE can include a metal nitride. For example, the base electrodes SE can have a single-layer or multi-layer structure including at least one of TiN, WN, TaN, HfN, ZrN, TiAlN, TaSiN, TiSiN, TaAlN, TiBN, TiON, TiAlON, TiCN, TiAlCN, or TiSiCN.

[0075] A third mask pattern 378 can be formed on the second mold layer 376. The third mask pattern 378 can have a plurality of openings 378h. Each of the openings 378h can expose top surfaces of the base electrodes SE adjacent to each other and the second mold layer 376 located between the base electrodes SE.

[0076] Referring to Figure 12 and Figure 15 An anisotropic etching process (e.g., a dry etching process) can be performed using the third mask pattern 378 as an etching mask to remove the second mold layer 376 and the support layer 374 thereunder exposed through the openings 378h. Accordingly, a support pattern 374a can be formed, and the first mold layer 372 under the openings 378h can be exposed.

[0077] Referring to Figure 12 and Figure 16 The third mask pattern 378 can be removed to expose the second mold layer 376. The first mold layer 372 and the second mold layer 376 can be removed by an isotropic etching process to expose surfaces of the base electrodes SE, the support pattern 374a, and the etch stop layer 370.

[0078] Referring to Figure 12 andFigure 17 The lower electrode 10 can be formed on the exposed surface of the base electrode SE. The lower electrodes 10 on the base electrode SE can be separated from each other. For example, the process of forming the lower electrode 10 may include removing portions deposited between the base electrodes SE to expose the etch stop layer 370. The lower electrode 10 can cover the sidewalls and top surface of the base electrode SE. The lower electrode 10 can be connected to a reference... Figures 1 to 11 The lower electrode 10 described is substantially the same and can be used with... Figures 1 to 11 The lower electrode 10 is formed in essentially the same way. (See reference) Figure 17 The lower electrode 10 can conform to the shape of the base electrode SE; for example, the lower electrode 10 can be deposited in a manner that follows the shape of the base electrode SE.

[0079] refer to Figure 12 and Figure 18 A dielectric layer 30 can be formed to cover the lower electrode 10. The dielectric layer 30 can collectively cover multiple lower electrodes 10. The dielectric layer 30 can be connected to a reference electrode. Figures 1 to 11 The dielectric layer 30 described is substantially the same and can be connected with... Figures 1 to 11 The dielectric layer 30 is formed in essentially the same way. (See reference) Figure 16 The dielectric layer 30 can be conformally shaped to the lower electrode 10; for example, the dielectric layer 30 can be deposited in a manner that follows the shape of the lower electrode 10.

[0080] refer to Figure 12 and Figure 19 An upper electrode 50 can be formed on the dielectric layer 30. The upper electrode 50 can be connected to a reference electrode. Figures 1 to 11 The described upper electrode 50 is substantially the same and can be used with Figures 1 to 11 The upper electrode 50 is formed in essentially the same way. (See reference) Figure 19 The upper electrode may conform to the shape of the dielectric layer 30 and / or may completely fill the opening 378h. A semiconductor memory device with a capacitor CAP can be formed by forming the upper electrode 50, which includes a base electrode SE, a lower electrode 10, a dielectric layer 30, and an upper electrode 50. Other processes (not shown) may include planarizing the upper surface of the upper electrode 50 (e.g., planarization by etch-back and / or CMP processes). The capacitor CAP may be used as, as, or correspond to a memory element of a DRAM cell; however, the example embodiments are not limited thereto.

[0081] According to some exemplary embodiments of the present invention, the contact surface of the lower electrode in contact with the dielectric layer can be controlled to reduce the leakage current of the semiconductor device and improve the reliability of the semiconductor device.

[0082] While the inventive concept has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made within the spirit and scope of the inventive concept. Accordingly, it is intended that the present embodiments be taken only by way of example and not limiting. Therefore, the scope of the inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be limited or restricted to the foregoing description of the preferred embodiments.

Claims

1. A semiconductor device, comprising: substrate; as well as A capacitor, on the substrate, comprising a lower electrode, a dielectric layer, and an upper electrode sequentially stacked on the substrate. The lower electrode includes ABO3, where "A" is a first metallic element and "B" is a second metallic element, and the work function of the second metallic element is greater than that of the first metallic element. The dielectric layer includes CDO3, where "C" is the third metal element and "D" is the fourth metal element; The lower electrode comprises an alternating and repeatedly stacked first and second layer; The first layer comprises the first metallic element and oxygen; The second layer comprises the second metallic element and oxygen; and The dielectric layer is in contact with the lower electrode at the first contact surface, and the first contact surface corresponds to the second layer.

2. The semiconductor device according to claim 1, wherein, The first contact surface has a {100} crystal plane.

3. The semiconductor device according to claim 1, wherein, Each of the lower electrode and the dielectric layer has a perovskite crystal structure.

4. The semiconductor device according to claim 1, wherein, The dielectric layer comprises alternating and repeating stacked third and fourth layers; The third layer includes the third metallic element and oxygen; The fourth layer includes the fourth metallic element and oxygen; and The dielectric layer is in contact with the lower electrode at the second contact surface, which corresponds to the third layer.

5. The semiconductor device according to claim 4, wherein, The work function of the fourth metal element is greater than that of the third metal element.

6. The semiconductor device according to claim 1, wherein, The work function of the second metal element is greater than that of the fourth metal element.

7. The semiconductor device according to claim 1, wherein, The work function of the second metallic element is greater than 4.5 eV and less than 6 eV.

8. The semiconductor device according to claim 1, wherein, The first metallic element is at least one of Sr, Ba, La or Ca.

9. The semiconductor device according to claim 1, wherein, The second metallic element is at least one of Ru, Mo, Ir, Co, or Ni.

10. The semiconductor device according to claim 1, wherein, The third metallic element is at least one of Ba, Sr, or Ca.

11. The semiconductor device according to claim 1, wherein, The fourth metallic element is at least one of Ti, Zr, or Hf.

12. The semiconductor device of claim 1, wherein the thickness of the lower electrode is between 50 Å and 100 Å.

13. The semiconductor device according to claim 1, wherein, The capacitor further includes a base electrode; and The lower electrode covers the sidewall of the base electrode and the top surface of the base electrode.

14. A semiconductor device, comprising: substrate; as well as A capacitor, on the substrate, comprising a lower electrode, a dielectric layer, and an upper electrode sequentially stacked on the substrate. The lower electrode comprises a first metal element, a second metal element, and oxygen; The dielectric layer comprises a third metal element, a fourth metal element, and oxygen. The lower electrode comprises an alternating and repeatedly stacked first and second layer; The first layer comprises the first metal element and oxygen, and the second layer comprises the second metal element and oxygen; The first metallic element is at least one of Sr, Ba, La, or Ca, and the second metallic element is at least one of Ru, Mo, Ir, Co, or Ni; and The dielectric layer is in contact with the lower electrode at the first contact surface, and the first contact surface corresponds to the second layer.

15. The semiconductor device according to claim 14, wherein, The dielectric layer comprises alternating and repeating stacked third and fourth layers; The third layer includes the third metallic element and oxygen; The fourth layer includes the fourth metallic element and oxygen; and The dielectric layer contacts the lower electrode at the second contact surface, which corresponds to one of the third or fourth layers. The work function of the third or fourth layer is less than the work function of the other layer.

16. The semiconductor device according to claim 14, wherein, The third metallic element is at least one of Ba, Sr, or Ca; and The fourth metallic element is at least one of Ti, Zr, or Hf.

17. The semiconductor device according to claim 14, wherein, The capacitor further includes a base electrode; and The lower electrode covers the sidewall of the base electrode and the top surface of the base electrode.

18. A semiconductor device, comprising: A first wire is embedded in the upper part of the substrate, and the first wire extends along a first direction; An active portion in the upper part of the substrate, the active portion being defined by a device isolation pattern, the active portion including a first doped region and a second doped region spaced apart from each other, the first wire being inserted between the first doped region and the second doped region; The second wire on the substrate extends along a second direction intersecting the first direction and is connected to the first doped region; Contact element, connected to the second doped region; as well as The capacitor on the substrate is connected to the second doped region via the contact element. The capacitor includes a lower electrode, a dielectric layer, and an upper electrode that are sequentially stacked on the substrate. The lower electrode includes ABO3, where "A" is a first metallic element and "B" is a second metallic element, and the work function of the second metallic element is greater than that of the first metallic element. The dielectric layer includes CDO3, where "C" is the third metal element and "D" is the fourth metal element; The lower electrode comprises an alternately and repeatedly stacked first layer and a second layer, the first layer comprising the first metal element and oxygen, and the second layer comprising the second metal element and oxygen; and The dielectric layer is in contact with the lower electrode at the first contact surface, and the first contact surface corresponds to the second layer.

19. The semiconductor device according to claim 18, wherein, The dielectric layer comprises alternating and repeatedly stacked third and fourth layers; the third layer comprises the third metal element and oxygen; and the fourth layer comprises the fourth metal element and oxygen; and The work function of the fourth metal element is greater than that of the third metal element.

20. The semiconductor device according to claim 18, wherein, The first metallic element is at least one of Sr, Ba, La or Ca; The second metallic element is at least one of Ru, Mo, Ir, Co, or Ni; The third metallic element is at least one of Ba, Sr, or Ca; and The fourth metallic element is at least one of Ti, Zr, or Hf.

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