Resonant voltage decay detection circuit, semiconductor device for switching power supply, and switching power supply device

Abstract

The present application provides a kind of resonant voltage attenuation detection circuit, switching power supply semiconductor device and switching power supply device, which can realize the power supply device with high average power efficiency and without hum. The switching power supply semiconductor device generates driving signal for the on-off control of the switching element connected in series with the primary winding of the voltage transformation transformer with auxiliary winding, and is provided with resonant voltage attenuation detection circuit, which is input the voltage induced in the auxiliary winding of the transformer, and detects the attenuation of resonant voltage, the switching power supply semiconductor device has: on-off control circuit, which generates the timing signal for the on of the switching element based on the attenuation detection signal output by resonant voltage attenuation detection circuit;And off control circuit, which generates the timing signal for the off of switching element, the switching power supply semiconductor device can operate in quasi-resonant mode.

Description

Technical Field

[0001] This invention relates to a resonant voltage decay detection circuit for detecting the decay of resonance generated in a winding with intermittent current flow, a semiconductor device (power control IC) for a switching power supply, and a switching power supply device. In particular, it relates to a power control IC for controlling the switching elements on the primary side of a DC power supply device equipped with a voltage conversion transformer, a resonant voltage decay detection circuit effectively integrated into the power control IC, and a switching power supply device using the power control IC. Background Technology

[0002] A DC power supply device includes an isolated switching power supply device consisting of a diode bridge circuit that rectifies AC power and a DC-DC converter that converts the rectified DC voltage into a desired DC voltage. Examples of isolated switching power supplies include those that control the current flowing in the primary winding by switching on and off a switching element connected in series with the primary winding of a voltage conversion transformer using PWM (Pulse Width Modulation) control or quasi-resonant control methods, thereby controlling the voltage induced in the secondary winding.

[0003] In existing switching power supply devices employing PWM control, control is performed by switching between PWM control and PFM (Pulse Frequency Modulation) control. On the other hand, inventions related to existing switching power supply devices employing quasi-resonant control include, for example, those described in Patent Documents 1 and 2. As described in Patent Documents 1 and 2, existing switching power supply devices employing quasi-resonant control are configured to operate only in quasi-resonant control mode.

[0004] PWM control and quasi-resonant control each have their advantages and disadvantages. For example, while PWM control has disadvantages such as high switching losses and noise, and slightly lower power efficiency, it has the advantage of low noise, operation even in continuous current mode, and suppression of transformer current peaks, thus allowing for a reduction in transformer size. On the other hand, quasi-resonant control has the disadvantage of increased size of components such as transformers and output capacitors due to the noise generated by bottom skip and operation only in discontinuous current mode. However, it has the advantage of low switching losses and noise, and good power efficiency due to soft switching (soft turn-on) at the bottom of the zero-current resonant voltage.

[0005] In addition, there is an invention related to a switching power supply device that is configured for PWM control during the soft start period when the power is started, and switches to quasi-resonant control in frequency control mode after the soft start period ends, thereby eliminating audible frequency band oscillation (Patent Document 3).

[0006] However, it is desirable to have a switching power supply device in which the primary-side control IC (semiconductor device) switches between PWM control and quasi-resonant control during normal operation after power-on, thereby combining the advantages of both control methods.

[0007] Therefore, the applicant of this application has filed an application for the following invention of a semiconductor device for a switching power supply and a switching power supply device, which uses a transformer with an auxiliary winding, monitors the voltage induced in the auxiliary winding (including the voltage after voltage division), and switches between PWM control and quasi-resonant control during normal operation after power-on, thereby reducing the size of components such as transformers and realizing the miniaturization of power supply devices (Japanese Patent Application No. 2018-188861).

[0008] The inventors of this invention subsequently studied the semiconductor device for switching power supplies and the switching power supply device described in the prior art, which achieved the desired effect when applied to a power supply device where the output voltage remains constant without change. However, when applied to a power supply device, for example, that has the function of switching the output voltage (e.g., 5V and 20V) as specified in the USB-PD standard, the voltage induced in the auxiliary winding of the transformer is lower on average when the output voltage is switched to a lower voltage (e.g., 5V).

[0009] Therefore, the amplitude of the resonance generated in the auxiliary winding may sometimes be smaller. Consequently, the circuit may sometimes operate under critical conditions where the amplitude of the resonance can or cannot be detected by a predetermined threshold voltage. Moreover, in this case, the following problems exist: there is a mixture of cases where the switching element on the primary winding side is disconnected by detecting the amplitude of the resonance and cases where the switching element is disconnected according to the timer period instead of detecting the amplitude of the resonance. The switching period varies greatly, the output voltage pulsation increases, or a buzzing sound is generated.

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2014-124038

[0011] [Patent Document 2] U.S. Patent No. 9601983

[0012] [Patent Document 3] Japanese Patent Application Publication No. 2011-78240 Summary of the Invention

[0013] The purpose of this invention is to provide a resonant voltage decay detection circuit capable of detecting the decay of resonance generated in a winding with intermittent current flow.

[0014] Another object of the present invention is to provide a semiconductor device for a switching power supply with low switching loss and switching noise and good power efficiency, as well as a switching power supply device.

[0015] Another object of the present invention is to provide a semiconductor device for a switching power supply and a switching power supply device that can suppress humming even when the amplitude of the resonance decreases, resulting in a critical condition where the amplitude of the resonance can or cannot be detected by a predetermined threshold voltage, by switching the output voltage.

[0016] Another object of the present invention is to provide a semiconductor device for a switching power supply and a switching power supply device that achieves high average power efficiency and miniaturization of the power supply device by switching between PWM control and quasi-resonant control during normal operation after power-on, thereby reducing the size of components such as transformers.

[0017] To achieve the above objectives, the first invention of this application is a resonant voltage attenuation detection circuit that detects the attenuation of the resonant voltage of a transformer winding.

[0018] The resonant voltage attenuation detection circuit includes:

[0019] A first voltage comparison circuit compares the voltage of the winding with a predetermined first voltage; and

[0020] The timeout circuit performs a timing operation corresponding to the output of the first voltage comparator circuit.

[0021] The timeout circuit is configured to output an attenuation detection signal when a preset time has been elapsed. This preset time is shorter than the time required for the peak voltage of the winding to attenuate from the first voltage to a predetermined second voltage that is lower than the first voltage.

[0022] The resonant voltage decay detection circuit based on this structure can reliably detect the decay of resonance generated in a winding with intermittent current flow.

[0023] Preferably, the timeout circuit includes: a constant current source; a capacitor element capable of being charged by the current from the constant current source; a switch capable of discharging the charged charge of the capacitor element; and a second voltage comparison circuit that compares the voltage of the capacitor element with a predetermined voltage.

[0024] The switch is turned on and off according to the output of the first voltage comparison circuit.

[0025] The output signal of the second voltage comparison circuit is used as the attenuation detection signal.

[0026] Based on this structure, the timing time of the timeout circuit can be arbitrarily set according to the current value of the constant current source and the capacitance value of the capacitor element.

[0027] The second invention of this application is a semiconductor device for a switching power supply, which generates a drive signal for controlling the switching on and off of a switching element connected in series with the primary winding of a voltage conversion transformer having an auxiliary winding.

[0028] The semiconductor device for the switching power supply includes a resonant voltage attenuation detection circuit. This circuit is input with the voltage induced in the auxiliary winding and detects the attenuation of the resonant voltage.

[0029] The semiconductor device for the switching power supply has:

[0030] The control circuit, based on the attenuation detection signal output by the resonant voltage attenuation detection circuit, generates a timing signal to turn on the switching element; and

[0031] The disconnect control circuit generates a timing signal that causes the switching element to disconnect.

[0032] The semiconductor device for the switching power supply is capable of operating in a quasi-resonant mode.

[0033] The semiconductor device for switching power supplies based on this structure can realize a DC power supply device with low switching losses and switching noise and good power efficiency.

[0034] Here, the resonant voltage attenuation detection circuit preferably includes:

[0035] A voltage comparison circuit compares the voltage of the auxiliary winding with a predetermined first voltage; and

[0036] The timeout circuit performs a timing action corresponding to the output of the voltage comparator circuit.

[0037] The timeout circuit is configured to start timing at the point when the voltage comparison circuit detects that the peak voltage of the auxiliary winding is lower than the first voltage, and to output an attenuation detection signal when the time required for the voltage of the auxiliary winding to decrease from the first voltage to a predetermined second voltage lower than the first voltage is longer than the period of the resonant voltage but shorter than the predetermined time.

[0038] According to this structure, the attenuation of resonance generated in the winding with intermittent current flow can be reliably detected by the resonant voltage attenuation detection circuit, and the switching element can be turned on at an appropriate timing.

[0039] The third invention of this application is a semiconductor device for a switching power supply that generates a drive signal for controlling the switching on and off of a switching element connected in series with the primary winding of a voltage conversion transformer having an auxiliary winding.

[0040] The semiconductor device for the switching power supply includes:

[0041] The first external terminal is input with a feedback voltage corresponding to the voltage output from the secondary side of the transformer;

[0042] The second external terminal is input with the voltage induced in the auxiliary winding;

[0043] A resonance detection circuit that detects the resonance of the voltage in the auxiliary winding based on the voltage at the second external terminal;

[0044] A resonant voltage attenuation detection circuit detects the attenuation of the resonant voltage of the auxiliary winding based on the voltage of the second external terminal;

[0045] The control circuit generates a timing signal to turn on the switching element based on the detection signal from the resonant detection circuit and the detection signal from the resonant voltage decay detection circuit.

[0046] The disconnection control circuit generates a timing signal to disconnect the switching element based on the voltage at the first external terminal and a voltage proportional to the current flowing through the switching element; and

[0047] A drive pulse generation circuit generates a pulse signal that forms the basis of the drive signal based on the output signal of the on control circuit and the output signal of the off control circuit.

[0048] By generating a timing signal near the bottom of the resonance of the voltage in the auxiliary winding by the turn-on control circuit, the switching element can be turned on, enabling operation in a quasi-resonant mode.

[0049] The semiconductor device for switching power supplies based on this structure can realize a DC power supply device with low switching losses and switching noise and good power efficiency.

[0050] Preferably, a timer circuit is included, which counts the time corresponding to the voltage at the first external terminal.

[0051] The turn-on control circuit is configured to generate a timing signal that turns on the switching element based on the detection signal from the resonant detection circuit, the detection signal from the resonant voltage attenuation detection circuit, and the output signal from the timer circuit.

[0052] When the resonant voltage attenuation detection circuit does not detect attenuation of the resonant voltage, the drive pulse generation circuit is controlled so that after the output of the timer circuit changes, the pulse signal rises at the timing of the detection output of the resonant detection circuit.

[0053] When the resonant voltage decay detection circuit detects the decay of the resonant voltage, it controls the driving pulse generation circuit so that the pulse signal rises in time with the change in the output of the timer circuit.

[0054] According to this structure, the switching element is turned on in quasi-resonant mode when no attenuation of the resonant voltage is detected, and the switching element is turned on in PWM mode when attenuation of the resonant voltage is detected. Therefore, the average power efficiency can be improved, and the size of components such as transformers can be reduced, thereby realizing the miniaturization of the power supply device.

[0055] Furthermore, the resonance detection circuit preferably includes a first voltage comparison circuit that compares the voltage at the second external terminal with a predetermined first voltage, and outputs a resonance detection signal when the voltage at the second external terminal is lower than the first voltage.

[0056] The resonant voltage decay detection circuit includes: a second voltage comparison circuit that compares the voltage at the second external terminal with a predetermined second voltage that is higher than the first voltage; and a timing circuit capable of timing for a predetermined time shorter than the timing time of the timer circuit.

[0057] The timing circuit is configured to start timing when the peak voltage of the second external terminal is detected by the second voltage comparator circuit to be lower than the second voltage. If the time required for the voltage at the second external terminal to decrease from the second voltage to the first voltage is longer than the period of the resonant voltage but shorter than the predetermined time required for attenuation, an attenuation detection signal is output.

[0058] The turn-on control circuit is configured to control the drive pulse generation circuit to raise the timing pulse signal when the attenuation detection signal is output before the timer circuit has counted a predetermined time.

[0059] According to this structure, even if the amplitude of the resonance decreases, creating a critical condition where the amplitude of the resonance can or cannot be detected by a predetermined threshold voltage, the switching period will not change significantly, thus preventing increased output voltage ripple or buzzing. Furthermore, in cases where the zero-current resonance period is relatively long, the attenuation of the resonant voltage of the auxiliary winding can be detected to ensure the switching element is turned on at an appropriate timing.

[0060] Furthermore, the resonant voltage attenuation detection circuit preferably includes: a delay circuit that delays the signal output from the driving pulse generation circuit; and a logic circuit that, based on the output signal of the delay circuit, temporarily disables the supply of the detection signal output from the second voltage comparison circuit to the timing circuit.

[0061] Similarly, the resonant detection circuit may also be configured to include: a delay circuit that delays the signal output from the driving pulse generation circuit; and a logic circuit that, based on the output signal of the delay circuit, disables the output of the detection signal from the first voltage comparison circuit.

[0062] Based on the above structure, it is possible to prevent unwanted actions such as false detections in the resonance detection circuit that accompany the ringing that occurs immediately after the voltage of the auxiliary winding (the drain voltage of the switching element) rises.

[0063] Furthermore, it is preferable that the delay circuit delays the signal obtained by inverting the signal output from the driving pulse generation circuit.

[0064] The resonant voltage decay detection circuit includes: a latch circuit that takes in the output signal of the delay circuit at the point where the second voltage comparison circuit drops; and a logic circuit that obtains the logical sum of the output signal of the latch circuit and the output signal of the timing circuit.

[0065] According to this structure, since there are more conditions for operation in continuous current mode, the size of the transformer can be reduced, and the components can be miniaturized and the cost reduced.

[0066] In addition, it is preferable to set the timing of the timer circuit to be longer when the voltage of the first external terminal is low and shorter when the voltage of the first external terminal is high, based on the voltage of the first external terminal.

[0067] According to this structure, when the voltage of the first external terminal (FB) is high, the timing time of the timer circuit becomes shorter, and when the voltage of the first external terminal is low, the timing time of the timer circuit becomes longer. Therefore, during normal operation after the power supply is started, PWM control and quasi-resonant control can be switched, the average power efficiency can be improved, and the size of components such as transformers can be reduced, thereby realizing the miniaturization of the power supply device.

[0068] The fourth invention of this application is a switching power supply device comprising: a switching power supply semiconductor device having the above-described structure; a transformer having an auxiliary winding for applying a voltage obtained by rectifying an AC voltage to a primary winding; and a switching element connected to the primary winding. The switching power supply device is configured to control the switching element using the switching power supply semiconductor device to output a predetermined voltage to the secondary winding side, and to switch the magnitude of the output voltage on the secondary winding side based on an external signal.

[0069] According to this structure, in a switching power supply device that can switch the output voltage, switching the output voltage can prevent the output voltage pulsation from becoming large or the humming from occurring.

[0070] According to the present invention, a resonant voltage decay detection circuit capable of detecting the decay of resonance generated in a winding with intermittent current flow can be provided. Furthermore, a semiconductor device for a switching power supply and a switching power supply device with low switching losses and switching noise, and good power efficiency can be provided.

[0071] Furthermore, a semiconductor device for a switching power supply and a switching power supply device are provided that, even when the amplitude of the resonance decreases, creating a critical condition where the amplitude of the resonance can or cannot be detected by a predetermined threshold voltage, the switching period will not change significantly, thus suppressing the increase of output voltage ripple or the generation of buzzing.

[0072] In addition, the semiconductor device and the switching power supply device are capable of achieving the following effects: during normal operation after power-on, the semiconductor device and the switching power supply device achieve high average power efficiency by switching between PWM control and quasi-resonant control, and can reduce the size of components such as transformers, thereby achieving miniaturization of the power supply device. Attached Figure Description

[0073] Figure 1 This is a circuit diagram illustrating one embodiment of a DC-DC converter that is an effective DC power supply device using the semiconductor device for switching power supplies of the present invention.

[0074] Figure 2 It means in Figure 1 A functional block diagram of a first embodiment of the semiconductor device for switching power supplies of the present invention, which is disposed on the primary side of a transformer in a DC-DC converter.

[0075] Figure 3 It is a waveform diagram used to illustrate the appropriate detection timing of the resonant detection circuit constituting a semiconductor device for a switching power supply.

[0076] Figure 4This is a circuit diagram showing a specific example of a timeout circuit constituting a semiconductor device for a switching power supply.

[0077] Figure 5 This is a circuit diagram showing a specific example of a timer circuit that constitutes a semiconductor device for a switching power supply.

[0078] Figure 6 (A) and (B) are circuit structure diagrams representing specific examples of the turn-on control circuits of the semiconductor devices for switching power supplies that constitute the first and second embodiments, respectively.

[0079] Figure 7 This is a circuit structure diagram illustrating a specific example of the disconnection trigger generation circuit of the semiconductor device for the switching power supply constituting the first and second embodiments.

[0080] Figure 8 (A) is a graph showing the relationship between the voltage at the FB terminal in the semiconductor device for the switching power supply according to the first embodiment and the timing time of the timer circuit. Figure 8 (B) is a graph showing the relationship between the voltage at the FB terminal and the threshold value of Vcs when the trigger generation circuit is disconnected.

[0081] Figure 9 This is a timing diagram showing the signal changes of each part when the semiconductor device for the switching power supply of the first embodiment operates under the condition that the voltage at the FB terminal is sufficiently high and the amplitude of the resonant voltage is large.

[0082] Figure 10 This is a timing diagram showing the signal changes of each part of the semiconductor device for the switching power supply in the first embodiment when the voltage at the FB terminal is low.

[0083] Figure 11 This is a timing diagram showing the signal changes of each part of the semiconductor device for switching power supply in the first embodiment when the voltage at the FB terminal is high and the amplitude of the resonant voltage is small.

[0084] Figure 12 It means in Figure 1 A circuit diagram of a second embodiment of the semiconductor device for switching power supplies of the present invention, which is disposed on the primary side of the transformer in a DC-DC converter.

[0085] Figure 13 (A) is a circuit structure diagram showing a specific example of the attenuation detection circuit for the resonant voltage of the semiconductor device for the switching power supply in the second embodiment. Figure 13 (B) is a waveform diagram showing the relationship between the resonant voltage and the reference voltage in the attenuation detection circuit of the embodiment.

[0086] Figure 14This is a timing diagram showing the changes in signals of each part in the semiconductor device for switching power supplies in the second embodiment, when the timer circuit starts timing before the zero-current resonant voltage decays.

[0087] Figure 15 It is a timing diagram showing the changes in signals of each part when the timer circuit starts timing after the zero-current resonant voltage decays.

[0088] Figure 16 It is a timing diagram showing the changes in signals of each part when the timer circuit starts timing under the condition of low voltage (low output voltage) at the DMG terminal during the demagnetization period of the secondary winding.

[0089] Figure 17 It is a timing diagram showing the changes in signals of each part when the timer circuit starts timing under the condition that the voltage at the DMG terminal is sufficiently high (high output voltage) during the demagnetization of the secondary winding.

[0090] Figure 18 It means Figure 12 Functional block diagram of a modified example of a semiconductor device for a switching power supply according to the second embodiment.

[0091] Figure 19 It constitutes Figure 18 The circuit structure diagram of a specific example of a resonant voltage attenuation detection circuit for a semiconductor device used in a switching power supply is shown in the modified example.

[0092] Figure 20 It means in Figure 18 In a modified example of a semiconductor device for a switching power supply, a timing diagram showing the changes in signals of various components when the timer circuit starts timing under conditions where the voltage at the DMG terminal is sufficiently high (high output voltage) during the demagnetization of the secondary winding.

[0093] Figure 21 (A) is a graph showing the characteristics of the peak turn-on current (peak current flowing through the primary winding) relative to the load current in the semiconductor device for switching power supplies in the second embodiment and the modified embodiment. Figure 21 (B) is a graph showing the switching frequency characteristics of the semiconductor device for switching power supply in the second embodiment and the modified embodiment, relative to the load current output to the load. Detailed Implementation

[0094] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[0095] Figure 1 This is a circuit diagram showing one embodiment of a DC-DC converter of a DC power supply device that uses a semiconductor device for a switching power supply according to the present invention.

[0096] The DC-DC converter of this embodiment includes: a pair of voltage input terminals 11 for inputting DC voltage; a voltage conversion transformer 12 having a primary winding Np, a secondary winding Ns, and an auxiliary winding Nb; a switching transistor SW1 connected in series with the primary winding Np of the transformer 12; and a switching power supply semiconductor device (hereinafter referred to as a power control IC) 13 for driving the switching transistor SW1 to turn on and off. When configuring the switching power supply device, a diode bridge circuit and a smoothing capacitor for rectifying the AC voltage from the AC power supply are connected in front of the input terminals 11.

[0097] In this embodiment, the switching transistor SW1 is a discrete component composed of an N-channel MOSFET (Insulated Gate Field Effect Transistor). The power control IC 13 is provided with a gate drive signal output terminal GATE for driving the gate of transistor SW1.

[0098] Furthermore, in the DC-DC converter of this embodiment, a rectification and smoothing circuit is provided on the primary side of the transformer 12. This rectification and smoothing circuit consists of a rectifier diode D1 connected in series with the auxiliary winding Nb and a smoothing capacitor C1 connected between the cathode terminal of the diode D1 and the ground point GND. The voltage rectified and smoothed by this rectification and smoothing circuit is applied to the power supply voltage terminal VDD of the power control IC 13. In addition, the power control IC 13 is provided with an external terminal DMG for the applied voltage VDMG, which is obtained by dividing the voltage induced in the auxiliary winding Nb by resistors R1 and R2.

[0099] Furthermore, the power control IC13 is provided with an external terminal FB for connecting a phototransistor (light-receiving element) PT. This phototransistor PT constitutes an optocoupler for transmitting the output detection signal from the secondary side as a feedback voltage VFB to the primary side.

[0100] In addition, the power control IC13 is provided with an external terminal CS as a current sensing terminal. This external terminal CS is input with voltage Vcs after current-to-voltage conversion through a current sensing resistor Rs connected between the source terminal of the switching transistor SW1 and the ground point GND.

[0101] On the other hand, a rectifier diode D2 connected in series with the secondary winding Ns is provided on the secondary side of the transformer 12, and a smoothing capacitor C2 is connected between the cathode terminal of the diode D2 and another terminal of the secondary winding Ns. The AC voltage induced in the secondary winding Ns by the intermittent flow of current in the primary winding Np is rectified and smoothed, thereby generating and outputting a DC voltage Vout.

[0102] Furthermore, a constant voltage control circuit (shunt regulator) 14 constituting an output voltage detection circuit for detecting the output voltage Vout is provided on the secondary side of the transformer 12, and a photodiode (light-emitting element) PD constituting an optocoupler for transmitting the output voltage detection signal corresponding to the detection voltage of the constant voltage control circuit 14 to the primary side.

[0103] A current corresponding to the detection voltage of the photodiode PD flows through the constant voltage control circuit 14, and is transmitted to the primary side as a light signal with an intensity corresponding to the detection voltage. A current corresponding to the light intensity then flows through the phototransistor PT, and through the pull-up resistor inside the power control IC13 (…). Figure 2 The Rp) is converted into voltage VFB and then input.

[0104] The constant voltage control circuit 14 includes: a bipolar transistor TR1 connected in series with a photodiode PD; resistors R3 and R4 that divide the output voltage Vout on the secondary side; an error amplifier AMP0 that compares the divided voltage with a reference voltage Vref0 and outputs a voltage corresponding to the potential difference; and a phase compensation circuit 14a. This constant voltage control circuit 14 is configured to apply the output voltage of the error amplifier AMP0 to the base terminal of the transistor TR1, allowing a current corresponding to the output voltage Vout to flow through it. In this embodiment, the higher the output voltage Vout on the secondary side, the greater the current flowing through the photodiode PD and the phototransistor PT, and the lower the voltage VFB at the external terminal FB of the power control IC 13.

[0105] Furthermore, in this embodiment, although not specifically limited, an output voltage switching circuit is provided that supplies a switching signal to the constant voltage control circuit 14 based on the output voltage switching signal VC from the load device side. By switching the reference voltage Vref0 according to the switching signal from the output voltage switching circuit, the output voltage Vout can be switched to, for example, 5V or 20V for output. Here, the structure of the secondary side circuit can also be a synchronous rectification method in which the rectifier diode D2 is replaced with a switch.

[0106] (First embodiment)

[0107] Next, use Figures 2 to 11 illustrate Figure 1 The first embodiment of the power control IC13 for the primary side of the power supply device describes the functional block structure and the function of each block.

[0108] like Figure 2As shown, the power control IC 13 of this embodiment includes: a resonance detection circuit 31, which has a comparator (voltage comparison circuit) for detecting resonance by monitoring the voltage VDMG of the external terminal DMG; a timeout circuit 32, which starts timing based on the detected resonance and causes the output signal to rise when a predetermined time T2 has elapsed; an FB comparator 33, which compares the voltage VFB of the external terminal FB with a predetermined reference voltage VFBREF and determines whether VFB is below VFBREF; and a timer circuit 34, which generates the switching cycle of the switching element SW1 by timing for a time corresponding to the voltage VFB of the external terminal FB. The timeout circuit 32 is a circuit provided to forcibly turn on the switching element SW1 if the resonance detection circuit 31 has not detected resonance before the timer circuit 34 has elapsed for a predetermined time T1.

[0109] In addition, the power control IC13 includes: an on-control circuit 35, which takes the output signals of the resonant detection circuit 31, the timeout circuit 32, the FB comparator 33, and the timer circuit 34 as inputs to generate a timing signal that turns on the switching element SW1; an off-trigger generation circuit 36, which takes the voltage VFB of the external terminal FB and the voltage Vcs of the external terminal CS as input voltages to generate a timing signal that turns off SW1; a latch circuit 37, which is composed of an RS flip-flop that takes the output of the on-control circuit 35 and the output of the off-trigger generation circuit 36 ​​as inputs; and a driver circuit 38, which generates a gate drive signal for driving the switching element SW1 based on the output EN of the latch circuit 37 and outputs it from the external terminal GATE.

[0110] Furthermore, the output EN of the latch circuit 37 is input to the timer circuit 34 as a signal to activate the timer circuit 34, and also input to the power-on control circuit 35 as a signal to reset the power-on control circuit 35. Specific examples and operations of each of the above functional blocks will be explained below.

[0111] The resonant detection circuit 31 in the functional blocks 31 to 38 of the power control IC13 can be, for example, constructed by a comparator (voltage comparison circuit). This comparator compares, for example, the voltage VDMG at the external terminal DMG with a predetermined reference voltage VDMGREF, and the output changes to a low level (or a high level) when VDMG exceeds VDMGREF.

[0112] Here, the resonance detection circuit 31 is a circuit provided for detecting the timing of turning on the switching element SW1 in quasi-resonant mode. Therefore, it is preferably configured to detect... Figure 3(A) shows the bottom of the resonance of the drain voltage VD of the switching element SW1 (the part marked with ○). However, sometimes the drain voltage VD of SW1 exceeds 500V depending on the specifications of the power supply device. Even with voltage division, the losses will increase and the components will become larger. Furthermore, the center value of the resonant voltage depends on the input voltage, making it difficult to set a reference in the semiconductor device and difficult to detect the bottom in the semiconductor device based on the drain voltage VD.

[0113] Therefore, in this embodiment, an external terminal DMG is provided for inputting the voltage VDMG obtained by dividing the voltage appearing in the auxiliary winding Nb of transformer 12 through resistors R1 and R2, and this voltage VDMG is monitored. Furthermore, as described above, a comparator is used as the resonance detection circuit 31 to detect the waveform of the resonant VDMG, such as... Figure 3 As shown in (B), the reference voltage VDMGREF is set to a value slightly higher than 0V (zero volts).

[0114] The resonant voltage of the auxiliary winding Nb varies around 0V, making it easy to set a reference voltage VDMGREF in the semiconductor device. Furthermore, semiconductor devices typically have diodes (ESD protection diodes) on external terminals to prevent electrostatic discharge (ESD). In the power control IC13 of this embodiment, for example… Figure 2 As shown, an ESD protection diode DESD is provided at the DMG terminal. The forward voltage of the diode DESD clamps the voltage at the DMG terminal to approximately -0.7V.

[0115] When using a comparator as the resonant detection circuit 31, it is preferable to set the reference voltage VDMGREF by considering the delay (td) of the comparator, driver, switch turn-on, etc., so that the switching element SW1 can be turned on at the bottom of the drain voltage VD. Therefore, in this embodiment, as Figure 3 As shown in (B), the reference voltage VDMGREF is set to a voltage slightly higher than 0V.

[0116] Furthermore, in this embodiment, a comparator is used to detect the voltage VDMG obtained by resistive voltage division of the voltage appearing in the auxiliary winding Nb, slightly ahead of the bottom, but a predetermined phase of resonance can also be detected. When detecting the timing of the turn-on based on the phase of resonance, the detection circuit can be configured such that the resonance start is set to 0°, enabling detection within a range of 90° to 180°.

[0117] exist Figure 4 The diagram shows a specific circuit structure example of the timeout circuit 32. For example... Figure 4As shown, the timeout circuit 32 includes: a constant current source CC0 and a capacitor C0 connected in series with the constant current source CC0; a MOS transistor M0 connected in parallel with the capacitor C0; an inverter INV0 that inverts the output signal of the resonance detection circuit 31 and applies it to the gate terminal of the MOS transistor M0; and a comparator CMP0 that applies the voltage of the connection node N0 of the constant current source CC0 and the capacitor C0 to the non-inverting input terminal and applies the reference voltage VTOREF to the inverting input terminal.

[0118] In this timeout circuit 32, the MOS transistor M0 is normally turned on, the voltage at node N0 is low (ground potential), and the output TO of comparator CMP0 is also low. However, when the resonance detection circuit 31 detects resonance and the output signal RSN changes to a high level, the MOS transistor M0 turns off, thus starting a predetermined time T2. Capacitor C0 is charged through constant current source CC0. When the voltage at node N0 gradually rises and exceeds the reference voltage VTOREF, the output TO of comparator CMP0 changes to a high level. The time from the start of capacitor C0 charging to the voltage at node N0 reaching the reference voltage VTOREF is the timeout period T2 of the timeout circuit 32.

[0119] Figure 5 An example of the specific circuit structure of timer circuit 34 is shown. For example... Figure 5 As shown, the timer circuit 34 includes: an amplifier circuit 341, which includes an operational amplifier (operational amplifier circuit) AMP2 that amplifies the voltage VFB at the external terminal FB, voltage divider resistors R7 and R8 that divide the output of the operational amplifier, and a reference voltage Vref1 disposed between resistor R8 and ground to increase the voltage at the connection node N1 of R7 and R8 by a predetermined amount; a clamping circuit 342 that performs operational amplification on the output voltage of the amplifier circuit 341 and clamps it; and a variable timer 343. The clamping circuit 342 is composed of an operational circuit with voltage clamping function.

[0120] The variable timer 343 includes: a voltage-to-current converter unit that converts the output voltage of the clamping circuit 342 into a current, comprising an operational amplifier AMP3, a MOS transistor M1, and a resistor R9; a current mirror circuit that generates a current proportional to the converted current, consisting of MOS transistors M2 and M3; a capacitor C3 that is charged by the current through the MOS transistor M3; and a discharge switch S3 for discharging the charge of the capacitor C3.

[0121] In addition, the variable timer 343 includes: two comparators CMP3 and CMP4 that take the charging voltage of capacitor C3 as input; RS flip-flops FF1 and FF2 that latch the outputs of comparators CMP3 and CMP4 respectively; and an AND gate G1 that takes the output of comparator CMP4 and the inverted output / Q of RS flip-flop FF2 as input.

[0122] The discharge switch S3 is switched on and off via the output of flip-flop FF1. RS flip-flop FF1 is set via the output of comparator CMP3, and RS flip-flop FF2 is set via the output of AND gate G1. Furthermore, RS flip-flops FF1 and FF2 are reset via the output EN of latch circuit 33. The circuit is configured such that when RS flip-flop FF1 is reset, the discharge switch S3 is opened, thus starting the timing.

[0123] The comparison voltage Vref2 applied to the inverting input terminal of comparator CMP3 and the comparison voltage Vref3 applied to the non-inverting input terminal of comparator CMP3 are set to a relationship of Vref2 > Vref3. When the charging voltage of capacitor C3 reaches Vref3, assuming FF2 is reset, the RS flip-flop FF2 is set through the output of CMP4, and its output changes from low to high. The output of FF2 is provided as a timeout signal TIM to the aforementioned turn-on control circuit 35. Alternatively, when the charging voltage of capacitor C3 reaches Vref2, the RS flip-flop FF1 is set through the output of CMP3, and its output changes from low to high, turning on the discharge switch S3, thereby discharging the charged charge of capacitor C3.

[0124] exist Figure 8 (A) shows the relationship between the time T1, which is timed by the timer circuit 34, and the voltage VFB at the external terminal FB. Figure 8 As shown in (A), the timing time T1 of the timer circuit 34 is designed to be related to the voltage VFB at the external terminal FB as indicated by the dashed line. Furthermore, the maximum value of the timing time T1 is limited by the clamping voltage VMIN applied to the clamping circuit 342, and the minimum value is limited by the clamping voltage VMAX (VMAX > VMIN) applied to the clamping circuit 342. Additionally, the clamping circuit 342 provides a T1-VFB curve between VMIN and VMAX through its operational functions.

[0125] Therefore, the higher the voltage VFB at the external terminal FB (the smaller the load current on the secondary side), the shorter the timing time of the timer circuit 34. As will be explained below, in this embodiment, this timing time is used as the switching cycle in PWM mode (continuous current mode) and also as the zero-current detection period in quasi-resonant mode (discontinuous current mode). Thus, in the switching power supply device using the power control IC13 of this embodiment, the reciprocal of the timing time T1 of the timer circuit 34 becomes the switching frequency.

[0126] exist Figure 6 Example of a specific circuit structure for the power control IC 13's on-time control circuit 35 according to the first embodiment is shown in (A). Figure 6 As shown in (A), the turn-on control circuit 35 includes: an OR gate G2 that takes the output signal TO of the timeout circuit 32 and the output signal FBL of the FB comparator 33 as inputs; an AND gate G3 that takes the output signal of the OR gate G2 and the output signal TIM of the timer circuit 34 as inputs; a flip-flop FF3 that takes the output signal TIM of the timer circuit 34 as input at the data terminal D and the signal after the output signal EN of the latch circuit 37 is inverted by the inverter INV1 as input at the reset terminal; and an OR gate G4 that takes the output signal of the flip-flop FF3 and the output signal of the AND gate G3 as inputs.

[0127] In the turn-on control circuit 35 of this embodiment, the trigger FF3 receives the output signal RSN of the resonance detection circuit 31 at the clock terminal. Therefore, it synchronously receives the input signal of the data terminal D, namely the output signal TIM of the timer circuit 34, with the rising of the output signal RSN of the resonance detection circuit 31. Thus, when the output signal RSN of the resonance detection circuit 31 rises, if the output signal TIM of the timer circuit 34 is at a high level, the output SET, which serves as the turn-on signal, changes to a high level.

[0128] Furthermore, assuming the output signal TIM of timer circuit 34 is high, when timeout circuit 32 times out and its output signal TO changes to high, the output SET of control circuit 35 changes to high. Additionally, when the output signal FBL of FB comparator 33 is high (i.e., the voltage VFB at external terminal FB is lower than the reference voltage VFBREF), the output SET changes to high due to the change of timer circuit 34's output signal TIM to high. Then, when the output SET of control circuit 35 changes to high... Figure 2 When latch circuit 37 is set, the output of driver circuit 38, i.e., the gate drive signal (GATE), changes to a high level, and switching element SW1 is turned on. Furthermore, in the following... Figure 6 The second embodiment of (B) will be described using the turn-on control circuit.

[0129] Figure 7 The diagram shows a specific circuit structure example of the disconnect trigger generation circuit 36. For example... Figure 7 As shown, the disconnect trigger generation circuit 36 ​​is configured, for example, to include: an amplifier circuit consisting of an operational amplifier AMP1 and voltage divider resistors R5 and R6 that divide the output voltage of the operational amplifier AMP1, amplifying the voltage Vcs at the external terminal CS; and a comparator CMP1 that compares the output voltage of the amplifier circuit with the voltage VFB at the external terminal FB. Voltage divider resistors R5 and R6 are provided between the output terminal of the operational amplifier AMP1 and the ground point. The output voltage of the operational amplifier AMP1 is amplified to a voltage Vcs' such that the voltage at the connection node of the voltage divider resistors R5 and R6 is made consistent with the voltage Vcs at the non-inverting input terminal through a virtual grounding operation. Then, when the output voltage Vcs' of the operational amplifier AMP1 exceeds VFB, the output RST of the comparator CMP1 changes to a high level.

[0130] Figure 8 (B) illustrates the relationship between the threshold voltage Vcs of the external terminal CS in the disconnect trigger generation circuit 36 ​​(Vcs voltage when disconnected) and the voltage VFB of the external terminal FB. Figure 8 As shown in (B), the threshold voltage Vcs is proportional to the voltage VFB; the higher the voltage VFB, the higher the threshold voltage Vcs. The slope of the straight line representing the relationship between the threshold voltage Vcs and the voltage VFB can be obtained through... Figure 7 The resistance ratio of the voltage divider resistors R5 and R6 is adjusted.

[0131] Next, use Figure 9 and Figure 10 The timing diagram illustrates the operation of IC13, a power control IC with the above-described structure. Figure 9 This indicates the signal changes of various parts of the power control IC13 when the voltage VFB at external terminal FB is high and the amplitude of the resonance occurring in the voltage VDMG at external terminal DMG is sufficiently large. Figure 10 This indicates the signal changes of various parts of the power control IC13 when the voltage VFB at the external terminal FB is low, but the resonance amplitude of the voltage VDMG at the external terminal DMG is relatively large.

[0132] exist Figure 9In the timing circuit, after timer circuit 34 completes timing at t11 ​​and t14, and its output signal TIM changes from low to high, at timings t12 and t15, when the initial voltage VDMG becomes lower than the reference voltage VDMGREF and the output RSN of the resonant detection circuit 31 changes to high, the output SET of the turn-on control circuit 35 changes to high, the output EN of the latch circuit 37 changes to high, and the gate drive signal (GATE) output from the driver circuit 38 changes to high, turning on the switching element SW1. Furthermore, when the output EN of the latch circuit 37 changes to high, the flip-flop FF2 of timer circuit 34 is reset, and the TIM signal changes to low (t12, t15). Additionally, flip-flop FF1 is also reset, and the discharge switch S3 is opened, thus starting the timing of the next cycle.

[0133] Additionally, when the switching element SW1 is turned on, current flows through the primary winding of the transformer, and the potential of the sensing resistor, i.e., the voltage Vcs at the external terminal CS, gradually increases. At timings t13 and t16 when the output voltage Vcs' of the amplifier AMP1 of the disconnected trigger generation circuit 36 ​​reaches the voltage VFB at the external terminal FB, the output RST of the disconnected trigger generation circuit 36 ​​changes from low level to high level, the gate drive signal (GATE) output by the driver circuit 38 changes to low level, and the switching element SW1 is turned off.

[0134] Thus, in Figure 9 In this case, at the bottom of the resonance point detected by the resonance detection circuit 31 after the voltage VDMG at the external terminal DMG begins to resonate, the switching element SW1 is turned on. Therefore, the power control IC13 performs switching control in quasi-resonant mode. Furthermore, in Figure 9 In this case, because the voltage VFB of the external terminal FB is high, the timing time T1 of the timer circuit 34 becomes shorter, thus the switching cycle becomes shorter, and the on-time of the switching element SW1 becomes relatively longer relative to the cycle.

[0135] On the other hand, when the voltage VFB at the external terminal FB is low, the timing time T1 of the timer circuit 34 becomes longer, but by setting the output voltage Vout high, for example, to 25V, ... Figure 10 As shown, when the voltage VDMG at the external terminal DMG is relatively high during the demagnetization period of the secondary winding Ns, after the demagnetization period of the secondary winding Ns of the transformer ends at time t21 and zero-current resonance begins, the timer circuit 34 starts timing for the set time T1 before the resonance detection circuit 31 can detect the resonance.

[0136] Therefore, at the time point (t22) when the timer circuit 34 has timed the set time T1, the output signal TIM of the timer circuit 34 changes to a high level. Then, when TIM changes to a high level, the turn-on trigger signal SET changes to a high level, the output EN of the latch circuit 37 changes to a high level, the gate drive signal (GATE) output from the driver circuit 38 changes to a high level, and the switching element SW1 is turned on.

[0137] Additionally, when the switching element SW1 is turned on, current flows through the primary winding of the transformer, the voltage drop in the sensing resistor Rs increases, and the voltage Vcs at the external terminal CS gradually increases. Then, at timing t23 when the output voltage Vcs' of the amplifier AMP1 of the disconnect trigger generation circuit 36 ​​reaches the voltage VFB at the external terminal FB, the output RST of the disconnect trigger generation circuit 36 ​​changes from low to high, the gate drive signal (GATE) output by the driver circuit 38 changes to low, and the switching element SW1 is turned off. Thus, in Figure 10 In this case, when the timer circuit 34 has timed the set time T1, the switching element SW1 is turned on, so the power control IC13 switches in PWM mode.

[0138] As can be seen from the above description of operation, the turn-on control circuit 35 functions as a switching unit between PWM mode and quasi-resonant mode. Furthermore, in the power control IC 13 of this embodiment, by appropriately designing the timing time T1 of the timer circuit 34, it can operate in PWM mode in the region where the load current is close to 100% of the rated load current, and in quasi-resonant mode when it is less than 100%. In addition, in power supply devices using the power control IC 13 of this embodiment, the power efficiency of PWM mode is worse than that of quasi-resonant mode. Therefore, the power supply device is inefficient when operating near 100% of the rated load current. However, it operates in quasi-resonant mode with good power efficiency in areas such as 75%, 50%, and 25%. Therefore, compared to a power supply device operating in PWM mode throughout the entire region, it has the advantage of improving average power efficiency.

[0139] Furthermore, regarding the size of transformer 12, it needs to be the size required for the core to be unsaturated when the winding current flowing through the primary winding is at its maximum. A larger winding current requires a larger transformer. Because quasi-resonant mode inherently operates in a discontinuous current mode, the switching frequency decreases near the rated load, resulting in a larger peak winding current. In contrast, in PWM mode, due to continuous current operation, the frequency does not decrease even near the rated load, thus the peak winding current is smaller than in quasi-resonant mode, allowing the transformer size to be smaller compared to a single quasi-resonant mode.

[0140] Furthermore, the higher the frequency of the output capacitor, the lower the impedance and the better the suppression of output ripple. Therefore, as mentioned above, the frequency is higher when operating in PWM mode near the rated load compared to operating in quasi-resonant mode, thus suppressing the capacitance and size of the output capacitor.

[0141] However, in the switching power supply device using the power control IC13 of the first embodiment described above, by switching the output voltage Vout to a low voltage such as 5V, Figure 11 As shown, when the voltage VDMG of the external terminal DMG is low during the demagnetization period of the secondary winding Ns, and resonance begins after the demagnetization period of the secondary winding Ns of the timing t31 transformer ends, sometimes the resonance detection circuit 31 may or may not be able to detect resonance when it reaches near the reference voltage VDMGRE.

[0142] When such a state occurs at the end of the set time T1 of the timer circuit 34, the following situations exist: as with timer t32, when resonance is initially detected after the timer circuit 34 has timed the set time T1, the output TIM of the timer circuit 34 changes to a high level, and the turn-on signal SET rises, thereby turning on the switching element SW1; or, before the timer circuit 34 has timed the set time T1, resonance cannot be detected, and timer t33, which is when the timeout circuit 32 has timed the set time T2, causes the turn-on signal SET to rise, thereby turning on the switching element SW1; sometimes, the above two actions coexist.

[0143] Here, if the timer setting time T1 is set to 25μs and T2 is set to 9μs, then the minimum value of period TP1 is 25μs and the maximum value of period TP2 is 34μs. Therefore, under the critical condition of whether resonance can be detected, there is a mixed existence of switching periods between 25μs and 34μs, resulting in undesirable conditions such as large pulsation of the output voltage or buzzing.

[0144] Therefore, an improved power control IC is considered to eliminate the aforementioned drawbacks. Hereinafter, as a second embodiment, a power control IC is used... Figures 12-17 The improved power control IC is described in detail.

[0145] (Second Embodiment)

[0146] Figure 12 The structure of the functional block of IC13 for power control according to the second embodiment is shown.

[0147] Figure 12 The power control IC shown in the second embodiment has the same characteristics as... Figure 2The power control IC shown in the first embodiment has a structure that is substantially the same. (And...) Figure 2 The difference between the power control IC of the first embodiment shown is that the power control IC of the second embodiment does not have the FB comparator 33 found in the power control IC of the first embodiment, but instead includes an attenuation detection circuit 39 for monitoring the voltage VDMG of the external terminal DMG to detect the attenuation of the resonant voltage. Furthermore, in Figure 12 The power control IC 13 of the second embodiment shown does not show the timeout circuit 32 of the power control IC of the first embodiment. However, in the second embodiment, the attenuation detection circuit 39 is configured to have the same function as the timeout circuit 32 of the first embodiment. Therefore, the substantial difference is that the FB comparator 33 is replaced by the attenuation detection circuit 39.

[0148] Figure 13 (A) shows a specific circuit example of the attenuation detection circuit 39.

[0149] like Figure 13 As shown in (A), the attenuation detection circuit 39 of this embodiment has a connection with the attenuation detection circuit 39 of the embodiment. Figure 4 The structure is the same as the structure after replacing the inverter INV0 in the timeout circuit 32 shown with the comparator CMP5.

[0150] The comparator CMP5 compares the voltage VDMG obtained by dividing the voltage of the auxiliary winding Nb input to the external terminal DMG with a predetermined reference voltage VDMGREF2. If the voltage VDMG at the external terminal DMG is lower than the reference voltage VDMGREF2, the output changes to a low level, the MOS transistor M0 turns off, and the subsequent timeout circuit (M0, CC0, C0, CMP0) starts timing.

[0151] like Figure 13 As shown in (B), the reference voltage VDMGREF2 applied to the inverting input terminal of comparator CMP5 is set to be higher than the voltage VDMGREF1 (e.g., 0.1V) and higher than the resonant amplitude, as shown in (B). Figure 13 The dashed line B in (B) represents the voltage required for VDMGREF2 to decay to VDMGREF1 in a time Ta that is sufficiently short and longer than the resonant period. This voltage VDMGREF1 is set to a voltage that enables the switching element to turn on at the bottom of the resonance, taking into account delays (td) from the comparator, driver, and switch activation. Specifically, assuming a decay time Ta of 40 μs and a resonant period of 5 μs, the timing time T2 of the timeout circuit (M0, CC0, C0, CMP0) can be set, for example, to 9 μs. In this case, the reference voltage VDMGREF2 is set to 0.5V.

[0152] like Figure 6 As shown in (B), the control circuit 35 is configured to switch on from Figure 6 In the first embodiment of (A), the OR gate G2 is omitted in the turn-on control circuit 35, and the output ATT of the attenuation detection circuit 39 is input to the AND gate G3.

[0153] The resonance detection circuit 31, timer circuit 34, disconnect trigger generation circuit 36, latch circuit 37, and driver circuit 38 can have the same structure as in the first embodiment; therefore, they will be used in the following embodiments. Figures 14-17 The timing diagram is used to illustrate the operation of the power control IC13 of the second embodiment equipped with the above-described attenuation detection circuit 39.

[0154] exist Figure 14 A timing diagram is shown, which illustrates the signal changes of each part in the switching power supply control IC13 of the second embodiment when the timer circuit 34 starts timing before the zero-current resonant voltage decays.

[0155] exist Figure 14 In the timing diagram, the comparator CMP5 of the resonance detection circuit 31 and the attenuation detection circuit 39 detects the resonance of VDMG at time t41. The output RSN of the resonance detection circuit 31 and the output ATCMP of the comparator CMP5 are inverted. Moreover, the timeout circuit (M0, CC0, C0, CMP0) of the attenuation detection circuit 39 starts timing for a predetermined set time T2 each time the output ATCMP of CMP5 drops. However, since the output ATCMP rises before the timing of T2, the period Tb during which ATCMP is judged to be low is shorter than the predetermined time T2, that is, the resonance of VDMG has not attenuated, and the output ATT of the attenuation detection circuit 39 remains low.

[0156] Therefore, after the timer circuit 34 starts timing and the output TIM changes to a high level at timing t42, the resonance detection circuit 31 initially detects the resonance at timing t43, the output SET of the turn-on control circuit 35 changes to a high level, the latch circuit 37 is set, and the switching element SW1 is turned on. Then, the trigger generation circuit 36 ​​detects a voltage Vcs' proportional to the voltage Vcs at terminal CS ( Figure 7 When the output of amplifier AMP1 reaches the voltage VFB at terminal FB at timing t44, the latch circuit 37 is reset and the switching element SW1 is disconnected.

[0157] Through the actions described above, the power control IC13 operates in quasi-resonant mode under these conditions.

[0158] exist Figure 15A timing diagram is shown, which illustrates the signal changes of each part in the switching power supply control IC13 of the second embodiment when the timer circuit 34 has completed the timing of the set time T1 after the zero current resonant voltage decays.

[0159] exist Figure 15 In the timing diagram, the comparator CMP5 of the resonance detection circuit 31 and the attenuation detection circuit 39 detects the resonance of VDMG at time t51, and the output RSN of the resonance detection circuit 31 and the output ATCMP of the comparator CMP5 are inverted. Moreover, the timeout circuit of the attenuation detection circuit 39 starts timing for time T2 each time the output ATCMP of CMP5 decreases. However, when the resonance is attenuating, even if time T2 has been completed, ATCMP will not rise. Therefore, the attenuation detection circuit 39 judges it as the resonance attenuation of VDMG, and the output ATT changes to a high level at time t52 after timing T2.

[0160] Therefore, simultaneously with the timing t53 when the timer circuit 34 starts timing and the output TIM changes to a high level, the output SET of the turn-on control circuit 35 changes to a high level, the latch circuit 37 is set, and the switching element SW1 is turned on. Then, the trigger generation circuit 36 ​​detects a voltage Vcs' proportional to the voltage Vcs at terminal CS. Figure 7 When the output of amplifier AMP1 reaches the voltage VFB at terminal FB at timing t54, the latch circuit 37 is reset and the switching element SW1 is disconnected.

[0161] By performing the aforementioned actions, when the zero-current resonance period is relatively longer, the attenuation of VDMG can be detected, thereby turning on the switching element SW1.

[0162] exist Figure 16 A timing diagram is shown in the figure, which illustrates the signal changes of each part in the switching power supply control IC13 of the second embodiment, where the output voltage Vout is set to a low value (e.g., 5V), so that the voltage VDMG of the external terminal DMG is lower than the reference voltage VDMGREF2 in the attenuation detection circuit 39 during the demagnetization of the secondary winding of the transformer 12, and the timer circuit 34 has completed the timing of the set time T1 during the demagnetization period.

[0163] exist Figure 16In the timing diagram, it is determined that the output ATCMP of comparator CMP5 of the attenuation detection circuit 39 remains at a low level, while the output ATT of comparator CMP0 remains at a high level, indicating that the voltage VDMG is attenuating. Therefore, at timings t61 and t63, timer circuit 34 times the set time T1, causing its output TIM to change to a high level. At the same time, the output SET of the turn-on control circuit 35 changes to a high level, latch circuit 37 is set, and switching element SW1 is turned on. That is, it operates in the so-called continuous current mode with SW1 on during the demagnetization of the secondary winding. Then, when the trigger generation circuit 36 ​​is turned off, it detects a voltage Vcs' proportional to the voltage Vcs at terminal CS. Figure 7 The output of amplifier AMP1 reaches the voltage VFB at terminal FB at timings t62 and t64, which resets latch circuit 37 and disconnects switching element SW1.

[0164] Through the actions described above, the power control IC13 operates in PWM mode under these conditions.

[0165] exist Figure 17 A timing diagram is shown in the figure, which illustrates the signal changes of each part in the switching power supply control IC13 of the second embodiment when the output voltage Vout is set to a high value (e.g., 25V), so that the voltage VDMG of the external terminal DMG is sufficiently higher than the reference voltage VDMGREF2 in the attenuation detection circuit 39 during the demagnetization of the secondary winding of the transformer 12, and the timer circuit 34 starts timing during the demagnetization period.

[0166] exist Figure 17 In the timing diagram, the resonant detection circuit 31 detects a decrease in VDMG at timings t71 and t73, and its output RSN changes to a high level. On the other hand, the comparator CMP5 output ATCMP of the attenuation detection circuit 39 remains high during the demagnetization period T3 of the secondary winding, while the comparator CMP0 output ATT remains low, indicating that the voltage VDMG has not attenuated. Therefore, after the timer circuit 34 starts timing at timing t72, the demagnetization of the secondary winding ends, thus entering zero-current resonance. The output TIM of the VDMG decrease timing circuit t73 changes to a low level, the output SET of the turn-on control circuit 35 changes to a high level, the latch circuit 37 is set, and the switching element SW1 is turned on.

[0167] Then, upon disconnecting the trigger generation circuit 36, a voltage Vcs' proportional to the voltage Vcs at terminal CS is detected. Figure 7 When the output of amplifier AMP1 reaches the voltage VFB at terminal FB at timing t74, the latch circuit 37 is reset and the switching element SW1 is disconnected.

[0168] Through the actions described above, the power control IC13 operates in PWM mode under these conditions.

[0169] In the power control IC of the second embodiment, it operates in PWM mode near the rated load, and otherwise in quasi-resonant mode. This allows for suppression of the capacitance value and size of the capacitor connected to the secondary output terminal. Furthermore, the power control IC according to the second embodiment has the advantage that, when the output voltage Vout is switched, the attenuation of the resonant voltage can be detected without changing the reference voltage VDMGREF2 of the comparator CMP5 in the attenuation detection circuit 39.

[0170] (Variation example)

[0171] Figure 18 The diagram shows the structure of a functional block of a modified example of the power control IC13 of the second embodiment. Additionally, Figure 19 The circuit structure example of the attenuation detection circuit 39 in the power control IC13 of this modified example is shown.

[0172] like Figure 18 As shown, in this modified example of the power control IC13, a terminal for the output EN of the input latch circuit 37 is provided in the attenuation detection circuit 39. Furthermore, the attenuation detection circuit 39 having this EN input terminal is as follows... Figure 19 It is constructed as shown. (And) Figure 13 By comparing the attenuation detection circuit 39 of the power control IC13 shown in (A) with that of the second embodiment described above, it can be seen that the attenuation detection circuit 39 of this modified example has a relative Figure 13 The circuit shown in (A) has an additional section of circuit structure enclosed by dashed lines.

[0173] Specifically, in the attenuation detection circuit 39 of the power control IC13 in this modified example, such as Figure 19 As shown, the following structure is added: an inverter INV2 that logically inverts the output EN of latch circuit 37; a delay circuit DLY that delays the output of inverter INV2 by a short time Td of about 1 to 3 μs; an AND gate G5 that takes the logical multiplication of the output ATCMP of comparator CMP5 and the output / EN_DEL of the delay circuit DLY, wherein comparator CMP5 compares the voltage VDMG of external terminal DMG with the reference voltage VDMGREF2; an inverter INV3 that inverts the output of comparator CMP5; a flip-flop FF4 that takes the output of inverter INV3 as a clock signal and inputs it into the output / EN_DEL of delay circuit DLY; and an OR gate G6 that takes the logical sum of the inverted output / Q of flip-flop FF4 and the output of comparator CMP0.

[0174] exist Figure 20 A timing diagram is shown in the figure, which illustrates the changes in the signals of each part in the power control IC13 of this variant when the output voltage Vout is set to a high voltage value (e.g., 25V) so that the voltage VDMG of the external terminal DMG is sufficiently higher than the reference voltage VDMGREF2 in the attenuation detection circuit 39 during the demagnetization of the secondary winding of the transformer 12, and when the timer circuit 34 starts timing during the demagnetization period.

[0175] exist Figure 20 In the timing diagram, at timer t81, the output EN of latch circuit 37 changes to a high level, thus turning on switching element SW1. This causes resonant detection circuit 31 to detect a drop in voltage VDMG, and its output RSN changes to a high level. Furthermore, RSN changes to a low level at timer t83 when VDMG rises.

[0176] In the power control IC13 of this variant, in the attenuation detection circuit 39, the delay circuit DLY generates a signal / EN_DEL that delays the inverted signal of the output EN of the latch circuit 37 by Td. Based on this signal, the shielding period of the ringing RG immediately after the voltage VDMG of the external terminal DMG rises is set. Furthermore, due to the drop (t82) in the output ATCMP of comparator CMP5, the delayed signal / EN_DEL of the delay circuit DLY is latched by trigger FF4, and the inverted output / Q of FF4 changes to a high level (illustration omitted).

[0177] Therefore, the output ATCMP of comparator CMP5 changes to a high level during the demagnetization period of the secondary winding T3, but the inverted output / Q of flip-flop FF4 keeps the output ATT of OR gate G6 high. Figure 6 (B) The AND gate G3 of the turn-on control circuit 35 is opened, and the timer circuit 34 outputs TIM to a high level at the same time that the timer circuit 34 completes the timing. Figure 20 When the output SET of the control circuit 35 changes to a high level (t84), the latch circuit 37 is set, and the output EN of the latch circuit 37 changes to a high level, thus turning on the switching element SW1. The disconnection operation is the same as in the second embodiment described above.

[0178] In the flyback power supply device as described in the above embodiments, such as Figure 20As shown, immediately after the switch is turned off, ringing RG occurs in the drain voltage VD of the switching element SW1 and the voltage VGMD of the terminal DMG due to the leakage inductance of the transformer and the capacitive component of its surrounding components. Therefore, the resonance detection circuit 31 may falsely detect the signal. However, in the switching power supply control IC13 of this modified example, since the AND gate G5 is used to shield the ringing period immediately after the voltage VDMG rises through the output signal of the delay circuit DLY, accidental operation such as false detection by the resonance detection circuit 31 can be prevented. Alternatively, the same circuit as the delay circuit DLY and the AND gate G5 described above can be incorporated into the resonance detection circuit 31, thereby achieving the same effect of avoiding false operation caused by the ringing of the voltage VDMG.

[0179] Furthermore, in the power control IC13 of the second embodiment described above, except when the voltage VDMG of the external terminal DMG becomes below the reference voltage VDMGREF2 during demagnetization (see reference... Figure 16 Apart from that, it only operates in the current discontinuous mode, but... Figure 18 and Figure 19 In the power control IC13 of the modified example shown, since a delay circuit DLY, a flip-flop FF4, and an OR gate G6 are provided, for example, according to Figure 20 It can be seen that, in addition to the conditions mentioned above (VDMG < VDMGREF2), operation in continuous current mode is also possible. Therefore, it has the advantages of reducing transformer size, miniaturizing components, and reducing costs.

[0180] Figure 21 (A) and (B) show the characteristics of the peak current flowing through the primary winding relative to the load current and the switching frequency characteristics of the power control IC of the second embodiment and the power control IC of the modified embodiment described above. Figure 21 In (A) and (B), the dashed line represents the characteristics of the power control IC of the second embodiment, and the solid line represents the characteristics of the power control IC of the modified example.

[0181] according to Figure 21 As can be seen from (A), in the power control IC of the modified example, even if the load current increases, the peak value of the current flowing through the primary winding does not increase much. Therefore, compared with the power control IC of the second embodiment, the transformer of the power control IC of the modified example is less likely to saturate, thus having the advantages of enabling transformer miniaturization and using low-rated and inexpensive components for the switching element SW1.

[0182] In addition, according to Figure 21As can be seen from (B), the power control IC of the second embodiment has a lower switching frequency in the region of high load current, but the power control IC of the modified embodiment does not have a lower switching frequency in the region of high load current and can maintain a high state. Therefore, the power control IC of the modified embodiment has the following advantages compared with the power control IC of the second embodiment: it can reduce the output voltage ripple, and relative to the standard value of the predetermined output voltage ripple, it can use a capacitor with a small capacitance value and low cost as the output capacitor.

[0183] The invention described above is based on specific embodiments, but the invention is not limited to the above embodiments. For example, in the above embodiments, the voltage obtained by dividing the voltage of the auxiliary winding through resistors R1 and R2, which are external components, is input to the external terminal DMG. However, the voltage of the auxiliary winding can also be directly input to the external terminal DMG. Alternatively, the voltage obtained by dividing the voltage through a resistor element installed inside the power control IC, or the voltage obtained by dividing the voltage through a resistor element installed inside the power control IC and an external resistor element, can be input to the external terminal DMG.

[0184] Furthermore, in the above embodiment, the switching transistor SW1 and the current sensing resistor Rs are different components from the power control IC 13. However, the switching transistor SW1 can also be integrated into the power control IC 13 to form a single semiconductor integrated circuit (with the current sensing resistor Rs being an external component), or the switching transistor SW1 and the current sensing resistor Rs can be integrated into the power control IC 13. Alternatively, the voltage Vcs can be generated and detected by detecting the drain current based on the drain voltage of the internal switching transistor SW1, thereby replacing the use of the current sensing resistor Rs.

[0185] Furthermore, in the above embodiments, the present invention was described as being applied to a switching power supply device that has the function of switching output voltage, but the present invention can also be applied to a switching power supply device that does not have the function of switching output voltage.

[0186] Explanation of reference numerals in the attached figures

[0187] 12 Transformer, 13 Semiconductor device for switching power supply (IC for power control), 14 Constant voltage control circuit, 31 Resonance detection circuit, 32 Timeout circuit, 33 FB comparator, 34 Timer circuit, 35 Turn-on control circuit, 36 Turn-off trigger generation circuit (turn-off control circuit), 37 Latch circuit (pulse generation circuit for drive), 38 Driver circuit, 39 Attenuation detection circuit (resonance voltage attenuation detection circuit).

Claims

1. A semiconductor device for a switching power supply, comprising generating a drive signal for controlling the on / off switching of a switching element connected in series with the primary winding of a voltage conversion transformer having an auxiliary winding. Its features are, The semiconductor device for the switching power supply includes: The resonant voltage attenuation detection circuit is input with the voltage induced in the auxiliary winding to detect the attenuation of the resonant voltage. A timer circuit that performs timing corresponding to the time of the voltage output from the secondary side of the transformer; The control circuit generates a timing signal to turn on the switching element based on the attenuation detection signal output by the resonant voltage attenuation detection circuit and the output signal of the timer circuit. as well as The disconnect control circuit generates a timing signal that causes the switching element to disconnect. When the resonant voltage decay detection circuit does not detect the decay of the resonant voltage, after the output of the timer circuit changes, a timing signal is generated to turn on the switching element when the resonant detection circuit initially detects resonance. When the resonant voltage decay detection circuit detects the decay of the resonant voltage, a timing signal is generated to turn on the switching element when the output of the timer circuit changes.

2. The semiconductor device for a switching power supply according to claim 1, characterized in that, The resonant voltage attenuation detection circuit includes: A first voltage comparison circuit compares the voltage of the auxiliary winding with a predetermined first voltage; and The timeout circuit performs a timing operation corresponding to the output of the first voltage comparator circuit. The timeout circuit is configured to start timing when the first voltage comparison circuit detects that the peak voltage of the auxiliary winding is lower than the first voltage. If the time required for the voltage of the auxiliary winding to decrease from the first voltage to a predetermined second voltage lower than the first voltage is longer than the period of the resonant voltage and shorter than the preset timing time of the timeout circuit, the circuit outputs an attenuation detection signal.

3. The semiconductor device for a switching power supply according to claim 2, characterized in that, The timeout circuit includes: Constant current source; A capacitor element that can be charged by the current from the constant current source; A switch that can discharge the charged charge of the capacitor element; as well as The second voltage comparison circuit compares the voltage of the capacitor element with a predetermined voltage. The switch is turned on and off according to the output of the first voltage comparison circuit. The output signal of the second voltage comparison circuit is used as the attenuation detection signal.

4. A semiconductor device for a switching power supply, comprising generating a drive signal for controlling the on / off switching of a switching element connected in series with the primary winding of a voltage conversion transformer having an auxiliary winding. Its features are, The semiconductor device for the switching power supply includes: The first external terminal is input with a feedback voltage corresponding to the voltage output from the secondary side of the transformer; The second external terminal is input with the voltage induced in the auxiliary winding; A resonance detection circuit that detects the resonance of the voltage in the auxiliary winding based on the voltage at the second external terminal; A resonant voltage attenuation detection circuit detects the attenuation of the resonant voltage of the auxiliary winding based on the voltage of the second external terminal; The control circuit generates a timing signal to turn on the switching element based on the detection signal from the resonant detection circuit and the detection signal from the resonant voltage decay detection circuit. The disconnection control circuit generates a timing signal that disconnects the switching element based on the voltage at the first external terminal and a voltage proportional to the current flowing through the switching element. A driving pulse generation circuit generates a pulse signal that forms the basis of the driving signal based on the output signal of the turn-on control circuit and the output signal of the turn-off control circuit. as well as A timer circuit that performs timing corresponding to the voltage at the first external terminal. The turn-on control circuit is configured to generate a timing signal that turns on the switching element based on the detection signal from the resonant detection circuit, the detection signal from the resonant voltage attenuation detection circuit, and the output signal from the timer circuit. When the resonant voltage attenuation detection circuit does not detect attenuation of the resonant voltage, the driving pulse generation circuit is controlled so that after the output of the timer circuit changes, the pulse signal rises when the resonant detection circuit initially detects resonance. When the resonant voltage decay detection circuit detects the decay of the resonant voltage, it controls the driving pulse generation circuit so that the pulse signal rises when the output of the timer circuit changes.

5. The semiconductor device for a switching power supply according to claim 4, characterized in that, The resonance detection circuit includes a first voltage comparison circuit that compares the voltage at the second external terminal with a predetermined first voltage, and outputs a resonance detection signal when the voltage at the second external terminal is lower than the first voltage. The resonant voltage attenuation detection circuit includes: The second voltage comparison circuit compares the voltage of the second external terminal with a predetermined second voltage that is higher than the first voltage. as well as A timing circuit capable of timing for a predetermined period shorter than the timing duration of the timer circuit. The timing circuit is configured to start timing when the peak voltage of the second external terminal is detected by the second voltage comparator circuit to be lower than the second voltage. If the time required for the voltage at the second external terminal to decrease from the second voltage to the first voltage is longer than the period of the resonant voltage but shorter than the predetermined time required for attenuation, an attenuation detection signal is output. The turn-on control circuit is configured to control the drive pulse generation circuit to increase the pulse signal when the attenuation detection signal is output before the timer circuit has counted a predetermined time, in the case that the timer circuit has counted a predetermined time.

6. The semiconductor device for a switching power supply according to claim 5, characterized in that, The resonant voltage attenuation detection circuit includes: A delay circuit that delays the signal output from the driving pulse generation circuit; and A logic circuit, based on the output signal of the delay circuit, disables the supply of the detection signal output from the second voltage comparison circuit to the timing circuit.

7. The semiconductor device for a switching power supply according to claim 5, characterized in that, The resonant detection circuit includes: A delay circuit that delays the signal output from the driving pulse generation circuit; and A logic circuit that, based on the output signal of the delay circuit, temporarily disables the output of a detection signal from the first voltage comparison circuit.

8. The semiconductor device for a switching power supply according to claim 6, characterized in that, The delay circuit delays the signal obtained by inverting the signal output from the driving pulse generation circuit. The resonant voltage attenuation detection circuit includes: A latching circuit that takes in the output signal of the delay circuit when the output of the second voltage comparator circuit decreases; and A logic circuit that obtains the logical sum of the output signal of the latch circuit and the output signal of the timing circuit.

9. The semiconductor device for a switching power supply according to any one of claims 4 to 8, characterized in that, The timing of the timer circuit is set to increase when the voltage of the first external terminal is low and decrease when the voltage of the first external terminal is high, based on the voltage of the first external terminal.

10. A switching power supply device, characterized by comprising: have: The semiconductor device for a switching power supply according to any one of claims 4 to 9; A transformer, which has an auxiliary winding, applies an alternating current voltage to the primary winding to obtain a voltage; and A switching element, which is connected to the primary winding, The switching power supply device is configured to control the switching element by using the semiconductor device for the switching power supply, thereby outputting a predetermined voltage to the secondary winding side, and being able to switch the magnitude of the output voltage on the secondary winding side based on signals from the outside.

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