Methods for fabricating advanced substrates for hybrid integration

Abstract

The method comprises the following steps: providing an acceptor substrate (20) and a donor substrate (10), wherein the donor substrate (10) comprises, in sequence: a carrier substrate (11), a sacrificial layer (12) capable of being selectively etched relative to an active layer (13), and a silicon oxide layer (14) disposed on the active layer (13); forming a cavity in the oxide layer (14) so ​​as to form a first portion (14a) having a first thickness and a second portion (14b) having a second thickness greater than the first thickness; filling the cavity with polysilicon (40) so as to form a continuous and substantially flat surface (41); assembling the acceptor substrate (20) and the donor substrate (10) on the surface (41); and removing the carrier substrate (11) while retaining the active layer (13) and the sacrificial layer (12).

Description

Technical Field

[0001] The present invention relates to the field of manufacturing semiconductor components of the SOI (acronym for Silicon On Insulator) type and in particular to the field of manufacturing advanced substrates for hybrid integration of components configured for different applications or functions. Background Art

[0002] The SOI structure generally comprises an active layer of silicon in which the components themselves are located and below which a buried silicon oxide layer is placed. The buried silicon oxide layer constitutes an insulation with respect to parasitic currents and charges originating from ionized particles. The buried silicon oxide layer also allows good insulation of adjacent components manufactured in the same silicon layer and, in particular, significantly reduces the parasitic capacitance between such adjacent components. The buried silicon oxide layer itself is located on a silicon substrate that serves as a mechanical support.

[0003] This type of substrate is usually made by Smart Cut TM The method comprises the following steps:

[0004] - providing a carrier substrate,

[0005] - providing a single crystal silicon donor substrate,

[0006] - forming a weakened zone in the donor substrate so as to define the future active layer in the weakened zone (the weakened zone may be formed by implanting atomic substances at a defined depth in the donor substrate),

[0007] - bonding the first donor substrate to the carrier substrate after forming an oxide layer on the carrier substrate or on the donor substrate or on both, the oxide layer being intended to form a buried oxide layer,

[0008] - separation of the first donor substrate along the weakened zone, resulting in transfer of the active layer to the carrier substrate,

[0009] - Finishing treatment of the transferred layer in order to repair or remove defects related to the separation step and to achieve optimal roughness and thickness characteristics on said layer, so as to obtain the final SOI type substrate on which the intended components will be integrated.

[0010] The finishing treatment generally comprises: a thermal treatment aimed at correcting defects caused by the implantation and separation methods, which is accomplished by chemical mechanical polishing, which aims to improve the surface roughness of the transferred layer while helping to bring its thickness to the target value; or a thermal treatment aimed at bringing the thickness of the transferred layer to the target thickness, which can be accomplished by additional thermal treatments at high temperatures (generally above 1100° C.), which aim to smooth the surface of the active layer by thermally activated diffusion of silicon atoms.

[0011] Typically, the thickness of the transferred silicon active layer is typically in the range of several nanometers to several hundred nanometers, while the thickness of the buried oxide layer is in the range of approximately ten nanometers to several hundred nanometers (typically 1000 nm) or more.

[0012] The thickness of the active layer and the buried oxide layer generally varies according to the intended application. For example, for a substrate used to manufacture a FD (fully depleted) type SOI device, the thickness of the silicon active layer is generally between about 3 nm and 40 nm, and the thickness of the buried oxide layer is generally between about 10 nm and 40 nm. In addition, for a substrate constructed to manufacture a RF (radio frequency) type SOI device, the thickness of the silicon active layer and the buried oxide layer is generally greater than about 50 nm.

[0013] In fact, various thicknesses of the buried silicon oxide layer make it possible to obtain different degrees of insulation, different leakage currents, different voltage strengths, different equivalent capacitances, a multitude of parameters chosen by the developer. In addition, one or more functional layers can be inserted between the buried oxide layer and the silicon carrier substrate. The purpose of this type of layer structure is to limit self-bias and crosstalk between components transmitted via the substrate, in particular those caused by the strong electromagnetic radiation of the radio frequency components.

[0014] As a result, for certain applications or functions, it is preferred to instead select an SOI type substrate with a fine buried silicon oxide layer, for example for the manufacture of FDSOI type transistors; for other applications, an SOI type substrate with a thick buried silicon oxide layer and / or with functional additional layers will be preferred for the manufacture of, for example, power components or RF components.

[0015] Furthermore, due to the very fact of industrial manufacturing methods well known to those skilled in the art, the vast majority of substrates of SOI type are “homogeneous”, in other words the thickness of the buried oxide layer and of the active layer are constant over the entire substrate.

[0016] However, attempts are known to manufacture components on the same substrate by alternating regions of “bulk” type and SOI type.

[0017] The article “Transistors on hybrid UTBB / Bulk substrates fabricated by local internal BOX dissolution” published by P. Nguyen et al. in “Solid State Electronics, Vol. 90, pp 39-43, 2013” ​​describes the fabrication of CMOS components on hybrid SOI / bulk substrates obtained by local internal dissolution of buried oxide layers. However, this technology has two major problems for industrial use.

[0018] In practice, this dissolution method results in a poorly controlled transition between portions of the buried oxide layer having different thicknesses. The transition zone between said portions is long (at most of the order of a few micrometers due to the dissolution method used) and is therefore not compatible with large-scale co-integration.

[0019] In addition, for a dissolved oxide layer with a thickness of about ten nanometers, the dissolution method causes considerable inhomogeneity in the buried oxide layer and the subsequent active layer on the insulator. This inhomogeneity leads to a mismatch in electrical properties between regions with different thicknesses in the buried oxide layer, which is detrimental to the correct operation of various components manufactured on this type of hybrid substrate. Summary of the invention

[0020] There is a need to provide a "monolithic" substrate of SOI type having an electrically insulating buried layer (or active layer) comprising at least two regions with different thicknesses, while ensuring:

[0021] the uniformity of the thickness of the various parts of these layers,

[0022] Optimal roughness, and

[0023] abrupt transitions between parts of a layer with different thicknesses,

[0024] This is compatible with the specification of large-scale integration of various types of components on the monolithic substrate, including, for example, FDSOI type components.

[0025] It is also necessary to provide a method for manufacturing a substrate with the above specifications, which method is easy to implement and is compatible with specific donor and / or acceptor substrates, for example including trapping layers or doping layers of the "trap-rich" type. In fact, this type of substrate requires a limited finishing thermal budget, in particular for smoothing the surface of the active layer on insulator (a "rapid thermal annealing" type method as opposed to a "thermal batch annealing" type method).

[0026] These requirements are becoming increasingly important, in particular in the field of systems-on-chip or SOCs, where multiple functions are integrated on the same chip, or in the field of co-integration of digital and RF components, or in the field of microsystems that integrate, for example, sensors or accelerometers and readout circuits.

[0027] The above needs can be met while avoiding the above disadvantages by providing a method for manufacturing an advanced substrate, the method comprising the steps of:

[0028] a) providing a receptor substrate and a donor substrate, wherein the donor substrate comprises:

[0029] - a carrier substrate;

[0030] - an active layer made of a single-crystalline semiconductor material; and

[0031] a sacrificial layer made of a material that can be selectively etched relative to the active layer, the sacrificial layer being interposed between the carrier substrate and the active layer;

[0032] a silicon oxide layer having a free surface and arranged such that the active layer is interposed between the sacrificial layer and the oxide layer;

[0033] b) forming a cavity in the oxide layer, the cavity having an opening flush with the free surface, so that the oxide layer includes a first portion having a first thickness e1 and disposed between the cavity and the active layer, and a second portion having a second thickness e2 greater than the first thickness e1, the second portion being disposed between the free surface and the active layer;

[0034] c) forming a polysilicon filling layer so as to completely fill the cavity and form a continuous and substantially flat second free surface, the second free surface including at least one first polysilicon surface;

[0035] d) assembling an acceptor substrate and a donor substrate on the second free surface;

[0036] e) Removing the carrier substrate after step d) while retaining the active layer and the sacrificial layer.

[0037] According to one embodiment, the method may comprise the step of, after step e), selectively etching the sacrificial layer while retaining the active layer. Furthermore, the assembling step d) may comprise the step of bonding by molecular adhesion.

[0038] According to one embodiment, the method may further include the following steps:

[0039] b0) before step b) and after step a), forming a weakened area in the carrier substrate, the weakened area being substantially flat and being located near the interface between the sacrificial layer and the carrier substrate;

[0040] e0) After step d), the carrier substrate is fractured along the weakened area.

[0041] Furthermore, the sacrificial layer is made of a material that can be selectively etched relative to the material of the carrier substrate. As a result, after the breaking step e0), the remaining portion of the carrier substrate placed on the sacrificial layer is selectively etched. The filling layer can also be formed by chemical vapor deposition at a temperature between 150° C. and 250° C.

[0042] According to one embodiment, the single-crystalline silicon active layer can be produced by epitaxy. Furthermore, the active layer remaining after step e) can be thinned locally in order to locally reduce the thickness of the active layer.

[0043] According to one embodiment, the filling layer may cover the silicon oxide layer. Furthermore, an additional polysilicon layer may be formed on the second portion of the silicon oxide layer, the additional layer preferably having a thickness e' between 1 nm and 1000 nm, in which case the second free surface formed after step c) is completely made of polysilicon.

[0044] Furthermore, step c) may include thinning the filling layer and / or the oxide layer so that the second free surface also includes a second silicon oxide surface.

[0045] The present invention also provides an advanced substrate, comprising:

[0046] - receptor substrate;

[0047] - an active layer made of a single-crystalline semiconductor material; and

[0048] - an electrically insulating silicon oxide layer, which is interposed between the active layer and the acceptor substrate;

[0049] The advanced substrate is characterized in that the advanced substrate comprises a polysilicon layer placed on an acceptor substrate, the polysilicon layer being coated with an electrical insulating layer, thereby defining a first portion of the electrical insulating layer having a first thickness e1 and being inserted between the polysilicon layer and the active layer, and a second portion of the electrical insulating layer having a second thickness e2 greater than the first thickness e1, the second portion being placed between the acceptor substrate and the active layer.

[0050] According to one embodiment, the substrate comprises an additional layer made of polysilicon, which is inserted between the acceptor substrate and the assembly formed by the electrically insulating layer and the polysilicon layer. The substrate may also comprise an additional electrically insulating layer inserted between the additional layer and the acceptor substrate. Preferably, the acceptor substrate comprises: an epitaxially grown and doped layer, which is configured to form a microelectronic element in said epitaxially grown layer. Moreover, the acceptor substrate may comprise an integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Other features and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0052] - Figures 1A to 1F (include Figure 1D' and Figure 1F' ) represents a schematic cross-sectional view showing steps of a method for manufacturing an advanced substrate according to various embodiments; and

[0053] - Figures 2 to 4 Schematic cross-sectional views of advanced substrates according to various embodiments are shown.

[0054] To make the drawings clearer, the various layers are not necessarily drawn to scale. The same reference numbers have been used from one drawing to the next to refer to elements that are the same or perform the same function. DETAILED DESCRIPTION

[0055] To simplify the description, for the various embodiments, the same reference numerals will be used for elements that are the same or perform the same function.

[0056] Figures 1A to 1F An embodiment of the method according to the invention is schematically represented. For ease of illustration, the respective thicknesses of the individual layers are not shown to scale.

[0057] According to one embodiment, the method for manufacturing an advanced substrate 1 comprises: step a), providing a receptor substrate 20 (see Figure 1E , Figure 1F and Figure 1F'). The acceptor substrate 20 can be made of a semiconductor material or of another material, depending on whether it has to perform a mechanical load-bearing function or an electrical function alone within the final advanced substrate 1. Preferably, the acceptor substrate 20 is based on silicon. Furthermore, the acceptor substrate 20 can comprise one or more functional additional layers, such as a trapping layer, known as a "Trap Rich" layer, which is, for example, based on polysilicon (optionally with a silicon oxide layer inserted between the substrate 20 and the trapping layer), or, for example, an epitaxially grown layer made of a doped semiconductor material, etc.

[0058] like Figure 1A As shown, the step further includes the step of providing a donor substrate 10, wherein the donor substrate 10 includes:

[0059] - a carrier substrate 11;

[0060] - an active layer 13 made of a single-crystalline semiconductor material; and

[0061] a sacrificial layer 12 made of a material that can be selectively etched relative to the active layer, the sacrificial layer 12 being interposed between the carrier substrate 11 and the active layer 13;

[0062] A silicon oxide layer 14 having a free surface 15 and arranged such that the active layer 13 is interposed between the sacrificial layer 12 and the oxide layer 14 .

[0063] The carrier substrate 11 may be made of a semiconductor material or of another material, taking into account the desired crystal quality of the layers 12 and 13. Preferably, the carrier substrate 11 is silicon-based.

[0064] The active layer 13 is a layer configured to receive microelectronic components. In other words, said components will be formed in the active layer 13. Preferably, the active layer 13 is made of single-crystal silicon or single-crystal silicon germanium which can be strained or relaxed.

[0065] According to one embodiment, the active layer 13 is advantageously formed by epitaxy. This is because a layer formed by epitaxy makes it possible to obtain optimal roughness, thickness uniformity and surface finish, in particular compatible with the most demanding specifications of a process for manufacturing microelectronic components, for example a process for manufacturing components of the FDSOI type.

[0066] Advantageously, the sacrificial layer 12 is also produced by epitaxy to facilitate any epitaxy of the active layer 13. When the active layer is based on silicon or silicon germanium, the sacrificial layer can be based on silicon and germanium. Furthermore, the layer 12 can also be based on any material that allows selective etching of the sacrificial layer 12 relative to the active layer 13, as long as the crystal quality of the sacrificial layer 12 remains compatible with the crystal quality required for the active layer 13.

[0067] Even more advantageously, the materials of the carrier substrate 11 and the sacrificial layer 12 are configured such that the material of the carrier substrate 11 is selectively etched relative to the sacrificial layer 12 , and such that the sacrificial layer 12 is selectively etched relative to the active layer 13 .

[0068] The oxide layer 14 may be manufactured by any technique known to those skilled in the art that is compatible with conventional methods in the field of microelectronics. Preferably, the oxide layer 14 is a conventional thermal oxide.

[0069] For a substrate with a diameter of about 300 mm, the thickness of the carrier substrate 11 can be about several hundred μm, typically 775 μm. The thickness of the sacrificial layer 12 depends on the etching solution and / or technique used. Those skilled in the art will know how to adjust the thickness of the sacrificial layer 12 relative to the active layer 13 so that the sacrificial layer 12 can be etched efficiently and selectively. Advantageously, the thickness of the sacrificial layer 12 can also be adjusted so that the material of the carrier substrate 11 can be selectively etched relative to the sacrificial layer 12 while maintaining the crystal properties of the active layer 13.

[0070] The thickness of the active layer 13 is preferably between 5 nm and 500 nm, and the thickness of the oxide layer 14 is preferably between 10 nm and 500 nm.

[0071] like Figure 1B As shown, the method comprises: step b), forming at least one cavity 30 in the silicon oxide layer 14. The cavity 30 is open and includes an opening flush with the free surface 15 of the oxide layer 14. The cavity 30 includes a wall. The wall of the cavity 30 and the opening of the cavity 30 limit the volume of the cavity 30. Advantageously, the cavity 30 is not a through cavity and does not include an opening flush with the interface between the oxide layer 14 and the active layer 13, so that the oxide layer 14 includes a first portion 14a having a non-zero first thickness e1. The first portion 14a is between the cavity 30 and the active layer 13.

[0072] Therefore, the oxide layer 14 includes a second portion 14 b having a second thickness e2 that is greater than the first thickness e1 of the first portion 14 a. The second portion 14 b is between the free surface 15 and the active layer 13 .

[0073] In order to simplify the drawings, two cavities 30 have been shown, but it goes without saying that the donor substrate 10 can in principle include a large number of cavities extending parallel to each other. Preferably, the network of cavities 30 is distributed in the oxide layer 14 so as to define several patterns defining the second portion 14b. In other words, each pattern forming the second portion 14b of the oxide layer 14 is defined by the cavity 30.

[0074] The cavity 30 or the cavity network can be manufactured by any conventional technique. Advantageously, the cavity 30 can be manufactured by a series of lithography and etching steps known and widely used in the field of microelectronics. Thus, sharp transitions between various portions of the oxide layer with various thicknesses are advantageously obtained. This also ensures uniformity of the thickness of the layers, in particular the oxide layer.

[0075] After forming the cavity 30, the method comprises a step c) for forming a filling layer of the cavity 30. Figure 1C , Figure 1D and Figure 1D' As shown, a filling layer 40 is formed to completely fill the cavity 30 and form a second free surface 41 that is continuous and substantially flat and includes at least one first surface 43 based on the filling material.

[0076] According to one embodiment, the filling layer 40 covers the silicon oxide layer 14 .

[0077] Advantageously, the filling layer 40 is made of polysilicon. Polysilicon is a material that is easily deposited on silicon oxide layers. In addition, this material offers the possibility of deposition at low temperatures, which makes it compatible with structures including epitaxially grown and / or implanted donor substrates. Finally, polysilicon can advantageously be used both as a conducting layer under a future thin buried oxide defined, for example, in the region 14a and as a trapping layer (often referred to as a layer of the "trap-rich" type) in the region 14b, while being compatible with bonding by molecular adhesion to the acceptor substrate 20.

[0078] Additionally, polysilicon is known to have better thermal conductivity than silicon oxide. As a result, the use of buried silicon oxide based layers including polysilicon layers in combination with a silicon acceptor substrate advantageously enables better dissipation of heat from the active area to and in the acceptor substrate.

[0079] Preferably, step c) comprises a planarization or thinning step configured to substantially planarize the second free surface 41. The planarization step may comprise a combination of mechanical and chemical forces, such as a chemical mechanical polishing method (commonly referred to as a CMP method).

[0080] According to one embodiment, Figure 1D As shown, step c) is performed, in particular a planarization step, to completely remove the polysilicon covering the second portion 14b of the oxide layer 14. In other words, step c) comprises a planarization or thinning step of the layer 40 and / or a planarization or thinning step of the oxide layer 14, so that the second free surface 41 also comprises a second silicon oxide surface 44.

[0081] According to another embodiment, Figure 1D' As shown, a polysilicon layer 42 is formed on the second portion 14b of the silicon oxide layer 14 and the filled cavity 30. Preferably, the layer 42 has a thickness e' between 1 nm and 1000 nm. According to this embodiment, the second free surface 41 formed after step c) is completely made of polysilicon. For example, the layer 42 can be formed by successively adjusting the thickness of the formed layer 40 and then the thickness removed from the layer 40 after a step of flattening or thinning the polysilicon layer 40.

[0082] As a result, the obtained advanced substrate 1 (see Figure 3 The example final substrate obtained (shown) will advantageously comprise a buried insulating layer comprising a thick layer 14b and a thin oxide layer 14a, with a functional layer (a trapping layer, generally called a layer of “trap-rich” type) inserted between the acceptor substrate 20 and the buried insulating layer 14b. This type of substrate will offer the possibility of efficient co-integration of FDSOI type components arranged on the thin buried insulator (portion 14a) and of radio frequency components arranged on the thick buried insulator (portion 14b and polysilicon layer), while limiting at the same time the self-biases and crosstalks between the components transmitted via the advanced substrate 1, in particular those caused by the strong electromagnetic radiation of the radio frequency components. This is possible thanks to the functional layer (layer 42) situated “under” the thick silicon oxide portion 14b.

[0083] In addition, the method further comprises: step d), assembling the acceptor substrate 20 and the donor substrate 10 at the second free surface 41 (see Figure 1E Advantageously, the assembly step d) is performed by molecular adhesion. Advantageously, the assembly is performed by bringing the second free surface 41 of the donor substrate 10 into direct contact with the acceptor substrate 20 .

[0084] In one embodiment, before the assembly step, an additional electrically insulating layer, preferably made of silicon oxide, may be formed on the donor substrate 10 and / or on the acceptor substrate 20. Advantageously, the additional layer is formed on the acceptor substrate 20 so as not to destroy the quality of the layer already made on the donor substrate 10. Thus, the additional layer is inserted between the acceptor substrate 20 and the donor substrate 10 (see, for example, the obtained and Figure 4 ). This layer makes it possible to improve the quality of the assembly by molecular adhesion, in particular if one of the surfaces in contact comprises polysilicon. The substrate thus formed will resemble a double SOI and have the advantages of a double SOI. It is also possible to electrically insulate the acceptor substrate 20 from the influence of the potential applied in the active layer 13 and the filling layer 40. Thus, the acceptor substrate 20 itself carries an integrated circuit or a functional layer ( Figure 4For example, a doped (preferably epitaxially grown) semiconductor layer allows additional components to be co-integrated on the bulk substrate (substrate 20), such as an integrated memory (embedded DRAM).

[0085] The method further comprises: step e), after step d), removing the carrier substrate 11 and retaining the active layer 13 and the sacrificial layer 12, so as to obtain an advanced substrate 1 (see Figure 1F and Figure 1F' ). The removal can be carried out by any conventional technique known to those skilled in the art that is compatible with the methods used in the field of microelectronics. For example, the removal can be carried out by abrasion or chemical etching, or preferably by introducing a weakened area and then by breaking.

[0086] The method according to the invention is easy to implement and advantageously allows the formation of a "monolithic" substrate having a buried electrically insulating layer comprising at least two regions of different thicknesses, while at the same time ensuring a matching of the electrical properties between the regions of different thicknesses in the buried oxide layer. In fact, due to the formation of cavities in the oxide layer already filled with polysilicon before assembling the donor substrate and the acceptor substrate, the advanced substrate obtained benefits from the uniformity of the thickness of the various portions of the layer, an optimal roughness and sharp transitions between the various portions of the layer with different thicknesses. These characteristics therefore make possible a large-scale integration optimized for the manufacture of different types of components on the same substrate, in particular devices of the FDSOI type and radiofrequency devices.

[0087] According to one embodiment, the method comprises the step of etching the sacrificial layer 12 selectively with respect to the active layer 13 , the active layer 13 being retained on the final advanced substrate 1 .

[0088] The selective etching is preferably wet chemical etching. For example, the selective etching of the silicon layer relative to the sacrificial silicon germanium layer can be performed using a TMAH solution. The selective etching of the silicon germanium layer relative to the silicon layer can be performed using an acetic acid solution.

[0089] Selective etching advantageously makes it possible to obtain at the end the desired active layer whose thickness and roughness correspond to the properties of the epitaxially grown substrate, which would not be the case if a single mechanical or chemical-mechanical polishing was carried out.

[0090] Advantageously, the step of etching the sacrificial layer 12 selectively with respect to the active layer 13 is performed just before the method of manufacturing components on the active layer 13. This is because the sacrificial layer 12 can also serve as a passivation layer, thus avoiding the formation of a native oxide layer on the active layer 13 and also protecting the active layer 13 during the substrate storage phase.

[0091] According to one embodiment, the method further comprises the following steps (see Figures 1A to 1E ):

[0092] b0) before step b) and after step a), forming a weakened area 50 in the carrier substrate 11, the weakened area 50 being substantially flat and located near the interface between the sacrificial layer 12 and the carrier substrate 11;

[0093] e0) After step d), and preferably before the sacrificial layer 12 is selectively etched (if this is to be done), the carrier substrate 11 is broken along the weakened zone 50 .

[0094] In other words, the removal of the carrier substrate 11 can be performed by separation and breaking of said substrate.Therefore, the carrier substrate is not completely lost and can advantageously be reused, in particular in a further cycle of manufacturing another advanced substrate according to the invention.

[0095] The weakened zone 50 and the interface between the sacrificial layer 12 and the carrier substrate 11 define a residual layer 51 which is intended to be transferred to the sacrificial layer 12 after fracture of the carrier substrate 11 .

[0096] Preferably, the material of the sacrificial layer 12 and the material of the carrier substrate may be selected so that the residual layer can be selectively etched relative to the sacrificial layer 12. Figure 1F and Figure 1F' As shown, the method advantageously comprises etching the residual layer 51 selectively with respect to the sacrificial layer 12 after the breaking step e0).

[0097] Advantageously, the filling layer 40 is formed by chemical vapor deposition at a temperature low enough to enable it to be performed without affecting the weakened zone 50. Preferably, the filling layer 40 is formed by chemical vapor deposition at a temperature between 150°C and 250°C.

[0098] According to one embodiment, the weakened zone 50 may be obtained by implanting at least one species selected from the following group: hydrogen and helium. The weakening implant may also be performed by implanting several species sequentially. Preferably, the carrier substrate 11 is based on silicon.

[0099] The conditions for producing the weakened zone 50 (implanted substance, implantation energy and dose) and the conditions for fracture depend on the thickness of the layers 12 and 13. Moreover, a person skilled in the art will know how to adjust these conditions to form the weakened zone 50 in the carrier substrate 11. Furthermore, the fracture step e0) is preferably carried out by heat treatment at a temperature between 350°C and 500°C.

[0100] Linking together the steps of the method according to the invention makes it possible to advantageously form the weakened zone before constructing the buried oxide layer by forming a cavity and then filling the cavity with a semiconductor material. Thus, a substantially flat weakened zone can be easily and routinely obtained, thereby facilitating fracture and separation. In addition, the deposition of the filling material can advantageously be carried out at low temperatures to avoid premature fracture and / or detrimental modification of the carrier substrate before assembling the donor substrate and the acceptor substrate.

[0101] Although all the steps of the method according to the invention can be carried out at a temperature not exceeding 500° C., it is advantageously possible to obtain a uniform layer with optimal surface roughness and surface characteristics (in particular compatible with the method for manufacturing components of FDSOI type). The method according to the invention also makes it possible to dispense with high-temperature finishing steps and advantageously prevent recrystallization of the polysilicon layer. As a result, the polysilicon layer can act as a functional layer, such as a trapping layer (trap-rich layer) within the final advanced substrate. Finally, according to a particular embodiment of the invention, the use of this reduced temperature range will enable the transfer of the formed donor substrate to a "structured" receptor substrate comprising functional devices in the context of a three-dimensional layer transfer.

[0102] According to one embodiment, the active layer 13 remaining after step e) is locally thinned to locally reduce the thickness of the active layer 13. Thus, an advanced substrate is advantageously obtained, which includes an active layer having portions of various thicknesses and a buried oxide layer also having portions of various thicknesses. Thus, the advanced substrate can be configured to efficiently manufacture components having various functions.

[0103] Furthermore, the previously stated needs can be met while avoiding the above-mentioned disadvantages by also providing an advanced substrate 1, which comprises (see Figure 2 and Figure 3 ):

[0104] - receptor substrate 20;

[0105] - an active layer 13 made of a single-crystalline semiconductor material; and

[0106] An electrically insulating silicon oxide layer 14 , which is interposed between the active layer 13 and the acceptor substrate 20 .

[0107] The substrate further comprises a polysilicon layer 40 disposed on the acceptor substrate 20. The polysilicon layer 40 is coated with the electrically insulating layer 14 so as to define a first portion 14a and a second portion 14b of the electrically insulating layer 14. The first portion 14a has a first thickness e1 and is interposed between the polysilicon layer 40 and the active layer 13. The second portion 14b of the electrically insulating layer 14 has a second thickness e2 greater than the first thickness e1. The portion 14b is between the acceptor substrate 20 and the active layer 13. Preferably, the active layer 13 is covered by a sacrificial layer 12, which can be selectively etched relative to the active layer 13 just before the fabrication of the components in the active layer. In other words, the sacrificial layer also serves as a protective layer for the advanced substrate 1.

[0108] According to one embodiment, Figure 3 As shown, the advanced substrate comprises an additional layer 42 made of polysilicon, which is interposed between the acceptor substrate 20 and the assembly formed by the electrically insulating layer 14 and the polysilicon layer 40 .

[0109] According to another embodiment, Figure 4 As shown, the advanced substrate 1 comprises, below the layer 42, a second electrically insulating layer 60, for example a silicon oxide layer, disposed on an acceptor substrate 20. The acceptor substrate 20 may itself comprise a functional layer 61 (for example a doped epitaxially grown layer) or may also comprise a microelectronic device (for example an integrated circuit) in the context of a 3D process.

Claims

1. A method for manufacturing an advanced substrate (1), the method comprising the following steps: a) providing an acceptor substrate (20) and a donor substrate (10), wherein the donor substrate (10) comprises: - a carrier substrate (11); - an active layer (13), said active layer (13) being made of a single-crystalline semiconductor material; and - a sacrificial layer (12), the sacrificial layer (12) being made of a material that can be selectively etched relative to the active layer (13), the sacrificial layer (12) being interposed between the carrier substrate (11) and the active layer (13); a silicon oxide layer (14) having a free surface (15) and arranged such that the active layer (13) is interposed between the sacrificial layer (12) and the silicon oxide layer (14); b) forming a cavity (30) in the silicon oxide layer (14), the cavity (30) having an opening flush with the free surface (15), so that the silicon oxide layer (14) includes a first portion (14a) and a second portion (14b), the first portion (14a) having a first thickness (e1) and being disposed between the cavity (30) and the active layer (13), and the second portion (14b) having a second thickness (e2) greater than the first thickness (e1), and being disposed between the free surface (15) and the active layer (13); c) forming a polysilicon filling layer so as to completely fill the cavity (30) and form a continuous and substantially flat second free surface (41), wherein the second free surface (41) includes at least one first polysilicon surface (43); d) assembling the acceptor substrate (20) and the donor substrate (10) on the second free surface (41); e) removing the carrier substrate (11) after step d), while retaining the active layer (13) and the sacrificial layer (12).

2. The method according to claim 1, comprising the steps of: After step e), the sacrificial layer (12) is selectively etched while the active layer (13) remains.

3. The method according to claim 1 or 2, wherein: Step d) of assembling comprises a step of joining by molecular adhesion.

4. The method according to claim 1 or 2, comprising the following steps: b0) before step b) and after step a), forming a weakened area (50) in the carrier substrate (11), wherein the weakened area is substantially flat and is located near the interface between the sacrificial layer (12) and the carrier substrate (11); e0) After step d), the carrier substrate (11) is broken along the weakened area (50).

5. The method according to claim 4, wherein: The carrier substrate (11) is made of a material that can be selectively etched relative to the material of the sacrificial layer (12), and the method further comprises the following steps: after the breaking step e0), selectively etching the remaining part of the carrier substrate (11) placed on the sacrificial layer (12).

6. The method according to claim 4, wherein: The polysilicon filling layer is formed by chemical vapor deposition at a temperature between 150° C. and 250° C.

7. The method according to claim 1 or 2, wherein: The active layer (13) is manufactured by epitaxy.

8. The method according to claim 1 or 2, wherein: The polysilicon filling layer covers the silicon oxide layer (14).

9. The method according to claim 8, wherein: A polysilicon layer is formed on the second portion (14b) of the silicon oxide layer (14), the polysilicon layer having a thickness (e') between 1 nm and 1000 nm, and the second free surface (41) formed after step c) is completely made of polysilicon.

10. The method according to claim 1 or 2, wherein: Step c) comprises the following steps: thinning the polysilicon filling layer and / or the silicon oxide layer (14) so ​​that the second free surface (41) also comprises a second silicon oxide surface (44).

11. The method according to claim 1 or 2, wherein: The active layer (13) remaining after step e) is locally thinned so as to locally reduce the thickness of the active layer (13).

12. An advanced substrate (1), comprising: - a receptor substrate (20); - an active layer (13), said active layer (13) being made of a single-crystalline semiconductor material; as well as - an electrically insulating silicon oxide layer (14) which is interposed between the active layer (13) and the receptor substrate (20); The advanced substrate (1) comprises a polysilicon layer disposed on the acceptor substrate (20), the polysilicon layer being coated with the electrically insulating silicon oxide layer (14), thereby defining: a first portion (14a) of the electrically insulating silicon oxide layer (14) having a first thickness (e1) and being inserted between the polysilicon layer and the active layer (13); and a second portion (14b) of the electrically insulating silicon oxide layer (14) having a second thickness (e2) greater than the first thickness (e1), the second portion (14b) being disposed between the acceptor substrate (20) and the active layer (13), the advanced substrate (1) comprising an additional layer made of polysilicon and an additional electrically insulating layer (60) inserted between the additional layer and the acceptor substrate (20).

13. The advanced substrate (1) according to claim 12, characterized in that The additional layer is interposed between the acceptor substrate (20) and the assembly formed by the electrically insulating silicon oxide layer (14) and the polysilicon layer.

14. The advanced substrate (1) according to claim 12, characterized in that The acceptor substrate (20) includes an epitaxially grown and doped layer (61) configured to form a microelectronic element in the epitaxially grown layer.

15. The advanced substrate (1) according to claim 12 or 14, characterized in that The receptor substrate (20) includes an integrated circuit.

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