Pixel circuit for controlling a light-emitting element

Abstract

A pixel circuit for controlling a light-emitting element, the pixel circuit comprising: a driving transistor configured to supply a driving current to the light-emitting element; a first switching transistor configured to transmit a data signal corresponding to the driving current; a storage capacitor configured to receive a signal from the first switching transistor and store a voltage to be applied to a gate of the driving transistor; a second switching transistor configured to correct the voltage to be stored in the storage capacitor; and a first capacitor including an electrode connected to a drain of the driving transistor and an electrode to which a predetermined potential is to be supplied.

Description

Technical Field

[0001] The present disclosure relates to a pixel circuit for controlling a light-emitting element. Background Art

[0002] An organic light-emitting diode (OLED) element is a current-driven self-luminous element and thus does not require a backlight. In addition, the OLED element has advantages of low power consumption, wide viewing angle, and high contrast, and is expected to contribute to the development of flat panel display devices.

[0003] An active matrix (AM) OLED display device includes a transistor for selecting a pixel and a driving transistor for supplying current to the pixel. The transistors in the OLED display device are thin film transistors (TFTs), and in particular, low temperature polycrystalline silicon (LTPS) TFTs are generally used.

[0004] TFTs vary in their threshold voltage and charge mobility. Since the driving transistors determine the light-emitting intensity of the OLED display device, variations in their electrical characteristics may cause problems. Therefore, a typical OLED display device includes a correction circuit for compensating for variations and offsets in the threshold voltage of the driving transistors.

[0005] The OLED display device may display a ghost image (also simply referred to as ghosting), and this phenomenon is called image retention. For example, when a black-and-white checkerboard pattern is displayed for a certain period of time and then a full-screen pattern with an intermediate emission level is displayed, the OLED display device will display a ghost image of the checkerboard pattern with different emission levels for a while.

[0006] This is caused by the hysteresis effect of the driving transistors. The hysteresis effect causes the following phenomenon in field effect transistors: the flow of the drain current is different between the case where the gate-source voltage changes from a high voltage to a low voltage and the case where the gate-source voltage changes from a low voltage to a high voltage.

[0007] That is, the flow of the drain current is different between a pixel whose emission level changes from a black level to an intermediate level and a pixel whose emission level changes from a white level to an intermediate level. For this reason, the OLED display device emits light of different intensities. This difference in the drain current persists over several frames, and thus the different intensities of the emitted light are perceived as ghosting. This behavior of the drain current is called the current transient response due to the hysteresis effect. Summary of the Invention

[0008] After displaying a black-and-white checkerboard pattern, the ghost image caused by image retention can be of a type in which the area that has been displayed in black becomes relatively darker, or of a type in which the area that has been displayed in black becomes relatively brighter. The current transient response caused by the hysteresis effect of the driving TFT and the correction of the threshold voltage of the driving TFT by the pixel circuit cause image retention. Therefore, a technique is needed to reduce image retention in the pixel circuit.

[0009] One aspect of the present disclosure is a pixel circuit configured to control a driving current for a light-emitting element. The pixel circuit includes: a driving transistor configured to supply a driving current to the light-emitting element; a first switching transistor including a source, a gate, and a drain, the first switching transistor configured to transmit a data signal corresponding to the driving current; a storage capacitor configured to receive a signal from the first switching transistor and store a voltage to be applied to the gate of the driving transistor; a second switching transistor configured to correct the voltage to be stored in the storage capacitor; and a first capacitor including an electrode connected to the drain of the driving transistor and an electrode to which a predetermined potential is to be supplied.

[0010] One aspect of the present disclosure reduces image retention in a display device.

[0011] It should be understood that the foregoing general description and the following detailed description are exemplary and not restrictive of the present disclosure. Description of the Drawings

[0012] Figure 1 Exemplarily shows a configuration example of an OLED display device of a display device;

[0013] Figure 2A Exemplarily shows an example of negative ghosting;

[0014] Figure 2B Shows the change in the driving current of a sub-pixel, which corresponds to Figure 2A the change in the displayed image shown in;

[0015] Figure 3A Exemplarily shows an example of positive ghosting;

[0016] Figure 3B Shows the change in the driving current of a sub-pixel, which corresponds to Figure 3A the change in the displayed image shown in;

[0017] Figure 4 Is a diagram for explaining the relationship between image retention in an OLED display device, the characteristics of a driving TFT, and the correction operation of a pixel circuit for a data signal;

[0018] Figure 5 Shows a configuration example of a pixel circuit in an embodiment of the present disclosure;

[0019] Figure 6 is a timing diagram of signals for controlling the pixel circuit in one frame period; Figure 5 in the;

[0020] Figure 7 provides simulation results on the relationship between the time constant τst and the ghosting intensity;

[0021] Figure 8A provides simulation results on the relationship between the ratio of the capacitance of capacitor Cp to the capacitance of storage capacitor Cst and the ghosting intensity;

[0022] Figure 8B provides the voltage waveform at node N1 when the value of capacitor Cp is greater than the value of storage capacitor Cst;

[0023] Figure 8C provides the voltage waveform at node N1 when the value of capacitor Cp is less than the value of storage capacitor Cst;

[0024] Figure 9 provides simulation results on the time variation of the ghosting intensity when resistor Rst has different resistances;

[0025] Figure 10 exemplarily shows the luminance change in one frame caused by resistor Rst;

[0026] Figure 11 provides simulation results on the relationship between the intensity of flicker and the time constant τst;

[0027] Figure 12 provides simulation results on the relationship between the ratio of the capacitance of capacitor Cp to the capacitance of storage capacitor Cst, the time constant τst, and the ghosting intensity;

[0028] Figure 13 provides simulation results on the relationship between the ratio of the capacitance of capacitor Cp to the capacitance of storage capacitor Cst, the time constant τst, and the flicker intensity;

[0029] Figure 14 provides simulation results on the relationship between the ratio of the capacitance of capacitor Cp to the charge of storage capacitor Cst, the time constant τst, and the ghosting intensity under the condition that the flicker intensity is not greater than 0.5;

[0030] Figure 15 is an exemplary plan view showing a structural part including a storage capacitor Cst and a resistor Rst;

[0031] Figure 16 exemplarily shows alongFigure 15 Cross-sectional structure of the mid-section line XVI-XVI;

[0032] Figure 17 is an exemplary plan view of a pixel circuit portion including its storage capacitor Cst, capacitor Cp, and resistor Rst;

[0033] Figure 18 Exemplarily shows along Figure 17 Cross-sectional structure of the mid-section line XVIII-XVIII;

[0034] Figure 19 Shows an example configuration of capacitor Cp;

[0035] Figure 20 is an exemplary plan view of a pixel circuit portion including its storage capacitor Cst, capacitor Cp, and resistor Rst;

[0036] Figure 21 Exemplarily shows along Figure 20 Cross-sectional structure of the mid-section line XXI-XXI;

[0037] Figure 22 Shows another example configuration of the pixel circuit;

[0038] Figure 23 Shows a planar pattern of a pixel including a variable capacitor and a lead;

[0039] Figure 24 Is a cross-sectional view along Figure 23 Mid-section line XXIV-XXIV; and

[0040] Figure 25 Shows an example of the voltage-capacitance characteristic of the variable capacitor. Detailed implementation

[0041] Embodiments of the present disclosure will be specifically described below with reference to the accompanying drawings. Common elements in the figures are denoted by the same reference numerals, and the dimensions and / or shapes of the various elements in the figures are enlarged for a clear understanding of the description herein.

[0042] Disclosed below is a technique for improving the drive current control in a light-emitting display device, more specifically, a technique for reducing image sticking in an electroluminescent display device. A light-emitting display device is a display device that uses a light-emitting element that emits light in response to a drive current, such as an organic light-emitting diode (OLED) display device.

[0043] Configuration of the display device

[0044] Figure 1An exemplary configuration example of the OLED display device 10 of a display device is shown. The OLED display device 10 includes a thin film transistor (TFT) substrate 100 on which an OLED element (organic light emitting element) is formed, a packaging substrate 200 for encapsulating the OLED element, and a bonding member (glass frit seal) 300 for bonding the TFT substrate 100 and the packaging substrate 200. The space between the TFT substrate 100 and the packaging substrate 200 is filled with an inert gas such as dry nitrogen and sealed with the bonding member 300.

[0045] Around the periphery of the cathode region 114 outside the display region 125 of the TFT substrate 100, a scan circuit 131, 132, a driver IC 134, and a demultiplexer 136 are provided. The driver IC 134 is connected to an external device via a flexible printed circuit (FPC) 135. The scan circuits 131 and 132 drive the scan lines on the TFT substrate 100.

[0046] The driver IC 134 is mounted with, for example, an anisotropic conductive film (ACF). The driver IC 134 supplies power and timing signals (control signals) to the scan circuits 131 and 132, and also supplies data signals to the demultiplexer 136.

[0047] The demultiplexer 136 sequentially outputs the output of one pin of the driver IC 134 to d (d is an integer greater than 1) data lines. The demultiplexer 136 changes the output data line for the data signal from the driver IC 134 d times per scan cycle to drive data lines whose number is d times the number of output pins of the driver IC 134.

[0048] The display region 125 includes a plurality of OLED elements (pixels) and a plurality of pixel circuits for controlling the light emission of the plurality of pixels. In the example of a color OLED display device, each OLED element emits light of one color among red, blue, and green. The plurality of pixel circuits form a pixel circuit array.

[0049] As will be described later, each pixel circuit includes a driving TFT (driving transistor) and a storage capacitor for storing a signal voltage that determines the driving current of the driving TFT. The data signal sent by the data line is corrected and stored in the storage capacitor. The voltage of the storage capacitor determines the gate voltage (Vgs) of the driving TFT. The corrected data signal changes the conductivity of the driving TFT in an analog manner to supply a forward bias current corresponding to the light emission level to the OLED element.

[0050] Image retention

[0051] The OLED display device 10 of the present disclosure has a pixel circuit including a configuration for reducing ghosting caused by image sticking. For example, when the image displayed on the OLED display device changes from a fixed black and white checkerboard pattern to an image of an intermediate emission level, a ghost image corresponding to the fixed pattern is displayed for a while.

[0052] The intensity and duration of the ghost image depends on how long the fixed pattern is displayed (the strain time); the ghost image disappears over time. Image persistence produces two types of ghost images: negative ghost images have brightness and darkness opposite to that of the fixed pattern (have opposite polarity), and positive ghost images have brightness and darkness the same as that of the fixed pattern (have the same polarity).

[0053] Figure 2A An example of negative ghosting is exemplarily shown. The OLED display device 10 displays a checkerboard pattern for a predetermined time (fixed pattern strain is applied), and then attempts to display an expected full-screen image 255 of an intermediate emission level. However, a ghost 253 caused by image sticking is displayed instead of the expected image 255. The ghost 253 is a checkerboard pattern of a different intermediate emission level.

[0054] The lightness and darkness pattern of the ghost image 253 is opposite to that of the original image 251. In other words, the light portion of the ghost image 253 corresponds to the black portion of the original image 251, and the dark portion of the ghost image 253 corresponds to the white portion of the original image 251.

[0055] Figure 2B shows the variation of the sub-pixel driving current, which corresponds to Figure 2A The change of the display image is shown in . The driving current is the current flowing in the OLED element; when the driving current is higher, the brightness of the OLED element increases. Figure 2B In FIG. 1 , the horizontal axis represents time, and the vertical axis represents driving current. Current I1 represents the driving current of the sub-pixel when the black level changes to the intermediate level. Current I2 represents the driving current of the sub-pixel when the white level changes to the intermediate level.

[0056] At time T0, the data signal of the sub-pixel changes from the value for the original image 251 to the value for the expected image 255. The drive current I1 of the sub-pixel that has displayed black increases to be higher than (overshoots) the target drive current I7, and then gradually decreases to the target drive current I7. In contrast, the drive current I2 of the sub-pixel that has displayed white decreases to be lower than (undershoots) the target drive current I7, and then gradually increases to the target drive current I7.

[0057] Now, the intensity IR of the ghost is defined as follows:

[0058] IR=2.0×(I1-I2) / (I1+I2)

[0059] Figure 2A and Figure 2B The intensity IR of the positive ghosting shown in Figure 2B is positive.

[0060] Figure 3A An example of positive ghosting is exemplarily shown. The OLED display device 10 displays the original image 251 of a checkerboard pattern for a predetermined time (applying a fixed pattern strain), and then attempts to display the expected full-screen image 255 at an intermediate emission level. However, instead of the expected image 255, the ghosting 257 caused by image retention is displayed. The ghosting 257 is a checkerboard pattern of different intermediate emission levels.

[0061] The brightness and darkness patterns of the ghosting 257 correspond to the brightness and darkness patterns of the original image 251. In other words, the bright part of the ghosting 257 corresponds to the white part of the original image 251, and the dark part of the ghosting 257 corresponds to the black part of the original image 251.

[0062] Figure 3B The change in the driving current of the sub-pixel is shown, which corresponds to Figure 3A the change in the displayed image shown in Figure 3A . In Figure 3B Figure 3B , the horizontal axis represents time, and the vertical axis represents the driving current. The current I1 represents the driving current of the sub-pixel changing from the black level to the intermediate level. The current I2 represents the driving current of the sub-pixel changing from the white level to the intermediate level.

[0063] At time T0, the data signal of the sub-pixel (for the pixel circuit therefor) changes from the value for the original image 251 to the value for the expected image 257. The driving current I1 of the sub-pixel that has displayed black increases significantly to a value lower than the target driving current I7, and then gradually increases to the target driving current I7. On the contrary, the driving current I2 of the sub-pixel that has displayed white decreases significantly to a value higher than the target driving current I7, and then gradually decreases to the target driving current I7. Figure 3A and Figure 3B The intensity IR of the positive ghosting shown in Figure 3B is negative.

[0064] The main cause of image retention is the transient response characteristic of the driving TFT, and whether the image retention (ghosting) is positive or negative is determined by the correction action of the pixel circuit (TFT substrate) on the threshold voltage of the driving TFT. Next, the relationship between image retention, the characteristics of the driving TFT, and the correction action of the pixel circuit on the data signal will be specifically described.

[0065] Figure 4 Figure 4 is a diagram for explaining the relationship between image retention, the characteristics of the driving TFT, and the correction action of the pixel circuit on the data signal in the OLED display device 10. In Figure 4In the figure, the horizontal axis represents time, and the vertical axis represents the drive current supplied to the OLED element. The driver IC 134 writes a new data signal to the pixel circuit in each frame. The pixel circuit corrects the threshold voltage (Vth correction) of the driving TFT by correcting the data signal (voltage) from the driver IC 134, and stores the data signal in the storage capacitor.

[0066] In Figure 4 the example, the driver IC 134 changes the data signal to be applied to the pixel circuit at time T0 from the data signal of the black level to the data signal of the intermediate level. Subsequently, the driver 134 writes the data signal of the intermediate level to the pixel circuit in each frame. The pixel circuit performs Vth correction on the data signal (voltage) and stores the corrected data signal in the storage capacitor.

[0067] Line 301 represents the transient response characteristic of the driving TFT from the black level to the intermediate level (when Vth correction is not performed). According to the transient response characteristic 301 of the driving TFT, the drive current increases from the value of the black level and overshoots the target current value 311 of the intermediate level at time T0, and then gradually decreases to approach the target current value 311. The driving TFT has a negative transient response characteristic.

[0068] Line 303 represents the change in the drive current of the ideal correction. The ideal drive current 303 becomes the target current value 311 each time the driver IC134 writes the data signal, and then changes according to the transient response characteristic of the driving TFT.

[0069] Line 305 represents the change in the drive current of the overcorrection. This correction changes the drive current so that the transient response characteristic of the driving TFT will be compensated. Therefore, the overcorrected drive current 305 becomes lower than the target current value 311 each time the driver IC 134 writes the data signal, and then changes according to the transient response characteristic of the driving TFT. The excessive correction amount gradually becomes smaller so that the drive current gradually becomes closer to the target current value 311. In the case of overcorrection, the response of the drive current has the opposite polarity to the transient response of the driving TFT; positive image sticking occurs.

[0070] Line 307 represents the change in the drive current of the undercorrection. This correction changes the drive current so that the transient response characteristic of the driving TFT will be compensated. Therefore, the undercorrected drive current 307 becomes higher than the target current value 311 each time the driver IC 134 writes the data signal, and then changes according to the transient response characteristic of the driving TFT. The insufficient correction gradually weakens so that the drive current gradually becomes closer to the target current value 311. In the case of undercorrection, the response of the drive current has the same polarity as the transient response of the driving TFT; negative image sticking occurs.

[0071] As described above, image retention is caused by the current transient response due to the hysteresis effect of the driving TFT and the correction operation of the pixel circuit. Since the correction operation of the pixel circuit is determined by the circuit system of the pixel circuit, by appropriately designing the pixel circuit, the intensity of ghosting (image retention) can be made close to zero.

[0072] Embodiments of the present disclosure provide a pixel circuit that includes a circuit (circuit element) for adjusting its correction operation. As a result, a pixel circuit that eliminates ghosting of image retention can be easily designed.

[0073] Pixel circuit

[0074] Figure 5 An example of the configuration of the pixel circuit 500 in an embodiment of the present disclosure is shown. The pixel circuit 500 includes a correction operation adjustment element (circuit). In the pixel circuit 500, a capacitor (first capacitor) Cp and a resistor Rst are used to adjust the correction operation to reduce image retention. The resistor Rst may be optional.

[0075] The pixel circuit 500 corrects the data signal supplied by the driver IC 134 and controls the light emission of the OLED element using the corrected data signal. The pixel circuit 500 includes seven transistors (TFTs) M1 - M7, each having a gate terminal, a source terminal, and a drain terminal. The transistors M1 - M7 in this example are P-type TFTs.

[0076] The transistor M3 is a driving transistor for controlling the amount of current supplied to the OLED element E1. The driving transistor M3 controls the amount of current to be supplied from the anode power supply VDD to the OLED element according to the voltage held by the storage capacitor Cst. The cathode of the OLED element E1 is connected to the cathode power supply VEE. The storage capacitor Cst holds the gate-source voltage (also simply referred to as the gate voltage) of the driving transistor M3.

[0077] The transistors M1 and M6 control whether the OLED element E1 is lit. The transistor (third switching transistor) M1 is connected to the anode power supply VDD through its source terminal to switch on / off the current supply to the driving transistor M3 connected through its drain terminal. The transistor (fifth switching transistor) M6 is connected to the drain terminal of the driving transistor M3 through its source terminal to switch on / off the current supply to the OLED element E1 connected through its drain terminal. The transistors M1 and M6 are controlled by the emission control signal Emi input to their gate terminals from the scanning circuits 131 or 132.

[0078] The transistor (sixth switching transistor) M7 operates to supply a reset potential (second reset potential) to the anode of the OLED element E1. In response to the input of the selection signal S2 from the scan circuit 131 or 132 to the gate terminal, the transistor M7 is turned on to supply the reset potential from the reset power supply Vrst to the anode of the OLED element E1. The other terminal of the reset power supply Vrst is grounded.

[0079] The transistor (fourth switching transistor) M5 controls whether to supply a reset potential (first reset potential) to the gate of the driving transistor M3. In response to the input of the selection signal S1 from the scan circuit 131 or 132 to the gate terminal, the transistor M5 is turned on to supply the reset potential from the reset power supply Vrst connected to the drain terminal to the gate of the driving transistor M3. The other terminal of the reset power supply Vrst is grounded. The reset potential supplied to the gate of the driving transistor M3 may be different from the reset potential supplied to the anode of the OLED element E1.

[0080] The transistor (first switching transistor) M2 is a selection transistor for selecting the pixel circuit 500 to which the data signal is to be supplied. The gate voltage of the transistor M2 is controlled by the selection signal S2 supplied from the scan circuit 131 or 132. When the selection transistor M2 is turned on, it supplies the data signal Vdata supplied from the driver IC 134 to the gate (storage capacitor Cst) of the driving transistor M3 through the data line.

[0081] In this example, the selection transistor M2 (its source and drain) is connected between the data line and the source M3S of the driving transistor M3. In addition, the transistor (second switching transistor) M4 is connected between the drain M3D and the gate of the driving transistor M3.

[0082] The transistor M4 operates to correct the threshold voltage of the driving transistor M3. When the transistor M4 is on, the driving transistor M3 becomes a diode-connected transistor. The data signal Vdata from the data line is supplied to the storage capacitor Cst through the on-state selection transistor M2 and the channels (source and drain) of the driving transistor M3 and the transistor M4.

[0083] The storage capacitor Cst stores the gate-source voltage of the driving transistor M3. In Figure 5 the example, one end of the storage capacitor Cst is connected to the gate of the driving transistor M3, and the other end is connected to the node between the source of the transistor M1 and the anode power supply VDD.

[0084] The storage capacitor Cst stores the data signal (voltage) corrected based on the threshold voltage Vth of the driving transistor M3. As Figure 5As shown, the pixel circuit 500 includes another capacitor Cp, one end of which is connected to the drain of the driving transistor M3 (the node on the drain side). One end (electrode) of the capacitor Cp has the same potential as the potential of the drain, and the other end (electrode) is supplied with a fixed potential. In Figure 5 In the configuration example, the other end of the capacitor Cp is connected to the anode power supply VDD. The value and polarity of the fixed potential supplied to the other end of the capacitor Cp are not particularly limited.

[0085] The pixel circuit 500 also includes a finite resistor Rst connected in parallel with the storage capacitor Cst. One end of the resistor Rst is connected to the gate of the driving transistor M3, and the other end is connected to the node between the source of the transistor M1 and the anode power supply VDD. As will be described below, by appropriately selecting the values of the storage capacitor Cst, the capacitor Cp, and the resistor Rst, the ghosting caused by image retention can be reduced to near zero.

[0086] Figure 6 is a timing diagram of the signals for controlling Figure 5 the pixel circuit 500 in one frame period. Figure 6 The timing diagram of Figure 6 will select the Nth row and write the data signal Vdata to the pixel circuit 500. Specifically, Figure 5 shows the changes in the emission control signal Emi, the selection signal S1, the selection signal S2, and

[0087] the potential N1S of the node N1 in

[0088] one frame. The potential N1S of the node N1 is equal to the gate potential of the driving transistor M3.

[0089] At time T3, the selection signal S1 changes from low to high. At this time T3, the emission control signal Emi and the selection signal S2 are high. According to the change of the selection signal S1, the transistor M5 is turned off. From time T3 to time T4, the transistors M1, M2, and M4 to M7 are off.

[0090] At time T4, the selection signal S2 changes from high to low. At this time T4, the emission control signal Emi and the selection signal S1 are high. According to the change of the selection signal S2, the transistors M2, M4, and M7 are set to be turned on. The transistors M1, M5, and M6 are off.

[0091] The reset potential of the reset power supply Vrst is supplied to the anode of the OLED element E1 by the transistor M7 that becomes on. Since the transistor M4 is on, the driving transistor M3 is diode-connected. Since the transistor M2 is on, the data signal Vdata from the data line is written to the storage capacitor Cst through the transistors M2, M3, and M4.

[0092] The voltage to be written to the storage capacitor Cst is the voltage obtained by correcting the data signal Vdata, thereby including the correction of the threshold voltage Vth of the driving transistor M3. In the period from time T4 to time T5, the writing of the data signal Vdata to the pixel circuit 500 and the Vth correction of the data signal Vata are performed.

[0093] At time T5, the selection signal S2 changes from low to high. At this time T5, the emission control signal Emi and the selection signal S1 are high. According to the change of the selection signal S2, the transistors M2, M4, and M7 are turned off. The transistors M1, M2, and M4 to M7 are off. The control signal and the transistors are maintained in these states from time T5 to time T6.

[0094] At time T6, the emission control signal Emi changes from high to low, and the transistors M1 and M6 are changed from off to on. The selection signals S1 and S2 are high, while the transistors M2, M4, M5, and M7 remain off. The driving transistor M3 controls the driving current to be supplied to the OLED element E1 based on the corrected data signal stored in the storage capacitor Cst. This means that the OLED element E1 emits light.

[0095] The operation of the above pixel circuit shows that the amount of correction of the threshold voltage Vth, or the point of the node potential N1S obtained in the period from time T4 to time T5, can be controlled by changing the period during which the selection signal S2 is low. The point at which the node potential N1S is obtained determines whether the correction of the threshold voltage Vth is excessive or insufficient.

[0096] However, data signal Vdata also needs to be written during this period. Therefore, the flexibility to actually change the low period of selection signal S2 is relatively small. Thus, if it is possible to configure the pixel circuit that can control ghosting in a way different from selection signal S2 without increasing the size of the pixel circuit and the manufacturing process, the OLED display device will achieve more performance improvements.

[0097] As mentioned above, by appropriately selecting the capacitances of storage capacitor Cst and capacitor Cp, and the resistance of resistor Rst, the intensity of ghosting can be reduced to nearly zero. Next, a method for designing such circuit elements will be described.

[0098] Figure 7 Simulation results regarding the relationship between time constant τst and the intensity of ghosting are provided. Time constant τst is the product of the capacitance of storage capacitor Cst and the resistance of resistor Rst (value of Cst × value of Rst). In Figure 7 the figure, the horizontal axis represents time constant τst, and the vertical axis represents the intensity of ghosting. The dot markers with different shapes represent the relationship between time constant τst and the intensity of ghosting when capacitor Cp has different capacitances. In Figure 7 the figure, the results showing different intensities under the conditions of the same capacitance of capacitor Cp and the same time constant are based on different combinations of the capacitance of storage capacitor Cst and the resistance of resistor Rst.

[0099] When the intensity of ghosting is higher than zero, the ghosting (image retention) is negative; when the intensity of ghosting is lower than zero, the ghosting (image retention) is positive. Figure 7 The simulation results in

[0100] show that by reducing time constant τst, positive ghosting can be transformed into negative ghosting. Conversely, by increasing time constant τst, negative ghosting can be transformed into positive ghosting. In the range 601 where time constant τst is not less than 0.05 seconds (s) but not more than 0.1 s, the intensity of ghosting can be controlled to be almost zero. Considering less perceivable ghosting, it is well known that the human eye cannot perceive a difference if the brightness difference between adjacent regions is less than 1%. Therefore, the intensity of ghosting is designed to be in a range 603 such as the absolute value of the intensity is not greater than 0.005 (this value is not less than -0.005 but not more than +0.005).

[0101] Figure 8AThe simulation results regarding the relationship between the ratio of the capacitance of capacitor Cp to the capacitance of storage capacitor Cst (value of Cp / value of Cst) and the ghosting intensity are provided. The horizontal axis represents the ratio of capacitances (value of Cp / value of Cst), while the vertical axis represents the ghosting intensity. The point markers with different shapes represent the relationship between the ratio of the capacitance of capacitor Cp to the capacitance of storage capacitor Cst and the ghosting intensity under the condition that the time constant τst (value of Cst × value of Cp) takes different values. In Figure 8A 's figure, the results with different intensities are shown under the conditions of the same time constant and the same value of capacitance ratio based on different combinations of the capacitance of storage capacitor Cst and the resistance of resistor Rst.

[0102] Figure 8A The simulation results show that as the capacitance of capacitor Cp (value of Cp / value of Cst) decreases, the negative intensity of the ghosting turns to zero. On the contrary, as the capacitance of capacitor Cp increases, the positive intensity of the ghosting turns to zero. Figure 8A These simulation results also show that when the condition that the capacitance of capacitor Cp is greater than the capacitance of storage capacitor Cst (value of Cp > value of Cst) is satisfied, the intensity of the ghosting can be reduced within a wider range of time constants.

[0103] The operation of capacitor Cp can generally be assumed as follows. In Figure 8B , the dashed line 602 represents the voltage waveform of node N1 when the value of capacitor Cp is greater than the value of storage capacitor Cst. In Figure 8C , the dashed line 604 represents the voltage waveform of node N1 when the value of capacitor Cp is less than the value of storage capacitor Cst. Figure 8B and Figure 8C The times T1 to T6 in Figure 6 correspond to the times T1 to T6 in

[0104] In the instance where the select signal S2 becomes low at time T4, the redistribution of charge begins between the charge Qst held by storage capacitor Cst and the charge Qp held by capacitor Cp. The electric potential Vz of node N1 at time T4 is the following value determined by the ratio of the value of capacitor Cp to the value of storage capacitor Cst:

[0105]

[0106] Where Vx represents the potential of the drain node of driving transistor M3 immediately before time T1, and Vrst represents the reset potential of reset power supply Vrst. The reset potential Vrst is typically equal to the potential of VEE or a negative value close thereto; the relationship Vrst < Vx is always satisfied. According to formula (1), if the value of storage capacitor Cst is greater than the value of capacitor Cp, the value of Vz takes a negative value close to the reset potential Vrst; if the value of capacitor Cp is greater than the value of storage capacitor Cst, the value of Vz takes a value close to Vx.

[0107] Figure 8B and Figure 8C These characteristics are shown in . The value of the current used to charge storage capacitor Cst through the channel of driving transistor M3 during the period from time T4 to time T5 depends on the value of Vz. When Vz is a larger negative value, a larger charging current is required. As Vz shifts towards the positive value, the charging current decreases. This difference in the value of Vz also causes differences in the amount of Vth correction and image residue.

[0108] Figure 9 Simulation results regarding the time variation of ghost intensity in the case where resistor Rst has different resistances are provided. The horizontal axis represents time, and the vertical axis represents ghost intensity. As Figure 9 shown by the simulation results in Figure 9 , as the resistance of resistor Rst becomes smaller, the ghost caused by image residue changes from a positive ghost to a negative ghost, and conversely, as the resistance of resistor Rst becomes larger, it changes from a negative ghost to a positive ghost.

[0109] The operation of resistor Rst can generally be assumed as follows. Resistor Rst discharges storage capacitor Cst, thereby reducing the driving current of driving transistor M3. This means that resistor Rst reduces the amount of correction for the data signal, so that the operation of driving transistor M3 changes from an overcorrection state to an undercorrection state in terms of direction. That is, the ghost caused by image residue changes from a positive ghost to a negative ghost.

[0110] In this connection, when the resistance of resistor Rst is small, the driving current decreases as storage capacitor Cst discharges during the frame period, causing a brightness change (flicker). Figure 10 Exemplarily, the brightness change in one frame caused by resistor Rst is shown. In Figure 10 the figure of Figure 10 , the horizontal axis represents time, and the vertical axis represents the driving current. As storage capacitor Cst is discharged due to resistor Rst, the decrease in the driving current increases during one frame period, causing a greater change in brightness.

[0111] The intensity F of the flicker is defined as follows:

[0112] F = (I3 – I4) / (I3 + I4)

[0113] Here, I3 represents the driving current at the start of a frame, and I4 represents the driving current at the end of a frame.

[0114] Figure 11 The simulation results regarding the relationship between the intensity F of the flicker and the time constant τst (the value of Cst × the value of Rst) are provided. The horizontal axis represents the time constant τst (the value of Cst × the value of Rst), and the vertical axis represents the intensity F of the flicker. The dot markers with different shapes represent the relationship between the time constant and the flicker intensity in the case where the capacitor Cp has different capacitances.

[0115] Considering the image quality of the OLED display device 10, the intensity of the flicker is selected to be in the range 605 of, for example, not greater than 0.5. According to Figure 11 the simulation results in, the corresponding range of the time constant τst is not less than 0.1 s. As Figure 11 shown by the simulation results in, the intensity of the flicker does not depend on the capacitance of the capacitor Cp.

[0116] As described above, considering both the ghosting intensity and the flicker intensity, it is important to determine the ratio of the capacitance of the capacitor Cp to the capacitance of the storage capacitor Cst (the value of Cp / the value of Cst) and the time constant (the value of Cst × the value of Rst).

[0117] First, the range of the time constant τst (the value of Cst × the value of Rst) and the range of the ratio of the capacitance of the capacitor Cp to the capacitance of the storage capacitor Cst (the value of CP / the value of Cst) that make the absolute value of the ghosting intensity fall within the range of not greater than 0.005 (the intensity value is not less than -0.005 but not greater than +0.005) are described. Figure 12 The simulation results regarding the relationship between the ratio of the capacitance of the capacitor Cp to the capacitance of the storage capacitor Cst, the time constant τst, and the ghosting intensity are provided.

[0118] In Figure 12 the figure of, the horizontal axis represents the ratio of the capacitance of the capacitor Cp to the capacitance of the storage capacitor Cst, and the vertical axis represents the logarithm of the time constant τst. The axis (not shown) along the Figure 12 normal represents the ghosting intensity. In Figure 12 the figure of, the region 611 surrounded by the dashed line represents the range where the absolute value of the ghosting intensity is not greater than 0.005.

[0119] Figure 12 The simulation results in show that one of the following two conditions must be satisfied for the absolute value of the ghosting intensity to be in the range of not greater than 0.005. One condition is that the time constant τst is not less than 0.06 s but less than 0.1 s (0.06 s ≤ τst < 0.1 s).

[0120] Another condition is that the ratio of the capacitance of capacitor Cp to the capacitance of storage capacitor Cst is not less than 2.0 (value of Cp / value of Cst ≥ 2.0), and the time constant τst is not less than 0.06 (τst ≥ 0.06). When any of these conditions is satisfied, the combination of the ratio of the capacitance of capacitor Cp to the capacitance of storage capacitor Cst and the time constant can obtain an absolute value of the ghosting intensity not greater than 0.005.

[0121] Next, the range of the time constant τst (value of Cst × value of Rst) and the range of the ratio of the capacitance of capacitor Cp to the capacitance of storage capacitor Cst (value of CP / value of Cst) that make the absolute value of the flicker intensity fall within the range not greater than 0.5 are described. Figure 13 Simulation results regarding the relationship between the ratio of the capacitance of capacitor Cp and the capacitance of storage capacitor Cst, the time constant τst, and the flicker intensity are provided.

[0122] In Figure 13 the graph, the horizontal axis represents the ratio of the capacitance of capacitor Cp to the capacitance of storage capacitor Cst, and the vertical axis represents the logarithm of the time constant τst. The axis (not shown) along the Figure 13 normal represents the flicker intensity. In Figure 13 the graph, the region 613 surrounded by the dashed line represents the range where the flicker intensity is not greater than 0.5. Figure 13 The simulation results in

[0123] Figure 14 show that for the flicker intensity to be within the range not greater than 0.5, the time constant τst must be not less than 0.1 (τst ≥ 0.1). In this range, the combination of the ratio of the capacitance of capacitor Cp to the capacitance of storage capacitor Cst and the time constant can obtain a value of the flicker intensity not greater than 0.5. Figure 14 The simulation results in Figure 14 show that for the absolute value of the ghosting intensity to be within the range not greater than 0.005, the ratio of the capacitance of capacitor Cp to the capacitance of storage capacitor Cst must be not less than 2.0 (value of Cp / value of Cst ≥ 2.0). The above research reveals that if the following conditions are met, the absolute value of the ghosting intensity will not be greater than 0.005 and the flicker intensity will not be greater than 0.5.

[0124] Figure 14 The simulation results in

[0125] The conditions to be satisfied are that the ratio of the capacitance of capacitor Cp to the capacitance of storage capacitor Cst is not less than 2.0 (Cp value / Cst value ≥ 2.0), and the time constant τst (Cst value × Rst value) is not less than 0.1 s (τst ≥ 0.1 s).

[0126] As described above, by determining the capacitances of storage capacitor Cst and capacitor Cp and the resistance of resistor Rst to satisfy a predetermined condition, image sticking of the OLED display device 10 can be more effectively reduced. Even if the finite resistor Rst (the resistance is infinite) is not included, image sticking can be reduced by increasing capacitor Cp.

[0127] Device Structure

[0128] Next, an example of the device structure of storage capacitor Cst, resistor Rst, and capacitor Cp in the pixel circuit will be described. Figure 15 is a plan view exemplarily showing a structural portion including storage capacitor Cst and resistor Rst. Storage capacitor Cst includes upper electrode 631 and lower electrode 633 opposed to upper electrode 631. The metal materials for upper electrode 631 and lower electrode 633 can be ideally selected; for example, molybdenum, tungsten, niobium, or aluminum can be used. An insulating layer is provided between upper electrode 631 and lower electrode 633, although Figure 15 not shown in. Some portions of upper electrode 631 overhang the edge of lower electrode 633. These overlapping regions 635A and 635B become resistor Rst.

[0129] Figure 16 Exemplarily shows along Figure 15 the cross-sectional structure of the section line XVI-XVI in. Gate insulating film 639 is placed to cover polysilicon film 637. Gate insulating film 639 can be a silicon oxide film, a silicon nitride film, or a stack of these films. Lower electrode (gate) 633 is placed on gate insulating film 639 and furthermore, interlayer metal dielectric film 641 is placed to cover lower electrode (gate) 633. Upper electrode 631 is placed on interlayer metal dielectric film 641, opposed to lower electrode 633.

[0130] Interlayer metal dielectric film 641 is an inorganic thin film (for example, having a thickness of 100 nm), and can be a silicon nitride film or a silicon oxide film. Thin interlayer metal dielectric film 641 has a finite resistance, which can become the resistor between the edge of lower electrode 633 and the overhanging portion of upper electrode 631. The resistance of resistor Rst can be controlled by changing the perimeter by which lower electrode 633 is overhung by upper electrode 631. Specifically, the resistance can be reduced by extending this perimeter.

[0131] As described above, the storage capacitor Cst includes a part of the lower electrode 633, a part of the upper electrode 631, and a part of the interlayer metal dielectric film 641. The resistor Rst is formed in a part of the interlayer metal dielectric film 641 located between the edge of the lower electrode 633 and the part of the upper electrode 631 that overhangs the edge.

[0132] Figure 17 is an exemplary plan view of a pixel circuit portion including its storage capacitor Cst, capacitor Cp, resistor Rst, and driving transistor M3. The gate GM is provided to cover a part of the polysilicon film p-Si. The gate GM is the gate of the driving transistor M3. The polysilicon film p-Si includes the source M3S and drain M3D of the driving transistor M3. In addition, the upper electrode MC is provided to cover the gate GM.

[0133] Figure 18 Exemplarily shown along Figure 17 the cross-sectional structure taken along the section line XVIII-XVIII in. The underlying film UC made of, for example, silicon nitride is provided on the substrate SUB. The polysilicon film p-Si is placed on the underlying film UC. In addition, the gate insulating film GI is placed to cover the polysilicon film p-Si.

[0134] The gate GM is placed on the gate insulating film GI. The interlayer metal dielectric film IMD is placed to cover the gate GM. The upper electrode MC is placed on the interlayer metal dielectric film IMD. A part of the upper electrode MC straddles the interlayer metal dielectric film IMD and faces the gate GM to form the storage capacitor Cst.

[0135] A part of the upper electrode MC overhangs the edge of the gate GM to form the resistor Rst there. Another part of the upper electrode MC straddles the interlayer metal dielectric film IMD and the gate insulating film GI and faces the polysilicon film p-Si to form the capacitor Cp.

[0136] The interlayer insulating film IDL is placed to cover the upper electrode MC. A contact hole is opened through the interlayer insulating film IDL, the upper electrode MC, and the interlayer metal dielectric film IMD. The metal wire ML2 contacts the gate GM in the contact hole. The passivation film PV and the planarization film PLN thereon are provided to cover Figure 18 the entire element shown in. The interlayer insulating film IDL and the passivation film PV can be inorganic films such as silicon nitride films or silicon oxide films. The planarization film PLN can be an organic film.

[0137] As described above, configuring the pixel circuit to include the capacitor Cp and the resistor Rst does not increase the layout area significantly. In addition, the capacitor Cp and the resistor Rst can be fabricated without adding to the manufacturing process of the TFTs and the pixel circuit. Therefore, an OLED display device that can display high-quality images with less image retention can be provided without increasing the cost or reducing the yield.

[0138] Next, another configuration example of the capacitor Cp will be described. Figure 19 A configuration example of the capacitor Cp is shown. As Figure 19 shown, the capacitor Cp can be configured as a TFT in which the source 673 and the drain 675 are short-circuited. The gate 671, the source / drain 673, 675, and the gate insulating film therebetween form the capacitor. The gate 671 is supplied with a reset potential such as the reset power supply Vrst. Figure 19 The TFT in the example of is a p-type TFT, and thus the gate potential is lower than the source / drain potential. This configuration results in a small-sized capacitor Cp.

[0139] Figure 20 is an exemplary plan view of a pixel circuit portion including its storage capacitor Cst, capacitor Cp, resistor Rst, and driving transistor M3. The capacitor Cp has Figure 19 the configuration shown. The gate GM1 is provided to cover a part of the polysilicon film p-Si. The gate GM1 is the gate of the driving transistor M3. The polysilicon film p-Si includes the source M3S and the drain M3D of the driving transistor M3. In addition, the upper electrode MC1 is provided to cover the gate GM1.

[0140] Another gate GM2 is provided on the same layer as the gate GM1 to cover another part of the polysilicon film p-Si. The gate GM2 is the gate of the capacitor Cp configured as a TFT. The upper electrode MC2 is provided on the same layer as the upper electrode MC1 to cover a part of the gate GM2.

[0141] Figure 21 An exemplary cross-sectional structure along the Figure 20 section line XXI-XXI in is shown. The differences from the Figure 18 configuration example will be mainly described below. The gate GM2, the part of the polysilicon film p-Si opposite to the gate GM2, and the gate insulating film GI therebetween form the capacitor Cp. The upper electrode MC2 is in contact with the gate GM2 through a contact hole opened through the interlayer metal dielectric film IMD. The upper electrode MC2 supplies the reset potential from the reset power supply Vrst to the gate GM2. As described in this description, the capacitor Cp is a metal-insulator-semiconductor (MIC) type capacitor formed by stacking an insulating layer and a metal layer on a semiconductor film.

[0142] Figure 22 shows a configuration example 800 of a pixel circuit based on Figure 19 . It is known that the OLED display device 10 has differences in characteristics when being produced. As Figure 12 shown, there is a relationship such as that in region 611 between the time constant for obtaining weak ghosting and the value of Cp / the value of Cst. For example, when there are differences in the value of Rst or the value of Cst among a plurality of OLED display devices, if the capacitor Cp is a variable capacitor, the ratio of the value of Cp to the value of Cst can be adjusted according to such differences.

[0143] Figure 22 The pixel circuit 800 in [[ ]] includes a variable capacitor Cpv connected to the drain node of the driving transistor M3, rather than Figure 5 the capacitor Cp in the pixel circuit 500 in [[ ]]. The variable capacitor Cpv can be a MIS capacitor. The driver IC 134 applies a variable control potential VCTL to the gate of the variable capacitor Cpv through the lead Vct. As a result, the capacitance of the variable capacitor Cpv can be controlled using its gate potential from the outside. By controlling the capacitance of the variable capacitor Cpv using the control potential VCTL, the intensity of image retention of each product can be minimized individually.

[0144] Figure 23 shows a planar pattern of a pixel including the variable capacitor Cpv and the lead Vcl. In the configuration described with reference to Figure 19 and 20 , the gate GM2 of the capacitor Cp configured as a TFT is supplied with a reset potential from the reset power supply Vrst. In contrast, Figure 22 and Figure 23 the gate GCP of this variable capacitor Cpv in [[ ]] is supplied with the variable control potential VCTL through the line Vct.

[0145] Figure 24 is a cross-sectional view along the Figure 23 section line XXIV - XXIV in [[ ]]. Except that the capacitor Cpv replaces the capacitor Cp, this cross-sectional structure is the same as the cross-sectional structure shown in Figure 21 . The variable capacitor Cpv has the same stacked structure as the structure described with reference to Figure 21 . The gate GCP of the variable capacitor Cpv is led out of the panel area through the lead Vct. The lead Vct is made of the same material as the upper electrode MC1. The lead Vct is led out in parallel with the row scan line, and all the leads Vct are connected together outside the display area to be supplied with the control potential together.

[0146] Figure 25An example of the voltage-capacitance characteristics of the variable capacitor Cpv is provided. The capacitance is variable with the control potential VCTL in the range of 15 fF to 40 fF. Thus, the capacitor Cpv enables adjustment of the ratio of the value of Cpv to the value of Cst from the outside. In an actual product, due to differences in the transient response characteristics of the TFT, the value of Rst, and the value of Cst, there are differences within a certain range in the manifestation of their ghosting. By adjusting the value of the variable capacitor Cpv of the completed panel from the outside to optimize the ratio of the value of Cpv to the value of Cst, the image residual intensity of each panel can be minimized.

[0147] As described above, embodiments of the present disclosure have been described; however, the present disclosure is not limited to the foregoing embodiments. Those of ordinary skill in the art can easily modify, add, or transform each element in the foregoing embodiments within the scope of the present disclosure. A part of the configuration of one embodiment can be replaced by the configuration of another embodiment, or the configuration of one embodiment can be incorporated into the configuration of another embodiment.

Claims

1. A pixel circuit configured to control a driving current for a light-emitting element, the pixel circuit comprising: A driving transistor configured to supply a driving current to the light-emitting element; A first switching transistor including a source, a gate connected to a scan line, and a drain, the first switching transistor configured to transmit a data signal corresponding to the driving current, one of the source and the drain of the first switching transistor being connected to a data line, and the other of the source and the drain of the first switching transistor being connected to the source of the driving transistor; A storage capacitor including two electrodes connected between the gate of the driving transistor and a power supply line and configured to receive the data signal from the first switching transistor and store a voltage to be applied to the gate of the driving transistor; A second switching transistor including a source, a gate connected to the scan line, and a drain and configured to correct the voltage to be stored in the storage capacitor, one of the source and the drain of the second switching transistor being connected to the drain of the driving transistor, and the other of the source and the drain of the second switching transistor being connected to the gate of the driving transistor; And A first capacitor including an electrode connected to the drain of the driving transistor and an electrode to which a predetermined potential is to be supplied; A resistor connected in parallel with the storage capacitor; A lower electrode; An upper electrode; And A dielectric film between the lower electrode and the upper electrode; Wherein the storage capacitor includes a part of the lower electrode, a part of the upper electrode, and a part of the dielectric film between the part of the lower electrode and the part of the upper electrode, and Wherein the resistor is formed in a part of the dielectric film located between an edge of the lower electrode and a part of the upper electrode overhanging the edge, Wherein a product of a capacitance of the storage capacitor and a resistance of the resistor is not less than 0.1 second, and Wherein a value obtained by dividing a capacitance of the first capacitor by a capacitance of the storage capacitor is not less than 2.

2. A pixel circuit configured to control a driving current for a light-emitting element, the pixel circuit comprising: A driving transistor configured to supply a driving current to the light-emitting element; A first switching transistor including a source, a gate connected to a scan line, and a drain, the first switching transistor configured to transmit a data signal corresponding to the driving current, one of the source and the drain of the first switching transistor being connected to a data line, and the other of the source and the drain of the first switching transistor being connected to the source of the driving transistor; A storage capacitor including two electrodes connected between the gate of the driving transistor and a power supply line and configured to receive the data signal from the first switching transistor and store a voltage to be applied to the gate of the driving transistor; A second switching transistor, comprising a source, a gate connected to a scan line, and a drain, and configured to correct a voltage to be stored in the storage capacitor, one of the source and the drain of the second switching transistor is connected to the drain of the driving transistor, and the other of the source and the drain of the second switching transistor is connected to the gate of the driving transistor; and a first capacitor, comprising an electrode connected to the drain of the driving transistor and an electrode to which a predetermined potential is to be supplied, wherein the first capacitor is a variable capacitor, a resistor, connected in parallel with the storage capacitor; wherein the product of the capacitance of the storage capacitor and the resistance of the resistor is not less than 0.1 second, and wherein a value obtained by dividing the capacitance of the first capacitor by the capacitance of the storage capacitor is not less than 2.

3. A pixel circuit configured to control a driving current for a light-emitting element, the pixel circuit comprising: a driving transistor configured to supply a driving current to the light-emitting element; a first switching transistor, comprising a source, a gate connected to a scan line, and a drain, the first switching transistor configured to transmit a data signal corresponding to the driving current, one of the source and the drain of the first switching transistor is connected to a data line, and the other of the source and the drain of the first switching transistor is connected to the source of the driving transistor; a storage capacitor, comprising two electrodes connected between the gate of the driving transistor and a power supply line, and configured to receive the data signal from the first switching transistor and store a voltage to be applied to the gate of the driving transistor; a second switching transistor, comprising a source, a gate connected to a scan line, and a drain, and configured to correct a voltage to be stored in the storage capacitor, one of the source and the drain of the second switching transistor is connected to the drain of the driving transistor, and the other of the source and the drain of the second switching transistor is connected to the gate of the driving transistor; and a first capacitor, comprising an electrode connected to the drain of the driving transistor and an electrode to which a predetermined potential is to be supplied, a third switching transistor configured to control on / off of current supply to the driving transistor; a fourth switching transistor configured to supply a first reset potential to the gate of the driving transistor; a fifth switching transistor located between the driving transistor and the light-emitting element, the fifth switching transistor configured to control on / off of current supply to the light-emitting element; and a sixth switching transistor configured to supply a second reset potential to the anode of the light-emitting element, a resistor, connected in parallel with the storage capacitor; wherein the product of the capacitance of the storage capacitor and the resistance of the resistor is not less than 0.1 second, and wherein a value obtained by dividing the capacitance of the first capacitor by the capacitance of the storage capacitor is not less than 2.

4. The pixel circuit according to claim 2, wherein a capacitance value of the variable capacitor can be adjusted by a potential provided outside the pixel circuit.

5. The pixel circuit according to claim 1, 2 or 3, wherein all transistors of the pixel circuit are p-type transistors.

6. The pixel circuit according to claim 1, 2 or 3, wherein the first capacitor is a metal-insulator-semiconductor capacitor having a stacked structure of an insulating layer, a metal layer and a semiconductor film.

7. The pixel circuit according to claim 1, 2 or 3, wherein the first switching transistor and the second switching transistor are configured to be turned on simultaneously, wherein the second switching transistor is configured to hold the driving transistor in a diode-connected state when the second switching transistor is on, and wherein the charge to be stored in the storage capacitor is supplied to the storage capacitor through the channel of the driving transistor in the diode-connected state.

8. The pixel circuit according to claim 1, 2 or 3, wherein the first capacitor includes: a lower electrode included in the same semiconductor film as the drain of the driving transistor; and an insulating film and an upper electrode stacked on the lower electrode.

Images