Semiconductor device and method

Abstract

The present disclosure relates to semiconductor devices and methods. In an embodiment, a device includes: a semiconductor substrate; a first interlayer dielectric (ILD) located above the semiconductor substrate; a first conductive feature extending through the first ILD; a first etch stop layer located above the first conductive feature and the first ILD, the first etch stop layer being a first dielectric material; a second ILD located above the first etch stop layer; a contact having a first portion extending through the second ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature; and a first protective layer surrounding the second portion of the contact, the first portion of the contact being free of the first protective layer, the first protective layer being a second dielectric material, the second dielectric material being different from the first dielectric material.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and methods. Background Art

[0002] Typically, active and passive devices are formed on and in a semiconductor substrate. Once formed, these active and passive devices can be connected to each other and to external devices using a series of conductive and insulating layers. These layers can help interconnect the various active and passive devices and provide electrical connections to external devices through, for example, contact pads.

[0003] To form these interconnects within these layers, a range of lithography, etching, deposition, and planarization techniques may be employed. However, the use of these techniques has become more complex as the size of active and passive devices has decreased, which has also led to a desire to reduce the size of the interconnects. Therefore, there is a need to improve the formation and structure of the interconnects to make the overall device smaller, cheaper, more efficient, and with fewer defects or problems. Summary of the invention

[0004] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: depositing an etch stop layer over a first interlayer dielectric (ILD), the etch stop layer comprising a first dielectric material; depositing a second ILD over the etch stop layer; etching a first opening through the second ILD using a first dry etching process, the first opening exposing a first region of the etch stop layer, the first region being modified into a second dielectric material by the first dry etching process, a second region of the etch stop layer remaining covered by the second ILD, the second region being the first dielectric material after the first dry etching process; and extending the first opening through the etch stop layer using a first wet etching process, the etch stop layer being exposed to a first etching solution during the first wet etching process, the first etching solution comprising a dielectric protectant for the first dielectric material and an etchant for the second dielectric material.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a semiconductor substrate; a first interlayer dielectric (ILD) located above the semiconductor substrate; a first conductive feature extending through the first ILD; a first etch stop layer located above the first conductive feature and the first ILD, the first etch stop layer being a first dielectric material; a second ILD located above the first etch stop layer; a contact having a first portion extending through the second ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature; and a first protective layer surrounding the second portion of the contact, the first portion of the contact being free of the first protective layer, the first protective layer being a second dielectric material, the second dielectric material being different from the first dielectric material.

[0006] According to another embodiment of the present disclosure, a semiconductor device is provided, including: a semiconductor substrate; a first conductive feature located above the semiconductor substrate; a first etch stop layer located above the first conductive feature, the first etch stop layer being a first dielectric material; an interlayer dielectric (ILD) located above the first etch stop layer; and a contact having a first portion extending through the ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature, wherein the first portion of the contact has a first width, the second portion of the contact has a second width, the second width is greater than the first width by a first distance, and the first distance is in the range of 1 nm to 9 nm. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a simplified fin field effect transistor (FinFET) in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figures 2 to 19 is a cross-sectional view of an intermediate stage in fabricating a contact for a FinFET according to some embodiments.

[0010] Figures 20 to 28 is a cross-sectional view of an intermediate stage in fabricating a contact for a FinFET according to some other embodiments.

[0011] Figures 29 to 38is a cross-sectional view of an intermediate stage in fabricating a contact for a FinFET according to some other embodiments.

[0012] Figures 39 to 47 is a cross-sectional view of an intermediate stage in fabricating a contact for a FinFET according to some other embodiments.

[0013] Figures 48 to 57 is a cross-sectional view of an intermediate stage in fabricating a contact for a FinFET according to some other embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0016] According to some embodiments, an etch stop layer (ESL) is formed between adjacent dielectric layers, for example, between interlayer dielectrics (ILDs). The ESL is formed of aluminum oxide, and the ILD is formed of silicon oxide, allowing the ESL and the ILD to have high etching selectivity relative to a set of etching processes. Therefore, over-etching of the ESL can be avoided, thereby reducing the pattern loading effect. When forming an opening or gate contact for a source / drain, a multi-step etching is performed. Specifically, a dry etch is performed to pattern the overlying ILD, and then a wet etch is performed to extend the opening through the ESL. The wet etch includes a dielectric protectant, and during etching, the dielectric protectant assists in controlling the amount of lateral etching of the ESL by forming a protective layer on the sidewalls of the ESL. By controlling the amount of lateral etching, the amount of lateral etching of the ESL can be reduced, which helps to reduce the amount of leakage current from the contact subsequently formed in the opening.

[0017] Figure 1 An example of a simplified fin field effect transistor (FinFET) in a three-dimensional view according to some embodiments is shown. For clarity of illustration, some other features of the FinFET (discussed below) are omitted. The FinFET can be electrically connected or coupled in a manner such as to function as one or more transistors (e.g., four transistors). The FinFET includes a substrate 70 and a fin 72 extending from the substrate 70. Shallow trench isolation (STI) regions 74 are disposed above the substrate 70, and the fin 72 is above and protrudes between adjacent STI regions 74. The FinFET further includes a gate stack 76 disposed on the fin 72 and the STI regions 74. The gate stack 76 extends along the sidewalls of the fin 72 and above the top surface of the fin 72, and covers a corresponding channel region 78 of the fin 72 (see Figure 2 ). The FinFET also includes a source / drain region 80 disposed in the fin 72 on an opposite side of the gate stack 76 adjacent to the channel region 78 of the fin 72. Gate spacers 82 are disposed along sidewalls of the gate stack 76 and physically and electrically isolate the source / drain region 80 from the gate stack 76. A first interlayer dielectric (ILD) 84 is disposed over the source / drain region 80 along an opposite side of the gate stack 76. As further described below, a second ILD may be deposited over the first ILD 84.

[0018] The substrate 70 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 70 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. For example, the insulator layer may be a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate (typically a silicon substrate or a glass substrate). Other substrates may also be used, such as a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 70 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination of the foregoing. For example, when a p-type device is formed, the substrate 70 may be a strained material, such as silicon germanium (Si x Ge 1-x , where x may be in the range of 0 to 1), with a germanium concentration in the range of about 0% to about 40%, thereby forming a FinFET with a p-type fully strained channel (PFSC) region.

[0019] Fin 72 is a semiconductor strip. In some embodiments, fin 72 can be formed in substrate 70 by etching trenches in substrate 70, and the remaining material of substrate 70 between the trenches forms fin 72. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching process can be anisotropic.

[0020] The STI region 74 is formed of an insulating material. The insulating material may be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., deposition of a material based on chemical vapor deposition (CVD) in a remote plasma system, and post-curing to convert it into another material, e.g., oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable method may be used. In some embodiments, the insulating material is silicon oxide formed by an FCVD process. In some embodiments, a liner (not shown) may first be formed along the surface of the substrate 70 and the fin 72, and a filling material (e.g., the above-mentioned insulating material) may be formed on the liner. A removal process is applied to the insulating material to expose the fin 72. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be used to expose the fin 72, and the portion of the insulating material remaining after the planarization process forms the STI region 74.

[0021] The above process is only one example of how the fin 72 may be formed. The fin 72 and the STI region 74 may be formed by any acceptable process. In another embodiment, the fin 72 is formed after the STI region 74. For example, a layer of insulating material may be formed over the substrate 70, and an opening may be formed in the insulating material. The fin 72 may then be grown in the opening by an epitaxial growth process, and the portion of the insulating material remaining between the fins 72 forms the STI region 74.

[0022] Appropriate wells (not shown) may be formed in the fins 72 and / or substrate 70. When forming an n-type device such as an NMOS transistor (e.g., an n-type FinFET), a p-type well may be formed. When forming a p-type device such as a PMOS transistor (e.g., a p-type FinFET), an n-type well may be formed. In some embodiments, the wells are formed by implantation doping. In some embodiments, the growth material of the fins 72 and / or substrate 70 may be in-situ doped during growth, which may eliminate implantation doping, but in-situ doping and implantation doping may be used together.

[0023] The gate stack 76 may be formed by a gate-first process or a gate-last process. When the gate-first process is used, the gate stack 76 is initially formed over the corresponding channel region 78 of the fin 72, and then a gate spacer 82 is deposited along the sidewalls of the gate stack 76, a source / drain region 80 is grown adjacent to the gate spacer 82, and a first ILD 84 is deposited over the source / drain region 80. When the gate-last process is used, a dummy gate stack is initially formed over the channel region 78 of the fin 72, a gate spacer 82 is deposited along the sidewalls of the dummy gate stack, a source / drain region 80 is grown adjacent to the gate spacer 82, a first ILD 84 is deposited over the source / drain region 80, and then the dummy gate stack is replaced with a replacement gate stack 76. The gate stack 76 includes a gate dielectric 86 on the fin 72 and the STI region 74, and a gate electrode 88 over the gate dielectric 86. When a gate-last process is used, the gate dielectric 86 may extend along the sidewalls of the gate spacer 82 ; when a gate-first process is used, the gate dielectric 86 does not extend along the sidewalls of the gate spacer 82 .

[0024] The gate spacer 82 may be formed of a dielectric material such as silicon nitride, silicon carbide, combinations thereof, or the like. In some embodiments (not shown), the gate spacer 82 is formed of a multilayer insulating material and includes multiple layers. For example, the gate spacer 82 may include multiple layers of silicon nitride, or may include a silicon oxide layer disposed between two layers of silicon nitride.

[0025] The gate dielectric 86 may be formed of a dielectric material such as silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric 86 includes a high-k dielectric material, and in these embodiments, the gate dielectric 86 may have a k value greater than about 7.0 and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation method of the gate dielectric 86 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc.

[0026] The gate electrode 88 is deposited over the gate dielectric 86. The gate electrode 88 may include a metal-containing material, such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiple layers thereof. Figure 1 A single-layer gate electrode 88 is shown in FIG. 1 , but the gate electrode 88 may include any number of liner layers (not shown), any number of work function adjustment layers, and a fill material 88A (see FIG. 1 ). Figure 2 In some embodiments, the gate electrode 88 includes a cap layer 88B (see Figure 2 ), which can help reduce the resistance of the gate contact formed subsequently. After filling the gate electrode 88, a planarization process such as CMP can be performed to remove the gate dielectric 86 and the excess portion of the gate electrode 88 above the gate spacer 82.

[0027] The source / drain region 80 may be formed by an epitaxial growth process. In such an embodiment, a recess is formed in the fin 72 adjacent to the gate spacer 82. One or more epitaxial processes are performed to grow the source / drain region 80 in the recess. The source / drain region 80 may be formed of any acceptable material for a p-type or n-type device. For example, when an n-type device is required, the source / drain region 80 may include a material that applies tensile strain in the channel region of the fin 72, such as silicon, SiC, SiCP, SiP, etc. Similarly, when a p-type device is required, the source / drain region 80 may include a material that applies compressive strain in the channel region of the fin 72, such as SiGe, SiGeB, Ge, GeSn, etc. The source / drain region 80 is doped with n-type and / or p-type impurities and may be in-situ doped during growth, or dopants may be implanted after growth. In an embodiment in which multiple transistors are formed, the source / drain region 80 may be shared between the transistors. For example, in an embodiment where a transistor is formed from multiple fins 72, adjacent source / drain regions 80 may be electrically connected, such as by coalescing the source / drain regions 80 during epitaxial growth or by coupling the source / drain regions 80 to the same source / drain contact.

[0028] After forming the source / drain regions 80, a first ILD 84 is deposited over the source / drain regions 80. The first ILD 84 may be formed of a dielectric material and may be deposited by any suitable method, for example, CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable method may be used. In some embodiments, a contact etch stop layer (CESL) is disposed between the first ILD 84 and the gate stack 76, the source / drain regions 80, and the gate spacer 82. A planarization process such as CMP may then be performed to level the top surface of the first ILD 84 with the top surfaces of the gate stack 76 and the gate spacer 82. Therefore, the top surfaces of the gate stack 76, the gate spacer 82, and the first ILD 84 are level. Therefore, the top surface of the gate stack 76 is exposed through the first ILD 84.

[0029] Figures 2 to 19 is a cross-sectional view of an intermediate stage in fabricating a contact for a FinFET according to some embodiments. Figures 2 to 19 along Figure 1 The reference cross section AA shown in FIG. 8 shows that, in addition to the plurality of FinFETs, the cross section AA is along the longitudinal axis of the fin 72 and in the direction of current flow, for example, between the source / drain regions 80 .

[0030] Figure 2 shows that in the formation similar to Figure 1 70A and 70B of substrate 70 after the features of the FinFET shown in FIG. In some embodiments, region 70A is used to form an n-type device, and region 70B is used to form a p-type device. In some embodiments, regions 70A and 70B are used to form the same type of device. Regions 70A and 70B may include the same fin 72 or different fins 72.

[0031] exist Figure 3In the embodiment of the present invention, a gate mask 102 is formed over the gate stack 76. The gate mask 102 protects the gate stack 76 during subsequent processes, and the gate contact formed subsequently will penetrate the gate mask 102 to contact the top surface of the gate electrode 88. The gate mask 102 may also be formed over the gate spacer 82. As an example of forming the gate mask 102, the gate dielectric 86 and the gate electrode 88 are recessed by, for example, an acceptable etching process (e.g., wet etching or dry etching). The gate spacer 82 may also be partially recessed by an etching process. Due to the difference in etching rates of different materials, the gate electrode 88 may be recessed more than the gate dielectric 86 and the gate spacer 82. One or more layers of dielectric material, such as silicon nitride, silicon oxynitride, etc., are filled in the recess. In some embodiments, the gate mask 102 is formed of silicon nitride. A planarization process may be performed to remove the excess portion of the dielectric material extending over the first ILD 84. The remaining portion of the dielectric material in the recess forms the gate mask 102.

[0032] exist Figure 4A In the embodiment, the lower source / drain contacts 104 are formed through the first ILD 84 to physically and electrically couple them to the source / drain regions 80 . Figure 4B yes Figure 4A Detailed view of region 4B in FIG. 8 shows additional details of the lower source / drain contact 104. An opening of the lower source / drain contact 104 is formed through the first ILD 84. The opening can be formed using acceptable photolithography and etching techniques. For example, a liner 104A (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material 104B can be formed in the opening. The liner 104A can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material 104B can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. In some embodiments, the conductive material 104B is cobalt. A planarization process such as CMP can be performed to remove excess material from the top surface of the first ILD 84. The remaining liner 104A and the conductive material 104B form the lower source / drain contact 104. An annealing process can be performed to form a silicide at the interface between the lower source / drain contact 104 and the source / drain region 80.

[0033] In some embodiments, a contact liner 106 is formed around the lower source / drain contact 104. The contact liner 106 can be formed by conformally depositing a layer of a dielectric material such as silicon nitride, silicon oxynitride, etc. in the opening of the lower source / drain contact 104. The deposition can be performed by MBD, ALD, PECVD, etc. An acceptable etch (e.g., an anisotropic etch) can then be performed to remove the horizontal portion of the dielectric layer, forming the contact liner 106 along the remaining portion of the sidewall of the opening. The lower source / drain contact 104 can then be formed in the opening. The contact liner 106 is an additional layer that helps to physically and electrically separate the lower source / drain contact 104 from the gate stack 76.

[0034] exist Figure 5 In the embodiment of the present invention, an etch stop layer 108 is formed over the first ILD 84, the gate mask 102, the lower source / drain contacts 104, and the contact liner 106 (when formed). A second ILD 110 is then formed over the etch stop layer 108. The etch stop layer 108 is formed of a material having a high etch selectivity relative to the second ILD 110, so that the second ILD 110 is etched at a higher etch rate than the etch stop layer 108 for the same etching process. For example, the etch stop layer 108 is formed of an insulating material, such as a single layer of aluminum oxide. The etch stop layer 108 can be formed by a deposition process such as ALD, CVD, PECVD, etc. Because the etch stop layer 108 has a high etch selectivity relative to the second ILD 110 for the same etching process, it can be formed to a smaller thickness T 1 For example, the etch stop layer 108 may have a thickness of about to about The thickness T in the range 1 .

[0035] The second ILD 110 is a flowable film that can be formed by a flowable CVD method. In some embodiments, the second ILD 110 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD.

[0036] exist Figure 6, a source / drain contact opening 112 is formed through the second ILD 110. The source / drain contact opening 112 exposes the etch stop layer 108. The source / drain contact opening 112 can be formed using acceptable photolithography and etching techniques. A photoresist (not shown) is formed over the second ILD 110 and patterned with the pattern of the source / drain contact opening 112. In some embodiments, a dry etching process 114 is performed to transfer the pattern of the photoresist to the second ILD 110, thereby forming the source / drain contact opening 112. For example, in some embodiments, the dry etching process 114 includes generating a plasma sheath over the second ILD 110 using chlorine gas or bromine gas. The dry etching process 114 can be performed in an environment including argon or nitrogen, and can be performed for a duration ranging from about 10 seconds to about 150 seconds.

[0037] The material of the etch stop layer 108 (e.g., aluminum oxide) has a high etch selectivity relative to the material of the second ILD 110 (e.g., silicon oxide), so that the second ILD 110 is etched at a higher rate than the etch stop layer 108 for the dry etching process 114. For example, the ratio of the etch rate of the second ILD 110 to the etch rate of the etch stop layer 108 relative to the dry etching process 114 may be in a range of about 10:1 to about 100:1. Thus, during the dry etching process 114, the thickness T of the etch stop layer 108 is 1 The over-etching of the etch stop layer 108 can be reduced to reduce the loading effect in the subsequent process.

[0038] Figure 7 The dry etching process 114 is shown. Figure 6 Although the thickness T of the etch stop layer 108 is 1There is no substantial reduction during the dry etching process 114, but some regions 108D of the etch stop layer 108 are damaged (or more generally, modified) by the dry etching process 114. For example, the etchant of the dry etching process 114 may react with the material of the etch stop layer 108, thereby changing the material composition of the damaged etch stop layer region 108D. Depending on the precise parameters of the dry etching process 114, the new material composition of the damaged etch stop layer region 108D may be more porous. In some embodiments, the dry etching process 114 replaces oxygen in the damaged etch stop layer region 108D with fluoride or bromide. Therefore, the damaged etch stop layer region 108D is a different material from the undamaged etch stop layer region 108U. For example, the undamaged etch stop layer region 108U may still be formed of aluminum oxide, but the damaged etch stop layer region 108D may be formed of aluminum chloride, aluminum bromide, etc. As discussed further below, the damaged etch stop layer region 108D will be etched faster in subsequent processes.

[0039] exist Figure 8 , the source / drain contact opening 112 extends through the etch stop layer 108. The extended source / drain contact opening 112 exposes the lower source / drain contact 104. The source / drain contact opening 112 can be extended using acceptable etching techniques. In some embodiments, a wet etching process 116 is performed to extend the source / drain contact opening 112 through the etch stop layer 108.

[0040] Fig.9A The wet etching process 116 is shown in FIG. Figure 8 Additional detail of region 70C of . A wet etching process 116 is performed until the damaged etch stop layer region 108D is removed and the lower source / drain contact 104 is exposed. The wet etching process 116 is selective to the material (e.g., aluminum chloride or aluminum bromide) of the damaged etch stop layer region 108D, such that the damaged etch stop layer region 108D is etched at a higher rate than the lower source / drain contact 104 and the undamaged etch stop layer region 108U. The wet etching process 116 can be anisotropic, but some non-uniformity may still occur in the profile of the sidewalls of the undamaged etch stop layer region 108U. For example, Fig. 9B An embodiment is shown in which the undamaged etch stop layer region 108U has a curved profile in its etched sidewalls.

[0041] The wet etching process 116 is performed by exposing the etch stop layer 108 to an etching solution, which includes an etchant, a dielectric protectant, and a cobalt protectant. The etching solution may include: deionized water with a concentration of about 20% to about 98% (e.g., about 95%), an etchant with a concentration of about 0.1% to about 3% (e.g., about 2.5%), a dielectric protectant with a concentration of about 0.01% to about 3% (e.g., about 2.5%), and a cobalt protectant with a concentration of about 0.01% to about 3% (e.g., less than about 1%). In some embodiments, the etching solution may also include an ammonia peroxide mixture (APM) or carbonated deionized water. The etchant reacts with the material of the damaged etch stop layer region 108D to remove the damaged etch stop layer region 108D while removing a limited amount of the undamaged etch stop layer region 108U, as discussed in more detail below. In some embodiments, the etchant is an acid with high alkalinity, such as hydrofluoric acid, ammonia, etc.

[0042] The dielectric protectant reacts with the material of the etch stop layer 108 (eg, aluminum oxide) to slow down the etching rate of the undamaged etch stop layer region 108U. In some embodiments, the dielectric protectant is an oxidizing agent, such as hydrogen peroxide (H 2 O 2 ), ozone, etc. During the wet etching process 116, the damaged etch stop layer region 108D is quickly removed. Since the sidewalls of the undamaged etch stop layer region 108U are exposed, the dielectric protectant reacts with the material of the undamaged etch stop layer region 108U (e.g., aluminum oxide) to form a protective layer 117. The protective layer 117 includes a product of the dielectric protectant and the material of the undamaged etch stop layer region 108U. For example, when the undamaged etch stop layer region 108U is aluminum oxide, the protective layer 117 may include a high density of aluminum oxide or aluminum hydroxide. The density of the protective layer 117 may be greater than the density of the undamaged etch stop layer region 108U. In some embodiments, a thermal process is performed to promote the formation of the protective layer 117. For example, an annealing or baking process may be performed before etching to thermally oxidize the sidewalls of the undamaged etch stop layer region 108U. The protective layer 117 protects the sidewalls of the undamaged etch stop layer region 108U. The amount of undamaged etch stop layer region 108U removed during the wet etching process 116 may therefore be greatly reduced or controlled.

[0043] The cobalt protectant reacts with the material (e.g., cobalt) of the lower source / drain contact 104 to slow down the etching rate of the lower source / drain contact 104. In some embodiments, the cobalt protectant is a cobalt inhibitor, for example, a benzotriazole (BTA) polymer with a methyl or ethyl side chain. During the wet etching process 116, the cobalt protectant passivates the exposed surface of the lower source / drain contact 104 to form a protective layer 119 covering the lower source / drain contact 104. The protective layer 119 can be, for example, anthracene and can be conductive. Some protective layers 119 can be retained after the wet etching process 116. The lower source / drain contact 104 can therefore remain protected during the wet etching process 116. In addition, since the dielectric protectant is an oxidant, it can form an oxide (e.g., cobalt oxide) of the material of the lower source / drain contact 104. The cobalt protectant can also remove oxide from the lower source / drain contact 104, thereby reducing contact resistance.

[0044] After formation, the source / drain contact opening 112 has an upper width W through the second ILD 110. U1 , and the lower width W through the etch stop layer 108 L1 . Upper width W U1 The wet etching process 116 may be in the range of about 3 nm to about 100 nm. As described above, the wet etching process 116 is selective to the material (e.g., aluminum chloride or aluminum bromide) of the damaged etch stop layer region 108D. Therefore, although some lateral etching of the undamaged etch stop layer region 108U occurs during the wet etching process 116, the amount of lateral etching is small. For example, the wet etching process 116 may laterally etch the undamaged etch stop layer region 108U by an amount in the range of about 1 nm to about 9 nm (e.g., less than about 1.5 nm). Therefore, the lower width W L1 It can be in the range of about 4 nm to about 109 nm. Because the amount of lateral etching is small, the upper width W U1 With lower width W L1 The ratio of φ is close to 1, for example, in the range of about 3:4 to about 100: 109. Depending on the amount of the lateral etching, portions of the gate mask 102 and / or the contact liner 106 may also be exposed.

[0045] In some embodiments, source / drain contact openings 112A may be formed with different widths. For example, a first subset of source / drain contact openings 112A may have a smaller upper width W U1 , for example, an upper width W of about 3 nm U1 , and the second subset of source / drain contact openings 112B may have a larger upper width W U1 , for example, an upper width W of about 10 nm U1. The desired width of the source / drain contact openings 112 can depend on the limits of the photolithography process used to initially form the source / drain contact openings 112. When wider source / drain contact openings 112 are formed, they can also expose one or more of the gate mask 102 and / or the contact liner 106. Because the wet etching process 116 is selective to the material of the undamaged etch stop layer region 108U (e.g., aluminum oxide), etching of the material of the gate mask 102 (e.g., silicon nitride) can be avoided or reduced. For example, the ratio of the etch rate of the undamaged etch stop layer region 108U to the etch rate of the gate mask 102 relative to the wet etching process 116 can be greater than about 100:1.

[0046] exist Fig.10 In the embodiment of the present invention, an upper source / drain contact 118 is formed by the second ILD 110 and the etch stop layer 108 to be physically and electrically coupled to some of the lower source / drain contacts 104. In some embodiments, the upper source / drain contact 118 includes a liner, such as a diffusion barrier layer, an adhesion layer, etc., and a conductive material formed in the source / drain contact opening 112. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. In some embodiments, the conductive material is tungsten. In some embodiments, the lower source / drain contact 104 is formed of a first conductive material (e.g., cobalt), and the upper source / drain contact 118 is formed of a different second conductive material (e.g., tungsten). A planarization process such as CMP may be performed to remove excess material from the top surface of the second ILD 110. The remaining liner and conductive material form the upper source / drain contact 118.

[0047] Fig.11 shows the structure after forming the upper source / drain contacts 118. Fig.10 The portion of the upper source / drain contact 118 extending through the second ILD 110 has an upper width W U1 , and the portion of the upper source / drain contact 118 extending through the etch stop layer 108 has a lower width W L1 The upper source / drain contacts 118 include an upper source / drain contact 118A in the source / drain contact opening 112A and an upper source / drain contact 118B in the source / drain contact opening 112B.

[0048] It should be understood that not all lower source / drain contacts 104 have corresponding upper source / drain contacts 118. In some types of devices, a subset of the lower source / drain contacts 104 remain covered and will subsequently be coupled to a shared contact, for example, in the gate stack 76 (see Fig.10) and the source / drain regions 80. Shared contacts may be used to form some types of memory devices, such as static random access memory (SRAM) devices.

[0049] exist Fig.12 , a gate contact opening 120 is formed through the second ILD 110. The gate contact opening 120 exposes the etch stop layer 108. The gate contact opening 120 may be formed using acceptable photolithography and etching techniques. A photoresist (not shown) is formed over the second ILD 110 and patterned with a pattern of the gate contact opening 120. In some embodiments, a dry etching process 122 is performed to transfer the pattern of the photoresist to the second ILD 110, thereby forming the gate contact opening 120. The material of the etch stop layer 108 (e.g., aluminum oxide) has a high etching selectivity relative to the material of the second ILD 110 (e.g., silicon oxide), so that the second ILD 110 is etched at a higher rate than the etch stop layer 108 for the dry etching process 122. Thus, during the dry etching process 122, the thickness T of the etch stop layer 108 is reduced. 1 The loading effect in the subsequent process can be reduced by reducing the over-etching of the etch stop layer 108 .

[0050] The dry etching process 122 may be similar to the dry etching process 114 (see Figure 6 ). After the dry etching process 122, a post-etch cleaning process is performed. During the post-etch cleaning process, the intermediate structure is exposed to a tungsten protectant. The tungsten protectant is adsorbed to the exposed surface of the upper source / drain contact 118 (e.g., tungsten) to form a protective layer 123, which protects the upper source / drain contact 118 during subsequent processes. In some embodiments, the tungsten protectant is a tungsten inhibitor, for example, a benzotriazole (BTA) polymer with chlorine side chains. The protective layer 123 can be, for example, anthracene, and can be conductive. Some of the protective layer 123 can remain after the dry etching process 122.

[0051] Fig.13 The dry etching process 122 is shown in FIG. Fig.12 As described above, although substantially no etching of the thickness T of the etch stop layer 108 occurs during the dry etching process 122, 1 , but some regions 108D of the etch stop layer 108 are modified or damaged by the dry etching process 122. The damaged etch stop layer regions 108D are a different material than the undamaged etch stop layer regions 108U and will be etched faster in subsequent processes.

[0052] exist Fig.14In the embodiment, the gate contact opening 120 extends through the etch stop layer 108. The extended gate contact opening 120 exposes the gate mask 102. The gate contact opening 120 can be extended using acceptable etching techniques. In some embodiments, a wet etching process 124 is performed to extend the gate contact opening 120 through the etch stop layer 108.

[0053] Fig.15 The wet etching process 124 is shown. Fig.14 108D. A wet etching process 124 is performed until the damaged etch stop layer region 108D is removed and the gate mask 102 is exposed. The wet etching process 124 is selective to the material (e.g., aluminum chloride or aluminum bromide) of the damaged etch stop layer region 108D, so that the damaged etch stop layer region 108D is etched at a higher rate than the lower source / drain contacts 104 and the undamaged etch stop layer region 108U. The wet etching process 124 forms a protective layer 117 that protects the undamaged etch stop layer region 108U from being etched.

[0054] The wet etching process 124 is performed by exposing the etch stop layer 108 to an etching solution including an etchant, a dielectric protectant, and a cobalt protectant. The etching solution may include: water having a concentration of about 20% to about 98% (e.g., about 95%), an etchant having a concentration of about 0.1% to about 3% (e.g., about 2.5%), a dielectric protectant having a concentration of about 0.01% to about 3% (e.g., about 2.5%), and a cobalt protectant having a concentration of about 0.01% to about 3% (e.g., less than about 1%). The etchant, the dielectric protectant, and the cobalt protectant are similar to the corresponding reagents used in the wet etching process 116. The material of the etch stop layer 108 (e.g., aluminum oxide) has a high etching selectivity relative to the material of the gate mask 102 (e.g., silicon nitride), so that the etch stop layer 108 is etched at a higher rate than the gate mask 102 for the wet etching process 124. In this way, the height of the gate mask 102 is not substantially reduced.

[0055] During the wet etching process 124, the upper source / drain contact 118 is protected. In some embodiments, the upper source / drain contact 118 is protected by including a tungsten protector in the etching solution used for the wet etching process 124. The tungsten protector may be similar to the tungsten protector used during the post-etch cleaning process after the dry etching process 122. In some embodiments, the upper source / drain contact 118 is protected by adjusting the environment of the wet etching process 124 to reduce the etching rate of tungsten. For example, the wet etching process 124 may be performed at a low temperature (e.g., a temperature of about 20°C to about 40°C) and using an etching solution with a low pH (e.g., a pH of about 5 to about 7), thereby reducing the etching rate of tungsten and limiting or reducing the removal of tungsten. In some embodiments, both the tungsten protector and the adjusted environment are used during the wet etching process 124. By protecting the upper source / drain contact 118, the height of the upper source / drain contact 118 is not substantially reduced.

[0056] exist Fig.16 In the embodiment of the present invention, the gate contact opening 120 extends through the gate mask 102. The extended gate contact opening 120 exposes the gate stack 76. The gate contact opening 120 may be extended using an acceptable etching technique. In some embodiments, a dry etching process 126 is performed to extend the gate contact opening 120 through the gate mask 102. For example, in some embodiments, the dry etching process 126 includes using a fluorocarbon (e.g., C x F y ) gas to generate a plasma sheath over the second ILD 110. The dry etching process 126 may be performed in an environment including argon or nitrogen, and may be performed for a duration ranging from about 10 seconds to about 150 seconds. The dry etching process 126 is performed until a portion of the gate mask 102 is removed and the gate stack 76 is exposed. Some portions of the gate stack 76 (e.g., portions of the cap layer 88B) may also be removed. The material of the gate mask 102 (e.g., silicon nitride) has a high etching selectivity compared to the material of the second ILD 110 (e.g., silicon oxide) and the material of the etch stop layer 108 (e.g., aluminum oxide), so that the gate mask 102 is etched at a higher rate than the etch stop layer 108 and the second ILD 110 for the dry etching process 126. Therefore, the height of the second ILD 110 is not substantially reduced, and there is substantially no lateral etching of the etch stop layer 108. Furthermore, since the upper source / drain contacts 118 and the lower source / drain contacts 104 are exposed to the cobalt and tungsten protectants during the wet etching process 124 , the height of the upper source / drain contacts 118 or the lower source / drain contacts 104 is not substantially reduced during the dry etching process 126 .

[0057] Fig.17The dry etching process 126 is shown in FIG. Fig.16 After formation, the gate contact opening 120 has an upper width W through the second ILD 110. U2 , passing through the middle width W of the etch stop layer 108 I2 and the lower width W through the gate mask 102 L2 . Upper width W U2 The intermediate width W may be in the range of about 3 nm to about 100 nm. As described above, the wet etching process 124 is selective to the material (e.g., aluminum chloride or aluminum bromide) of the damaged etch stop layer region 108D. Therefore, although some lateral etching of the undamaged etch stop layer region 108U occurs during the wet etching process 124, the amount of lateral etching is small. For example, the amount by which the wet etching process 124 laterally etches the undamaged etch stop layer region 108U may be in the range of about 1 nm to about 9 nm (e.g., less than about 1.5 nm). Therefore, the intermediate width W I2 It can be in the range of about 4 nm to about 109 nm. In addition, the lower width W L2 Can be smaller than the middle width W I2 For example, the lower width W L2 It may be in the range of about 2 nm to about 90 nm.

[0058] In some embodiments, gate contact openings 120A may be formed with different widths. For example, a first subset of gate contact openings 120A may have a small upper width W U2 , for example, an upper width W of about 3 nm U2 , and the second subset of gate contact openings 120B may have a large upper width W U2 , for example, an upper width W of about 10 nm U2 A first subset of gate contact openings 120A may be used for gate contacts only for gate stack 76, and a second subset of gate contact openings 120B may be used for shared contacts, e.g., contacts shared between gate stack 76 and source / drain regions 80. Thus, the second subset of gate contact openings 120B may also expose one or more of lower source / drain contacts 104 and / or contact liner 106.

[0059] exist Fig.18In the embodiment of the present invention, a gate contact 128 is formed by the second ILD 110, the etch stop layer 108 and the gate mask 102 to physically and electrically couple to the gate stack 76 and optionally to some lower source / drain contacts 104. A liner (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the gate contact opening 120. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. In some embodiments, the conductive material is tungsten. In some embodiments, the gate contact 128 and the upper source / drain contact 118 are formed of the same conductive material (e.g., tungsten). A planarization process such as CMP may be performed to remove excess material from the top surface of the second ILD 110. The remaining liner and conductive material form the gate contact 128. The gate contact 128 includes a gate contact 128A located in the gate contact opening 120A, and a gate contact 128B located in the gate contact opening 120B. The gate contacts 128B may each be a shared contact coupling the source / drain regions 80 to the gate stack 76 .

[0060] Although the shared contact is shown as being formed during the process of forming the gate contact 128, it should be understood that the shared contact can also be formed during the process of forming the upper source / drain contact 118. For example, a dry etching process similar to the dry etching process 126 can be performed to form the source / drain contact opening 112B (see Figure 8 ) extends through the gate mask 102. Therefore, some of the upper source / drain contacts 118 may also be shared contacts. In other words, the shared contacts may be formed simultaneously with the source / drain contacts, the gate contacts, or both.

[0061] Fig.19 shows the gate contact 128 after it is formed. Fig.18 The portion of the gate contact 128 extending through the second ILD 110 has an upper width W U2 , the portion of the gate contact 128 extending through the etch stop layer 108 has an intermediate width W I2 , and the portion of the gate contact 128 extending through the gate mask 102 has a lower width W L2 .

[0062] Figures 20 to 28 is a cross-sectional view of an intermediate stage in fabricating a contact for a FinFET according to some other embodiments. Figures 20 to 28 Along Figure 1Reference cross section AA shown in FIG. 1 shows that, in addition to the plurality of FinFETs, in this embodiment, a buffer layer 130 is formed over the etch stop layer 108 , which helps protect the etch stop layer 108 from being over-etched during the dry etching process 114 for the second ILD 110 .

[0063] exist Fig. 20 In the figure, a similar Figure 5 The buffer layer 130 is formed between the etch stop layer 108 and the second ILD 110. The buffer layer 130 is formed of a material having a high etch selectivity relative to the etch stop layer 108, so that the buffer layer 130 is etched at a higher rate than the underlying etch stop layer 108 for the same etching process. The buffer layer 108 can assist in controlling the etching of the etch stop layer 108. For example, the buffer layer 130 is formed of an insulating material, such as a layer of silicon nitride, silicon oxynitride, silicon oxycarbide, tungsten carbide, etc. The buffer layer 130 can be formed by a deposition process such as ALD, CVD, PECVD, etc. The buffer layer 130 can be the same material as the gate mask 102. In the embodiment shown, the buffer layer 130 is a single layer of silicon nitride. The etch stop layer 108 can be formed to a small thickness T 2 For example, the etch stop layer 108 may have a thickness of about to about Thickness T in the range 2 The buffer layer 130 may also be formed to have a small thickness T 3 For example, the buffer layer 130 may have a thickness of about to about The thickness T in the range 3 .

[0064] exist Fig.21 In the embodiment, a dry etching process is performed to form source / drain contact openings 112 through the second ILD 110 and the buffer layer 130. The dry etching process may be similar to that described above with reference to Figure 6 The dry etching process 114 discussed. The dry etching process 114 is selective to the materials of the second ILD 110 and the buffer layer 130, and removes material of both layers, but at different rates.

[0065] exist Fig. 22 In the embodiment of the present invention, a wet etching process is performed to extend the source / drain contact opening 112 through the etch stop layer 108. The wet etching process may be similar to that described above with reference to Figure 8 The wet etching process 116 discussed. The wet etching process 116 is selective to the material of the damaged etch stop layer region 108D (see Figure 7), so that the damaged etch stop layer region 108D is etched at a higher rate than the lower source / drain contact 104, the undamaged etch stop layer region 108U, the gate mask 102 and the buffer layer 130.

[0066] exist Fig.23 In the embodiment, upper source / drain contacts 118 are formed by the second ILD 110, the etch stop layer 108 and the buffer layer 130 to be physically and electrically coupled to some lower source / drain contacts 104. Fig.10 The upper source / drain contact 118 is formed in the source / drain contact opening 112 in a similar manner as discussed above. Although not shown separately, a protective layer 119 may be formed between the upper source / drain contact 118 and the lower source / drain contact 104 (see FIG. Fig.9A ).

[0067] exist Fig.24 In the embodiment, a dry etching process is performed to form a gate contact opening 120 through the second ILD 110 and the buffer layer 130. The dry etching process may be similar to that described above with reference to Fig.12 The dry etching process 122 discussed above is selective to the materials of the second ILD 110 and the buffer layer 130 and removes the materials of the two layers, but at different rates. Although not shown separately, a protective layer 123 may be formed on the upper source / drain contacts 118 during the dry etching process (see FIG. Fig.12 ).

[0068] exist Fig.25 In the embodiment of the present invention, a wet etching process is performed to extend the gate contact opening 120 through the etch stop layer 108. The wet etching process may be similar to that described above with reference to Fig.14 The wet etching process 124 discussed above is selective to the material of the damaged etch stop layer region 108D (see Figure 7 ), so that the damaged etch stop layer region 108D is etched at a higher rate than the lower source / drain contact 104, the undamaged etch stop layer region 108U and the buffer layer 130.

[0069] exist Fig.26 In the embodiment of the present invention, a dry etching process is performed to extend the gate contact opening 120 through the gate mask 102. The dry etching process may be similar to that described above with reference to Fig.16 The dry etching process 126 is discussed. The extended gate contact opening 120 exposes the gate stack 76. The dry etching process may also laterally etch the etch stop layer 108, but the etching rate of the etch stop layer 108 is negligible compared to the etching rate of the gate mask 102.

[0070] exist Fig. 27 In the embodiment, a gate contact 128 is formed by the second ILD 110, the etch stop layer 108, the gate mask 102 and the buffer layer 130 to be physically and electrically coupled to the gate stack 76 and optionally to some of the lower source / drain contacts 104. Fig.18 A gate contact 128 is formed in the gate contact opening 120 in a manner similar to that discussed above.

[0071] Fig.28 shows the gate contact 128 after it is formed. Fig. 27 The portion of the gate contact 128 extending through the second ILD 110 has an upper width W U2 , the portion of the gate contact 128 extending through the etch stop layer 108 has an intermediate width W I2 , and the portion of the gate contact 128 extending through the gate mask 102 has a lower width W L2 In addition, the portion of the gate contact 128 extending through the buffer layer 130 has an intermediate width W I3 , the middle width W I3 Smaller than the middle width W I2 For example, the middle width W I3 It can be in the range of 3nm to 100nm.

[0072] Figures 29 to 38 is a cross-sectional view of an intermediate stage in fabricating a contact for a FinFET according to some other embodiments. Figures 29 to 38 Along Figure 1 The reference cross section AA shown shows that, in addition to the plurality of FinFETs, in this embodiment, a buffer layer 132 is formed below the etch stop layer 108 , which helps to protect the lower source / drain contacts 104 during the wet etching process 116 .

[0073] exist Fig.29 In the figure, a similar Figure 5 A buffer layer 132 is formed over the first ILD 84, and an etch stop layer 108 is formed over the buffer layer 132. The buffer layer 132 is formed of a material having a high etch selectivity relative to the etch stop layer 108 for the same etching process. For example, the buffer layer 132 is formed of an insulating material, such as a layer of silicon nitride, silicon oxynitride, silicon oxycarbide, tungsten carbide, etc. The buffer layer 132 may be formed by a deposition process such as ALD, CVD, PECVD, etc. The buffer layer 132 may be the same material as the gate mask 102. In the illustrated embodiment, the buffer layer 132 is a single layer of silicon nitride. The etch stop layer 108 may be formed to a small thickness T 4 For example, the etch stop layer 108 may have a thickness of about to about The thickness T in the range 4 The buffer layer 132 may also be formed to have a small thickness T 5 For example, the buffer layer 132 may have a thickness of about to about The thickness T in the range 5 .

[0074] exist Fig.30 In the embodiment of the present invention, a dry etching process is performed to form source / drain contact openings 112 through the second ILD 110. The dry etching process may be similar to that described above with reference to Figure 6 The dry etching process 114 is discussed.

[0075] exist Fig.31 In the embodiment of the present invention, a wet etching process is performed to extend the source / drain contact opening 112 through the etch stop layer 108. The wet etching process may be similar to that described above with reference to Figure 8 The wet etching process 116 discussed above is selective to the material of the damaged etch stop layer region 108D (see Figure 7 ), so that the damaged etch stop layer region 108D is etched at a higher rate than the lower source / drain contact 104 and the undamaged etch stop layer region 108U.

[0076] exist Fig.32 In the embodiment, the source / drain contact opening 112 extends through the buffer layer 132. The extended source / drain contact opening 112 exposes the lower source / drain contact 104. The source / drain contact opening 112 can be extended using an acceptable etching technique. In some embodiments, a dry etching process 134 is performed to extend the source / drain contact opening 112 through the buffer layer 132. For example, in some embodiments, the dry etching process 134 includes using a fluorocarbon (e.g., C x F y) gas to generate a plasma sheath over the second ILD 110. The dry etching process 134 may be performed in an environment including argon or nitrogen, and may be performed for a duration in the range of about 10 seconds to about 150 seconds. The dry etching process 134 is performed until a portion of the buffer layer 132 is removed and the lower source / drain contact 104 is exposed. Some portions of the gate mask 102 may also be removed. The dry etching process 134 is similar to the dry etching process 126, but may be performed for different durations. In embodiments where the materials of the gate mask 102 and the buffer layer 132 are the same material or materials with similar etching rates, the dry etching process 134 may remove some of the gate mask 102. Therefore, the dry etching process 134 may be a timed etching such that the buffer layer 132 is removed, and the dry etching process 134 is stopped when little or no material of the gate mask 102 is removed. For example, the dry etching process 134 may be performed for a duration of about 10 seconds to about 150 seconds. Therefore, the height of the gate mask 102 is not substantially reduced.

[0077] exist Fig.33 In the embodiment, upper source / drain contacts 118 are formed by the second ILD 110, the etch stop layer 108 and the buffer layer 132 to be physically and electrically coupled to some lower source / drain contacts 104. Fig.10 A source / drain contact 118 is formed in the source / drain contact opening 112 in a similar manner as discussed above. Although not shown separately, a protective layer 119 may be formed between the upper source / drain contact 118 and the lower source / drain contact 104 (see FIG. Fig.9A ).

[0078] exist Fig.34 In the embodiment of the present invention, a dry etching process is performed to form a gate contact opening 120 through the second ILD 110. The dry etching process may be similar to that described above with reference to Fig.12 Although not shown separately, a protective layer 123 may be formed on the upper source / drain contacts 118 during the dry etching process (see Fig.12 ).

[0079] exist Fig.35 In the embodiment of the present invention, a wet etching process is performed to extend the gate contact opening 120 through the etch stop layer 108. The wet etching process may be similar to that described above with reference to Fig.14 The wet etching process 124 discussed above is selective to the material of the damaged etch stop layer region 108D (see Figure 7), so that the damaged etch stop layer region 108D is etched at a higher rate than the lower source / drain contact 104, the undamaged etch stop layer region 108U and the buffer layer 132.

[0080] exist Fig.36 In the embodiment of the present invention, a dry etching process is performed to extend the gate contact opening 120 through the buffer layer 132 and the gate mask 102. The dry etching process may be similar to that described above with reference to Fig.16 The dry etching process 126 is discussed. The extended gate contact opening 120 exposes the gate stack 76. Since the buffer layer 132 and the gate mask 102 may be formed of similar materials, the dry etching process 126 may remove materials of both layers at a similar rate.

[0081] exist Fig.37 In the embodiment, a gate contact 128 is formed by the second ILD 110, the etch stop layer 108, the gate mask 102 and the buffer layer 132 to be physically and electrically coupled to the gate stack 76 and optionally to some of the lower source / drain contacts 104. Fig.18 A gate contact 128 is formed in the gate contact opening 120 in a manner similar to that discussed above.

[0082] Fig.38 shows the gate contact 128 after it is formed. Fig.37 The portion of the gate contact 128 extending through the second ILD 110 has an upper width W U2 , the portion of the gate contact 128 extending through the etch stop layer 108 has an intermediate width W I2 , the portion of the gate contact 128 extending through the buffer layer 132 has an intermediate width W I3 , and the portion of the gate contact 128 extending through the gate mask 102 has a lower width W L2 , which can be measured at the top of the gate mask 102 .

[0083] Figures 39 to 47 is a cross-sectional view of an intermediate stage in fabricating a contact for a FinFET according to some other embodiments. Figures 39 to 47 Along Figure 1 The reference cross section AA shown shows that in addition to the plurality of FinFETs, in this embodiment, another etch stop layer 136 is formed, and a buffer layer 138 is formed between the etch stop layers 108 and 136 .

[0084] exist Fig.39 In the figure, a similar Figure 5An etch stop layer 136 is formed over the first ILD 84, a buffer layer 138 is formed over the etch stop layer 136, and an etch stop layer 108 is formed over the buffer layer 138. Using multiple etch stop layers can help to better control pattern loading in a subsequent process of forming source / drain contact openings. The etch stop layer 136 is formed of a material having a high etch selectivity relative to the second ILD 110 for the same etching process. For example, the etch stop layer 136 is formed of an insulating material, such as a single layer of aluminum oxide. The etch stop layer 136 can be formed by a deposition process such as ALD, CVD, PECVD, etc. Since the etch stop layer 136 has a high etch selectivity relative to the second ILD 110 for the same etching process, it can be formed to a small thickness T 6 For example, the etch stop layer 136 may have a thickness of about to about Thickness T in the range 6 .

[0085] The buffer layer 138 is formed of a material having a high etching selectivity relative to the etching stop layers 108 and 136 for the same etching process. For example, the buffer layer 138 is formed of an insulating material, such as a layer of silicon nitride, silicon oxynitride, silicon oxycarbide, tungsten carbide, etc. The buffer layer 138 can be formed by a deposition process such as ALD, CVD, PECVD, etc. The buffer layer 138 can be the same material as the gate mask 102. In the embodiment shown, the buffer layer 138 is a single layer of silicon nitride. The buffer layer 138 can also be formed to a small thickness T 7 For example, the buffer layer 138 may have a thickness of about to about The thickness T in the range 7 The etch stop layer 108 may be formed to have a small thickness T 8 For example, the etch stop layer 108 may have a thickness of about to about The thickness T in the range 8 .

[0086] exist Fig.40 In the embodiment of the present invention, a dry etching process is performed to form source / drain contact openings 112 through the second ILD 110. The dry etching process may be similar to that described above with reference to Figure 6 The dry etching process 114 is discussed.

[0087] exist Fig.41, the source / drain contact opening 112 extends through the etch stop layers 108 and 136, and through the buffer layer 138. The extended source / drain contact opening 112 exposes the lower source / drain contact 104. The source / drain contact opening 112 can be extended using an acceptable etching technique. In some embodiments, a combined etching process 140 is performed to extend the source / drain contact opening 112. The combined etching process 140 can include two wet etches and one dry etch. Each wet etch is similar to the wet etching process 116, and etches the etch stop layers 108 and 136 with a small amount of lateral etching. The dry etch etches the buffer layer 138, and can be similar to the dry etching process 134.

[0088] exist Fig.42 In the embodiment, upper source / drain contacts 118 are formed by second ILD 110, etch stop layers 108 and 136, and buffer layer 138 to be physically and electrically coupled to some lower source / drain contacts 104. Fig.10 The upper source / drain contact 118 is formed in the source / drain contact opening 112 in a similar manner as discussed above. Although not shown separately, a protective layer 119 may be formed between the upper source / drain contact 118 and the lower source / drain contact 104 (see Fig.9A ).

[0089] exist Fig.43 In the embodiment of the present invention, a dry etching process is performed to form a gate contact opening 120 through the second ILD 110. The dry etching process may be similar to that described above with reference to Fig.12 Although not shown separately, a protective layer 123 may be formed on the upper source / drain contacts 118 during the dry etching process (see Fig.12 ).

[0090] exist Fig.44 In the embodiment of the present invention, the gate contact opening 120 extends through the etch stop layers 108 and 136 and through the buffer layer 138. Acceptable etching techniques may be used to extend the gate contact opening 120. In some embodiments, a combined etching process 142 is performed to extend the gate contact opening 120. The combined etching process 142 is similar to the above description of Fig.41 A combinatorial etching process 140 is discussed.

[0091] exist Fig.45 In the embodiment of the present invention, a dry etching process is performed to extend the gate contact opening 120 through the buffer layer 138 and the gate mask 102. The dry etching process may be similar to that described above with reference to Fig.16 The dry etching process 126 is discussed. The extended gate contact opening 120 exposes the gate stack 76.

[0092] exist Fig.46 In the embodiment, a gate contact 128 is formed by the second ILD 110, the etch stop layers 108 and 136, the gate mask 102 and the buffer layer 138 to physically and electrically couple to the gate stack 76 and optionally to some of the lower contact source / drain contacts 104. Fig.18 A gate contact 128 is formed in the gate contact opening 120 in a manner similar to that discussed above.

[0093] Fig.47 shows the gate contact 128 after it is formed. Fig.46 The portion of the gate contact 128 extending through the second ILD 110 has an upper width W U2 , the portion of gate contact 128 extending through etch stop layers 108 and 136 has an intermediate width W I2 , the portion of the gate contact 128 extending through the buffer layer 138 has an intermediate width W I3 , and the portion of the gate contact 128 extending through the gate mask 102 has a lower width W L2 .

[0094] Figures 48 to 57 is a cross-sectional view of an intermediate stage in fabricating a contact for a FinFET according to some other embodiments. Figures 48 to 57 Along Figure 1 The reference cross section AA shown shows that, in addition to the plurality of FinFETs, in this embodiment, two buffer layers 144 and 146 are formed sandwiching the etch stop layer 108 .

[0095] exist Fig.48 In the figure, a similar Figure 5 A buffer layer 144 is formed over the first ILD 84, an etch stop layer 108 is formed over the buffer layer 144, and a buffer layer 146 is formed over the etch stop layer 108. The buffer layers 144 and 146 are formed of a material having a high etch selectivity relative to the etch stop layer 108 for the same etching process. For example, the buffer layers 144 and 146 are formed of an insulating material, such as a layer of silicon nitride, silicon oxynitride, silicon oxycarbide, tungsten carbide, or the like. The buffer layers 144 and 146 may be formed by a deposition process such as ALD, CVD, PECVD, or the like. The buffer layers 144 and 146 may be the same material as the gate mask 102. In the illustrated embodiment, the buffer layers 144 and 146 are each a single layer of silicon nitride. The buffer layer 144 is formed to a small thickness T 9 For example, the buffer layer 144 may have a thickness of about to about The thickness T in the range 9The etch stop layer 108 may be formed to have a small thickness T 10 For example, the etch stop layer 108 may have a thickness of about to about The thickness T in the range 10 In addition, the buffer layer 146 is formed to have a small thickness T 11 For example, the buffer layer 146 may have a thickness of about to about Thickness T in the range 11 .

[0096] exist Fig.49 In the embodiment, a dry etching process is performed to form source / drain contact openings 112 through the second ILD 110 and the buffer layer 146. The dry etching process may be similar to that described above with reference to Figure 6 The dry etching process 114 discussed. The dry etching process 114 is selective to the materials of the second ILD 110 and the buffer layer 146 and removes material from both layers, but at different rates.

[0097] exist Fig.50 In the embodiment of the present invention, a wet etching process is performed to extend the source / drain contact opening 112 through the etch stop layer 108. The wet etching process may be similar to that described above with reference to Figure 8 The wet etching process 116 discussed. The wet etching process 116 is selective to the material of the damaged etch stop layer region 108D (see Figure 7 ), so that the damaged etch stop layer region 108D is etched at a higher rate than the undamaged etch stop layer region 108U and the buffer layers 144 and 146.

[0098] exist Fig.51 In the embodiment, the source / drain contact opening 112 extends through the buffer layer 144. The extended source / drain contact opening 112 exposes the lower source / drain contact 104. The source / drain contact opening 112 can be extended using an acceptable etching technique. In some embodiments, a dry etching process 148 is performed to extend the source / drain contact opening 112 through the buffer layer 144. For example, in some embodiments, the dry etching process 148 includes using a fluorocarbon (e.g., C x F y) gas generates a plasma sheath over the second ILD 110. The dry etching process 148 may be performed in an environment including argon or nitrogen, and may be performed for a duration in the range of about 10 seconds to about 150 seconds. The dry etching process 148 is performed until a portion of the buffer layer 144 is removed and the lower source / drain contact 104 is exposed. Some portions of the gate mask 102 may also be removed. The dry etching process 148 is similar to the dry etching process 126, but may be performed for different durations. Since the materials of the gate mask 102 and the buffer layer 144 are similar, the dry etching process 148 may remove some of the gate mask 102. Therefore, the dry etching process 148 may be a timed etching such that the buffer layer 144 is removed, and then the dry etching process 148 is stopped when little or no material of the gate mask 102 is removed. For example, the dry etching process 148 may be performed for a duration of about 10 seconds to about 150 seconds. Therefore, the height of the gate mask 102 is not substantially reduced.

[0099] exist Fig.52 In the embodiment, upper source / drain contacts 118 are formed by second ILD 110, etch stop layer 108, and buffer layers 144 and 146 to be physically and electrically coupled to some lower source / drain contacts 104. Fig.10 The upper source / drain contact 118 is formed in the source / drain contact opening 112 in a similar manner as discussed above. Although not shown separately, a protective layer 119 may be formed between the upper source / drain contact 118 and the lower source / drain contact 104 (see Fig.9A ).

[0100] exist Fig.53 In the embodiment of the present invention, a dry etching process is performed to form a gate contact opening 120 through the second ILD 110 and the buffer layer 146. The dry etching process may be similar to that described above with reference to Fig.12 The dry etching process 122 discussed above is selective to the materials of the second ILD 110 and the buffer layer 146 and removes the materials of the two layers, but at different rates. Although not shown separately, a protective layer 123 may be formed on the upper source / drain contacts 118 during the dry etching process (see FIG. Fig.12 ).

[0101] exist Fig.54 In the embodiment of the present invention, a wet etching process is performed to extend the gate contact opening 120 through the etch stop layer 108. The wet etching process may be similar to that described above with reference to Fig.14 The wet etching process 124 discussed above is selective to the material of the damaged etch stop layer region 108D (see Figure 7), so that the damaged etch stop layer region 108D is etched at a higher rate than the undamaged etch stop layer region 108U and the buffer layers 144 and 146.

[0102] exist Fig.55 In the embodiment of the present invention, a dry etching process is performed to extend the gate contact opening 120 through the buffer layer 144 and the gate mask 102. The dry etching process may be similar to that described above with reference to Fig.16 The dry etching process 126 discussed. The extended gate contact opening 120 exposes the gate stack 76. Since the buffer layer 144 and the gate mask 102 may be formed of similar materials, the dry etching process 126 may remove the materials of both layers at a similar rate.

[0103] exist Fig.56 In the embodiment, a gate contact 128 is formed by the second ILD 110, the etch stop layer 108, the gate mask 102, and the buffer layers 144 and 146 to physically and electrically couple to the gate stack 76 and optionally to some of the lower contact source / drain contacts 104. Fig.18 A gate contact 128 is formed in the gate contact opening 120 in a manner similar to that discussed above.

[0104] Fig.57 shows the gate contact 128 after it is formed. Fig.56 The portion of the gate contact 128 extending through the second ILD 110 has an upper width W U2 , the portion of the gate contact 128 extending through the etch stop layer 108 has an intermediate width W I2 , the portion of gate contact 128 extending through buffer layers 144 and 146 has an intermediate width W I3 , and the portion of the gate contact 128 extending through the gate mask 102 has a lower width W L2 .

[0105] Embodiments can achieve advantages. By forming the etch stop layer 108 using a material having a high etch selectivity with respect to the gate mask 102 and the second ILD 110 for the same etching process, the amount of over-etching of the etch stop layer 108 can be reduced. The loading effect in subsequent processes can be reduced by reducing the over-etching of the etch stop layer 108. In addition, by opening the etch stop layer 108 with an etching solution including a dielectric protectant, the amount of lateral etching of the etch stop layer 108 can be reduced when forming the source / drain contact opening 112 and the gate contact opening 120. Reducing the lateral etching of the etch stop layer 108 can allow the amount of current leakage of the upper source / drain contact 118 and the gate contact 128 to be reduced.

[0106] In an embodiment, a method includes: depositing an etch stop layer over a first interlayer dielectric (ILD), the etch stop layer comprising a first dielectric material; depositing a second ILD over the etch stop layer; etching a first opening through the second ILD using a first dry etching process, the first opening exposing a first region of the etch stop layer, the first region being modified to the second dielectric material by the first dry etching process, a second region of the etch stop layer remaining covered by the second ILD, the second region being the first dielectric material after the first dry etching process; and extending the first opening through the etch stop layer using a first wet etching process, the etch stop layer being exposed to a first etching solution during the first wet etching process, the first etching solution comprising a dielectric protectant for the first dielectric material and an etchant for the second dielectric material.

[0107] In some embodiments of the method, the first dielectric material is aluminum oxide, and the second dielectric material is aluminum chloride or aluminum bromide. In some embodiments of the method, the etchant is hydrofluoric acid or ammonia, and the dielectric protectant is hydrogen peroxide or ozone. In some embodiments, the method further includes: forming a first conductive feature above the semiconductor substrate, the first conductive feature including the first conductive material; and depositing a first ILD above the first conductive feature, wherein the first etching solution also includes a first metal protectant for the first conductive material. In some embodiments, the method further includes: forming a first contact in the first opening, the first contact being physically and electrically coupled to the first conductive feature, the first contact including the second conductive material; etching a second opening through the second ILD using a second dry etching process; and extending the second opening through the etch stop layer using a second wet etching process, the etch stop layer being exposed to a second etching solution during the second wet etching process, the second etching solution including a dielectric protectant, an etchant, a first metal protectant, and a second metal protectant for the second conductive material. In some embodiments of the method, the first conductive material is cobalt, and the second conductive material is tungsten. In some embodiments of the method, the first metal protector is a benzotriazole polymer having a methyl side chain or an ethyl side chain, and the second metal protector is a benzotriazole polymer having a chlorine side chain. In some embodiments, the method further includes: forming a second conductive feature above the semiconductor substrate; depositing a mask above the second conductive feature; and depositing an etch stop layer above the mask. In some embodiments, the method further includes: extending the second opening through the mask using a third dry etching process; and forming a second contact in the second opening, the second contact being physically and electrically coupled to the second conductive feature. In some embodiments, the method further includes: depositing a buffer layer above the mask, the etch stop layer being deposited above the buffer layer; and extending the second opening through the buffer layer using a third dry etching process. In some embodiments, the method further includes: depositing a buffer layer above the etch stop layer, the second ILD being deposited above the buffer layer; and extending the first opening through the buffer layer using the first dry etching process.

[0108] In an embodiment, a device includes: a semiconductor substrate; a first interlayer dielectric (ILD) located above the semiconductor substrate; a first conductive feature extending through the first ILD; a first etch stop layer located above the first conductive feature and the first ILD, the first etch stop layer being a first dielectric material; a second ILD located above the first etch stop layer; a contact having a first portion extending through the second ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature; and a first protective layer surrounding the second portion of the contact, the first portion of the contact being free of the first protective layer, the first protective layer being a second dielectric material, the second dielectric material being different from the first dielectric material.

[0109] In some embodiments of the device, the first etch stop layer is aluminum oxide. In some embodiments of the device, the first protective layer is aluminum hydroxide. In some embodiments of the device, the first portion of the contact has a first width, the second portion of the contact has a second width, the second width is greater than the first width by a first distance, and the first distance is in a range of 1 nm to 9 nm. In some embodiments, the device further includes: a buffer layer disposed between the first conductive feature and the first etch stop layer, the contact having a third portion extending through the buffer layer, the third portion of the contact being free of the first protective layer. In some embodiments, the device further includes: a buffer layer disposed between the first etch stop layer and the second ILD, the contact having a third portion extending through the buffer layer, the third portion of the contact being free of the first protective layer. In some embodiments, the device further includes: a second etch stop layer disposed between the buffer layer and the second ILD, the second etch stop layer being a first dielectric material, the contact having a fourth portion extending through the second etch stop layer; and a second protective layer surrounding the fourth portion of the contact, the second protective layer being a second dielectric material. In some embodiments, the device further includes: a first buffer layer disposed between the first ILD and the first etch stop layer, the contact having a third portion extending through the first buffer layer, the third portion of the contact being free of the first protective layer; and a second buffer layer disposed between the first etch stop layer and the second ILD, the contact having a fourth portion extending through the second buffer layer, the fourth portion of the contact being free of the first protective layer.

[0110] In an embodiment, a device includes: a semiconductor substrate; a first conductive feature located above the semiconductor substrate; a first etch stop layer located above the first conductive feature, the first etch stop layer being a first dielectric material; an interlayer dielectric (ILD) located above the first etch stop layer; and a contact having a first portion extending through the ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature, wherein the first portion of the contact has a first width, the second portion of the contact has a second width, the second width is greater than the first width by a first distance, and the first distance is in a range of 1 nm to 9 nm.

[0111] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0112] Example 1 is a method for manufacturing a semiconductor device, comprising: depositing an etch stop layer over a first interlayer dielectric (ILD), the etch stop layer comprising a first dielectric material; depositing a second ILD over the etch stop layer; etching a first opening through the second ILD using a first dry etching process, the first opening exposing a first region of the etch stop layer, the first region being modified into a second dielectric material by the first dry etching process, a second region of the etch stop layer remaining covered by the second ILD, the second region being the first dielectric material after the first dry etching process; and extending the first opening through the etch stop layer using a first wet etching process, the etch stop layer being exposed to a first etching solution during the first wet etching process, the first etching solution comprising a dielectric protectant for the first dielectric material and an etchant for the second dielectric material.

[0113] Example 2 is the method of Example 1, wherein the first dielectric material is aluminum oxide and the second dielectric material is aluminum chloride or aluminum bromide.

[0114] Example 3 is the method of Example 2, wherein the etchant is hydrofluoric acid or ammonia, and wherein the dielectric protectant is hydrogen peroxide or ozone.

[0115] Example 4 is the method described in Example 1, further comprising: forming a first conductive feature above the semiconductor substrate, the first conductive feature comprising a first conductive material; and depositing the first ILD above the first conductive feature, wherein the first etching solution also comprises a first metal protectant for the first conductive material.

[0116] Example 5 is the method described in Example 4, further comprising: forming a first contact in the first opening, the first contact being physically and electrically coupled to the first conductive feature, the first contact comprising a second conductive material; etching a second opening through the second ILD using a second dry etching process; and extending the second opening through the etch stop layer using a second wet etching process, the etch stop layer being exposed to a second etching solution during the second wet etching process, the second etching solution comprising the dielectric protectant, the etchant, the first metal protectant, and a second metal protectant for the second conductive material.

[0117] Example 6 is the method of Example 5, wherein the first conductive material is cobalt and the second conductive material is tungsten.

[0118] Example 7 is the method of Example 6, wherein the first metal protecting agent is a benzotriazole polymer having a methyl side chain or an ethyl side chain, and the second metal protecting agent is a benzotriazole polymer having a chlorine side chain.

[0119] Example 8 is the method of Example 5, further comprising: forming a second conductive feature over the semiconductor substrate; depositing a mask over the second conductive feature; and depositing the etch stop layer over the mask.

[0120] Example 9 is the method of Example 8, further comprising: extending the second opening through the mask using a third dry etching process; and forming a second contact in the second opening, the second contact being physically and electrically coupled to the second conductive feature.

[0121] Example 10 is the method described in Example 9, further comprising: depositing a buffer layer over the mask, the etch stop layer being deposited over the buffer layer; and extending the second opening through the buffer layer using the third dry etching process.

[0122] Example 11 is the method of Example 1, further comprising: depositing a buffer layer over the etch stop layer, the second ILD being deposited over the buffer layer; and extending the first opening through the buffer layer using the first dry etching process.

[0123] Example 12 is a semiconductor device comprising: a semiconductor substrate; a first interlayer dielectric (ILD) located above the semiconductor substrate; a first conductive feature extending through the first ILD; a first etch stop layer located above the first conductive feature and the first ILD, the first etch stop layer being a first dielectric material; a second ILD located above the first etch stop layer; a contact having a first portion extending through the second ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature; and a first protective layer surrounding the second portion of the contact, the first portion of the contact being free of the first protective layer, the first protective layer being a second dielectric material, the second dielectric material being different from the first dielectric material.

[0124] Example 13 is the device of Example 12, wherein the first etch stop layer is aluminum oxide.

[0125] Example 14 is the device of Example 12, wherein the first protective layer is aluminum hydroxide.

[0126] Example 15 is the device of Example 12, wherein the first portion of the contact has a first width, the second portion of the contact has a second width, the second width is greater than the first width by a first distance, and the first distance is in the range of 1 nm to 9 nm.

[0127] Example 16 is the device described in Example 12, further comprising: a buffer layer disposed between the first conductive feature and the first etch stop layer, the contact having a third portion extending through the buffer layer, the third portion of the contact being free of the first protective layer.

[0128] Example 17 is the device of Example 12, further comprising: a buffer layer disposed between the first etch stop layer and the second ILD, the contact having a third portion extending through the buffer layer, the third portion of the contact being free of the first protection layer.

[0129] Example 18 is the device described in Example 17, further including: a second etch stop layer disposed between the buffer layer and the second ILD, the second etch stop layer being the first dielectric material, the contact having a fourth portion extending through the second etch stop layer; and a second protective layer surrounding the fourth portion of the contact, the second protective layer being the second dielectric material.

[0130] Example 19 is the device described in Example 12, further comprising: a first buffer layer, disposed between the first ILD and the first etch stop layer, the contact having a third portion extending through the first buffer layer, the third portion of the contact being free of the first protective layer; and a second buffer layer, disposed between the first etch stop layer and the second ILD, the contact having a fourth portion extending through the second buffer layer, the fourth portion of the contact being free of the first protective layer.

[0131] Example 20 is a semiconductor device comprising: a semiconductor substrate; a first conductive feature located above the semiconductor substrate; a first etch stop layer located above the first conductive feature, the first etch stop layer being a first dielectric material; an interlayer dielectric (ILD) located above the first etch stop layer; and a contact having a first portion extending through the ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature, wherein the first portion of the contact has a first width, the second portion of the contact has a second width, the second width is greater than the first width by a first distance, and the first distance is in a range of 1 nm to 9 nm.

Claims

1. A method for manufacturing a semiconductor device, include: depositing an etch stop layer over the first interlayer dielectric ILD, the etch stop layer comprising a first dielectric material; depositing a second ILD over the etch stop layer; etching a first opening through the second ILD using a first dry etching process, the first opening exposing a first region of the etch stop layer, the first region being modified into a second dielectric material by the first dry etching process, a second region of the etch stop layer remaining covered by the second ILD, the second region being the first dielectric material after the first dry etching process, wherein the first opening through the second ILD has a first width; as well as The first opening is extended through the etch stop layer using a first wet etching process, the etch stop layer is exposed to a first etching solution during the first wet etching process, the first etching solution including a dielectric protectant for the first dielectric material and an etchant for the second dielectric material, wherein the first opening through the etch stop layer has a second width, and the second width is greater than the first width by a first distance.

2. The method according to claim 1, in, The first dielectric material is aluminum oxide, and the second dielectric material is aluminum chloride or aluminum bromide.

3. The method according to claim 2, in, The etchant is hydrofluoric acid or ammonia, and wherein the dielectric protectant is hydrogen peroxide or ozone.

4. The method according to claim 1, further comprising: include: forming a first conductive feature over a semiconductor substrate, the first conductive feature comprising a first conductive material; as well as depositing the first ILD over the first conductive feature, Wherein, the first etching solution also includes a first metal protective agent for the first conductive material.

5. The method according to claim 4, further comprising: include: forming a first contact in the first opening, the first contact being physically and electrically coupled to the first conductive feature, the first contact comprising a second conductive material; etching a second opening through the second ILD using a second dry etching process; as well as The second opening is extended through the etch stop layer using a second wet etching process, the etch stop layer is exposed to a second etching solution during the second wet etching process, the second etching solution including the dielectric protectant, the etchant, the first metal protectant, and a second metal protectant for the second conductive material.

6. The method according to claim 5, in, The first conductive material is cobalt and the second conductive material is tungsten.

7. The method according to claim 6, in, The first metal protecting agent is a benzotriazole polymer having a methyl side chain or an ethyl side chain, and the second metal protecting agent is a benzotriazole polymer having a chlorine side chain.

8. The method according to claim 5, further comprising: include: forming a second conductive feature over the semiconductor substrate; depositing a mask over the second conductive feature; as well as The etch stop layer is deposited over the mask.

9. The method according to claim 8, further comprising: include: extending the second opening through the mask using a third dry etching process; as well as A second contact is formed in the second opening, the second contact being physically and electrically coupled to the second conductive feature.

10. The method according to claim 9, further comprising: include: depositing a buffer layer over the mask, the etch stop layer being deposited over the buffer layer; as well as The second opening is extended through the buffer layer using the third dry etching process.

11. The method according to claim 1, further comprising: include: depositing a buffer layer over the etch stop layer, wherein the second ILD is deposited over the buffer layer; as well as The first opening is extended through the buffer layer using the first dry etching process.

12. A semiconductor device, include: Semiconductor substrate; A first interlayer dielectric ILD, located above the semiconductor substrate; a first conductive feature extending through the first ILD; a first etch stop layer over the first conductive feature and the first ILD, the first etch stop layer being a first dielectric material; a second ILD, located above the first etch stop layer; a contact having a first portion extending through the second ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature; as well as a first protective layer surrounding the second portion of the contact, the first portion of the contact being free of the first protective layer, the first protective layer being a second dielectric material different from the first dielectric material, The first portion of the contact has a first width and the second portion of the contact has a second width that is greater than the first width by a first distance.

13. The device according to claim 12, in, The first etch stop layer is aluminum oxide.

14. The device according to claim 12, in, The first protective layer is aluminum hydroxide. The device according to claim 12 , wherein the first distance is in the range of 1 nm to 9 nm.

16. The device according to claim 12, further comprising: include: A buffer layer is disposed between the first conductive feature and the first etch stop layer, the contact having a third portion extending through the buffer layer, the third portion of the contact being free of the first protective layer.

17. The device according to claim 12, further comprising: include: A buffer layer is disposed between the first etch stop layer and the second ILD, the contact has a third portion extending through the buffer layer, and the third portion of the contact is free of the first protection layer.

18. The device according to claim 17, further comprising: include: a second etch stop layer disposed between the buffer layer and the second ILD, the second etch stop layer being the first dielectric material, the contact having a fourth portion extending through the second etch stop layer; as well as A second protective layer surrounds the fourth portion of the contact, the second protective layer being the second dielectric material.

19. The device according to claim 12, further comprising: include: a first buffer layer disposed between the first ILD and the first etch stop layer, the contact having a third portion extending through the first buffer layer, the third portion of the contact being free of the first protection layer; as well as A second buffer layer is disposed between the first etch stop layer and the second ILD, the contact has a fourth portion extending through the second buffer layer, and the fourth portion of the contact is free from the first protection layer.

20. A semiconductor device, include: Semiconductor substrate; a first conductive feature located above the semiconductor substrate; a first etch stop layer overlying the first conductive feature, the first etch stop layer being a first dielectric material; An interlayer dielectric ILD, located above the first etch stop layer; as well as a contact having a first portion extending through the ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature, The first portion of the contact has a first width, the second portion of the contact has a second width, the second width is greater than the first width by a first distance, and the first distance is in a range of 1 nm to 9 nm.

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