Method of forming a semiconductor device

Abstract

Embodiments of the present disclosure provide a method of forming a semiconductor device. When patterning an etch stop layer located below a dielectric layer, a photoresist layer is used to protect the dielectric layer and conductive elements embedded in the dielectric layer. The photoresist layer can further be used to etch another dielectric layer below the etch stop layer, wherein etching the next dielectric layer exposes contacts, such as gate contacts. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from damage by a wet etchant used to etch the etch stop layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for forming a semiconductor device, and more particularly to a method for forming a metal component. Background Art

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Generally, a semiconductor device is manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layer materials on a semiconductor substrate, and using photolithography to pattern various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum component size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] An object of the present invention is to provide a method for forming a semiconductor device to solve at least one of the above problems.

[0005] Some embodiments of the present invention provide a method for forming a semiconductor device, including: patterning a photoresist layer on a dielectric layer; etching the dielectric layer based on the pattern of the photoresist layer to form an opening in the dielectric layer, and the etching stops at an etch stop layer below the dielectric layer; when the photoresist layer is on the dielectric layer, etching the etch stop layer to penetrate the etch stop layer; and forming a conductive element in the opening in the dielectric layer, and the conductive element is electrically coupled to a first metal component below the etch stop layer.

[0006] Some embodiments of the present invention provide a method for forming a semiconductor device, including: forming a mask on a first dielectric layer; forming a first opening in the mask, and the first opening exposes a part of the first dielectric layer; using the mask as an etch mask to etch the first dielectric layer to form a second opening in the first dielectric layer, and the second opening exposes the etch stop layer; using the mask as an etch mask to etch the etch stop layer to form a third opening in the etch stop layer, and the third opening exposes a second dielectric layer; using the mask as an etch mask to etch the second dielectric layer to form a fourth opening in the second dielectric layer, and the fourth opening exposes a conductive element; and forming a first metal component in the first dielectric layer, and the first metal component is electrically coupled to the conductive element.

[0007] Some embodiments of the present invention provide a method of forming a semiconductor device, including: forming a first metal component in a first dielectric layer, the first metal component being electrically coupled to a source / drain contact of a transistor; depositing and patterning a mask layer on the first dielectric layer; patterning the first dielectric layer according to the pattern of the mask layer; when the mask layer is on the first dielectric layer, patterning an etch stop layer below the first dielectric layer according to the pattern of the mask layer; when the mask layer is on the first dielectric layer, patterning a second dielectric layer according to the pattern of the mask layer to expose a gate electrode of the transistor; and forming a conductive plug through the first dielectric layer and through the second dielectric layer, the conductive plug contacting the gate electrode.

[0008] The beneficial effect of the present invention is that when patterning the etch stop layer located below the dielectric layer, the embodiments of the present disclosure advantageously use the underlying layer of the photoresist mask to protect the dielectric layer and the conductive elements embedded in the dielectric layer, rather than removing the underlying layer first. The underlying layer can also be used to etch another dielectric layer below the etch stop layer, where etching the next dielectric layer exposes the contact, such as the gate contact. The underlying layer can be used to protect the conductive elements embedded in the dielectric layer from being damaged by the wet etchant used to etch the etch stop layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following will detail various aspects of the present disclosure in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the units may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

[0010] Figure 1 FIG. 12 shows a three-dimensional view of an exemplary fin field effect transistor (FinFET) according to some embodiments.

[0011] Figures 2 to 23 FIG. 16 shows a cross-sectional view of fin field effect transistors (FinFETs) at an intermediate stage of manufacturing according to some embodiments.

[0012] Figure 24 FIG. 20 shows a flowchart of a process for manufacturing a fin field effect transistor (FinFET) according to some embodiments.

[0013] Figures 25 to 31 FIG. 24 shows a cross-sectional view of an intermediate stage of manufacturing for forming a conductive element in a dielectric layer according to some embodiments.

[0014] The reference numerals are as follows:

[0015] 50: Substrate

[0016] 51: Separator

[0017] 52: Fin

[0018] 56: Shallow Trench Isolation (STI) region

[0019] 58: Channel region

[0020] 72: dummy gate

[0021] 80: Gate seal spacer

[0022] 82: Source / Drain region

[0023] 86: Gate spacer

[0024] 87: Contact Etch Stop Layer

[0025] 88: Interlayer Dielectric

[0026] 90: Notch

[0027] 92: Gate dielectric layer

[0028] 94: Gate

[0029] 96: Gate mask

[0030] 108: Bottom layer

[0031] 109: Opening

[0032] 110: Intermediate layer

[0033] 111: Opening

[0034] 112: Top layer

[0035] 114: Photomask

[0036] 121: Liner

[0037] 122: Conductive material

[0038] 124: Contact

[0039] 124: Contact

[0040] 132: Dielectric layer

[0041] 134: Etch Stop Layer

[0042] 138: Interlayer Dielectric

[0043] 142: Bottom layer

[0044] 144: Intermediate layer

[0045] 146: Top layer

[0046] 148: Photomask

[0047] 149: Opening

[0048] 152: Liner

[0049] 154: Conductive Plug

[0050] 162: Bottom Layer

[0051] 164: Intermediate Layer

[0052] 166: Upper Layer

[0053] 168: Photomask

[0054] 169: Opening

[0055] 171: Liner

[0056] 172: Conductive Material

[0057] 174: Gate Contact

[0058] 200: Process

[0059] 205: Step

[0060] 210: Step

[0061] 215: Step

[0062] 220: Step

[0063] 225: Step

[0064] 230: Step

[0065] 235: Step

[0066] 240: Step

[0067] 245: Step

[0068] 250: Step

[0069] 255: Step

[0070] 260: Step

[0071] 265: Step

[0072] 270: Step

[0073] 275: Step

[0074] 280: Step

[0075] 285: Step

[0076] 290: Step

[0077] 300: Structure

[0078] 310: Substrate

[0079] 320: Conductive component

[0080] 330: Etch stop layer

[0081] 340: Dielectric material layer

[0082] 350: Conductive element

[0083] 360: Photomask

[0084] 362: Bottom layer

[0085] 364: Intermediate layer

[0086] 366: Upper layer

[0087] 369: Opening

[0088] 370: Conductive element

[0089] 372: Liner

[0090] 374: Conductive material

[0091] 50N: Region

[0092] 50P: Region

[0093] A - A: Cross - section Detailed implementation manners

[0094] The following provides many different embodiments or examples to implement different components of the embodiments of the present disclosure. The following describes specific examples of components and configuration methods to simplify the embodiments of the present disclosure. Of course, these are only examples and are not intended to limit the embodiments of the present disclosure. For example, in the following description, it is mentioned that the first component is formed above or on the second component, which may include an embodiment where the first component and the second component are formed in direct contact, and may also include an embodiment where additional components are formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numerals and / or letters in each example. This repetition is for the purpose of simplification and clarity, and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0095] Furthermore, relative terms related to space may be used, such as "under", "below", "lower", "above", "higher", etc. Such terms are used to facilitate the description of the relationship between one (or more) components or features and another (or more) components or features in the accompanying drawings. Relative space terms are intended to cover different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the relative space adjectives used therein will also be interpreted according to the turned orientation.

[0096] Embodiments of the present disclosure include a process of forming contacts in a dielectric layer. When etching the dielectric layer, a mask is provided by a photomask layer, such as the bottom layer of a three-layer photomask. The mask protects the areas of the dielectric layer that are not to be etched. A stop layer may be located below the dielectric layer, such as an etch stop layer. The etchant used for etching the dielectric layer is selective to the dielectric layer, such that the etching rate relative to the dielectric layer is greater than the etching rate relative to the etch stop layer. A separate etchant is then used to break through the etch stop layer. The subsequent etchant is selective to the etch stop layer and does not significantly etch the dielectric layer. The mask layer is left in place instead of being removed (the mask that is no longer needed) to protect other metal components that may be formed and embedded in the dielectric layer. For example, if the dielectric layer covers a FinFET, a first contact may be formed to the source / drain region, and then a second contact may be formed in a process separate from the gate electrode. The mask layer can be retained in place to protect the first contact (e.g., to the source / drain region) while forming a through opening in the etch stop layer to form the second contact. In some embodiments, another dielectric layer may be below the etch stop layer, such as a dielectric layer related to forming self-aligned contacts. In such embodiments, the bottom layer can still be left in place to etch the next dielectric layer, thereby further protecting the dielectric layer and the embedded first contact.

[0097] Figure 1 According to some embodiments, an example of a FinFET is shown in a three-dimensional view. The FinFET includes fins 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are provided in the substrate 50, and the fins 52 protrude above and between adjacent isolation regions 56. Although the isolation regions 56 are described / illustrated as being separate from the substrate 50, as used in the present disclosure, the term "substrate" may refer to a separate semiconductor substrate or a semiconductor substrate combined with isolation regions. Additionally, although the fins 52 and the substrate 50 are shown as a single continuous material, the fins 52 and / or the substrate 50 may include a single material or multiple materials. In the present disclosure, a fin 52 refers to a portion that extends between adjacent isolation regions 56.

[0098] The gate dielectric layer 92 is disposed along the sidewalls of the fin and above the top surface of the fin 52, and the gate 94 is disposed above the gate dielectric layer 92. The source / drain regions 82 are disposed on both sides of the fin 52 with respect to the gate dielectric layer 92 and the gate 94. Figure 1 Further shown are reference cross-sections used in subsequent figures. Cross-section A-A is perpendicular to the gate dielectric layer 92 and along the longitudinal axis of the fin 52, and, for example, perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. For clarity, subsequent figures refer to these reference cross-sections.

[0099] Some embodiments described in the present disclosure are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments refer to planar devices such as planar FETs, nanostructure (nanosheet, nanowire, gate-all-around, etc.) field effect transistors (NSFETs).

[0100] In other embodiments, the process may be used to form contacts in an interconnect structure, such as an interconnect structure on a die or a redistribution structure on an embedded die. In some embodiments, the embodiments may be used in a mid-end of line (MEoL) process for metal plugs.

[0101] Figures 2 to 23 For some embodiments, it is a cross-sectional view in an intermediate stage of manufacturing FinFETs. Specifically, Figures 2 to 23 it relates to forming contacts in the manufacture of FinFETs. In addition to the plurality of fins / FinFETs, Figures 2 to 23 shown Figure 1 is the reference cross-section A-A shown. Figure 24 is related to Figures 2 to 23 the flowchart related to the formation of the FinFET shown, and the following description process will refer to the drawings.

[0102] In Figure 2 it, the FinFET has been partially formed. The following provides for forming Figure 2Processes and materials for FinFETs. Substrate 50 can be a semiconductor substrate, e.g., a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with p-type doping or n-type doping) or undoped. Substrate 50 can be a wafer, e.g., a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, e.g., a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is typically disposed on a substrate, e.g., a silicon substrate or a glass substrate. Other substrates can also be used, e.g., a multi-layer substrate or a gradient substrate. In some embodiments, the semiconductor material of substrate 50 can include silicon, germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0103] Substrate 50 has an n-type region 50N and a p-type region 50P. Thus, as Figure 2 shown, the illustrated embodiments can be applicable to either the n-type region 50N or the p-type region 50P. For simplicity, these designations are omitted in the remaining figures, but it should be understood that the remaining figures can also be applied to either region. For example, Figures 2 to 23 the structure shown can be applicable to both the n-type region 50N and the p-type region 50P. Structural differences (if any) between the n-type region 50N and the p-type region 50P will be described in the text accompanying each figure. The n-type region 50N can be used to form n-type devices, e.g., NMOS transistors (e.g., n-type FinFETs). The p-type region 50P can be used to form p-type devices, e.g., PMOS transistors (e.g., p-type FinFETs). The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separation symbol 51), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P.

[0104] Fins 52 are formed in substrate 50. This process corresponds to Figure 24 step 205 in flowchart 200 of. The fins 52 are semiconductor strips. In some embodiments, the fins 52 can be formed by etching trenches in substrate 50. The etching can be any acceptable etching process, e.g., reactive ion etch (RIE), neutral beam etch (NBE), etc. or combinations thereof. The etching can be anisotropic etching.

[0105] The fins can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern the fins, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine lithography processes with self-alignment processes, allowing the creation of patterns, for example, with pitches smaller than those achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins. In some embodiments, a mask (or other layer) can be retained on the fins 52.

[0106] An insulating material is formed over the substrate 50 and between adjacent fins 52. This process corresponds to Figure 24 step 210 in the flowchart 200 of. The insulating material can be an oxide, such as silicon oxide, nitride, etc. or a combination thereof, and can be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., depositing a CVD-based material in a remote plasma system and post-curing to convert the deposited material to another material, such as an oxide), etc. or a combination thereof. Other insulating materials formed by any acceptable process can be used. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed as an excessive insulating material to cover the fins 52. Although the insulating material is shown as a single layer, some embodiments can utilize multiple layers of insulating material. For example, in some embodiments, a liner layer (not shown separately) can be first formed along the surfaces of the substrate 50 and the fins 52. Thereafter, a filling material, such as the materials discussed above, can be formed over the liner layer.

[0107] A removal process is applied to the insulating material to remove the excess insulating material over the fins 52. This process corresponds to Figure 24 step 215 in the flowchart 200 of. In some embodiments, a planarization process, such as chemical mechanical polish (CMP), etchback process, a combination thereof, etc., can be utilized. The planarization process exposes the fins 52 such that after the planarization process is completed, the top surfaces of the fins 52 and the insulating material are horizontal. In embodiments where a mask is retained on the fins 52, after the planarization process is completed, the planarization process can expose the mask or remove the mask such that the top surface of the mask or the fins 52 is flush with the insulating material.

[0108] The insulating material is etched to form a shallow trench isolation (STI) region 56. This process corresponds to Figure 24 step 220 in flowchart 200 of. The insulating material is etched such that the upper portions of the fins 52 in the n-type region 50N and the p-type region 50P protrude between adjacent STI regions 56. Additionally, the top surface of the STI region 56 can have a flat surface, a convex surface, a concave surface (e.g., a dish-shaped surface), or a combination thereof as shown. The top surface of the STI region 56 can be formed to be flat, convex, and / or concave by appropriate etching. The STI region 56 can be etched using an acceptable etching process, such as an etching process selective to the material of the insulating material (e.g., an etching process that etches the material of the insulating material at a faster rate than the material of the fins 52). For example, oxide removal using, for example, dilute hydrofluoric (dHF) acid can be used.

[0109] The above process is merely one example of how the fins 52 can be formed. In some embodiments, the fins can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. A homoepitaxial structure can be epitaxially grown in the trenches, and the dielectric layer can be etched such that the homoepitaxial structure protrudes from the dielectric layer to form fins. Additionally, in some embodiments, a heteroepitaxial structure can be used for the fins 52. For example, Figure 5 the fins 52 in can be etched, and a material different from that of the fins 52 can be epitaxially grown over the recessed fins 52. In such an embodiment, the fins 52 include the recessed material and the epitaxially grown material disposed over the recessed material. In another embodiment, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trenches using a material different from that of the substrate 50, and the dielectric layer can be etched such that the heteroepitaxial structure protrudes from the dielectric layer to form the fins 52. In some embodiments of epitaxially growing a homoepitaxial structure or a heteroepitaxial structure, the epitaxially grown material can be in-situ doped during the growth process, which can eliminate the need for prior and subsequent implantations. Nevertheless, in-situ and implantation doping can also be used together.

[0110] Furthermore, it can be beneficial to epitaxially grow a material different in the n-type region 50N (e.g., an NMOS region) from that in the p-type region 50P (e.g., a PMOS region). In various embodiments, the upper portion of the fins 52 can be composed of silicon germanium (Si x Ge 1-x, where x can range from 0 to 1), silicon carbide, pure or substantially pure germanium, group III-V compound semiconductors, group II-VI compound semiconductors, etc. For example, the available materials for forming group III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0111] Appropriate wells (not shown separately) can be formed in the fin 52 and / or the substrate 50. This process corresponds to Figure 24 step 225 in the flowchart 200 of. In some embodiments, a P well can be formed in the n-type region 50N, and an N well can be formed in the p-type region 50P. In some embodiments, a P well or an N well is formed in both the n-type region 50N and the p-type region 50P.

[0112] In embodiments with different well types, a photoresist or other mask (not shown separately) can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist can be formed over the fins 52 and the STI regions 56 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P (e.g., the PMOS region) of the substrate 50. The photoresist can be formed by using a spin coating technique, and the photoresist can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type doping implantation can be performed in the p-type region 50P, and the photoresist can be used as a mask to substantially prevent the n-type doping from being implanted into the n-type region 50N (e.g., the NMOS region). The n-type doping can be phosphorus, arsenic, antimony, etc. implanted into its region, and its concentration is equal to or less than 10 18 atoms / cm 3 , for example, at about 10 16 atoms / cm 3 and about 10 18 atoms / cm 3 between. After the implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0113] After implanting the p-type region 50P, a photoresist is formed over the fins 52 and the STI regions 56 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N (e.g., the NMOS region) of the substrate 50. The photoresist can be formed by using a spin coating technique, and the photoresist can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type doping implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent the p-type doping from being implanted into the p-type region 50P (e.g., the PMOS region). The p-type doping can be boron, boron fluoride, indium, etc. implanted into its region. Its concentration is equal to or less than 10 18 atoms / cm3 , for example, at about 10 16 atoms / cm 3 and about 10 18 atoms / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0114] After implantation in the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type dopants. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can avoid implantation, although in-situ doping and implantation doping can be used together.

[0115] A dummy dielectric layer and a dummy gate layer can be formed and patterned to form a dummy gate, which is then replaced in a gate replacement process. This process corresponds to Figure 24 step 230 in the flowchart 200 of

[0116] A dummy dielectric layer is formed on the fin 52. The dummy dielectric layer can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown by an acceptable technique. A dummy gate layer is formed above the dummy dielectric layer, and a mask layer is formed above the dummy gate layer. The dummy gate layer can be deposited above the dummy dielectric layer and then planarized, for example, by CMP. The mask layer can be deposited above the dummy gate layer. The dummy gate layer can be a conductive material or a non-conductive material and can be selected from including amorphous silicon, polysilicon, poly-SiGe, metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer can be formed of other materials that have a high etch selectivity to the isolation regions, such as the STI region 56 and / or the dummy dielectric layer. The mask layer can include, for example, a single layer or multiple layers of silicon nitride, silicon oxynitride, etc. Figure 24 The mask layer can be patterned using acceptable lithography and etching techniques to form a mask. This process corresponds to

[0117] A gate seal spacer 80 may be formed on the exposed surfaces of the dummy gate, mask, and / or fin 52. This process corresponds to Figure 24 step 240 in the flowchart 200 of

[0118] The gate seal spacer 80 may be formed by thermal oxidation or deposition and subsequent anisotropic etching. The gate seal spacer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. 15 After forming the gate seal spacer 80, an implantation for lightly doped source / drain (LDD) regions (not shown separately) may be performed. In embodiments with different device types, similar to the implantations discussed above, a mask, such as photoresist, may be formed over the n-type region 50N while exposing the p-type region 50P, and impurities of a suitable type (e.g., p-type) may be implanted into the fins 52 exposed in the p-type region 50P. The mask may then be removed. Subsequently, a mask, such as photoresist, may be formed over the p-type region 50P while exposing the n-type region 50N, and impurities of a suitable type (e.g., n-type) may be implanted into the fins 52 exposed in the n-type region 50N. The mask may then be removed. The n-type impurities may be any of the n-type impurities discussed previously, and the p-type impurities may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have an impurity concentration of about 10 3 to about 10 19 atoms / cm 3 . Annealing may be used to repair implantation damage and activate the implanted impurities.

[0119] A gate spacer 86 is formed on the gate seal spacer 80 along the sidewalls of the dummy gate and the mask. The gate spacer 86 may be formed by conformally depositing an insulating material and then anisotropically etching the insulating material to form the gate spacer 86. The insulating material of the gate spacer 86 may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc.

[0120] It should be noted that the above disclosure describes the processes for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, and different step sequences may be used (e.g., the gate seal spacer 80 may not be etched before forming the gate spacer 86, resulting in an "L-shaped" gate seal spacer, and spacers may be formed and removed and / or similar steps). Additionally, different structures and steps may be used to form n-type and p-type devices. For example, the LDD region for the n-type device may be formed before forming the gate seal spacer 80, while the LDD region for the p-type device may be formed after forming the gate seal spacer 80.

[0121] An epitaxial source / drain region 82 is formed in the fin 52. This process corresponds to Figure 24 steps 245 and 250 in the flow chart 200 of. An epitaxial source / drain region 82 is formed in the fin 52 such that each dummy gate 72 is disposed between respective adjacent pairs of the epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain region 82 may extend into the fin 52 and may also penetrate the fin 52. In some embodiments, the gate spacers 86 are used to separate the epitaxial source / drain region 82 from the dummy gate 72 by an appropriate lateral distance so that the epitaxial source / drain region 82 does not short-circuit the gates of the subsequently formed FinFETs. The material of the epitaxial source / drain region 82 can be selected to apply stress in the respective channel regions 58, thereby improving performance.

[0122] The epitaxial source / drain region 82 in the n-type region 50N (e.g., NMOS region) may pass through a mask of the p-type region 50P (e.g., PMOS region), and the source / drain regions of the fins 52 in the n-type region 50N are etched to form notches in the fins 52. Thereafter, the epitaxial source / drain region 82 in the n-type region 50N is epitaxially grown in the notches. The epitaxial source / drain region 82 may include any acceptable material, such as suitable for an n-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the n-type region 50N may include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 82 in the n-type region 50N may have a surface that rises from the corresponding surface of the fin 52 and may have facets.

[0123] The epitaxial source / drain region 82 in the p-type region 50P (e.g., PMOS region) may pass through a mask of the n-type region 50N (e.g., NMOS region), and the source / drain regions of the fins 52 in the p-type region 50P are etched to form notches in the fins 52. Thereafter, the epitaxial source / drain region 82 in the p-type region 50P is epitaxially grown in the notches. The epitaxial source / drain region 82 may include any acceptable material, such as suitable for a p-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the p-type region 50P may include a material that applies compressive strain in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain region 82 in the p-type region 50P may have a surface that rises from the corresponding surface of the fin 52 and may have facets.

[0124] The epitaxial source / drain region 82 and / or the fin 52 may be implanted with dopants to form the source / drain regions, similar to the process discussed previously for forming lightly doped source / drain regions and then annealing. The impurity concentration of the source / drain regions may be about 1019 atoms / cm 3 to about 10 21 atoms / cm 3 Between. The n-type and / or p-type impurities for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 82 can be in-situ doped during growth.

[0125] As an epitaxial process for forming the epitaxial source / drain regions 82 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions has facets that laterally expand outward beyond the sidewalls of the fins 52. In some embodiments, these facets merge the epitaxial source / drain regions 82 adjacent to the same FinFET. In other embodiments, the adjacent epitaxial source / drain regions 82 remain separated after the epitaxial process is completed. In these embodiments, the gate spacers 86 are formed to cover the sidewalls of a portion of the fins 52, which extend above the STI region 56, thereby blocking epitaxial growth. In some other embodiments, the spacer etch used to form the gate spacers 86 can be adjusted to remove the spacer material to allow the region of epitaxial growth to extend to the surface of the STI region 56.

[0126] The first interlayer dielectric (ILD) 88 is deposited on the above structure. This process corresponds to Figure 24 step 255 in the flowchart 200 of. The first ILD 88 can be formed of any suitable material, which can include dielectric materials having a low dielectric constant (k value) below 3.8, below about 3.0, or below about 2.5, and can be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain regions 82, the mask, and the gate spacers 86. The CESL 87 can include dielectric materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., which have a lower etch rate than the material of the first ILD 88 above during the etching of the first ILD 88 above.

[0127] A planarization process such as CMP can be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate or the mask. The planarization process can also remove the mask on the dummy gate, as well as a part of the gate seal spacer 80 and the gate spacer 86 along the sidewalls of the mask. After the planarization process, the top surfaces of the dummy gate, the gate seal spacer 80, the gate spacer 86, and the first ILD 88 are flush. Thus, the top surface of the dummy gate is exposed through the first ILD 88. In some embodiments, the mask can be retained, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask.

[0128] The dummy gate is then replaced. This process corresponds to Figure 24 step 260 in the flowchart 200 of. In the etching step, the dummy gate and the mask (if present) are removed, thereby forming a notch. A part of the dummy dielectric layer in the notch can also be removed. In some embodiments, only the dummy gate is removed and the dummy dielectric layer is retained and exposed by the notch. In some embodiments, the dummy dielectric layer is removed from the notch in the first region (e.g., the core logic region) of the die and retained in the notch in the second region (e.g., the input / output region) of the die. In some embodiments, the dummy gate is removed by an anisotropic dry etching process. For example, the etching process can include a dry etching process using a reactive gas that selectively etches the dummy gate without etching the first ILD 88 or the gate spacer 86. Each notch can expose and / or cover the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of the epitaxial source / drain regions 82. During the removal, when etching the dummy gate, the dummy dielectric layer can be used as an etch stop layer. Then the dummy dielectric layer can be optionally removed after removing the dummy gate.

[0129] A gate dielectric layer 92 and a gate 94 are formed to replace the gate. The gate dielectric layer 92 includes a single layer or multiple layers deposited in the notch 90, such as on the top surface and sidewalls of the fin 52, as well as on the sidewalls of the gate seal spacer 80 and the gate spacer 86. The gate dielectric layer 92 can also be formed on the top surface of the first ILD 88. In some embodiments, the gate dielectric layer 92 includes one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, the gate dielectric layer 92 includes an interface layer of silicon oxide formed by thermal or chemical oxidation, and a high-k dielectric material above it, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and their combinations. The gate dielectric layer 92 can include a dielectric layer having a dielectric constant greater than about 7.0. The method of forming the gate dielectric layer 92 can include molecular-beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of the dummy dielectric layer remains in the notch 90, the gate dielectric layer 92 includes the material of the dummy dielectric layer (e.g., SiO2).

[0130] The gate 94 is deposited above the gate dielectric layer 92 respectively and fills the remaining part of the notch. The gate 94 can include a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, their combinations, or their multi-layer films. For example, although a single-layer gate 94 is shown in Figure 2 the gate 94 can include any number of liner layers, any number of work function adjustment layers, and filling materials. After filling the notch, a planarization process such as CMP can be performed to remove the excess portions of the gate dielectric layer 92 and the gate 94 material, which are above the top surface of the first ILD 88. The remaining portions of the gate 94 and the gate dielectric layer 92 thus form the replacement gate of the resulting FinFETs. The gate 94 and the gate dielectric layer 92 can be collectively referred to as the "gate stack". The gate and the gate stack can extend along the sidewalls of the fin 52 channel region 58.

[0131] The gate dielectric layer 92 can be formed simultaneously in the n-type region 50N and the p-type region 50P such that the gate dielectric layer 92 in each region is formed of the same material, and the gate 94 can be formed simultaneously such that the gate 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region can be formed by different processes such that the gate dielectric layer 92 can be different materials, and / or the gate 94 in each region can be formed by different processes such that the gate 94 can be different materials. When using different processes, various masking steps can be used to mask and expose the appropriate regions.

[0132] In some embodiments, a gate mask 96 is formed over a gate stack (including a gate dielectric layer 92 and a corresponding gate electrode 94), and the gate mask may be disposed between opposing portions of the gate spacers 86. In some embodiments, forming the gate mask 96 includes etching the gate stack such that a notch is directly formed above the gate stack and between the opposing portions of the gate spacers 86. The gate mask 96 includes one or more dielectric materials, such as silicon nitride, silicon oxynitride, etc., which are filled in the notch, and then a planarization process is performed to remove the excess dielectric material extending over the first ILD 88. In other embodiments, the gate mask 96 may be formed in subsequent process steps.

[0133] Figures 3 to 6 According to some embodiments, a process of forming self-aligned source / drain contacts is illustrated. This process corresponds to Figure 24 step 265 in the flowchart 200 of Figure 3 In

[0134] In Figure 4 , the photomask 114 may include a single photoresist or a three-layer photomask. The single photoresist may include only layer 108. In embodiments using a three-layer photoresist, the three layers may include a bottom layer 108, an intermediate layer 110 above the bottom layer 108, and an upper layer 112 above the intermediate layer 110. According to some embodiments of the present disclosure, the bottom layer 108 and the upper layer 112 are formed of a photoresist made of an organic material. The intermediate layer 110 may be formed of an inorganic material, and the inorganic material may be a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), etc. The intermediate layer 110 has a high etch selectivity relative to the upper layer 112 and the bottom layer 108. Thus, the upper layer 112 serves as an etch mask for patterning the intermediate layer 110, and the intermediate layer 110 serves as an etch mask for patterning the bottom layer 108. After the photomask 114 is applied, the upper layer 112 is patterned in a lithography process. Then, the patterned upper layer 112 is used to pattern the intermediate layer 110 by extending the opening 109 in the upper layer 112 into the intermediate layer 110.

[0135] In Figure 5In [the structure], the openings 111 and 109 are filled with a liner 121 (such as a diffusion barrier layer, an adhesion layer, etc.) and a conductive material 122. The liner 121 may include titanium, titanium nitride, tantalum, tantalum nitride, etc. formed by ALD, CVD, etc. The conductive material 122 may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, titanium, tantalum, their alloys, their combinations, etc., however, other suitable metals may be used in the present disclosure. A planarization process, such as CMP, may be performed to remove excess material from the surface of the underlying layer 108.

[0136] In Figure 6 [the structure], the conductive material 122 and the underlying layer 108 may continue to be planarized so that the upper surface of the conductive material 122 is flush with the upper surfaces of the gate spacers 86 and the gate mask 96. The conductive material 122 is thus separated into different self-aligned source / drain contacts 124.

[0137] In Figure 7 [the structure], a dielectric layer 132 may be formed over the gate electrode 94, the contacts 124, the first ILD 88, and the gate spacers 86. This process corresponds to Figure 24 step 270 in the flowchart 200 of [[reference]]. In some embodiments, the gate mask 96 and the contacts 124 may be etched before forming the dielectric layer 132. In some embodiments, the gate mask 96 is not pre-formed, and the gate electrode 94 is etched together with the contacts 124, and the dielectric layer 132 is formed over the gate electrode 94 such that a portion of the dielectric layer 132 becomes the gate mask 96. In one embodiment, the dielectric layer 132 may be a dielectric material, such as silicon nitride, although any suitable dielectric material may alternatively be utilized. A process such as chemical vapor deposition may be used to form the dielectric layer 132 to have a thickness between about and about for example, about However, any suitable process, such as PECVD, ALD, etc., and any suitable thickness may alternatively be used. The dielectric layer 132 may be formed to repair any damage that may be caused by forming the self-aligned source / drain contacts 124. In some embodiments, the dielectric layer 132 may be formed conformally and planarized so that its upper surface is horizontal, while in other embodiments, the dielectric layer 132 may not be planarized.

[0138] An etch stop layer (ESL) 134 may also be formed over the dielectric layer 132. This process corresponds to Figure 24Step 275 in the flowchart 200. In one embodiment, the ESL 134 may include a dielectric material such as alumina, silicon carbide, silicon nitride, etc. The ESL 134 may be formed of nitrides, silicon-carbon based materials, carbon-doped oxides, oxygen-doped carbides, nitrogen-doped silicon carbide, and / or combinations thereof. The ESL 134 may include a metal material. The method of forming the ESL 134 includes plasma-enhanced chemical vapor deposition (PECVD) or other methods such as high-density plasma CVD (HDPCVD), atomic layer deposition (ALD), low-pressure CVD (LPCVD), physical vapor deposition (PVD), etc. The material of the ESL 134 may be deposited to a total thickness between about and about , for example, about

[0139] In Figure 8 , the second ILD 138 is deposited on the ESL 134. This process corresponds to Figure 24 Step 280 in the flowchart 200. In some embodiments, the second ILD 138 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 138 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method such as CVD and PECVD.

[0140] Figures 9 to 15 Illustrates the process of forming a conductive plug to contact the self-aligned source / drain contact 124. This process corresponds to Figure 24 Step 285 in the flowchart 200. In Figure 9 , a three-layer photomask 148 is formed above the second ILD 138. The three-layer photomask 148 includes a bottom layer 142, an intermediate layer 144 on the bottom layer 142, and an upper layer 146 on the intermediate layer 144. According to some embodiments of the present disclosure, the bottom layer 142 and the upper layer 146 are formed of a photoresist formed of an organic material. The bottom layer 142 may have anti-reflection properties and may be a nitrogen-free anti-reflection coating. The intermediate layer 144 may be formed of an inorganic material, and the inorganic material may be a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), etc. The intermediate layer 144 has a high etch selectivity relative to the upper layer 146 and the bottom layer 142. Therefore, the upper layer 146 serves as an etch mask for patterning the intermediate layer 144, and the intermediate layer 144 serves as an etch mask for patterning the bottom layer 142. After forming the photomask 148, the upper layer 146 is patterned in a lithography process to form an opening 149.

[0141] In Figure 10In [description], while using the upper layer 146 as an etch mask, the opening 149 in the upper layer 146 is extended into the intermediate layer 144 through an etching process to pattern the intermediate layer 144 using the patterned upper layer 146. The upper layer 146 may be consumed in the process. If the upper layer is not consumed, after patterning the intermediate layer 144, the upper layer 146 can be removed through a cleaning process.

[0142] In Figure 11 In [description], while using the intermediate layer 144 as an etch mask, the opening 149 in the intermediate layer 144 is extended into the bottom layer 142 through an etching process to pattern the bottom layer 142 using the patterned intermediate layer 144. The intermediate layer 144 may be consumed in the process. If the intermediate layer is not consumed, after patterning the bottom layer 142, the intermediate layer 144 can be removed through a cleaning process.

[0143] In Figure 12 In [description], while using the bottom layer 142 as an etch mask, the opening 149 is extended into the second ILD 138 through an etching process to pattern the second ILD 138 using the bottom layer 142. A dry etching process (plasma etching) can be used to etch the second ILD 138. If dry etching is used, exemplary etchants for etching the second ILD 138 can include fluorine-reactive gases such as carbon-fluorine-based etchants (C x F y ), NF3, etc. Other process gases can be used in combination with the carbon-fluorine-based etchant, such as oxygen (O2), nitrogen (N2), argon (Ar), combinations thereof, etc. The ESL 134 can be used as an etch stop layer.

[0144] In Figure 13 In [description], after etching the second ILD 138, the bottom layer 142 is not removed, but is kept in place to etch the ESL 134 and the dielectric layer 132. The bottom layer 142 provides protection for the second ILD 138, thus avoiding processes for restoring or planarizing the second ILD 138. In addition, in some embodiments, other components can be formed in the second ILD 138, such as other conductive plugs, isolation regions, or other metal components. In such embodiments, these components can be protected by the bottom layer 142.

[0145] The ESL 134 is etched through a wet etching process to break through the ESL 134. If the underlying layer 142 is removed, the wet etching process may damage the second ILD 138. Deionized water (DI), DI mixed with carbon dioxide (CO2), DI mixed with ozone (O3), DI mixed with hydrogen peroxide (H2O2) (where the ratio of DI to H2O2 is between 5:1 and 30:1), DI mixed with ammonia (NH4OH) (where the ratio of DI to NH4OH is between 5:1 and 2000:1), and Standard Clean 1 (SC1) can be used to etch the ESL 134. The SC1 solution may contain NH4OH, H2O2, and H2O (where the ratio of NH4OH, H2O2, and H2O is between 1:1:5 and 1:1:400). At a process temperature between about 20 °C and about 65 °C, the etching may take 30 seconds to 300 seconds. After etching, isopropyl alcohol and / or acetone can be used to rinse and dry the opening 149.

[0146] In Figure 14 , after etching the ESL 134, when the underlying layer 142 is still above the second ILD 138, the dielectric layer 132 can be etched to extend the opening 149 into the dielectric layer 132. Any suitable process can be used to etch the dielectric layer 132, such as a dry etching process using any suitable etchant (such as a fluorine reactive gas, such as a fluorocarbon etchant (C x F y ), NF3, etc.). The above etching exposes the self-aligned source / drain contacts 124.

[0147] In Figure 15 , the underlying layer 142 can be removed by any suitable technique, such as by an ashing process using a remote plasma including nitrogen, hydrogen, or oxygen. The opening 149 is filled with a liner 152 (such as a diffusion barrier layer, an adhesion layer, etc.) and a conductive material. The liner 152 can include titanium, titanium nitride, tantalum, tantalum nitride, etc. formed by ALD, CVD, etc. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, titanium, tantalum, their alloys, their combinations, etc., however, other suitable metals can be used in the present disclosure. A planarization process, such as CMP, can be performed to remove excess material from the surface of the second ILD 138 and to make the upper surface of the second ILD 138 flush with the upper surfaces of the liner 152 and the conductive material, thereby forming a conductive plug 154.

[0148] Figures 16 to 23 Illustrates a process for forming a gate contact for the gate electrode 94. This process corresponds to Figure 24 step 290 in the flowchart 200 ofFigure 23 ) can be formed in different profiles, which can avoid short - circuits of the contact members. In Figure 16 , a three - layer photomask 168 is formed on the second ILD 138. The three - layer photomask 168 includes a bottom layer 162, an intermediate layer 164 on the bottom layer 162, and an upper layer 166 on the intermediate layer 164. A process and materials similar to those of Figure 9 's three - layer photomask 148 can be used to form the three - layer photomask 168. In the photolithography process, the upper layer 166 is patterned to form an opening 169.

[0149] In Figure 17 , while using the upper layer 166 as an etch mask, the opening 169 in the upper layer 166 is extended into the intermediate layer 164 through an etching process to pattern the intermediate layer 164 using the patterned upper layer 166. The upper layer 166 may be consumed in the process. If the upper layer is not consumed, after patterning the intermediate layer 164, the upper layer 166 can be removed through a cleaning process.

[0150] In Figure 18 , while using the intermediate layer 164 as an etch mask, the opening 169 in the intermediate layer 164 is extended into the bottom layer 162 through an etching process to pattern the bottom layer 162 using the patterned intermediate layer 164. The intermediate layer 164 may be consumed in the process. If the intermediate layer is not consumed, after patterning the bottom layer 162, the intermediate layer 164 can be removed through a cleaning process.

[0151] In Figure 19 , while using the bottom layer 162 as an etch mask, the opening 169 is extended into the second ILD 138 through an etching process to pattern the second ILD 138 using the bottom layer 162. A dry etching process (plasma etching) can be used, and materials such as those discussed above regarding Figure 12 can be used to etch the second ILD 138. The ESL 134 can be used as an etch stop layer.

[0152] In Figure 20 , after etching the second ILD 138, the bottom layer 162 is not removed, but is kept in place to etch the ESL 134 and the dielectric layer 132. The bottom layer 162 provides protection for the second ILD 138, thus avoiding processes for restoring or planarizing the second ILD 138. The bottom layer 162 also provides protection for the conductive plugs 154 that have been formed in the second ILD 138. In addition, in some embodiments, other components can be formed in the second ILD 138. In such embodiments, these components can be protected by the bottom layer 162.

[0153] Etch the ESL 134 through a wet etching process to break through the ESL 134. If the underlying layer 162 is removed, the wet etching process may damage the second ILD 138 and the conductive plug 154. The wet etching process for etching the ESL 134 can use, for example, the processes and materials discussed above with respect to Figure 13 The ESL 134 can be etched using the processes and materials discussed above.

[0154] In Figure 21 , after etching the ESL 134, when the underlying layer 162 is still above the second ILD 138, the dielectric layer 132 can be etched to extend the opening 169 into the dielectric layer 132 and into the gate mask 96. The dielectric layer 132 can be etched using any suitable process, such as a dry etching process using any suitable etchant (e.g., a fluorine reactive gas, such as a fluorocarbon etchant (C x F y ), NF3, etc.). In some embodiments, the gate mask 96 has the same material as the dielectric layer 132, while in other embodiments, the two have different materials. In such embodiments, the etchant used can be appropriately modified to etch the respective corresponding materials of the dielectric layer 132 and the gate mask 96. The above etching exposes the gate electrode 94.

[0155] In Figure 22 , the underlying layer 162 can be removed by any suitable technique, such as by an ashing process using a remote plasma including nitrogen, hydrogen, or oxygen. The opening 169 is filled with a liner layer 171 (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material 172. The liner layer 171 can include titanium, titanium nitride, tantalum, tantalum nitride, etc. formed by ALD, CVD, etc. The conductive material 172 can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, titanium, tantalum, their alloys, their combinations, etc., however, other suitable metals can also be used in the present disclosure.

[0156] In Figure 23 , a planarization process, such as CMP, can be performed to remove the excess material of the liner layer 171 and the conductive material 172 from the surface of the second ILD 138 and to make the upper surface of the second ILD 138 flush with the upper surfaces of the liner layer 171 and the conductive material 172, thereby forming the gate contact 174.

[0157] The disclosed FinFET embodiments can also be applied to nanostructure devices, such as nanostructure (e.g., nanosheets, nanowires, gate-all-around, etc.) field-effect transistors (NSFETs). In an NSFET embodiment, the fin is replaced by a nanostructure by patterning a stack of alternating channel layers and sacrificial layers. The dummy gate stack and source / drain regions are formed in a similar manner as in the above embodiments. After removing the dummy gate stack, the sacrificial layer can be partially or fully removed in the channel region. The replacement gate structure is formed in a similar manner as in the above embodiments, and the replacement gate structure can partially or fully fill the opening left by removing the sacrificial layer, and the replacement gate structure can partially or fully surround the channel layer in the channel region of the NSFET device. The ILDs and contacts to the replacement gate structure and source / drain regions can be formed in a similar manner as in the above embodiments. The nanostructure device can be formed as disclosed in U.S. Patent Application Publication No. 2016 / 0365414, which is incorporated herein by reference in its entirety.

[0158] In other embodiments, these processes can be used in back end of line (BEoL) processes to handle etch cleaning after vias or before metal plugs. Figures 25 to 31 As an intermediate step for forming a conductive element in a dielectric material layer of structure 300 is shown according to some embodiments. In some embodiments, the processes discussed with respect to Figures 25 to 31 can be used for forming interconnect structures in BEoL processes, such as interconnect structures on a die or redistribution structures. In other embodiments, the processes discussed with respect to Figures 25 to 31 can be used for forming contacts to transistors, such as FinFET transistors.

[0159] Figure 25 A substrate 310 is shown, which can be a part of a wafer. The substrate 310 can include different device regions that are later divided to form multiple integrated circuit dies. The substrate 310 can include a semiconductor substrate, such as doped or undoped silicon, or the active layer of a semiconductor-on-insulator (SOI) substrate. The substrate 310 can include other semiconductor materials, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Embodiments of the present disclosure can also use other substrates, such as multi-layer substrates or gradient substrates.

[0160] In other embodiments, the substrate 310 can be an interposer and can include one or more substrate cores formed of pre-impregnated composite fibers (“prepreg”), insulating films or stacked films, paper, glass fibers, non-woven glass fibers, silicon, etc. In other embodiments, the substrate 310 can be a carrier, such as a glass carrier, a ceramic carrier, etc. In some embodiments, the substrate 310 includes multiple layers, for example, a carrier and a semiconductor substrate attached thereto, with devices formed and embedded therein.

[0161] Figure 25 Also shown is a conductive component 320 embedded in the substrate 310. In some embodiments, the conductive component 320 can be formed in a separate layer above the substrate 310. The conductive component 320 can correspond to, for example, contact pads of dies or metal components in a redistribution structure or an interconnect structure. The conductive component 320 can be formed of any suitable conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof.

[0162] Figure 25 Also shown is an etch stop layer (ESL) 330 disposed above the conductive component 320. In some embodiments, the ESL 330 can be formed using, for example, the processes and materials discussed above with respect to Figure 7 It can be deposited to a total thickness between about and about For example, about

[0163] A dielectric material layer 340 is disposed above the ESL 330. The dielectric material layer 340 can correspond to an ILD or an inter-metal dielectric (IMD). The dielectric material layer 340 can include any suitable material, which can include, for example, a dielectric material having a low dielectric constant (k value) below 3.8, below about 3.0, or below about 2.5. The insulating material of the dielectric material layer 340 can be formed of PSG, BSG, BPSG, USG, fluorine-doped silicate glass (FSG), silicon oxide formed of tetraethyl orthosilicate (TEOS), Black Diamond (a registered trademark of Applied Materials Inc.), a carbon-containing low dielectric constant dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), etc. The dielectric material layer 340 can be selected such that it has an etch selectivity between the dielectric material layer and the ESL 330.

[0164] Figure 25 Also shown is a conductive element 350 disposed in the dielectric material layer 340. The conductive element 350 may include a via, a conductive wire, or an upper portion as a conductive wire and a lower portion as a via. The conductive element 350 is electrically and physically coupled to the conductive component 320. The conductive element 350 can be formed using similar processes and materials as those discussed with respect to the conductive element 370 (refer to Figure 30 ).

[0165] In Figure 25 , a three-layer photomask 360 is formed over the dielectric material layer 340. The three-layer photomask 360 includes a bottom layer 362, an intermediate layer 364 over the bottom layer 362, and an upper layer 366 over the intermediate layer 364. According to some embodiments of the present disclosure, the bottom layer 362 and the upper layer 366 are formed of a photoresist formed of an organic material. The bottom layer 362 may have antireflection properties and may be a nitrogen-free antireflection coating. The intermediate layer 364 may be formed of an inorganic material, and the inorganic material may be a nitride (such as silicon nitride), an oxynitride (such as silicon oxynitride), an oxide (such as silicon oxide), etc. The intermediate layer 364 has a high etch selectivity relative to the upper layer 366 and the bottom layer 362. Thus, the upper layer 366 serves as an etch mask for patterning the intermediate layer 364, and the intermediate layer 364 serves as an etch mask for patterning the bottom layer 362. After forming the photomask 360, the upper layer 366 is patterned in a lithography process to form an opening 369.

[0166] In Figure 26 , while using the upper layer 366 as an etch mask, the opening 369 in the upper layer 366 is extended into the intermediate layer 364 through an etching process to pattern the intermediate layer 364 using the patterned upper layer 366. The upper layer 366 may be consumed in the process. If the upper layer is not consumed, the upper layer 366 can be removed through a cleaning process after patterning the intermediate layer 364.

[0167] In Figure 27 , while using the intermediate layer 364 as an etch mask, the opening 369 in the intermediate layer 364 is extended into the bottom layer 362 through an etching process to pattern the bottom layer 362 using the patterned intermediate layer 364. The intermediate layer 364 may be consumed in the process. If the intermediate layer is not consumed, the intermediate layer 364 can be removed through a cleaning process after patterning the bottom layer 362.

[0168] In Figure 28In [description], while using the underlying layer 362 as an etch mask, the opening 369 is extended into the dielectric material layer 340 through an etching process to pattern the dielectric material layer 340 using the underlying layer 362. A dry etching process (plasma etching) can be used to etch the dielectric material layer 340. If dry etching is used, exemplary etchants for etching the dielectric material layer 340 can include fluorine-reactive gases such as carbon-fluorine-based etchants (C x F y ), NF3, etc. Other process gases can be used in combination with the carbon-fluorine-based etchant, such as oxygen (O2), nitrogen (N2), argon (Ar), combinations thereof, etc. The ESL 330 can be used as an etch stop layer.

[0169] In Figure 29 [description], after etching the dielectric material layer 340, the underlying layer 362 is not removed, but is kept in place to etch the ESL 330. The underlying layer 362 provides protection for the dielectric material layer 340, thereby avoiding processes for restoring or planarizing the dielectric material layer 340. In addition, in some embodiments where the conductive element 350 is formed in the dielectric material layer 340, the conductive element 350 can be protected by the underlying layer 362 during the etching of the ESL 330.

[0170] The ESL 330 is etched through a wet etching process to break through the ESL 330. If the underlying layer 362 is removed, the wet etching process may damage the dielectric material layer 340. Deionized water (DI), DI mixed with carbon dioxide (CO2), DI mixed with ozone (O3), DI mixed with hydrogen peroxide (H2O2) (where the ratio of DI to H2O2 is between 5:1 and 30:1), DI mixed with ammonia (NH4OH) (where the ratio of DI to NH4OH is between 5:1 and 2000:1), and Standard Clean 1 (SC1) can be used to etch the ESL 330. The SC1 solution can contain NH4OH, H2O2, and H2O (where the ratio of NH4OH, H2O2, and H2O is between 1:1:5 and 1:1:400). At a process temperature between about 20°C and about 65°C, the etching can take 30 seconds to 300 seconds. After etching, isopropyl alcohol and / or acetone can be used to rinse and dry the opening 369.

[0171] In Figure 30In [the structure], the underlying layer 362 can be removed by any suitable technique, such as by an ashing process using a remote plasma including nitrogen, hydrogen, or oxygen. The opening 369 is filled with a liner layer 372 (such as a diffusion barrier layer, an adhesion layer, etc.) and a conductive material 374. The liner layer 372 can include titanium, titanium nitride, tantalum, tantalum nitride, etc. formed by ALD, CVD, etc. The conductive material 374 can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, titanium, tantalum, their alloys, their combinations, etc., however, other suitable metals can be used in the present disclosure.

[0172] In Figure 31 [the structure], a planarization process, such as CMP, can be performed to remove the excess material from the surface of the dielectric material layer 340 and to make the upper surface of the dielectric material layer 340 flush with the upper surfaces of the liner layer 372 and the conductive material 374, thereby forming a conductive element 370. The conductive element 370 can be a conductive plug, a metal wire, a metal via, a metal wire with a metal via below it, etc.

[0173] When patterning the etch stop layer located below the dielectric layer, embodiments of the present disclosure beneficially use the underlying layer of the photoresist mask to protect the dielectric layer and the conductive elements embedded in the dielectric layer, rather than removing the underlying layer first. The underlying layer can also be used to etch another dielectric layer below the etch stop layer, where etching the next dielectric layer exposes contacts, such as gate contacts. The underlying layer can be used to protect the conductive elements embedded in the dielectric layer from being damaged by the wet etchant used to etch the etch stop layer.

[0174] According to some embodiments, the present disclosure provides a method of forming a semiconductor device, including: patterning a photoresist layer above a dielectric layer; etching the dielectric layer based on the pattern of the photoresist layer to form an opening in the dielectric layer, the etching stopping at an etch stop layer below the dielectric layer; etching the etch stop layer to penetrate the etch stop layer when the photoresist layer is on the dielectric layer; and forming a conductive element in the opening in the dielectric layer, the conductive element being electrically coupled to a first metal component below the etch stop layer.

[0175] In some embodiments, the dielectric layer includes a second metal component formed therein, where the photoresist layer covers the upper surface of the second metal component during the etching of the dielectric layer.

[0176] In some embodiments, the etch stop layer includes aluminum oxide.

[0177] In some embodiments, a dry etching process is used to etch the dielectric layer; and a wet etching process is used to etch the etch stop layer.

[0178] In some embodiments, the first metal component includes a gate electrode of a transistor.

[0179] In some embodiments, the conductive element includes a conductive plug to a gate electrode.

[0180] In some embodiments, it further includes: after etching the etch stop layer, etching the second dielectric layer to expose the first metal component.

[0181] In some embodiments, the second dielectric layer is etched using a dry etching process.

[0182] According to some embodiments of the present disclosure, a method of forming a semiconductor device is provided, including: forming a mask on a first dielectric layer; forming a first opening in the mask, the first opening exposing a portion of the first dielectric layer; using the mask as an etch mask to etch the first dielectric layer to form a second opening in the first dielectric layer, the second opening exposing the etch stop layer; using the mask as an etch mask to etch the etch stop layer to form a third opening in the etch stop layer, the third opening exposing the second dielectric layer; using the mask as an etch mask to etch the second dielectric layer to form a fourth opening in the second dielectric layer, the fourth opening exposing the conductive element; and forming a first metal component in the first dielectric layer, the first metal component being electrically coupled to the conductive element.

[0183] In some embodiments, etching the first dielectric layer includes dry etching, wherein etching the etch stop layer includes wet etching, and wherein etching the second dielectric layer includes dry etching.

[0184] In some embodiments, the conductive element is the gate electrode of a transistor.

[0185] In some embodiments, the first dielectric layer includes a dielectric material surrounding a second metal component, wherein the bottom surface of the mask contacts the upper surface of the second metal component.

[0186] In some embodiments, the second metal component is electrically coupled to the source / drain of the transistor.

[0187] In some embodiments, the etch stop layer includes a metal oxide.

[0188] According to some embodiments of the present disclosure, a method of forming a semiconductor device is provided, including: forming a first metal component in a first dielectric layer, the first metal component being electrically coupled to a source / drain contact of a transistor; depositing and patterning a mask layer on the first dielectric layer; patterning the first dielectric layer according to the pattern of the mask layer; when the mask layer is on the first dielectric layer, patterning the etch stop layer below the first dielectric layer according to the pattern of the mask layer; when the mask layer is on the first dielectric layer, patterning the second dielectric layer according to the pattern of the mask layer to expose the gate electrode of the transistor; and forming a conductive plug through the first dielectric layer and through the second dielectric layer, the conductive plug contacting the gate electrode.

[0189] In some embodiments, a dry etching process is used to pattern the first dielectric layer and to pattern the second dielectric layer.

[0190] In some embodiments, a wet etching process is used to pattern the etch stop layer.

[0191] In some embodiments, it further includes: after patterning the etch stop layer, applying isopropyl alcohol or acetone to the exposed portion of the second dielectric layer.

[0192] In some embodiments, the etch stop layer includes aluminum oxide.

[0193] In some embodiments, it further includes: before forming the first metal component, forming a second conductive plug to the source / drain contact; and planarizing the second conductive plug so that the upper surface of the second conductive plug is flush with the upper surface of the gate mask above the gate electrode.

[0194] The above outlines the components of several embodiments so that those skilled in the art to which the present invention pertains can better understand the viewpoints of the embodiments of the present invention. Those skilled in the art to which the present invention pertains should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and / or advantages as those introduced in the embodiments herein. Those skilled in the art to which the present invention pertains should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the appended claims.

Claims

1. A method of forming a semiconductor device, comprising: Patterning a photoresist layer over a dielectric layer, the dielectric layer including a first metal component formed therein; Etching the dielectric layer based on a pattern of the photoresist layer to form an opening in the dielectric layer, the etching stopping at an etch stop layer below the dielectric layer; When the photoresist layer is over the dielectric layer and over the first metal component, etching the etch stop layer to penetrate the etch stop layer; And Forming a conductive element in the opening in the dielectric layer, the conductive element being electrically coupled to a second metal component below the etch stop layer.

2. The method of forming a semiconductor device according to claim 1, wherein the etch stop layer comprises aluminum oxide.

3. The method of forming a semiconductor device according to claim 1, wherein: Etching the dielectric layer using a dry etching process; and Etching the etch stop layer using a wet etching process.

4. The method of forming a semiconductor device according to claim 1, wherein the second metal component comprises a gate electrode of a transistor.

5. The method of forming a semiconductor device according to claim 1, wherein the conductive element comprises a conductive plug to a gate electrode.

6. The method of forming a semiconductor device according to claim 1, further comprising: After etching the etch stop layer, etching a second dielectric layer to expose the second metal component.

7. The method of forming a semiconductor device according to claim 6, wherein etching the second dielectric layer uses a dry etching process.

8. A method of forming a semiconductor device, comprising: Forming a mask over a first dielectric layer and over a first metal component, the first dielectric layer surrounding the first metal component; Forming a first opening in the mask, the first opening exposing a portion of the first dielectric layer; Using the mask as an etch mask to etch the first dielectric layer to form a second opening in the first dielectric layer, the second opening exposing an etch stop layer; Using the mask as an etch mask to etch the etch stop layer to form a third opening in the etch stop layer, the third opening exposing a second dielectric layer; Using the mask as an etch mask to etch the second dielectric layer to form a fourth opening in the second dielectric layer, the fourth opening exposing a conductive element; And Forming a second metal component in the first dielectric layer, the second metal component being electrically coupled to the conductive element.

9. The method of forming a semiconductor device according to claim 8, wherein etching the first dielectric layer includes a dry etching, wherein etching the etch stop layer includes a wet etching, and wherein etching the second dielectric layer includes a dry etching.

10. The method of forming a semiconductor device according to claim 8, wherein the conductive element is a gate electrode of a transistor.

11. The method of forming a semiconductor device according to claim 8, wherein the first metal component is electrically coupled to a source / drain of a transistor.

12. The method of forming a semiconductor device according to claim 8, wherein the etch stop layer comprises a metal oxide.

13. A method of forming a semiconductor device, comprising: forming a first metal component in a first dielectric layer, the first metal component being electrically coupled to a source / drain contact of a transistor; depositing and patterning a mask layer on the first dielectric layer; patterning the first dielectric layer according to a pattern of the mask layer; when the mask layer is on the first dielectric layer, patterning an etch stop layer under the first dielectric layer according to the pattern of the mask layer; when the mask layer is on the first dielectric layer, patterning a second dielectric layer according to the pattern of the mask layer to expose a gate electrode of the transistor; forming a conductive plug through the first dielectric layer and through the second dielectric layer, the conductive plug contacting the gate electrode; forming a second conductive plug to the source / drain contact before forming the first metal component; and planarizing the second conductive plug so that an upper surface of the second conductive plug is flush with an upper surface of a gate mask above the gate electrode.

14. The method of forming a semiconductor device according to claim 13, wherein a dry etching process is used to pattern the first dielectric layer and the second dielectric layer.

15. The method of forming a semiconductor device according to claim 13, wherein a wet etching process is used to pattern the etch stop layer.

16. The method of forming a semiconductor device according to claim 13, further comprising: after patterning the etch stop layer, applying isopropyl alcohol or acetone to an exposed portion of the second dielectric layer.

17. The method of forming a semiconductor device according to claim 13, wherein the etch stop layer comprises alumina.

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