Semiconductor Structure and Method for Forming the Same

Abstract

The present invention is directed to a method for fabricating a MiM capacitor structure having metal electrodes with a nitrogen-rich metal nitride layer. The method includes depositing a first electrode bilayer on a first interconnect layer disposed on a substrate, wherein the first electrode bilayer includes a first layer and a second layer having different nitrogen concentrations. The method further includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect layer, wherein the second electrode includes a third layer and a fourth layer having different nitrogen concentrations. The method also includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer. Embodiments of the present invention also relate to semiconductor structures and methods of forming the same.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods of forming the same. Background Art

[0002] Decoupling capacitors can be built into a chip to prevent voltage spikes in the power supply, such as when initially powering on the chip or activating various components of the chip. In a chip manufacturing process, decoupling capacitors can be integrated in the back-end-of-line process after transistor formation. Summary of the Invention

[0003] Embodiments of the present invention provide a semiconductor structure, comprising: a first interconnect layer disposed on a substrate, wherein the first interconnect layer comprises a conductive structure; a capacitor structure formed on the conductive structure of the first interconnect layer, wherein the capacitor structure comprises: a first electrode bilayer including a first layer and a second layer, each of the first layer and the second layer including a different nitrogen concentration; a dielectric layer disposed on the second layer of the first electrode bilayer; and a second electrode bilayer located on the dielectric layer, the second electrode bilayer including a third layer and a fourth layer, each of the third layer and the fourth layer including a different nitrogen concentration; and a second interconnect layer located on the capacitor structure, wherein the conductive structure of the second interconnect layer is in contact with the fourth layer of the second electrode bilayer.

[0004] Another embodiment of the present invention provides a semiconductor structure, comprising: a first interconnect layer disposed on a substrate; a capacitor structure formed on the first interconnect layer, wherein the capacitor structure comprises: a first electrode bilayer including a first layer and a second layer, each of the first layer and the second layer including a different nitrogen concentration; and a second electrode bilayer including a third layer and a fourth layer, each of the third layer and the fourth layer including a different nitrogen concentration, wherein the first electrode bilayer and the second electrode bilayer have non-overlapping regions; and a second interconnect layer located on the capacitor structure.

[0005] Yet another embodiment of the present invention provides a method of forming a semiconductor structure, comprising: forming a first interconnect layer on a substrate; depositing a first electrode bilayer on the first interconnect layer, wherein the first electrode bilayer includes a first layer and a second layer having different nitrogen concentrations; depositing a dielectric layer on the first electrode bilayer such that the dielectric layer is in contact with the second layer; depositing a second electrode bilayer on the first interconnect layer, wherein the second electrode bilayer includes a third layer and a fourth layer having different nitrogen concentrations; patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer; and forming a second interconnect layer on the capacitor structure, wherein the conductive structure of the second interconnect layer is in contact with the second electrode bilayer. Description of the Drawings

[0006] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings, it should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, for the sake of clear discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 A method for forming a metal-insulator-metal stack having a nitrogen-rich electrode layer is shown in accordance with some embodiments.

[0008] Figures 2 to 12 is a cross-sectional view of an intermediate structure during the fabrication of a metal-insulator-metal stack having a nitrogen-rich electrode layer in accordance with some embodiments. Detailed Description

[0009] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components may not be in direct contact.

[0010] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to include different orientations of the device during use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0011] In some embodiments, the terms "about" and "substantially" may indicate a value of a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. It should be understood that the terms "about" and "substantially" may refer to a percentage of the value that would be interpreted by a person of ordinary skill in the relevant art in accordance with the teachings herein.

[0012] As used herein, the term "nominal" refers to the expected or target value of a characteristic or parameter for a component or process operation, as set during the design phase of a product or process, and the range above and / or below the expected value. The range of values may be attributable to minor variations in the manufacturing process or tolerances. Unless otherwise defined, the technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

[0013] Decoupling capacitors (DeCAPs) can be built into a chip to prevent voltage spikes in the power supply, such as when initially powering the chip or activating various components of the chip. Since the power supply cannot respond instantaneously to such changes in power demand, the power supply voltage of the chip may vary briefly until the power supply can respond and stabilize the voltage. Voltage spikes may occur during this transient time. Decoupling capacitors can suppress these voltage spikes. Decoupling capacitors with higher capacitance can further suppress voltage spikes.

[0014] Decoupling capacitors integrated in the back-end-of-line (BEOL) process have several advantages, including but not limited to reduced time delay due to short interconnect lengths, reduced power consumption, compact size, and a wide capacitance range due to their flexible design. Since the integrated decoupling capacitors are formed next to semiconductor devices and interconnect layers, they can benefit from the materials and methods used in semiconductor manufacturing, such as various metals, dielectrics, lithography and etching operations, metal and dielectric deposition methods, etc.

[0015] By way of example and not limitation, a decoupling capacitor integrated in the BEOL can have the form of a parallel-plate capacitor structure (e.g., a metal-insulator-metal (MiM) stack), where a dielectric layer is disposed between a pair of metal or metal layers (also referred to herein as "electrodes"). Interconnect structures (such as metal vias) can be formed on each electrode of the MiM stack to electrically couple the capacitor structure to other elements in the integrated circuit.

[0016] The dielectric layer used in the MiM stack may include a single dielectric material or a stack of dielectric materials having a thickness between about 1 nm and about 20 nm. Due to their limited thickness, these dielectric layers may be sensitive to charges generated by semiconductor manufacturing processes using plasma. Such semiconductor manufacturing processes include processes used during or after the formation of the MiM stack. By way of example and not limitation, processes that can generate charges include etching processes (e.g., dielectric etching, metal etching, etc.) and "plasma-assisted" deposition processes (e.g., physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), etc.). The presence of charges in the dielectric layer of the MiM capacitor can affect the operation of the capacitor. For example, the charges present in the dielectric can form a conductive path for current to flow between the electrodes of the MiM capacitor, thus preventing the MiM capacitor from operating as expected. Since "charge generation" processes are essential in semiconductor manufacturing, the MiM capacitor must be immune or more tolerant to the charges generated by semiconductor manufacturing processes.

[0017] To address the above challenges, embodiments described herein are directed to a method for forming a MiM capacitor structure having metal electrodes characterized by nitrogen-rich layers. These nitrogen-rich layers are formed in contact with the dielectric layer to prevent charges (e.g., charges generated by plasma-based processes) from reaching and damaging the dielectric layer of the MiM stack. In some embodiments, the metal electrodes include a bilayer of metal nitrides having different metal-to-nitrogen ratios ("M / N ratios"). In some embodiments, the nitrogen concentration of the metal nitride layer formed in contact with the dielectric layer is higher than the nitrogen concentration of the metal nitride layer formed not in contact with the dielectric layer. In some embodiments, the metals for forming the metal nitride layers of the electrode bilayer described herein include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), nickel (Ni), ruthenium (Ru), molybdenum (Mo), gold (Au), silver (Ag), and aluminum (Al). In some embodiments, the electrodes can be deposited by a CVD process, a PVD process, an atomic layer deposition (ALD) process, or any other suitable deposition method capable of depositing a metal nitride layer having a nitrogen concentration in the range of 0 (e.g., pure metal) to about 40%.

[0018] Figure 1 is a flowchart of a manufacturing method 100 for forming a MiM capacitor having electrodes characterized by nitrogen-rich layers according to some embodiments. The present invention is not limited to this operation description. For example, other manufacturing operations may be performed between the various operations of method 100 and may be omitted for clarity and ease of description. These various operations are within the spirit and scope of the present invention. Additionally, not all operations are required to perform the disclosure provided herein. Some operations may be performed simultaneously or in an order different from Figure 1executed in a different order than shown. In some embodiments, one or more other operations may be performed in addition to or instead of the currently described operations. Reference will be made to Figures 2 to 12 describe method 100, Figures 2 to 12 which is merely exemplary and may not be drawn to scale.

[0019] In some embodiments, Figure 2 is used as Figure 1 a cross-sectional view of a partially fabricated stack 200 that is part of the “starting point” structure of the method 100 shown. The partially fabricated structure 200 (“structure 200”) may be, for example, a partial cross-sectional view of a partially fabricated integrated circuit (IC). By way of example and not limitation, structure 200 may include a substrate 210 having a front-end-of-line (FEOL) / middle-of-line (MOL) layer 220 formed thereon and an interconnect layer 230 formed on the FEOL / MOL layer 220. For ease of description, selected portions and components of structure 200 are shown in Figure 2 For example, for simplicity purposes, isolation regions, doped regions, source / drain regions, and other components, structures, or elements formed within or on substrate 210 are not shown in Figure 2 In addition, for simplicity, active devices such as transistors, conductive structures (e.g., contacts), etch stop layers, or additional layers and structures formed in the FEOL / MOL layer 220 are not shown in Figure 2 These components, structures, elements, and layers are within the spirit and scope of the present invention.

[0020] In some embodiments, variations of structure 200 are possible. For example, the FEOL / MOL layer 220 may include one or more layers. Additionally, additional interconnect layers may be formed between the FEOL / MOL layer 220 and the interconnect layer 230. These variations are within the spirit and scope of the present invention.

[0021] As Figure 2 shown, the interconnect layer 230 includes conductive structures 240 embedded in a dielectric layer 250. By way of example and not limitation, the conductive structures 240 may be vias or lines formed by a damascene metallization process or any other suitable metallization process. By way of example and not limitation, the conductive structures 240 may be filled with a conductive material 260, such as copper or a copper alloy, which is surrounded by a barrier layer not shown in Figure 2 Since Figure 2 is a partial cross-sectional view of structure 200, the interconnect layer 230 may include Figure 2 additional conductive structures, such as conductive structures 240, not shown in

[0022] By way of example and not limitation, the dielectric layer 250 can be an interlayer dielectric (ILD). For example, the dielectric layer within the interconnect layer 230 electrically isolates the conductive structures 240. In some embodiments, the dielectric layer 250 is a material having a dielectric constant value less than about 3.9 (e.g., a low-k dielectric). In some embodiments, the dielectric layer 250 can include a stack of dielectric layers such as a low-k dielectric and another dielectric: (i) a low-k dielectric (e.g., carbon-doped silicon oxide) and silicon carbide with nitrogen doping; (ii) a low-k dielectric (e.g., carbon-doped silicon oxide) and silicon carbide with oxygen doping; (iii) a low-k dielectric (e.g., carbon-doped silicon oxide) and silicon nitride; (iv) a low-k dielectric (e.g., carbon-doped silicon oxide) and silicon oxide.

[0023] By way of example and not limitation, the dielectric layer 250 having a thickness between about 100 nm and about 200 nm can be deposited by a high-density chemical vapor deposition (HDCVD) process, a plasma-enhanced chemical vapor deposition process (PECVD), a plasma-enhanced atomic layer deposition process (PEALD), or any other suitable deposition process. The foregoing deposition thickness range, deposition method, and materials are exemplary and not restrictive. Thus, alternative materials, thickness ranges, or deposition methods can be used and are within the spirit and scope of the present invention.

[0024] In addition, the interconnect layer 230 can include one or more etch stop layers, such as the etch stop layer 270, to facilitate the formation of the conductive structures 240. For example, the etch stop layer 270 is between the dielectric layer 250 and the FEOL / MOL layer 220. In some embodiments, the interconnect layer 230 is a BEOL metallization layer that is electrically coupled to the conductive structures in the FEOL / MOL layer 220. For simplicity, Figure 2 the conductive structures of the FEOL / MOL layer 220 are not shown.

[0025] Referring Figure 1 , method 100 begins at operation 110 and at a first interconnect layer (e.g., Figure 2Process of forming a first electrode bilayer on the interconnect layer 230 shown. In some embodiments, bilayer deposition includes sequentially depositing a first metal nitride layer ("MN1") having a first metal-to-nitrogen ratio ("M / N1 ratio"), followed by a second metal nitride layer ("MN2") having a second metal-to-nitrogen ratio ("M / N2 ratio"), such that M / N1 is greater than M / N2 (e.g., M / N1 > M / N2). In some embodiments, MN1 is metal-rich compared to MN2 (e.g., MN1 contains a lower nitrogen concentration than MN2), while MN2 is nitrogen-rich compared to MN1 (e.g., MN2 contains a higher nitrogen concentration than MN1). In some embodiments, the metal M in MN1 and MN2 is common and can be selected from Ti, Ta, W, Co, Ni, Ru, Mo, Au, Ag, or Al. For example, MN1 can be TiN1 and MN2 can be TiN2, or MN1 can be TaN1 and MN2 can be TaN2, etc.

[0026] According to some embodiments, MN1 and MN2 can be deposited blanket on the interconnect layer 230. By way of example and not limitation, Figure 3 The structure 200 after operation 110 of method 100 is shown, where a first electrode bilayer 300 is deposited on the interconnect layer 230. As discussed above, the first electrode bilayer 300 includes MN1 310 and MN2 320, and MN2 320 is nitrogen-rich compared to MN1 310. In some embodiments, MN1 and MN2 are deposited by a PVD-based method, a CVD-based method, an ALD-based method, or another deposition method capable of adjusting the nitrogen concentration of MN1 310 and MN2 320 during deposition. By way of example and not limitation, in a PVD-based process, the nitrogen concentration can be adjusted by adjusting the nitrogen gas flow during metal sputtering; in a CVD-based process or an ALD-based process, the ammonia gas flow can be adjusted to incorporate a desired amount of nitrogen into the deposited layer. In some embodiments, the metal-to-nitrogen ratio M / N1 can range from about 0.5 to pure metal, without a large amount of nitrogen (e.g., 0 ≤ (M / N1) -1 ≤ 2), and the metal-to-nitrogen ratio M / N2 can range from about 0.4 to about 0.9 (e.g., 0.1 ≤ (M / N2) -1 ≤ 2.5). In some embodiments, the average nitrogen concentration and the nitrogen peak concentration in MN2 are greater than the corresponding average nitrogen concentration and nitrogen peak concentration in MN1. In some embodiments, the nitrogen peak concentration in MN2 320 is about 40%.

[0027] In some embodiments, MN1 310 is deposited with a thickness between about 10 nm and about 100 nm, and MN2 320 is deposited with a thickness between about 1 nm and about 20 nm, such that MN1 310 is thicker than MN2 320. For example, if MN1 310 is about 10 nm, then MN2 320 is deposited to a thickness less than about 10 nm (e.g., about 5 nm), such that MN2 is thinner than MN1.

[0028] Reference Figure 1 , method 100 proceeds to operation 120 and the process of depositing a dielectric layer on the first electrode bilayer 300. In some embodiments, the dielectric layer is deposited directly on MN2 320, e.g., there is no intermediate layer. By way of example and not limitation, Figure 4 Structure 200 after depositing dielectric layer 400 according to operation 120 is shown. In some embodiments, dielectric layer 400 includes silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), yttrium oxide (Y2O3), titanium oxide (TiO2), hafnium oxide (HfO2), or zirconium oxide (ZrO2); a stack of ZrO2 / Al2O3 / ZrO2; a stack of Al2O3 / ZrO2 / Al2O3; a stack of ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2; or a stack comprising any combination of SiO2, Si3N4, Al2O3, Y2O3, TiO2, HfO2, and ZrO2. In some embodiments, dielectric layer 400 is conformally deposited on MN2 320 with a thickness range between about 1 nm and about 20 nm by an ALD-based process, a CVD-based process, or a PVD-based process. In some embodiments, dielectric layers thinner than about 1 nm are more prone to leakage and should be avoided, while thicker dielectric layers (e.g., thicker than 20 nm) reduce the capacitance of the resulting MiM capacitor and are thus undesirable.

[0029] Reference Figure 1, Operation 100 continues with operation 130 and the process of forming a second electrode bilayer on dielectric layer 400. In some embodiments, the bilayer deposition includes sequential deposition of a third metal nitride layer (“MN3”) having a ratio of a third metal to N (“M / N3”), followed by a fourth metal nitride layer (“MN4”) having a ratio of a fourth metal to N (“M / N4”), such that M / N3 is greater than M / N4. In some embodiments, MN4 is metal-rich compared to MN3, and MN3 is nitrogen-rich compared to MN4. In some embodiments, the metal M in MN3 and MN4 is common and can be selected from Ti, Ta, W, Co, Ni, Ru, Mo, Au, Ag, or Al. By way of example and not limitation, the metals in MN1, MN2, MN3, and MN4 can be the same, or the metals within each electrode can be the same but different between electrodes. For example, the metal in MN1 and MN2 can be Ti, and the metal in MN3 and MN4 can be Ta.

[0030] According to some embodiments, MN3 and MN4 (such as MN1 and MN2) can be deposited blanketly on dielectric layer 400. By way of example and not limitation, Figure 5 Structure 200 after operation 130 of method 100 is shown, where a second electrode bilayer 500 is deposited on dielectric layer 400. As discussed above, the second electrode bilayer 500 includes MN3 510 and MN4 520, and MN3 510 is nitrogen-rich compared to MN4 520. MN3 and MN4, such as MN1 and MN2, are deposited by a PVD-based process, a CVD-based process, an ALD-based process, or another deposition process capable of adjusting the nitrogen concentration of MN3 510 and MN4 520 during deposition. By way of example and not limitation, in a PVD-based process, the nitrogen concentration can be adjusted by adjusting the nitrogen gas flow during metal sputtering. In a CVD-based process or an ALD-based process, the ammonia gas flow can be adjusted to incorporate a desired amount of nitrogen into the deposited layer. In some embodiments, the ratio of metal to nitrogen M / N3 can be in the range of about 0.4 to about 0.9 (e.g., 1.1 ≤ (M / N3) -1 ≤ 2.5), and the ratio of metal to nitrogen M / N4 can be in the range of 0.5 to pure metal, with substantially no nitrogen concentration (e.g., 0 ≤ (M / N4) -1 ≤ 2). In some embodiments, the average nitrogen and nitrogen peak concentration in MN3 are greater than the average nitrogen and nitrogen peak concentration in MN4. In some embodiments, the nitrogen peak concentration in MN3 510 can be about 40%, as in MN2 320.

[0031] In some embodiments, MN3 510 is deposited in a thickness range of from about 1 nm to about 20 nm, and MN4 520 is deposited in a thickness range of from about 10 nm to about 100 nm. In some embodiments, the deposited MN3 510 is thinner than MN4 520. For example, if MN4 520 is about 10 nm, then MN3 510 is deposited to a thickness less than about 10 nm (e.g., about 5 nm).

[0032] By way of example and not limitation, MN3 510 and MN2 320 may have substantially similar metal-to-nitrogen ratios, e.g., M / N3 may be substantially equal to M / N2. Additionally, MN4 520 and MN1 310 may have substantially similar metal-to-nitrogen ratios, e.g., M / N4 may be substantially equal to M / N1. In some embodiments, between MN2 320 and MN3 510 and between MN1 310 and MN4 520, the foregoing metal-to-nitrogen ratios may be different. For example, the metal-to-nitrogen ratio M / N3 may be greater than the metal-to-nitrogen ratio M / N2 (e.g., MN3 may have a lower nitrogen concentration than MN2) or vice versa depending on the plasma treatment to which MN2 320 and MN3 510 are exposed. For example, if in a subsequent operation after forming the MiM layer, MN2 320 is subjected to additional plasma treatment compared to MN3 510, then MN2 320 may be deposited to have a higher nitrogen concentration than MN3 510. This is possible because the nitrogen concentration in each layer of the first electrode bilayer 300 and the second electrode bilayer 500 can be independently adjusted during the deposition process.

[0033] In some embodiments, as the nitrogen concentration in the metal nitride layer increases, the ability of the metal nitride layer to block charges generated by the plasma process is greatly improved. At the same time, increasing the nitrogen concentration in the metal nitride layer also increases its resistance, which is undesirable. Therefore, the nitrogen-rich metal layer needs to be very thin to minimize the effect on resistance, but not too thin to provide sufficient protection against charges. Thus, in the metal nitride layer, it is necessary to balance the nitrogen concentration and thickness of the nitrogen-rich metal layer to provide optimal charge protection and electrical performance.

[0034] To address the above resistance issue, MN1 310 and MN4 520 (e.g., the "outer" layers of the MiM capacitor structure) are formed thicker and with a lower nitrogen concentration compared to MN2 320 and MN3 510 (e.g., the "inner" layers of the MiM capacitor structure) to reduce the total resistance of the first electrode bilayer and the second electrode bilayer. Correspondingly, MN2 320 and MN3 510 are formed thinner and with a higher nitrogen concentration compared to MN1 310 and MN4 520 to minimize their effect on resistance and provide sufficient charge protection for the dielectric layer 400.

[0035] In some embodiments, nitrogen-rich nitride layers thinner than about 1 nm (e.g., such as MN2 320 and MN3 510) provide insufficient charge protection for dielectric layer 400. Nitrogen-rich layers thicker than about 20 nm unnecessarily increase the resistance of the first and second electrode bilayers. Additionally, metal-rich metal nitride layers thinner than about 10 nm (e.g., such as MN1 310 and MN4 520) provide insufficient resistance reduction. Metal-rich metal nitride layers thicker than about 100 nm unnecessarily increase the height of the MiM capacitor structure without providing any additional benefit.

[0036] Furthermore, nitrogen-rich layers with a metal-to-nitrogen ratio below about 0.4 (e.g., MN2 320 and MN3 510) may provide insufficient charge protection. Nitrogen-rich layers with a metal-to-nitrogen ratio greater than about 0.9 may have a high resistivity. Similarly, as discussed above, metal-rich layers with a metal-to-nitrogen ratio below about 0.5 (e.g., MN1 310 and MN4 520) may provide insufficient resistance reduction.

[0037] Reference Figure 1 , operation 100 continues with operation 140 and the process of patterning the first electrode bilayer 300, dielectric layer 400, and second electrode bilayer 500 to form the MiM capacitor structure. In some embodiments, patterning the first electrode bilayer 300, dielectric layer 400, and second electrode bilayer 500 includes depositing an optional capping layer (e.g., a silicon oxynitride (SiON) layer) with a thickness between about 200 angstroms and about 500 angstroms on the second electrode bilayer 500 by a CVD process at a deposition temperature between about 300 °C and about 500 °C before patterning the stack. Patterning can be achieved, for example, by a combination of lithography and etching operations, where a photoresist is deposited on the capping layer and patterned. The patterned photoresist serves as an etch mask to protect areas of the stack from etching. Areas of the stack not covered by the patterned photoresist will be removed. Subsequently, an etching process removes the capping layer, first electrode bilayer 300, dielectric layer 400, and second electrode bilayer 500 not covered by the patterned photoresist. The resulting patterned structure is shown in Figure 6 where a patterned stack having a capping layer 600, second electrode bilayer 500, dielectric layer 400, and first electrode bilayer 300 is formed on the conductive structure 240. According to some embodiments, the second electrode bilayer 500, dielectric layer 400, and first electrode bilayer 300 together form the MiM capacitor structure 610.

[0038] In some embodiments, and with reference to Figure 7, an optional stack 700 including an oxide layer 710 and a silicon nitride layer 720 is formed on the MiM capacitor structure 610. In some embodiments, the optional stack 700 seals the MiM capacitor structure 610. By way of example and not limitation, the oxide layer 710 and the silicon nitride layer 720 may be deposited blanket-wise with thicknesses of about 20 nm and 75 nm, respectively, and then the oxide layer 710 and the silicon nitride layer 720 are patterned using lithography and etching operations. In some embodiments, the silicon nitride layer 710 is an etch stop layer for facilitating the formation of an electrical connection on the second electrode bilayer 500.

[0039] Reference Figure 1 , operation 100 proceeds to operation 150 and the process of forming electrical connections to the first electrode bilayer 300 and the second electrode bilayer 500. In Figure 7 the example, the conductive structure 240 serves as the electrical connection to the first electrode bilayer 300. By way of example and not limitation, an electrical connection to the second electrode bilayer 500 can be formed by depositing an oxide layer over the MiM capacitor structure 610 and forming a conductive structure through the deposited oxide layer, the optional stack 700, and the capping layer 600 to contact MN4520 in the second electrode bilayer 500. In some embodiments, Figure 8 FIG. shows a resulting structure in which a conductive structure 800 is formed in a dielectric stack 810 that includes dielectric layers 820 and 830 separated by an etch stop layer 840. In some embodiments, the conductive structure 800 is similar to the conductive structure 240 of the interconnect layer 230, the dielectric layers 820 and 830 are similar to the dielectric layer 250, and the etch stop layer 840 is similar to the etch stop layer 270. In some embodiments, the dielectric stack 810 and the conductive structure 800 are part of another interconnect layer formed on the interconnect layer 230.

[0040] In Figure 8 the example, the first electrode bilayer 300 has a surface area that is substantially equal to that of the second electrode bilayer 500. Additionally, in the MiM configuration shown in Figure 8 , a pre-existing conductive structure (e.g., the conductive structure 240) is used to form an electrical contact to one of the electrode bilayers in the MiM capacitor structure 610. However, this is not limiting, and the patterning process described in operation 140 of method 100 can be performed differently to form a MiM capacitor structure having electrodes with different surface areas (e.g., a surface area difference greater than about 5%). For example, instead of patterning the first electrode bilayer 300, the dielectric layer 400, and the second electrode bilayer 500 to form the MiM capacitor structure 610 on the conductive structure 240 as shown in Figure 6 , the patterning process can optionally form a MiM capacitor structure 900 on a dielectric stack 930 above the dielectric layer 250, as shown in Figure 9As shown. Subsequently, as Figure 10 shown, a second patterning process may pattern the overlying layer 600 and the second electrode bilayer 500 to selectively reduce the size (e.g., surface area) of the second electrode bilayer 500 relative to the first electrode bilayer 300. As Figure 11 shown, an optional stack 700 may subsequently be deposited over the MiM capacitor structure 900 and the stack 700 patterned. As Figure 12 shown, in a subsequent operation, conductive structures 1200 and 1210 may be formed in the dielectric stack 810 to contact the second electrode bilayer 500 and the first electrode bilayer 300, respectively. In some embodiments, Figures 9 to 12 the dielectric stack 930 described includes a bottom silicon carbide layer and a silicon oxide top layer, such as undoped silicate glass (USG) and plasma enhanced oxide (PEOX).

[0041] By way of example and not limitation, the MiM capacitor structures 610 and 900 shown in Figure 8 and Figure 12 respectively may be substantially similar to each other in terms of layer thickness, material, and ratio of metal to nitrogen. In some embodiments, both types of MiM capacitor structures 610 and 900 may be formed in the same integrated circuit. Even though the MiM capacitor structure 900 may require additional patterning operations compared to the MiM capacitor structure 610 shown in Figure 8 , the MiM capacitor structure 900 may be formed over the dielectric layer without an underlying conductive structure. The MiM capacitor structures 600 and 900 shown in Figure 8 and Figure 12 respectively are not limiting. Thus, Figure 8 and Figure 12 variations and combinations of the layouts shown are within the spirit and scope of the present invention.

[0042] As described herein, for the charge generated during the formation of the conductive structure 800 shown in Figure 8 or during the patterning process described above with respect to operation 140 of method 100 for the conductive structures 1220 and 1210 shown in Figure 12 , a nitrogen-rich layer MN2 320 and MN3 510 are formed at the interface with the dielectric layer 400 to provide sufficient protection for the dielectric layer 400. In the absence of the nitrogen-rich layers MN2 320 and MN3 510, the charge from the above processes would affect the performance of the MiM capacitor structure.

[0043] The present invention relates to a method for fabricating a MiM capacitor structure having metal electrodes with nitrogen-rich metal nitride layers that contact a dielectric layer of the MiM capacitor structure. These nitrogen-rich metal nitride layers effectively protect the dielectric layer from charges generated during subsequent operations, including plasma processing. In some embodiments, each metal electrode includes a stack of metal nitride bilayers, each bilayer having a metal-rich layer and a nitrogen-rich layer. In some embodiments, the nitrogen-rich layer is formed to contact the dielectric layer and has a metal-to-nitrogen ratio between about 0.4 and about 0.9. In some embodiments, the metal-to-nitrogen ratio of the metal-rich layer is from about 0.5 to pure metal. In some embodiments, the metals used for the metal nitride layers include Ti, Ta, W, Co, Ni, Ru, Mo, Au, Ag, and Al. According to some embodiments, the nitrogen-rich metal nitride layer is formed thinner than its metal-rich counterpart to reduce the resistance of the metal electrode.

[0044] In some embodiments, a structure includes a first interconnect layer having a conductive structure disposed on a substrate. The structure further includes a capacitor structure formed on the conductive structure of the first interconnect layer, wherein the capacitor structure includes a first electrode bilayer having a first layer and a second layer, wherein each of the first layer and the second layer includes a different nitrogen concentration. The capacitor structure further includes a dielectric layer disposed on the second layer of the first electrode bilayer and a second electrode bilayer located on the dielectric layer. The second electrode bilayer includes a third layer and a fourth layer, wherein each of the third layer and the fourth layer has a different nitrogen concentration. The structure further includes a second interconnect layer located on the capacitor structure, wherein the conductive structure of the second interconnect layer contacts the fourth layer of the second electrode bilayer.

[0045] In the above structure, wherein the third layer of the second electrode bilayer contacts the dielectric layer.

[0046] In the above structure, wherein the nitrogen concentration of the first layer is lower than that of the second layer.

[0047] In the above structure, wherein the nitrogen concentration of the fourth layer is lower than that of the third layer.

[0048] In the above structure, wherein the first layer is thicker than the second layer.

[0049] In the above structure, wherein the fourth layer is thicker than the third layer.

[0050] In the above structure, wherein the first electrode bilayer and the second electrode bilayer have similar surface areas.

[0051] In the above structure, further comprising: a cover layer disposed on the top surface of the fourth layer; and a stack covering the top surface of the cover layer and the sidewall surfaces of the capacitor structure.

[0052] In some embodiments, a structure includes a first interconnect layer disposed on a substrate and a capacitor structure formed on the first interconnect layer. The capacitor structure includes a first electrode bilayer having a first layer and a second layer, where each of the first layer and the second layer includes a different nitrogen concentration. The capacitor structure further includes a second electrode bilayer having a third layer and a fourth layer with different nitrogen concentrations. Additionally, the first electrode bilayer and the second electrode bilayer have non-overlapping regions. The structure further includes a second interconnect layer located on the capacitor structure.

[0053] In the above structure, the ratio of metal to nitrogen in the first layer is greater than the ratio of metal to nitrogen in the second layer.

[0054] In the above structure, the ratio of metal to nitrogen in the fourth layer is greater than the ratio of metal to nitrogen in the second layer.

[0055] In the above structure, each of the first layer, the second layer, the third layer, and the fourth layer includes titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), nickel (Ni), ruthenium (Ru), molybdenum (Mo), gold (Au), silver (Ag), aluminum (Al), or a metal nitride.

[0056] In the above structure, each of the first layer, the second layer, the third layer, and the fourth layer includes titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), nickel (Ni), ruthenium (Ru), molybdenum (Mo), gold (Au), silver (Ag), aluminum (Al), or a metal nitride, where a first conductive structure of the second interconnect layer contacts the fourth layer of the second electrode bilayer, and a second conductive structure of the second interconnect layer contacts the first layer and the second layer of the first electrode bilayer in the non-overlapping region.

[0057] In the above structure, the capacitor structure further includes a dielectric layer between the second layer of the first electrode bilayer and the third layer of the second electrode bilayer, and the dielectric layer includes silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), yttrium oxide (Y2O3), titanium oxide (TiO2), hafnium oxide (HfO2), zirconium oxide (ZrO2), or a combination thereof.

[0058] In the above structure, the capacitor structure is formed on a dielectric region of the first interconnect layer.

[0059] In some embodiments, a method includes forming a first interconnect layer on a substrate; depositing a first electrode bilayer on the first interconnect layer, wherein the first electrode bilayer includes a first layer and a second layer having different nitrogen concentrations. The method further includes depositing a dielectric layer on the first electrode bilayer such that the dielectric layer contacts the second layer; and further depositing a second electrode bilayer on the first interconnect layer, wherein the second electrode bilayer includes a third layer and a fourth layer having different nitrogen concentrations. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer, and forming a second interconnect layer on the capacitor structure, wherein the conductive structure of the second interconnect layer contacts the second electrode bilayer.

[0060] In the above method, depositing the first electrode bilayer includes depositing the first layer having a lower nitrogen concentration than the second layer, and wherein each of the first layer and the second layer includes titanium nitride.

[0061] In the above method, depositing the second electrode bilayer includes depositing the fourth layer having a lower nitrogen concentration than the third layer, and wherein each of the third and fourth layers includes titanium nitride.

[0062] In the above method, depositing the first electrode bilayer includes depositing the first layer thicker than the second layer.

[0063] In the above method, depositing the second electrode bilayer includes depositing the third layer thinner than the fourth layer.

[0064] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, comprising: A first interconnect layer is disposed on a substrate, wherein the first interconnect layer includes a conductive structure; A capacitor structure is formed on the conductive structure of the first interconnect layer, wherein the capacitor structure includes: A first electrode bilayer including a first layer and a second layer, each of the first layer and the second layer including a different nitrogen concentration; A dielectric layer is disposed on the second layer of the first electrode bilayer; and A second electrode bilayer is located on the dielectric layer, the second electrode bilayer including a third layer and a fourth layer, each of the third layer and the fourth layer including a different nitrogen concentration; and A second interconnect layer is located on the capacitor structure, wherein the conductive structure of the second interconnect layer is in contact with the fourth layer of the second electrode bilayer; A capping layer is disposed on the top surface of the fourth layer; A stack covers the top surface of the capping layer and the sidewall surfaces of the capacitor structure; Wherein, the sidewall surface of the capping layer is in contact with the stack and is coplanar with the sidewall surfaces of the second electrode bilayer.

2. The semiconductor structure according to claim 1, wherein, The third layer of the second electrode bilayer is in contact with the dielectric layer.

3. The semiconductor structure according to claim 1, wherein, The nitrogen concentration of the first layer is lower than that of the second layer.

4. The semiconductor structure according to claim 1, wherein, The nitrogen concentration of the fourth layer is lower than that of the third layer.

5. The semiconductor structure according to claim 1, wherein, The first layer is thicker than the second layer.

6. The semiconductor structure according to claim 1, wherein, The fourth layer is thicker than the third layer.

7. The semiconductor structure according to claim 1, wherein, The first electrode bilayer and the second electrode bilayer have similar surface areas.

8. The semiconductor structure according to claim 1, wherein, The metal-to-nitrogen ratio of the first layer is greater than that of the second layer, and the metal-to-nitrogen ratio of the fourth layer is greater than that of the second layer.

9. A semiconductor structure, comprising: A first interconnect layer is disposed on a substrate; A capacitor structure is formed on the first interconnect layer, wherein the capacitor structure includes: A first electrode bilayer including a first layer and a second layer, each of the first layer and the second layer including a different nitrogen concentration; and A second electrode bilayer including a third layer and a fourth layer, each of the third layer and the fourth layer including a different nitrogen concentration, wherein the first electrode bilayer and the second electrode bilayer have non-overlapping regions; and A second interconnect layer is located on the capacitor structure; A capping layer is disposed on the top surface of the fourth layer; A stack covers the top surface of the capping layer and the sidewall surfaces of the capacitor structure; Wherein, the sidewall surface of the capping layer is in contact with the stack and is coplanar with the sidewall surfaces of the second electrode bilayer.

10. The semiconductor structure according to claim 9, wherein, The metal-to-nitrogen ratio of the first layer is greater than that of the second layer.

11. The semiconductor structure according to claim 9, wherein, The metal-to-nitrogen ratio of the fourth layer is greater than that of the second layer.

12. The semiconductor structure according to claim 9, wherein, Each of the first layer, the second layer, the third layer, and the fourth layer includes titanium, tantalum, tungsten, cobalt, nickel, ruthenium, molybdenum, gold, silver, aluminum, or a metal nitride.

13. The semiconductor structure according to claim 12, wherein,The first conductive structure of the second interconnect layer is in contact with the fourth layer of the second electrode bilayer, and the second conductive structure of the second interconnect layer is in contact with the first layer and the second layer of the first electrode bilayer in the non-overlapping region.

14. The semiconductor structure according to claim 9, wherein, The capacitor structure further includes a dielectric layer between the second layer of the first electrode bilayer and the third layer of the second electrode bilayer, and wherein the dielectric layer includes silicon oxide, silicon nitride, aluminum oxide, yttrium oxide, titanium oxide, hafnium oxide, zirconium oxide, or a combination thereof.

15. The semiconductor structure according to claim 9, wherein, The capacitor structure is formed on a dielectric region of the first interconnect layer.

16. A method of forming a semiconductor structure, comprising: A first interconnect layer is formed on a substrate. A first electrode bilayer is deposited on the first interconnect layer, wherein the first electrode bilayer includes a first layer and a second layer having different nitrogen concentrations. A dielectric layer is deposited on the first electrode bilayer such that the dielectric layer contacts the second layer. A second electrode bilayer is deposited on the first interconnect layer, wherein the second electrode bilayer includes a third layer and a fourth layer having different nitrogen concentrations. The first electrode bilayer, the dielectric layer, and the second electrode bilayer are patterned to form a capacitor structure on the first interconnect layer; and A second interconnect layer is formed on the capacitor structure, wherein a conductive structure of the second interconnect layer contacts the second electrode bilayer. Wherein, the depositing the first electrode bilayer and the depositing the second electrode bilayer include: when the second layer undergoes additional plasma treatment compared to the third layer, the nitrogen concentration deposited in the second layer is higher than the nitrogen concentration deposited in the third layer; when the third layer undergoes additional plasma treatment compared to the second layer, the nitrogen concentration deposited in the third layer is higher than the nitrogen concentration deposited in the second layer.

17. The method according to claim 16, wherein, Depositing the first electrode bilayer includes depositing the first layer having a lower nitrogen concentration than the second layer, and wherein each of the first layer and the second layer includes titanium nitride.

18. The method according to claim 16, wherein, Depositing the second electrode bilayer includes depositing the fourth layer having a lower nitrogen concentration than the third layer, and wherein each of the third and fourth layers includes titanium nitride.

19. The method according to claim 16, wherein, Depositing the first electrode bilayer includes depositing the first layer thicker than the second layer.

20. The method according to claim 16, wherein, Depositing the second electrode bilayer includes depositing the third layer thinner than the fourth layer.

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