Semiconductor device and method

Abstract

This application discloses semiconductor devices and methods. A semiconductor device including a barrier layer surrounding a work function metal layer and a method of forming the same are disclosed. In one embodiment, a semiconductor device includes: a semiconductor substrate; a first channel region located above the semiconductor substrate; a second channel region located above the first channel region; a gate dielectric layer surrounding the first channel region and the second channel region; a work function metal layer surrounding the gate dielectric layer; and a barrier layer surrounding the work function metal layer, with a first barrier layer surrounding the first channel region merging with a second barrier layer surrounding the second channel region.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices and methods of manufacturing the same. Background Art

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials over a semiconductor substrate and patterning the respective material layers using lithography to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size is reduced, other problems arise that should be addressed. Summary of the Invention

[0004] According to one aspect of the present disclosure, there is provided a semiconductor device including: a semiconductor substrate; a first channel region over the semiconductor substrate; a second channel region over the first channel region; a gate dielectric layer surrounding the first channel region and the second channel region; a work function metal layer surrounding the gate dielectric layer; and a barrier layer surrounding the work function metal layer, wherein a first barrier layer surrounding the first channel region merges with a second barrier layer surrounding the second channel region.

[0005] According to another aspect of the present disclosure, there is provided a method including: forming a channel region over a semiconductor substrate; forming a gate dielectric layer surrounding the channel region; depositing a work function metal layer over the gate dielectric layer; depositing a barrier layer over the work function metal layer, wherein the barrier layer, the work function metal layer, and the gate dielectric layer fill an opening between the semiconductor substrate and the channel region; and depositing a filler material over the barrier layer.

[0006] According to still another aspect of the present disclosure, there is provided a semiconductor substrate; a first channel region over the semiconductor substrate and separated from the semiconductor substrate; a gate dielectric layer surrounding the first channel region; a work function metal layer surrounding the gate dielectric layer, wherein a thickness of the work function metal layer in a direction perpendicular to a main surface of the semiconductor substrate is equal to a thickness of the work function metal layer in a direction parallel to the main surface of the semiconductor substrate; and a barrier layer surrounding the work function metal layer. Brief Description of the Drawings

[0007] Aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figure 1 An example of a semiconductor device including a nanosheet field-effect transistor (NSFET) in a three-dimensional view according to some embodiments is shown.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 17C 、 Figure 17D 、 Figure 18A 、 Figure 18B 、 Figure 19A 、 Figure 19B 、 Figure 20A 、 Figure 20B 、 Figure 21A and Figure 21B are cross-sectional views of intermediate stages of manufacturing a semiconductor device according to some embodiments. Detailed Description

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming the first feature over or on the second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0011] In addition, spatially relative terms (e.g., "below", "beneath", "lower", "above", "upper", etc.) may be used herein to facilitate describing the relationship of one element or feature shown in the figures to another (one or more) element or (one or more) feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0012] Various embodiments provide a semiconductor device and a method of forming the same, wherein a barrier layer is formed between a work function metal layer and a filler material in a gate electrode. The barrier layer may be included to prevent metal from migrating from the work function metal layer deposited on a first channel region to a high-k layer deposited on an adjacent second channel region, and to prevent metal from migrating from the work function metal layer deposited on the second channel region to the high-k layer deposited on the first channel region. The barrier layer may further prevent the work function metal layers deposited on the first channel region and the second channel region from fusing, which helps to ensure that the thickness of the work function metal layer is the same around the perimeter of the first channel region and the second channel region. The barrier layer may be included in the gate electrodes of both the NMOS region and the PMOS region of the semiconductor device. In some embodiments, the barrier layer provided in the NMOS region may be formed of silicon, silicon oxide, etc., and the barrier layer provided in the PMOS region may be formed of tantalum nitride, tungsten nitride, tungsten carbonitride, etc. By preventing metal migration within the gate stack (including the high-k layer, the work function metal layer, the barrier layer, and the filler material), the barrier layer reduces device defects and improves device performance. Additionally, since the work function metal layer has a uniform thickness around the perimeter of the channel region, the electrical performance is improved and device defects are reduced.

[0013] Figure 1Shows an example of a nanostructure (e.g., nanosheet, nanowire, all-gate, etc.) field effect transistor (NSFET) according to some embodiments. The NSFET includes a nanostructure 55 over a substrate 50 (e.g., a semiconductor substrate). The nanostructure 55 includes second semiconductor layers 54A - 54C, which serve as the channel region of the nanostructure 55. Shallow trench isolation (STI) regions 58 are disposed in the substrate 50, and the nanostructure 55 is disposed above and between adjacent STI regions 58. Although the STI regions 58 are described / illustrated as being separate from the substrate 50, as used herein, the term "substrate" may refer to a separate semiconductor substrate or a combination of a semiconductor substrate and STI regions.

[0014] The gate dielectric layer 100 is along the top surface, sidewalls, and bottom surface of the nanostructure 55, e.g., on the top surface, sidewalls, and bottom surface of each of the second semiconductor layers 54A - 54C, and along the top surface and sidewalls of a portion of the substrate 50. The gate electrode 102 is over the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on opposite sides of the nanostructure 55, the gate dielectric layer 100, and the gate electrode 102. Figure 1 Also shown are reference cross-sections used in the subsequent figures. Cross-section A - A' is along the longitudinal axis of the gate electrode 102 and in a direction, e.g., perpendicular to the direction of current flow between the epitaxial source / drain regions 92 of the NSFET. Cross-section B - B' is perpendicular to cross-section A - A' and along the longitudinal axis of the nanostructure 55 and in the direction of current flow, e.g., between the epitaxial source / drain regions 92 of the NSFET. Cross-section C - C' is parallel to cross-section A - A' and extends through the epitaxial source / drain regions 92 of the NSFET. For clarity, the subsequent figures refer to these reference cross-sections.

[0015] Some embodiments discussed herein are in the context of NSFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, some embodiments consider aspects of using fin field effect transistors (FinFETs) or planar devices such as planar FETs.

[0016] Figures 2 to 21B Is a cross-sectional view of an intermediate stage in manufacturing an NSFET according to some embodiments. Figures 2 to 5 、 Figure 6A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 17C 、 Figure 18A 、 Figure 19A 、Figure 20A and Figure 21A shows Figure 1 the reference cross-section A-A' shown Figure 6B 、 Figure 7B 、 Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B 、 Figure 17D 、 Figure 18B 、 Figure 19B 、 Figure 20B and Figure 21B shows Figure 1 the reference cross-section B-B' shown Figure 7A 、 Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A and Figure 12C shows Figure 1 the reference cross-section C-C' shown

[0017] In Figure 2 ,a substrate 50 is provided for forming an NSFET. The substrate 50 can be a semiconductor substrate, e.g., a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 can be a wafer, e.g., a silicon wafer. Generally, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer can be, e.g., a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate that is typically a silicon substrate or a glass substrate. Other substrates can also be used, e.g., a multi-layer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate 50 can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium phosphoarsenide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium phosphoarsenide indium; or combinations thereof.

[0018] The substrate 50 has a region 50N and a region 50P. The region 50N can be used to form n-type devices, e.g., NMOS transistors, such as n-type NSFETs. The region 50P can be used to form p-type devices, e.g., PMOS transistors, such as p-type NSFETs. The region 50N can be physically separated from the region 50P (as shown by the spacer 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the region 50N and the region 50P.

[0019] Substrate 50 may be lightly doped with p-type or n-type impurities. Anti-punch-through (APT) implantation may be performed on the upper portion of substrate 50 to form APT region 53. During the APT implantation, dopants may be implanted into region 50N and region 50P. The conductivity type of the dopant may be the same as the source / drain region (e.g., epitaxial source / drain region 92, referred to below) to be formed in each of region 50N and region 50P. Figures 12A - 12C The APT region 53 may extend below the subsequently formed source / drain regions in the resulting NSFET, which will be formed in a subsequent process. The APT region 53 may be used to reduce leakage from the source / drain regions to the substrate 50. In some embodiments, the doping concentration in the APT region 53 may be from about 1×10 18 Atom / cm 3 To about 1×10 19 Atom / cm 3 , for example, about 5.5×10 18 Atom / cm 3 For the sake of simplicity and clarity, the APT region 53 is not shown in subsequent figures.

[0020] Further in Figure 2 In the embodiment of the present invention, a multilayer stack 56 is formed on a substrate 50. The multilayer stack 56 includes alternating first semiconductor layers 52 and second semiconductor layers 54 of different semiconductor materials. The first semiconductor layer 52 may be formed of a first semiconductor material, which may include, for example, silicon germanium (SiGe), etc. The second semiconductor layer 54 may be formed of a second semiconductor material, which may include, for example, silicon (Si), silicon carbide (SiC), etc. In other embodiments, the first semiconductor layer 52 may be formed of a second semiconductor material, and the second semiconductor layer 54 may be formed of a first semiconductor material. For the purpose of illustration, the multilayer stack 56 includes three first semiconductor layers 52 (e.g., first semiconductor layers 52A-52C) and three second semiconductor layers 54 (e.g., second semiconductor layers 54A-54C). In other embodiments, the multilayer stack 56 may include any number of first semiconductor layers 52 and second semiconductor layers 54. Each layer in the multilayer stack 56 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In some embodiments, a ratio of the thickness of the second semiconductor layer 54 to the thickness of the first semiconductor layer 52 may be from about 0.5 to about 0.9, for example, about 0.7.

[0021] For illustrative purposes, the second semiconductor layer 54 will be described as forming the channel region in a complete NSFET device. The first semiconductor layer 52 can be a sacrificial layer, which can be subsequently removed. However, in some embodiments, the second semiconductor layers 54A - 54C can form the channel region in a complete NSFET device, while the first semiconductor layers 52A - 52D can be sacrificial layers.

[0022] In Figure 3 this, nanostructures 55 are formed in the multi - layer stack 56, and the substrate 50 is etched. In some embodiments, the nanostructures 55 can be formed by etching trenches in the multi - layer stack 56 and the substrate 50. The etching can be any acceptable etching process, such as, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic.

[0023] The nanostructures 55 and the substrate 50 can be patterned by any suitable method. For example, one or more lithography processes (including double - patterning processes or multi - patterning processes) can be used to pattern the nanostructures 55 and the substrate 50. Generally, double - patterning processes or multi - patterning processes combine lithography processes and self - alignment processes, allowing the creation of patterns with, for example, smaller pitch than can be obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a lithography process. Spacers are formed beside the patterned sacrificial layer using a self - alignment process. The sacrificial layer is then removed, and then the remaining spacers can be used to pattern the nanostructures 55 and the substrate 50. In some embodiments, a mask (or other layer) can remain on the nanostructures 55 after patterning the nanostructures 55 and the substrate 50.

[0024] In Figure 4In this case, a shallow trench isolation (STI) region 58 is formed adjacent to the patterned portion of the substrate 50 and the nanostructures 55. The STI region 58 can be formed by forming an insulating material (not shown separately) over the substrate 50 and between adjacent patterned portions / nanostructures 55 of the substrate 50. The insulating material can be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and can be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to convert the deposited material into another material (e.g., an oxide)), etc., or a combination thereof. Other insulating materials formed by any acceptable method can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material is formed such that an excess of the insulating material covers the nanostructures 55. The insulating material can include a single layer or multiple layers can be utilized. For example, in some embodiments, a liner (not shown separately) can be formed first along the surfaces of the substrate 50 and the nanostructures 55. Thereafter, a filler material such as the filler material described above can be formed over the liner.

[0025] Then, a removal process is applied to the insulating material to remove the excess insulating material over the nanostructures 55. In some embodiments, a planarization process can be utilized, e.g., chemical mechanical polishing (CMP), etch-back process, a combination thereof, etc. The planarization process can planarize the insulating material and the nanostructures 55. The planarization process exposes the nanostructures 55 such that after the planarization process is completed, the top surfaces of the nanostructures 55 and the insulating material are flush.

[0026] Then the insulating material is recessed to form the STI region 58, as Figure 4 shown. The insulating material is recessed such that the nanostructures 55 and the upper portions of the substrate 50 protrude between adjacent STI regions 58. Additionally, the top surface of the STI region 58 can have a flat surface, a convex surface, a concave surface (e.g., a depression), or a combination thereof as shown. The top surface of the STI region 58 can be formed to be flat, convex, and / or concave by appropriate etching. The STI region 58 can be recessed using an acceptable etching process, e.g., an etching process selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the materials of the nanostructures 55 and the substrate 50). For example, oxide removal using dilute hydrofluoric acid (dHF) can be used.

[0027] Regarding Figures 2 - 4The described process is merely an example of the nanostructure 55. In some embodiments, the nanostructure 55 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. An epitaxial structure can be grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the nanostructure 55. In the nanostructure 55, the epitaxial structure can include layers of alternating first and second semiconductor materials. The substrate 50 can include an epitaxial structure, which can be a homoepitaxial structure or a heteroepitaxial structure. Subsequently, the dielectric layer can be recessed such that portions of the substrate 50 and the nanostructure 55 protrude from the dielectric layer. In embodiments where portions of the substrate 50 and the nanostructure 55 are epitaxially grown, the epitaxially grown materials can be doped in-situ during growth, which can eliminate prior and subsequent implantations, but in-situ doping and implant doping can be used together.

[0028] Further, it may be advantageous to epitaxially grow different materials in the region 50N (e.g., NMOS region) than in the region 50P (e.g., PMOS region). In various embodiments, the upper portion of the substrate 50 can be formed of silicon germanium (Si x Ge 1-x , where x can range from 0 to 1), silicon carbide, pure or substantially pure germanium, group III-V compound semiconductors, group II-VI compound semiconductors, etc. For example, available materials for forming group III-V compound semiconductors include, but are not limited to: indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0029] Further in Figure 4 it may be possible to form suitable wells (not shown separately) in the nanostructure 55 and / or the substrate 50. In some embodiments, a P well can be formed in the region 50N, and an N well can be formed in the region 50P. In additional embodiments, a P well or an N well can be formed in each of the region 50N and the region 50P.

[0030] In embodiments including different well types, a photoresist or other mask (not shown separately) can be used to implement different implantation steps for regions 50N and 50P. For example, a photoresist can be formed over nanostructures 55, substrate 50, and STI region 58 in region 50N. The photoresist is patterned to expose region 50P of substrate 50. The photoresist can be formed by using a spin coating technique, and the photoresist can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist can be used as a mask to substantially prevent the n-type impurity from being implanted into region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc. implanted into the region, and its concentration is equal to or less than 1×10 18 atoms / cm 3 , for example, from about 1×10 16 atoms / cm 3 to about 1×10 18 atoms / cm 3 , or about 5.05×10 17 atoms / cm 3 . After the implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0031] After the implantation of region 50P, a photoresist is formed over nanostructures 55, substrate 50, and STI region 58 in region 50P. The photoresist is patterned to expose region 50N of substrate 50. The photoresist can be formed by using a spin coating technique, and the photoresist can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implantation can be performed in region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P. The p-type impurity can be boron, boron fluoride, indium, etc. implanted into the region, and its concentration is equal to or less than 1×10 18 atoms / cm 3 , for example, from about 1×10 16 atoms / cm 3 to about 1×10 18 atoms / cm 3 , or about 5.05×10 17 atoms / cm 3 . After the implantation, the photoresist can be removed, for example, by an acceptable ashing process.

[0032] After the implantation in regions 50N and 50P, annealing can be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can eliminate the implantation, but in-situ doping and implant doping can be used together.

[0033] In Figure 5 a dummy dielectric layer 60 is formed on the nanostructure 55 and the substrate 50. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60 and then planarized by a process such as CMP. The mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive material or a non-conductive material and can be selected from the group including: amorphous silicon, polysilicon, poly-SiGe, metal-containing nitrides, metal-containing silicides, metal-containing oxides, and metals. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used for depositing the selected material. The dummy gate layer 62 can be made of other materials having a high etch selectivity with respect to the material of the STI region 58. The mask layer 64 can include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across regions 50N and 50P. Note that, for illustrative purposes only, the dummy dielectric layer 60 is shown as only covering the nanostructure 55 and the substrate 50. In some embodiments, the dummy dielectric layer 60 can be deposited such that the dummy dielectric layer 60 covers the STI region 58 and extends between the dummy gate layer 62 and the STI region 58.

[0034] Figures 6A to 21B Various additional steps in the fabrication of an exemplary device are shown. Figures 6B to 21B Features in one of regions 50N or 50P are shown. For example, Figures 6B to 21B the structures shown can be applicable to both regions 50N and 50P. Differences in the structures of regions 50N and 50P (if any) are described in the text accompanying each figure.

[0035] In Figure 6A and Figure 6B a, acceptable lithography and etching techniques can be used to pattern the mask layer 64 (see Figure 5)Patterning is performed to form a mask 74. Acceptable etching techniques can be used to transfer the pattern of the mask 74 to the dummy gate layer 62 to form dummy gates 72. In some embodiments, the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60. The dummy gates 72 cover the corresponding channel regions of the nanostructures 55. In an embodiment, the channel regions can be formed in a second semiconductor layer 54A - 54C including a second semiconductor material. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from adjacent dummy gates 72. The length direction of the dummy gates 72 can be substantially perpendicular to the length direction of the corresponding nanostructures 55.

[0036] In Figure 7A and 7B in Figure 6A and Figure 6B A first spacer layer 80 and a second spacer layer 82 are formed over the structures shown. In Figure 7A and Figure 7B In, a first spacer layer 80 is formed on the top surface of the STI region 58, the top surface and sidewalls of the nanostructures 55 and the mask 74, and the sidewalls of the substrate 50, the dummy gates 72, and the dummy dielectric layer 60. The second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 can be formed by thermal oxidation or deposited by CVD, ALD, etc. The first spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. The second spacer layer 82 can be deposited by CVD, ALD, etc. The second spacer layer 82 can be formed of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0037] In Figure 8A and Figure 8B in, the first spacer layer 80 and the second spacer layer 82 are etched to form a first spacer 81 and a second spacer 83. Appropriate etching processes can be used to etch the first spacer layer 80 and the second spacer layer 82, such as isotropic etching processes (e.g., wet etching processes), anisotropic etching processes (e.g., dry etching processes), etc. As Figure 8A shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the nanostructures 55 and the substrate 50. As Figure 8B shown, the second spacer layer 82 can be removed from above the first spacer layer 80 adjacent to the mask 74, the dummy gates 72, and the dummy dielectric layer 60, and the first spacer 81 is disposed on the sidewalls of the mask 74, the dummy gates 72, and the dummy dielectric layer 60.

[0038] After forming the first spacer 81 and the second spacer 83, implantation for lightly doped source / drain (LDD) regions (not shown separately) can be performed. In embodiments with different device types, similar to above in Figure 4The implantation discussed above can form a mask (e.g., photoresist) over region 50N while exposing region 50P, and impurities of a suitable type (e.g., p-type) can be implanted into the exposed nanostructures 55 and substrate 50 in region 50P. Then the mask can be removed. Subsequently, a mask (e.g., photoresist) can be formed over region 50P while exposing region 50N, and impurities of a suitable type (e.g., n-type) can be implanted into the exposed nanostructures 55 and substrate 50 in region 50N. Then the mask can be removed. The n-type impurities can be any of the previously discussed n-type impurities, and the p-type impurities can be any of the previously discussed p-type impurities. The impurity concentration of the lightly doped source / drain regions can range from about 1×10 15 atoms / cm 3 to about 1×10 19 atoms / cm 3 , e.g., about 5×10 18 atoms / cm 3 . Annealing can be used to repair implantation damage and activate the implanted impurities.

[0039] Note that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer spacers or additional spacers can be utilized, different step sequences can be employed (e.g., the first spacer 81 can be formed before the second spacer 83 is formed, additional spacers can be formed and removed, etc.). Additionally, different structures and steps can be used to form n-type devices and p-type devices.

[0040] In Figure 9A and Figure 9B , a first groove 86 is formed in the nanostructures 55 and substrate 50. The first groove 86 can extend through the first semiconductor layers 52A - 52C and the second semiconductor layers 54A - 54C and into the substrate 50. As Figure 9A shown, the top surface of the STI region 58 can be flush with the top surface of the substrate 50. In various embodiments, the first groove can extend to the top surface of the substrate 50 without etching the substrate 50; the substrate 50 can be etched such that the bottom surface of the first groove 86 is disposed below the top surface of the STI region 58; etc. The first groove 86 can be formed by etching the nanostructures 55 and substrate 50 using an anisotropic etching process (e.g., RIE, NBE, etc.). During the etching process for forming the first groove 86, the first spacer 81, the second spacer 83, and the mask 74 mask portions of the nanostructures 55 and substrate 50. A single etching process can be used to etch each layer in the multilayer stack 56. In other embodiments, multiple etching processes can be used to etch the layers of the multilayer stack 56. A timed etching process can be used to stop the etching of the first groove 86 after it reaches the desired depth.

[0041] In Figure 10A and Figure 10B the portion of the sidewalls of the layers of the multi-layer stack 56 formed of the first semiconductor material (e.g., the first semiconductor layers 52A - 52C) that is exposed by the first recess 86 is etched to form sidewall recesses 88. An isotropic etching process (e.g., wet etching, etc.) can be used to etch the sidewalls. The etchant used to etch the first semiconductor layers 52A - 52C can be selective to the first semiconductor material such that the second semiconductor layers 54A - 54C and the substrate 50 remain relatively unetched compared to the first semiconductor layers 52A - 52C. In embodiments where the first semiconductor layers 52A - 52C include, for example, SiGe and the second semiconductor layers 54A - 54C include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. can be used to etch the sidewalls of the multi-layer stack 56. In further embodiments, a dry etching process can be used to etch the layers of the multi-layer stack 56. Hydrogen fluoride, another fluorine-based gas, etc. can be used to etch the sidewalls of the multi-layer stack 56.

[0042] In Figure 11A and Figure 11B inner spacers 90 are formed in the sidewall recesses 88. The inner spacers 90 can be formed by depositing an inner spacer layer (not shown separately) over the structures shown in Figure 10A and Figure 10B The inner spacer layer can be deposited by a conformal deposition process such as CVD, ALD, etc. The inner spacer layer can include materials such as silicon nitride or silicon oxynitride, but any suitable material can be used, e.g., a low dielectric constant (low-k) material with a k value less than about 3.5. The inner spacer layer can then be etched to form the inner spacers 90. The inner spacer layer can be etched by an anisotropic etching process, e.g., RIE, NBE, etc. The inner spacers 90 can be used to prevent damage to the source / drain regions (e.g., the epitaxial source / drain regions 92, discussed below with respect to Figures 12A - 12C which are formed by subsequent etching processes).

[0043] In Figures 12A - Figure 12C epitaxial source / drain regions 92 are formed in the first recess 86 to apply stress to the second semiconductor layers 54A - 54C of the nanostructure 55, thereby improving performance. As Figure 12BAs shown, an epitaxial source / drain region 92 is formed in the first groove 86 such that each dummy gate 72 is disposed between an adjacent pair of the corresponding epitaxial source / drain regions 92. In some embodiments, the first spacer 81 is used to separate the epitaxial source / drain region 92 from the dummy gate 72 by an appropriate lateral distance such that the epitaxial source / drain region 92 does not short-circuit the gate of the resulting NSFET formed subsequently. The internal spacer 90 can be used to separate the epitaxial source / drain region 92 from the first semiconductor layers 52A - 52C by an appropriate lateral distance to prevent a short circuit between the epitaxial source / drain region 92 and the gate of the resulting NSFET formed subsequently.

[0044] The epitaxial source / drain region 92 in the region 50N (e.g., NMOS region) can be formed by masking the region 50P (e.g., PMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first groove 86. The epitaxial source / drain region 92 can include any acceptable material, e.g., a material suitable for an n-type NSFET. For example, if the second semiconductor layers 54A - 54C are silicon, the epitaxial source / drain region 92 can include a material that applies tensile strain on the second semiconductor layers 54A - 54C, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 can have a surface that protrudes from the corresponding surface of the multi-layer stack 56 and can have a facet.

[0045] The epitaxial source / drain region 92 in the region 50P (e.g., PMOS region) can be formed by masking the region 50N (e.g., NMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first groove 86. The epitaxial source / drain region 92 can include any acceptable material, e.g., a material suitable for a p-type NSFET. For example, if the second semiconductor layers 54A - 54C are silicon, the epitaxial source / drain region 92 can include a material that applies compressive strain on the second semiconductor layers 54A - 54C, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain region 92 can also have a surface that protrudes from the corresponding surface of the multi-layer stack 56 and can have a facet.

[0046] The epitaxial source / drain region 92, the second semiconductor layers 54A - 54C, and / or the substrate 50 can be implanted with dopants to form source / drain regions, similar to the process for forming lightly doped source / drain regions discussed previously, and then annealed. The impurity concentration of the source / drain regions can be between about 1×10 19 atoms / cm 3 and about 1×10 21 atoms / cm 3 For example, about 5.05×10 20atoms / cm 3 The n-type and / or p-type impurities for the source / drain regions can be any of the previously discussed impurities. In some embodiments, the epitaxial source / drain regions 92 can be in-situ doped during growth.

[0047] As a result of the epitaxial process for forming the epitaxial source / drain regions 92 in regions 50N and 50P, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of the nanostructures 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same NSFET to fuse, as Figure 12A shown. In other embodiments, adjacent epitaxial source / drain regions 92 remain separate after the epitaxial process is completed, as Figure 12C shown. In Figure 12A and Figure 12C the illustrated embodiments, a first spacer 81 can be formed to cover portions of the sidewalls of the nanostructures 55 and the substrate 50 that extend above the STI region 58, thereby preventing epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 can be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 58.

[0048] In Figure 13A and Figure 13B respectively, a first interlayer dielectric (ILD) 96 is deposited over the structures shown in Figure 6A and Figure 12B (the process of Figures 7A - Figure 12B does not change the cross-section shown in Figure 6A ). The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, e.g., CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 74, and the first spacer 81. The CESL 94 can include a dielectric material having an etch rate different from that of the overlying first ILD 96, e.g., silicon nitride, silicon oxide, silicon oxynitride, etc.

[0049] In Figure 14A and Figure 14BIn [the process], a planarization process such as CMP can be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process can also remove the mask 74 on the dummy gate 72 and the portions of the first spacers 81 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the first spacers 81, and the first ILD 96 are flush. Accordingly, the top surface of the dummy gate 72 is exposed through the first ILD 96. In some embodiments, the mask 74 can be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 74 and the first spacers 81.

[0050] In Figure 15A and Figure 15B In [the process], the dummy gate 72 and the mask 74 (if present) are removed in one or more etching steps such that a second recess 98 is formed. The portions of the dummy dielectric layer 60 in the second recess 98 can also be removed. In some embodiments, only the dummy gate 72 is removed and the dummy dielectric layer 60 is retained and exposed by the second recess 98. In some embodiments, the dummy dielectric layer 60 is removed from the second recess 98 in a first region of the die (e.g., the core logic region) and retained in the second recess 98 in a second region of the die (e.g., the input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process can include a dry etching process using one or more reactive gases that selectively etch the dummy gate 72 at a faster rate than the first ILD 96 or the first spacers 81. Each second recess 98 exposes and / or covers portions of the multilayer stack 56 that serve as the channel region in the subsequently completed NSFET. The portions of the multilayer stack 56 that serve as the channel region are disposed between adjacent pairs of the epitaxial source / drain regions 92. During removal, the dummy dielectric layer 60 can serve as an etch stop layer when the dummy gate 72 is etched. The dummy dielectric layer 60 can then optionally be removed after the dummy gate 72 is removed.

[0051] In Figure 16A and Figure 16BIn [the structure], the first semiconductor layers 52A - 52C are removed and the second recess 98 is extended. The first semiconductor layers 52A - 52C can be removed by an isotropic etching process (e.g., wet etching, etc.). An etchant selective to the material of the first semiconductor layers 52A - 52C can be used to remove the first semiconductor layers 52A - 52C, while the second semiconductor layers 54A - 54C, the substrate 50, and the STI regions 58 remain relatively unetched compared to the first semiconductor layers 52A - 52C. In embodiments where the first semiconductor layers 52A - 52C include, for example, SiGe and the second semiconductor layers 54A - 54C include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. can be used to remove the first semiconductor layers 52A - 52C. In some embodiments, the ratio of the thickness of the second semiconductor layers 54A - 54C to the distance between adjacent semiconductor layers 54A - 54C, or the distance between the semiconductor layer 54A and the substrate 50, can be from about 0.5 to about 0.9, e.g., about 0.7 in regions 50N and 50P.

[0052] In Figure 17A and Figure 17B for replacement gate formation, a gate dielectric layer 100 and a gate electrode 102 are formed. Figure 17C A detailed view of region 101 of Figure 17A is shown, and Figure 17D a detailed view of region 103 of Figure 17B is shown. The gate dielectric layer 100 is conformally deposited in the second recess 98, e.g., on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls, and bottom surfaces of the second semiconductor layers 54A - 54C. The gate dielectric layer 100 can also be deposited on the top surface of the first ILD 96, the CESL 94, and the STI regions 58, and on the top surface and sidewalls of the first spacer 81.

[0053] The gate electrode 102 is deposited separately on top of the gate dielectric layer 100 and fills the remaining portion of the second recess 98. After filling the second recess 98, a planarization process such as CMP can be performed to remove the excess material of the gate electrode 102 and the gate dielectric layer 100 that is above the top surface of the first ILD 96. The remaining portions of the materials of the gate electrode 102 and the gate dielectric layer 100 thus form the replacement gate of the resulting NSFET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the "gate stack".

[0054] As Figure 17C and Figure 17DAs shown, the gate dielectric layer 100 may include an interfacial layer 100A and a first dielectric layer 100B, and the gate electrode 102 may include a work function metal layer 102A, a barrier layer 102B, and a fill material 102C. The interfacial layer 100A may include a dielectric material, such as, for example, silicon dioxide (SiO2), silicon oxynitride (SiON), etc. The interfacial layer 100A may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), CVD, etc. The thickness of the interfacial layer 100A may be from about to about For example, about

[0055] The first dielectric layer 100B may be deposited over the interfacial layer 100A using a conformal process. The first dielectric layer 100B may be a high-k (high dielectric constant) material, such as, for example, hafnium oxide (HfO2), aluminum oxide (Al2O3), lanthanum oxide (LaO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO2), tantalum oxide (Ta2O3), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), combinations thereof, or multiple layers thereof, etc. The first dielectric layer 100B may be formed by ALD, CVD, etc. In some embodiments, the interfacial layer 100A may be omitted, and the first dielectric layer 100B may be directly deposited on the substrate 50 and the second semiconductor layers 54A - 54C. The thickness of the first dielectric layer 100B may be from about to about For example, about

[0056] The formation of the interfacial layer 100A and the first dielectric layer 100B in the regions 50N and 50P may occur simultaneously such that the gate dielectric layer 100 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by different processes such that the gate dielectric layer 100 may be different materials. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0057] After forming the first dielectric layer 100B, a work function metal layer 102A is formed on the first dielectric layer 100B. The work function metal layer 102A is formed to adjust the work function of the device. The work function metal layer 102A can be an n-type work function material for the n-type NSFET device in region 50N, or a p-type work function material for the p-type NSFET device in region 50P. Suitable examples of the n-type work function material include Ti, Ag, TaAl, TaAlC, HfAl, TiAl, TiAlN, TiAlC, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function metal materials, or combinations thereof. Suitable examples of the p-type work function material include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function metal materials, or combinations thereof. The work function metal layer 102A can be formed by ALD, CVD, etc. The thickness of the work function metal layer 102A can be from about to about For example, about The work function metal layer 102A can be formed such that a space is reserved between the work function metal layers 102A deposited on adjacent items in the substrate 50 and the second semiconductor layers 54A - 54C.

[0058] After forming the work function metal layer 102A, a barrier layer 102B is formed on the work function metal layer 102A. The barrier layer 102B is formed to prevent the metal in the work function metal layer 102A deposited on either the substrate 50 or the second semiconductor layers 54A - 54C from diffusing into the gate dielectric layer 100 of the adjacent substrate 50 or the second semiconductor layers 54A - 54C. The barrier layer 102B can further prevent the work function metal layers 102A deposited on adjacent items in the substrate 50 and the second semiconductor layers 54A - 54C from fusing, and can be used to ensure that the work function metal layer 102A has the same thickness around the perimeter of the second semiconductor layers 54A - 54C. As Figure 17C shown, the barrier layers 102B formed on adjacent items in the substrate 50 and the second semiconductor layers 54A - 54C can fuse with each other. The barrier layer 102B can fill the space left between the work function metal layers 102A deposited on adjacent items in the substrate 50 and the second semiconductor layers 54A - 54C.

[0059] The material for the barrier layer 102B in region 50N can include a semi-conductive material, a non-conductive material, or a conductive material. For example, suitable materials for the barrier layer 102B in region 50N include silicon, silicon oxide, tantalum nitride, etc. The barrier layer 102B in region 50N can have a thickness from about to about For example, about The ratio of the thickness T1 of the blocking layer 102B in the region 50N to the distance between the adjacent second semiconductor layers 54A - 54C, or the distance D1 between the second semiconductor layer 54A and the substrate 50, can be from about 0.1 to about 0.5, for example, about 0.3. The thickness T1 of the blocking layer 102B can be measured at a point flush with the middle of the second semiconductor layers 54A - 54C and in a direction parallel to the main surface of the substrate 50. The distance D1 can be measured between the centers of the second semiconductor layers 54A - 54C and the substrate 50 and in a direction perpendicular to the main surface of the substrate 50. The distance between the blocking layer 102B and the second semiconductor layers 54A - 54C is greater than the distance between the work function metal layer 102A and the second semiconductor layers 54A - 54C. Therefore, compared with the work function metal layer 102A, the blocking layer 102B can have a reduced impact on the work function of the device.

[0060] The material for the blocking layer 102B in the region 50P can include a semi - conductive material or a conductive material. For example, suitable materials for the blocking layer 102B in the region 50P include silicon, tantalum nitride, tungsten nitride, tungsten carbonitride, etc. The blocking layer 102B in the region 50P can have a thickness from about to about For example, about The ratio of the thickness T1 of the blocking layer 102B in the region 50P to the distance between the adjacent second semiconductor layers 54A - 54C, or between the semiconductor layer 54A and the substrate 50, which is D1, can be from about 0.1 to about 0.5, for example, about 0.3. The thickness T1 of the blocking layer 102B can be measured at a point flush with the middle of the second semiconductor layers 54A - 54C and in a direction parallel to the main surface of the substrate 50. The distance D1 can be measured between the centers of the second semiconductor layers 54A - 54C and the substrate 50 and in a direction perpendicular to the main surface of the substrate 50. The distance between the blocking layer 102B and the second semiconductor layers 54A - 54C is greater than the distance between the work function metal layer 102A and the second semiconductor layers 54A - 54C. Therefore, compared with the work function metal layer 102A, the blocking layer 102B can have a reduced impact on the work function of the device.

[0061] Then, a filling material 102C is deposited on the blocking layer 102B. The filling material 102C can be a material such as, for example, tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), manganese (Mn), zirconium (Zr), cobalt (Co), nickel (Ni), tantalum (Ta), AlCu, TiAlN, TaC, TaCN, TaSiN, TiN, TaN, their alloys or combinations, etc. The filling material 102C can be deposited by ALD, CVD, etc. In addition, the filling material 102C can be deposited to about and about The thickness between, for example, about However, any suitable material can be used. In some embodiments, the barrier layer 102B may not completely fill the space between the substrate and adjacent items in the second semiconductor layers 54A - 54C. In such embodiments, the fill material 102C may fill any space left between the barrier layers 102B deposited on the substrate 50 and adjacent items in the second semiconductor layers 54A - 54C.

[0062] The work function metal layer 102A, the barrier layer 102B, and the fill material 102C in the regions 50N and 50P can be formed by different processes such that the gate electrodes in each region can be formed of different materials. When different processes are used, various mask steps can be used to mask and expose appropriate regions. In additional embodiments, forming each of the work function metal layer 102A, the barrier layer 102B, and the fill material 102C in the regions 50N and 50P can occur simultaneously such that the gate electrodes 102 in each region are formed of the same material. In an embodiment, different processes can be used to form the work function metal layer 102A in the regions 50N and 50P, and the same process can be used to simultaneously form the barrier layer 102B and the fill material 102C in the regions 50N and 50P. In another embodiment, different processes can be used to form the work function metal layer 102A and the barrier layer 102B in the regions 50N and 50P, and the same process can be used to simultaneously form the fill material 102C in the regions 50N and 50P.

[0063] In Figure 18A and Figure 18B In, a second ILD 110 is deposited over the first ILD 96. In some embodiments, the second ILD 110 is a flowable film formed by FCVD. In some embodiments, the second ILD 110 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc. According to some embodiments, prior to forming the second ILD 110, the recessed gate stack (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) is recessed such that a groove is formed between directly above the gate stack and opposite portions of the first spacer 81. The gate mask 108 including one or more dielectric materials (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the groove, and then a planarization process is performed to remove the excess portion of the dielectric material extending over the first ILD 96. Subsequently formed gate contacts (e.g., as described below with reference to Figure 19A and 19BThe discussed gate contact 114) passes through the gate mask 108 to contact the top surface of the recessed gate electrode 102.

[0064] In Figure 19A and Figure 19B , the source / drain contact 112 and the gate contact 114 are formed through the second ILD 110 and the first ILD 96. Openings for the source / drain contact 112 are formed through the first ILD 96 and the second ILD 110, and openings for the gate contact 114 are formed through the second ILD 110 and the gate mask 108. Acceptable lithography and etching techniques can be used to form the openings. Liners (e.g., diffusion barrier layers, adhesion layers, etc.) and conductive materials are formed in the openings. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second ILD 110. The remaining liner and conductive material form the source / drain contact 112 and the gate contact 114 in the openings. An annealing process can be performed to form a silicide at the interface between the epitaxial source / drain region 92 and the source / drain contact 112. The source / drain contact 112 is physically and electrically coupled to the epitaxial source / drain region 92, and the gate contact 114 is physically and electrically coupled to the gate electrode 102. The source / drain contact 112 and the gate contact 114 can be formed by different processes or can be formed by the same process. Although shown as being formed in the same cross-section, it should be understood that each of the source / drain contact 112 and the gate contact 114 can be formed in a different cross-section, which can avoid short-circuiting of the contacts.

[0065] As described above, the gate electrode 102 includes a barrier layer 102B that prevents metal migration from the work function metal layer 102A to the first dielectric layer 100B. This reduces device defects and improves device performance. The barrier layer 102B also prevents the work function metal layer 102A deposited on the adjacent second semiconductor layers 54A - 54C from fusing, which ensures that the work function metal layer 102A has a uniform thickness around the periphery of the second semiconductor layers 54A - 54C. This improves the electrical performance of the device and reduces device defects.

[0066] Figure 20A and Figure 20B respectively show a detailed view of the region 101 according to some embodiments Figure 17A and Figure 17B a detailed view of the region 103, where the barrier layers 102B formed on adjacent items in the substrate 50 and the second semiconductor layers 54A - 54C do not fuse with each other. As Figure 20A and Figure 20BAs shown, the barrier layers 102B formed on adjacent items in the substrate 50 and the second semiconductor layers 54A - 54C are separated from each other by a certain distance. The filling material 102C can extend between the barrier layers 102B and fill the gaps between the barrier layers 102B.

[0067] Figure 21A and Figure 21B respectively show detailed views of the region 101 according to some embodiments Figure 17A and Figure 17B detailed views of the region 103, wherein the second semiconductor layers 54A - 54C and the substrate 50 have rounded corners. As Figure 21A and Figure 21B shown, the interface layer 100A, the first dielectric layer 100B, the work function metal layer 102A, and the barrier layer 102B can be conformally deposited such that the surface profile of each layer follows the surface profile of the underlying layer. As Figure 21A and Figure 21B further shown, some portions of the filling material 102C can extend between the barrier layers 102B formed on adjacent items in the substrate 50 and the second semiconductor layers 54A - 54C.

[0068] According to one embodiment, a semiconductor device includes: a semiconductor substrate; a first channel region located above the semiconductor substrate; a second channel region located above the first channel region; a gate dielectric layer surrounding the first channel region and the second channel region; a work function metal layer surrounding the gate dielectric layer; and a barrier layer surrounding the work function metal layer, wherein a first barrier layer surrounding the first channel region merges with a second barrier layer surrounding the second channel region. In one embodiment, the work function metal layer includes an n - type work function metal layer. In one embodiment, the work function metal layer includes a p - type work function metal layer. In one embodiment, the barrier layer includes silicon. In one embodiment, the work function metal layer includes titanium nitride. In one embodiment, the barrier layer includes tantalum nitride. In one embodiment, the barrier layer includes silicon. In one embodiment, the work function metal layer includes titanium aluminum carbide.

[0069] According to another embodiment, a method includes: forming a channel region over a semiconductor substrate; forming a gate dielectric layer surrounding the channel region; depositing a work function metal layer over the gate dielectric layer; depositing a barrier layer over the work function metal layer, the barrier layer, the work function metal layer, and the gate dielectric layer filling an opening between the semiconductor substrate and the channel region; and depositing a fill material over the barrier layer. In one embodiment, the barrier layer is deposited by atomic layer deposition (ALD). In one embodiment, the channel region is formed over a first region of the semiconductor substrate, and the method further includes: forming a second channel region over a second region of the semiconductor substrate; forming a gate dielectric layer surrounding the second channel region; and depositing a second work function metal layer over the gate dielectric layer in the second region, the second work function metal layer including a material different from that of the work function metal layer. In one embodiment, the method further includes: depositing a second barrier layer over the second work function metal layer, the second barrier layer including a material different from that of the barrier layer. In one embodiment, the method further includes: depositing a fill material over the second barrier layer, the fill material being deposited over the barrier layer and the second barrier layer simultaneously. In one embodiment, the method further includes: depositing a second barrier layer over the second work function metal layer, the second barrier layer being deposited simultaneously with the barrier layer and including the same material as the barrier layer.

[0070] According to yet another embodiment, a semiconductor device includes: a semiconductor substrate; a first channel region located over and separated from the semiconductor substrate; a gate dielectric layer surrounding the first channel region; a work function metal layer surrounding the gate dielectric layer, the thickness of the work function metal layer in a direction perpendicular to the main surface of the semiconductor substrate being equal to the thickness of the work function metal layer in a direction parallel to the main surface of the semiconductor substrate; and a barrier layer surrounding the work function metal layer. In one embodiment, the semiconductor device further includes: a second gate dielectric layer located on the semiconductor substrate; a second work function metal layer located on the second gate dielectric layer; and a second barrier layer located on the second work function metal layer, the second barrier layer being fused with the barrier layer between the first channel region and the semiconductor substrate. In one embodiment, the semiconductor device further includes: a second gate dielectric layer located on the semiconductor substrate; a second work function metal layer located on the second gate dielectric layer; a second barrier layer located on the second work function metal layer; and a fill material surrounding the barrier layer and located on the second barrier layer, the fill material extending from the barrier layer and the second barrier layer between the first channel region and the semiconductor substrate. In one embodiment, the thickness of the work function metal layer is to In one embodiment, the thickness of the barrier layer is to In one embodiment, the barrier layer includes silicon.

[0071] The foregoing has outlined the features of several embodiments, enabling those skilled in the art to better understand various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

[0072] Example 1. A semiconductor device, comprising: a semiconductor substrate; a first channel region located above the semiconductor substrate; a second channel region located above the first channel region; a gate dielectric layer surrounding the first channel region and the second channel region; a work function metal layer surrounding the gate dielectric layer; and a barrier layer surrounding the work function metal layer, wherein a first barrier layer surrounding the first channel region merges with a second barrier layer surrounding the second channel region.

[0073] Example 2. The semiconductor device according to Example 1, wherein the work function metal layer comprises an n-type work function metal layer.

[0074] Example 3. The semiconductor device according to Example 1, wherein the work function metal layer comprises a p-type work function metal layer.

[0075] Example 4. The semiconductor device according to Example 3, wherein the barrier layer comprises silicon.

[0076] Example 5. The semiconductor device according to Example 4, wherein the work function metal layer comprises titanium nitride.

[0077] Example 6. The semiconductor device according to Example 3, wherein the barrier layer comprises tantalum nitride.

[0078] Example 7. The semiconductor device according to Example 6, wherein the barrier layer comprises silicon.

[0079] Example 8. The semiconductor device according to Example 7, wherein the work function metal layer comprises titanium aluminum carbide.

[0080] Example 9. A method, comprising: forming a channel region above a semiconductor substrate; forming a gate dielectric layer surrounding the channel region; depositing a work function metal layer above the gate dielectric layer; depositing a barrier layer above the work function metal layer, wherein the barrier layer, the work function metal layer, and the gate dielectric layer fill an opening between the semiconductor substrate and the channel region; and depositing a filling material above the barrier layer.

[0081] Example 10. The method according to Example 9, wherein the barrier layer is deposited by atomic layer deposition (ALD).

[0082] Example 11. The method according to Example 9, wherein the channel region is formed over a first region of the semiconductor substrate, the method further comprising: forming a second channel region over a second region of the semiconductor substrate; forming the gate dielectric layer around the second channel region; and depositing a second work function metal layer over the gate dielectric layer in the second region, the second work function metal layer comprising a material different from the work function metal layer.

[0083] Example 12. The method according to Example 11, further comprising: depositing a second barrier layer over the second work function metal layer, the second barrier layer comprising a material different from the barrier layer.

[0084] Example 13. The method according to Example 12, further comprising: depositing a filling material over the second barrier layer, the filling material being deposited over both the barrier layer and the second barrier layer simultaneously.

[0085] Example 14. The method according to Example 11, further comprising: depositing a second barrier layer over the second work function metal layer, wherein the second barrier layer is deposited simultaneously with the barrier layer and comprises the same material as the barrier layer.

[0086] Example 15. A semiconductor device, comprising: a semiconductor substrate; a first channel region located over and separated from the semiconductor substrate; a gate dielectric layer surrounding the first channel region; a work function metal layer surrounding the gate dielectric layer, wherein a thickness of the work function metal layer in a direction perpendicular to a main surface of the semiconductor substrate is equal to a thickness of the work function metal layer in a direction parallel to the main surface of the semiconductor substrate; and a barrier layer surrounding the work function metal layer.

[0087] Example 16. The semiconductor device according to Example 15, further comprising: a second gate dielectric layer located on the semiconductor substrate; a second work function metal layer located on the second gate dielectric layer; and a second barrier layer located on the second work function metal layer, wherein the second barrier layer merges with the barrier layer between the first channel region and the semiconductor substrate.

[0088] Example 17. The semiconductor device according to Example 15 further includes: a second gate dielectric layer located on the semiconductor substrate; a second work function metal layer located on the second gate dielectric layer; a second barrier layer located on the second work function metal layer; and a filling material surrounding the barrier layer and located on the second barrier layer, wherein the filling material extends from the barrier layer and the second barrier layer between the first channel region and the semiconductor substrate.

[0089] Example 18. The semiconductor device according to Example 15, wherein the thickness of the work function metal layer is to

[0090] Example 19. The semiconductor device according to Example 18, wherein the thickness of the barrier layer is to

[0091] Example 20. The semiconductor device according to Example 15, wherein the barrier layer includes silicon.

Claims

1. A semiconductor device, comprising: A semiconductor substrate; A first channel region located above the semiconductor substrate; A second channel region located above the first channel region; A gate dielectric layer surrounding the first channel region and the second channel region; A work function metal layer surrounding the gate dielectric layer; And A barrier layer disposed around the work function metal layer to prevent metal migration from the work function metal layer, wherein a first barrier layer surrounding the first channel region merges with a second barrier layer surrounding the second channel region.

2. The semiconductor device according to claim 1, wherein, The work function metal layer includes an n-type work function metal layer.

3. The semiconductor device according to claim 1, wherein, The work function metal layer includes a p-type work function metal layer.

4. The semiconductor device according to claim 3, wherein, The barrier layer includes silicon.

5. The semiconductor device according to claim 4, wherein, The work function metal layer includes titanium nitride.

6. The semiconductor device according to claim 3, wherein, The barrier layer includes tantalum nitride.

7. The semiconductor device according to claim 6, wherein, The barrier layer includes silicon.

8. The semiconductor device according to claim 7, wherein, The work function metal layer includes titanium aluminum carbide.

9. A method for manufacturing a semiconductor device, comprising: Forming a first channel region above a semiconductor substrate; Forming a second channel region above the first channel region; Forming a first gate dielectric layer surrounding the first channel region and a second gate dielectric layer surrounding the second channel region; Depositing a first work function metal layer on the first gate dielectric layer and depositing a second work function metal layer on the second gate dielectric layer; Depositing a first barrier layer on the first work function metal layer and depositing a second barrier layer on the second work function metal layer to prevent metal migration from the work function metal layer, wherein the first barrier layer surrounding the first channel region merges with the second barrier layer surrounding the second channel region.

10. The method according to claim 9, wherein, The first barrier layer and the second barrier layer are deposited by atomic layer deposition (ALD).

11. The method according to claim 9, wherein, The second work function metal layer includes a material different from that of the first work function metal layer.

12. The method according to claim 11, wherein, The second barrier layer includes a material different from that of the first barrier layer.

13. The method according to claim 12 further comprises: Depositing a filling material on the second barrier layer, and the filling material is simultaneously deposited on the first barrier layer and the second barrier layer.

14. The method according to claim 11, wherein, The second barrier layer is deposited simultaneously with the first barrier layer and includes the same material as the first barrier layer.

15. A semiconductor device, comprising: A semiconductor substrate; A first channel region located above the semiconductor substrate and separated from the semiconductor substrate; A first gate dielectric layer surrounding the first channel region; A first work function metal layer surrounding the gate dielectric layer, wherein the thickness of the work function metal layer in a direction perpendicular to the main surface of the semiconductor substrate is equal to the thickness of the work function metal layer in a direction parallel to the main surface of the semiconductor substrate; A first barrier layer disposed around the work function metal layer to prevent metal migration from the work function metal layer; A second gate dielectric layer located on the semiconductor substrate; A second work function metal layer located on the second gate dielectric layer; and A second barrier layer located on the second work function metal layer, wherein the second barrier layer merges with the first barrier layer between the first channel region and the semiconductor substrate.

16. The semiconductor device according to claim 15 further comprises: A filling material located on the second barrier layer.

17. The semiconductor device according to claim 15, wherein, The thickness of the first work function metal layer is to 18. The semiconductor device according to claim 17, wherein, The thickness of the first barrier layer is to 19. The semiconductor device according to claim 15, wherein, The first barrier layer comprises silicon.

Images