integrated circuit

Abstract

An integrated circuit and a semiconductor device are provided herein. The semiconductor device includes a substrate; an input / output device located on the substrate; and a core device located on the substrate. The input / output device includes a first gate structure having an interface layer; a first high-k dielectric stack located on the interface layer; and a conductive layer located on and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having an interface layer; a second high-k dielectric stack located on the interface layer; and a conductive layer located on and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes a second high-k dielectric stack and a third dielectric layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to an integrated circuit device, and more particularly to an integrated circuit device having gate dielectric layers of different thicknesses and a method for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Technological advances in integrated circuit materials and design have produced generations of integrated circuits, each with smaller and more complex circuits than the previous one. Throughout the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has generally increased as geometry (i.e., the minimum device size or linewidth that can be manufactured using a process) has decreased. These process sizes have the advantages of increasing production efficiency and reducing associated costs. However, with these size reductions, the complexity of processing and manufacturing the integrated circuits has also increased.

[0003] For example, as integrated circuit technology progresses toward smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure, or a portion thereof, disposed on more than one side of a channel region. Gate-all-around (GAA) transistors are an example of multi-gate devices, and they have become a popular and promising candidate for high-performance and low-leakage applications. Compared to planar transistors, such a configuration provides superior channel control and significantly reduces short-channel effects (particularly by reducing sub-threshold leakage). A gate-all-around transistor has a gate structure that extends partially or completely around the channel region, providing access to the channel region from each side. The channel region of the all-around gate transistor can be formed by nanowires, nanosheets, other nanostructures, and / or other suitable structures. In some embodiments, such a channel region includes a plurality of vertically stacked nanowires (which extend horizontally to provide a horizontally aligned channel).

[0004] Integrated circuit devices include transistors with different functions, such as input / output functions and core functions. These different functions require transistors to have different structures. At the same time, it is advantageous to have similar processes and similar process windows to manufacture these different transistors to reduce costs and improve yields. Although existing fully wrapped gate transistors and processes are generally able to meet their intended purposes, they still cannot fully meet all requirements. For example, different core functions (such as high-speed applications and low-power (and / or low leakage current) applications) may require different gate dielectric layer thicknesses for fully wrapped gate transistors. Therefore, how to continue to shrink the gate stacks used for input / output devices and core devices with different gate dielectric layer thicknesses to suit different applications is a challenge facing the semiconductor industry. The goal of the present disclosure is to solve the above problems and other related problems. Summary of the Invention

[0005] One embodiment of the present disclosure is an integrated circuit, comprising: a substrate having a first region and a second region; a first wraparound gate device located in the first region, wherein the first wraparound gate device comprises: a first channel member extending longitudinally in a first direction; and a first gate structure wrapping a channel region of the first channel member, wherein the first gate structure comprises a first interface layer, the first interface layer having a first thickness measured in a second direction substantially perpendicular to the first direction; a second wraparound gate device located in the first region, wherein the second wraparound gate device comprises: a second channel member extending longitudinally in the first direction; and a second gate structure wrapping the channel region of the second channel member, wherein the second gate structure comprises a second interface layer, the second interface layer having a second thickness measured in the second direction, and the second thickness is greater than the first thickness; and a third wraparound gate device located in the second region, wherein the third wraparound gate device comprises: a third channel member extending longitudinally in the first direction; and a third gate structure wrapping the channel region of the third channel member, wherein the third gate structure comprises a third interface layer, the third interface layer having a third thickness measured in the second direction, and the third thickness is greater than the second thickness.

[0006] One embodiment of the present disclosure is to disclose an integrated circuit device, comprising: a core device, comprising: a first channel member; a first gate structure, engaged with the first channel member, wherein the first gate structure includes a first interface layer, wherein the first interface layer wraps the channel region of the first channel member; a second channel member; and a second gate structure, engaged with the second channel member, wherein the second gate structure includes a second interface layer, wherein the second interface layer wraps the channel region of the second channel member, wherein the thickness of the second interface layer in a direction approximately perpendicular to the longitudinal axis of the second channel member is greater than the thickness of the first interface layer in a direction approximately perpendicular to the longitudinal axis of the first channel member; and an input / output device, comprising: a third channel member; and a third gate structure, engaged with the third channel member, wherein the third gate structure includes a third interface layer, wherein the third interface layer wraps the channel region of the third channel member, wherein the thickness of the third interface layer in a direction approximately perpendicular to the longitudinal axis of the third channel member is greater than the thickness of the second interface layer.

[0007] One embodiment of the present disclosure is a method for manufacturing an integrated circuit device, comprising: providing a substrate, wherein the substrate has a first channel member, a second channel member, and a third channel member, wherein the first channel member and the second channel member are located in a core region of the integrated circuit, and the third channel member is located in an input / output region of the integrated circuit; forming a first oxide layer and a second oxide layer by a first process, wherein the first oxide layer encapsulates a channel region of the first channel member, and the second oxide layer encapsulates a channel region of the second channel member; forming a third oxide layer by a second process different from the first process, wherein the third oxide layer encapsulates the channel region of the third channel member; forming a first dielectric layer, a second dielectric layer, and a third dielectric layer on the first oxide layer, the second oxide layer, and the third oxide layer, respectively; forming a first cap layer, a second cap layer, and a third cap layer on the first dielectric layer, the second dielectric layer, and the third dielectric layer, respectively; removing the second cap layer to expose the second dielectric layer, wherein after removing the second cap layer, the first cap layer and the third cap layer remain on the first dielectric layer and the third dielectric layer, respectively; and performing an annealing process after removing the second cap layer to increase the thickness of the second oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description is accompanied by the accompanying drawings for a complete disclosure. It should be noted that, in accordance with common practice in the industry, the drawings are not necessarily drawn to scale. In fact, the dimensions of elements may be arbitrarily enlarged or reduced for clarity of illustration.

[0009] Figure 1A and Figure 1B is a schematic block diagram of a semiconductor device and corresponding partial cross-sectional diagrams of three gate stacks for input / output and core devices according to some embodiments.

[0010] Figure 2A and Figure 2B According to some embodiments, Figure 1A and Figure 1B A flow chart of a method for a semiconductor device is shown.

[0011] Figure 3 is a perspective diagram of a semiconductor device according to some embodiments.

[0012] Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 and Figure 18 A semiconductor device according to some embodiments is Figure 2A and Figure 2B Schematic cross-section during the process of the method described.

[0013] The description of the accompanying drawings is as follows:

[0014] 10: Semiconductor structure (integrated circuit)

[0015] 12: Core Area

[0016] 14: Input / Output Area

[0017] 16: Installation area

[0018] 18: Fully wound gate device

[0019] 20: Fully wound gate device

[0020] 22: Device area

[0021] 24: The third fully wound gate device

[0022] 26: Channel components

[0023] 27: Substrate

[0024] 28a: Gate dielectric layer

[0025] 28b: Gate dielectric layer

[0026] 28c: Gate dielectric layer

[0027] 30a: Interface layer

[0028] 30b: Interface layer

[0029] 30c: Interface layer

[0030] 32a: High dielectric constant dielectric layer

[0031] 32b: High-k dielectric layer

[0032] 32c: High dielectric constant dielectric layer

[0033] 36: Isolation Structure

[0034] 100: Method

[0035] 102: Operation steps

[0036] 104: Operation steps

[0037] 106: Operation steps

[0038] 108: Operation steps

[0039] 110: Operation steps

[0040] 112: Operation steps

[0041] 114: Operation steps

[0042] 116: Operation steps

[0043] 118: Operation steps

[0044] 120: Operation steps

[0045] 122: Operation steps

[0046] 124: Operation steps

[0047] 126: Operation steps

[0048] 200: Semiconductor structure (semiconductor device)

[0049] 202: First Area (Core Area)

[0050] 204: Second area (input / output area)

[0051] 206a: Device structure (all-wrap gate core device structure)

[0052] 206b: Device structure (full-wrap gate core device structure)

[0053] 206c: Device structure (full-wrap gate input / output device structure)

[0054] 208: Substrate

[0055] 210: Isolation Structure

[0056] 212a: Fin (stacked fins)

[0057] 212b: Fin (stacked fins)

[0058] 212c: Fin (stacked fins)

[0059] 216: Virtual gate structure

[0060] 220: Semiconductor layer (nanowire)

[0061] 222: Semiconductor layer

[0062] 230: Virtual interface layer

[0063] 232: Virtual gate electrode

[0064] 234: First gate hard mask layer

[0065] 236: Second gate hard mask layer

[0066] 238: Gate spacer

[0067] 240: Source / drain components

[0068] 242: Contact Etch Stop Layer

[0069] 244: Interlayer dielectric layer

[0070] 246: Gate trench

[0071] 248: Interface layer

[0072] 249: Mask layer

[0073] 250a: Gate dielectric layer

[0074] 250b: Gate dielectric layer

[0075] 250c: Gate dielectric layer

[0076] 252a: Interface layer

[0077] 252b: Interface layer

[0078] 252c: Interface layer

[0079] 254a: High dielectric constant dielectric layer

[0080] 254b: High dielectric constant dielectric layer

[0081] 254c: High dielectric constant dielectric layer

[0082] 260: Cover layer (thickness adjustment layer)

[0083] 261: Mask layer

[0084] 270: Annealing process

[0085] 271: Annealing process

[0086] 272: Part

[0087] 274: Movement of oxygen atoms

[0088] 276: Amorphous silicon layer

[0089] 282: Gate electrode layer

[0090] P1: channel pitch

[0091] S1: Interval

[0092] TIL1: thickness

[0093] TIL2: thickness

[0094] TIL3: thickness DETAILED DESCRIPTION

[0095] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if this specification describes a first component formed on or above a second component, it means that it may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component, so that the first component and the second component may not be in direct contact. In addition, the different examples disclosed below may reuse the same reference symbols and / or marks. These repetitions are for the purpose of simplicity and clarity, and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.

[0096] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "higher," and the like may be used to facilitate description of the relationship between one component or feature and another component or feature in the accompanying drawings. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the accompanying drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted based on the orientation after the rotation. In addition, unless otherwise defined, when "approximately," "approximately," or other similar terms are used to describe a value or a range of values, the term is intended to cover numbers within a range of + / - 10% of the stated value. For example, the technical term "approximately 5 nm" covers a size range from 4.5 nm to 5.5 nm.

[0097] The present disclosure relates generally to semiconductor devices, and more particularly to integrated circuits (ICs) having input / output (I / O) devices (or transistors) and core devices (or transistors) having nanowire channels on the same substrate. In one embodiment, at least two gate-all-around (GAA) devices with stacked nanowire channels are placed in the core region of the IC, for example, to implement high-speed applications and low-power (and / or low-leakage) applications, respectively, while a third gate-all-around device is placed in the I / O region of the IC to implement I / O applications (including electrostatic discharge (ESD) applications).

[0098] The operating voltage of the input / output region can be similar to the external voltage (the voltage level of the external / peripheral circuit) and higher than the operating voltage of the core region. In order to accommodate the higher operating voltage, the transistors in the input / output region may have a thicker gate dielectric layer than the transistors in the core region. In the core region, the thickness of the gate dielectric layer of the transistor is related to the circuit speed and leakage current performance. With a thinner gate dielectric layer, the fully wrapped gate device is more suitable for high-speed applications. With a thicker gate dielectric layer, the fully wrapped gate device is more suitable for low-power (and / or low leakage current) applications. In other embodiments, the fully wrapped gate device for high-speed applications has a thinner gate dielectric layer than the fully wrapped gate device for low-power (and / or low leakage current) applications. The embodiments of the present disclosure provide flexible design integration solutions to accommodate different circuits in the same integrated circuit. The manufacturing method according to the present disclosure can be easily integrated into existing semiconductor manufacturing processes. Reference Figures 1A to 18 Details of various embodiments of the present disclosure are described.

[0099] Please also refer to Figure 1A and Figure 1B , which shows a schematic block diagram of a semiconductor structure 10 (e.g., an integrated circuit 10) fabricated according to an embodiment of the present disclosure. The integrated circuit 10 includes a core region 12 and an input / output region 14. The core region 12 includes logic circuits, memory circuits, and other core circuits. The input / output region 14 includes an input / output unit, an electrostatic discharge unit, and other circuits. The core region 12 includes a device region 16, and a fully wrapped gate device 18 and a fully wrapped gate device 20 are formed in the device region 16. In some embodiments, as Figure 1B As shown, the full-wrap gate device 18 and the full-wrap gate device 20 are placed adjacent to (or abutting) each other, wherein Figure 1B is a partial cross-sectional schematic diagram. In some other embodiments, the full-wrap gate device 18 and the full-wrap gate device 20 are separated from each other, for example, by other full-wrap gate devices located between the two or in different device areas of the core area 12. The input / output region 14 includes a device area 22, and a third full-wrap gate device 24 is formed in the device area 24. The full-wrap gate device 24 is located at a position separated from the full-wrap gate devices 18 and 20 by a spacing "S1". In the embodiment shown, the spacing S1 is at least 4 times the gate pitch of the full-wrap gate device 18 or 20 or at least 4 times the channel pitch of the full-wrap gate device 18 or 20. The center-to-center distance or the edge-to-edge distance between two adjacent gates or channels can be used to define the gate pitch and the channel pitch. In Figure 1B An exemplary channel pitch P1, which is the edge-to-edge distance between two adjacent channels, is shown in FIG. The spacing S1 is designed to simplify the process by providing a margin when patterning the device regions 16 and 22 .

[0100] Each of the three wraparound gate devices 18, 20, and 24 includes a plurality of channel members 26 stacked vertically above a substrate 27. An isolation structure 36 is formed in substrate 27 adjacent to each of the wraparound gate devices 18, 20, and 24. The number of channel members 26 in each wraparound gate device can range from two to ten. Each channel member 26 comprises silicon or other suitable semiconductor material. The channel members 26 of the wraparound gate device 18 are surrounded by a gate dielectric layer 28a, which may include an interfacial layer 30a and a high-k dielectric layer 32a. The channel members 26 of the wraparound gate device 20 are surrounded by a gate dielectric layer 28b, which may include an interfacial layer 30b and a high-k dielectric layer 32b. The channel members 26 of the wraparound gate device 24 are surrounded by a gate dielectric layer 28c, which may include an interfacial layer 30c and a high-k dielectric layer 32c. A gate electrode (not shown) wraps around or over each gate dielectric layer 28a, 28b, and 28c. The gate electrode may include one or more work function metal layers and bulk metal layers. In this embodiment, wraparound gate devices 18 and 20 share the same gate electrode, and wraparound gate device 24 has a separate gate electrode.

[0101] The wraparound gate devices 18, 20, and 24 have different gate dielectric thicknesses. For example, the wraparound gate device 24 in the input / output region 14 includes a gate dielectric layer 28c having a first thickness (capacitance equivalent thickness (CET)), which is the thickest gate dielectric layer suitable for high voltage applications. The wraparound gate device 20 in the core region 12 includes a gate dielectric layer 28b having a second thickness, which is a medium thickness (medium CET) suitable for low power and low leakage current applications. The wraparound gate device 18 in the core region 12 includes a gate dielectric layer 28a having a third thickness, which is the thinnest gate dielectric layer (thinnest CET) best suited for high speed applications. Therefore, the integrated circuit 10 can be referred to as a tri-gate transistor device. In other embodiments, among the gate dielectric layers 28a, 28b, and 28c, the high-k dielectric layers 32a, 32b, and 32c may have substantially the same physical thickness (eg, from about 100 nm to about 100 nm). to approximately ), and the interface layers 30a, 30b, and 30c have different physical thicknesses. As an example, the interface layer 30b can be about 10% to about 20% thicker than the interface layer 30a. If the thickness of the interface layer 30b is less than 10% thicker than the thickness of the interface layer 30a, leakage current problems may begin to degrade the circuit performance; if the thickness of the interface layer 30b is greater than 20% thicker than the thickness of the interface layer 30a, the speed of the core device may be slowed down too much. The thickness of the interface layer 30c can be about 2 times to about 4 times the thickness of the interface layer 30a. If the thickness of the interface layer 30c is less than about 2 times thicker than the thickness of the interface layer 30a, the high voltage performance will be reduced; the thickness of the interface layer 30c will be reduced. If the thickness of the interface layer 30c is greater than 4 times thicker than the thickness of the interface layer 30a, the gate drive capability of the input / output device will be weakened due to the large oxide thickness. In a specific example, the thickness of the interface layer 30a is from about (Angstroms) to approximately The ratio of the thickness of the interface layer 30b to the thickness of the interface layer 30a is about 1.1:1 to about 1.2:1, and the thickness of the interface layer 30c is about to approximately The range between.

[0102] Figure 2A and Figure 2B 1 is a flow chart of a method 100 for forming a tri-gate transistor device according to various embodiments of the present disclosure. Figures 3 to 17 describe Figure 2A and Figure 2B ,in Figures 3 to 17 is a schematic partial cross-sectional view of a workpiece at various stages of manufacture according to method 100. Method 100 is merely an example and is not intended to limit the present disclosure beyond the scope expressly recited in the claims. Additional steps may be provided before, during, and after method 100, and some of the steps described may be moved, replaced, or omitted for additional embodiments of method 100. Figures 3 to 17 Additional components are added to the semiconductor device shown, and some of the components described below may be replaced, modified, or omitted in other embodiments of the semiconductor device.

[0103] In operation 102, method 100 ( Figure 2A ) provides a semiconductor structure 200 (or semiconductor device 200) including a first region 202 and a second region 204, such as Figure 3As shown. Each of regions 202 and 204 includes a device region that includes transistors that provide different functions. In some embodiments, first region 202 is a core region, and second region 204 is an input / output (I / O) region. In those embodiments, the core device region refers to a device region that includes logic cells (e.g., inverters, NAND gates, NOR gates, AND gates, OR gates, flip-flops) and memory cells (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), and flash memory). The I / O device region refers to a device region between the core device region and external / peripheral circuits (e.g., circuits on a printed circuit board (PCB) on which semiconductor device 200 is mounted). In the illustrated embodiment, core region 202 includes a fully wrapped gate core device structure 206a for high-speed applications and a fully wrapped gate core device structure 206b for low-power and low-leakage current applications. The I / O region 204 includes a wrap-around gate I / O device structure 206 c for I / O or ESD applications.

[0104] Each of the device structures 206a, 206b, and 206c includes a substrate 208, an isolation structure 210, a fin 212a, 212b, or 212c, wherein the fin 212a, 212b, or 212c includes vertically stacked alternating semiconductor layers 220 and 222 (also referred to as stacked fins 212a, 212b, or 212c), and a dummy gate structure 216 that engages with the stacked fin 212a, 212b, or 212c.

[0105] In some embodiments, substrate 208 comprises silicon. Alternatively or additionally, substrate 208 comprises another elemental semiconductor (e.g., germanium); a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or indium antimonide); an alloy semiconductor (e.g., silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP)); or combinations thereof. In some embodiments, substrate 208 comprises one or more Group III-V materials, one or more Group II-IV materials, or combinations thereof. In some embodiments, substrate 208 is a semiconductor-on-insulator (SOS) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SOS substrate can be manufactured by using separation by implantation of oxygen (SIMOX), chip bonding, and / or other suitable methods. Substrate 208 may include various doped regions configured according to the design requirements of semiconductor device 200. The P-type doped region may include a p-type dopant, such as boron, indium, other p-type dopant, or a combination thereof. The N-type doped region may include an n-type dopant, such as phosphorus, arsenic, other n-type dopant, or a combination thereof. In some embodiments, substrate 208 includes a doped region formed by a combination of p-type dopant and n-type dopant. Various doped regions can be formed directly on and / or in substrate 208, for example, to provide a p-type well structure, an n-type well structure, a dual-well structure, a raised structure, or a combination thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be performed to form the various doped regions. In some embodiments, a p-type wraparound gate device and a p-type FinFET device are formed above the n-well, while an n-type wraparound gate device and an n-type FinFET device are formed above the p-well. Each of device structures 206a, 206b, and 206c can independently be an n-type or p-type device.

[0106] The isolation structure 210 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. The isolation structure 210 may be a shallow trench isolation (STI) feature. Other isolation structures are also possible, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures. The isolation structure 210 may include a multi-layer structure, for example, having one or more thermal oxide liners.

[0107] Each of the stacked fins 212a, 212b, and 212c includes alternating semiconductor layers 220 and 222. The first semiconductor material in semiconductor layer 220 and the second semiconductor material in semiconductor layer 222 are different in material and / or composition. Each of the first and second semiconductor materials may include silicon, germanium, a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide), or an alloy semiconductor (including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP)). In the present embodiment, semiconductor layer 220 includes silicon, and semiconductor layer 222 includes germanium or a silicon-germanium alloy. The semiconductor layers 220 and 222 in the stacked fins 212 a and 212 b may additionally include dopants (eg, phosphorus, arsenic, boron, and / or indium) to improve the performance of subsequently formed all-around gate transistors.

[0108] The stacked fins 212a, 212b, and 212c can be formed by epitaxially growing semiconductor layers 220 and 222 on the substrate 208 and then patterning them by any suitable method to form individual independent stacked fins 212a, 212b, and 212c. For example, the structure can be patterned using one or more photolithography processes, including a double patterning process or a multiple patterning process. Generally, the double patterning or multiple patterning process combines a photolithography process with a self-aligned process to create a pattern with a smaller pitch, for example, a pattern with a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on the substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process. Thereafter, the sacrificial layer is removed and the stacked fins 212a, 212b, and 212c can be patterned using the remaining spacers or mandrels by etching the initial semiconductor layers 220, 222 and the substrate 208. The etching process includes dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In the embodiment shown, the stacked fins 212a, 212b, and 212c extend longitudinally in the same direction (with longitudinal axes parallel). In some embodiments, the stacked fins 212a and 212b in the core region 202 extend longitudinally in the same direction (e.g., along the y-direction), while the stacked fins 212c in the input / output region 204 can extend longitudinally in a different direction, for example, along a vertical direction (e.g., along the x-direction) or other directions.

[0109] The dummy gate structure 216 reserves an area for a metal gate stack and includes a dummy interface layer 230, a dummy gate electrode 232, a first gate hard mask layer 234, and a second gate hard mask layer 236. The dummy interface layer 230 is formed on the top surface and sidewall surfaces of each of the stacked fins 212a, 212b, and 212c, and on the top surface of the isolation structure 210. The dummy interface layer 230 may include a dielectric material, such as an oxide layer (e.g., silicon dioxide (SiO2)) or an oxynitride layer (e.g., silicon oxynitride (SiON)), and may be deposited by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods.

[0110] The dummy gate electrode 232 may include polysilicon (poly-Si) and may be formed by a suitable deposition process, such as low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD). Each of the gate hard mask layers 234 and 236 may include one or more layers of dielectric material, such as silicon oxide and / or silicon nitride, and may be formed by chemical vapor deposition or other suitable methods. For example, the first gate hard mask layer 234 may include a silicon oxide layer adjacent to the dummy gate electrode 232, and the second gate hard mask layer 236 may include a silicon nitride layer. The various film layers 230, 232, 234, and 236 may be patterned by photolithography and etching processes.

[0111] To make the description and drawings clearer, Figures 4 to 6 Including along Figure 3 A partial cross-sectional view of the fully wrapped gate core device structure 206a is shown along line AA, where line AA passes through each channel region along the length direction of the stacked fins 212a (in the YZ plane). The cross-sectional views of the fully wrapped gate core device structure 206b and the fully wrapped gate input / output device structure 206c in the YZ plane are similar to those in FIG. Figures 4 to 6 The cross-sectional schematic diagram shown is therefore omitted for the sake of brevity. Figures 7 to 18 Including along Figure 3 A partial cross-sectional view of the semiconductor device 200 is shown along line BB, where line BB passes through the plurality of channel regions along the length direction (in the XZ plane) of the stacked fins 212 a , 212 b , and 212 c .

[0112] In operation 104, method 100 ( Figure 2A ) to form a gate spacer 238 on the sidewall of the dummy gate structure 216, such as Figure 4 As shown. The gate spacer 238 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other dielectric materials, or combinations thereof, and may include one or more layers of material. The gate spacer 238 may be formed by depositing a spacer material as a capping layer on the semiconductor device 200. Thereafter, the spacer material is etched by an anisotropic etching process. The portion of the spacer material located on the sidewalls of the dummy gate structure 216 becomes the gate spacer 238. Operation step 104 further forms a source / drain feature 240 in the source / drain region, as shown in FIG. Figure 5As shown. For example, operation 104 may etch recesses in the stacked fins 212a, 212b, and 212c and epitaxially grow semiconductor material in the recesses. The semiconductor material may be caused to protrude above the top surface of each fin. Operation 104 may form source / drain features 240 for n-type and p-type devices, respectively. For example, operation 104 may form source / drain features 240 having n-type doped silicon for n-type devices and form source / drain features 240 having p-type doped silicon germanium for p-type devices. Operation 104 may further form a contact etch stop layer (CESL) 242 on the source / drain features 240 and form an interlayer dielectric (ILD) layer 244 on the CESL 242. The contact etch stop layer 242 may include silicon nitride, silicon oxynitride, silicon nitride containing oxygen (O) or carbon (C), and / or other materials; and may be formed by chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition, or other suitable methods. The interlayer dielectric layer 244 may include tetraethylorthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The interlayer dielectric layer 244 may be formed using chemical vapor deposition, flowable chemical vapor deposition (FCVD), or other suitable methods. After operation 104, a chemical mechanical polishing process may be performed to remove excess dielectric material. In some embodiments, the CMP process also removes the gate hard masks 234 and 236 and exposes the dummy gate electrode 232 .

[0113] In operation 106, method 100 ( Figure 2A ) removes the dummy gate electrode 232, thereby forming a gate trench 246, as shown in FIG. Figure 6As shown. Operation step 106 may include one or more etching processes that are selective to the material in the dummy gate electrode 232. By selecting an etchant that resists etching the gate spacer 238 and the interlayer dielectric layer 244, portions of the gate spacer 238 and the interlayer dielectric layer 244 adjacent to the dummy gate electrode 232 are exposed in the gate trench 246 without substantial etching loss. This may increase the tolerance of the photolithography process. The etching process may include any suitable etching technique, such as wet etching, dry etching, reactive ion etching, ashing and / or other etching methods. In one embodiment, the etching process is a dry etching process using a fluorine-based etchant (e.g., perfluoromethane (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), etc.). Operation step 106 also includes removing the dummy interface layer 230 from the gate trench 246, such as Figure 7 Shown.

[0114] In operation 108, method 100 ( Figure 2A ) Release the channel members in the channel regions of the all-around gate device structures 206a, 206b, and 206c from the gate trench 246, as shown in FIG. Figure 8 As shown. In the embodiment shown, the channel member is a nanowire. The technical term "nanowire" is used herein to refer to any material portion having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of this portion. Therefore, this technical term refers to elongated material portions with circular and substantially circular cross-sections, as well as, for example, beam-shaped or strip-shaped material portions with cylindrical or substantially rectangular cross-sections. For simplicity and clarity, the semiconductor layer 220 is represented as a nanowire 220 after operation step 110. In the present embodiment, the semiconductor layer 220 includes silicon, and the semiconductor layer 222 includes silicon germanium. The plurality of semiconductor layers 222 can be selectively removed. In some embodiments, the selective removal process includes using a suitable oxidant (e.g., ozone) to oxidize the plurality of semiconductor layers 222. Thereafter, the oxidized semiconductor layers 222 can be selectively removed. In other embodiments, operation 110 includes a dry etching process to selectively remove the semiconductor layer 222. The dry etching process is performed by, for example, applying HCl gas or a gas mixture of perfluoromethane (CF4), sulfur hexafluoride (SF6), and trifluoromethane (CHF3) at a temperature of 500°C to 700°C. Figure 8 As shown, vertically stacked nanowires 220 are formed in the channel regions of the all-around gate core device structures 206a, 206b and the channel region of the all-around gate input-output device structure 206c. Figure 9Each stack is shown with four nanowires 220, but in other embodiments there may be fewer or more vertically stacked nanowires 220. For example, the number of nanowires 220 in each all-around gate device structure may be in the range of 2 to 10.

[0115] In operation 110, method 100 ( Figure 2A ) forms an interface layer 248, which wraps all nanowires 220 located in the all-around gate device structures 206a, 206b, and 206c. The interface layer 248 may include a dielectric material, such as an oxide layer (e.g., silicon dioxide) or an oxynitride layer (e.g., silicon oxynitride), and may be deposited by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, and / or other suitable methods. The interface layer 248 has a thickness suitable for input / output applications, for example, a thickness ranging from about 1000 Å to about 1000 Å. to approximately In the embodiment shown, the interface layer 248 is a silicon dioxide layer deposited by a plasma-assisted atomic layer deposition process, which is suitable for growing relatively thick oxide layers. The plasma-assisted atomic layer deposition process can apply a plasma containing oxygen (O2) and argon (Ar) at a temperature range of from about 100°C to about 200°C with a radio frequency power of from about 500W to about 700W. After deposition, the interface layer 248 can further undergo a post oxide annealing (POA) process to improve the quality of the gate oxide. As shown subsequently, the interface layer 248 remains on the nanowires 220 in the fully wrapped gate input and output device structure 206c as an input and output oxide layer, while other portions of the interface layer 248 will be removed from the other nanowires 220 in the fully wrapped gate core device structures 206a and 206b.

[0116] In operation 112, method 100 ( Figure 2A ) a mask layer 249 is formed on the input / output region and the interface layer 248 is removed from the nanowires 220 in the all-around gate core device structures 206a and 206b. Figure 10As shown. The interfacial layer 248 can be removed by, for example, wet etching, dry etching, reactive ion etching, or other suitable etching methods. For example, operation step 108 can apply a hydrofluoric acid (HF-based) wet etchant for wet etching or an ammonia (NH3) and hydrogen (H2) mixture for dry etching. During this operation step, the mask layer 249 covers the portion of the interfacial layer 248 located in the all-around gate input and output device structure 206c. In the discussion below, the remaining portion of the interfacial layer 248 is labeled as interfacial layer 252c. In some embodiments, the mask layer 249 is a photoresist layer, such as a bottom antireflective coating (BARC).

[0117] In operation 114, the method 100 forms another interfacial layer in the gate-all-around core device structures 206a and 206b to encapsulate the nanowires 220, such as Figure 11 As shown. Interface layer 252a wraps around nanowires 220 in all-around gate core device structure 206a, while interface layer 252b wraps around nanowires 220 in all-around gate core device structure 206b. Interface layers 252a and 252b may include a dielectric material, such as an oxide layer (e.g., silicon dioxide) or an oxynitride layer (e.g., silicon oxynitride), and may be deposited by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, and / or other suitable methods. In some embodiments, each of interface layers 252a and 252b may have a thickness suitable for high-speed applications, for example, a thickness ranging from about 1000 Å to about 1000 Å. to approximately In some embodiments, the interface layers 252a and 252b are grown by a process different from the process used to form the interface layer 252c. In the illustrated embodiment, the interface layers 252a and 252b are silicon dioxide layers formed in a solution containing hydrogen peroxide (H2O2) (e.g., SC1, SC2, and SPM). During operation 114, the mask layer 249 protects the interface layer 252c from thickness changes. After operation 114, the mask layer 249 can be removed by an etching process or other suitable process (e.g., ashing or resist stripping).

[0118] In operation 116, method 100 ( Figure 2B ) forming a high-k dielectric layer 254 in the gate trench 246, as shown in FIG. Figure 12As shown, gate dielectric layers 250a, 250b, and 250c (collectively, gate dielectric layers 250) are formed in the channel regions of the wrapped gate core device structure 206a, the wrapped gate core device structure 206b, and the wrapped gate input / output device structure 206c, respectively. Gate dielectric layer 250a includes an interface layer 252a and a high-k dielectric layer 254a. The interface layer 252a surrounds the nanowires 220 of the wrapped gate core device structure 206a, while the high-k dielectric layer 254a surrounds the interface layer 252a. Gate dielectric layer 250b includes an interface layer 252b and a high-k dielectric layer 254b. The interface layer 252b surrounds the nanowires 220 of the wrapped gate core device structure 206b, while the high-k dielectric layer 254b surrounds the interface layer 252b. The gate dielectric layer 250c includes an interfacial layer 252c and a high-k dielectric layer 254c. The interfacial layer 252c surrounds the nanowires 220 of the all-around gate input / output device structure 206c, while the high-k dielectric layer 254c surrounds the interfacial layer 252c. In the illustrated embodiment, the interfacial layers 252a, 252b, 252c and the high-k dielectric layers 254a, 254b, 254c are deposited as substantially compliant films. The high-k dielectric layers 254a, 254b, and 254c can have substantially the same thickness. The high-k dielectric layer 254 can be deposited using any suitable technique, such as atomic layer deposition, chemical vapor deposition, metal-organic chemical vapor deposition (MOCVD), physical vapor deposition, thermal oxidation, combinations thereof, and / or other suitable techniques. The high-k dielectric layer 254 may include a metal oxide (e.g., lanthanum oxide (LaO), aluminum oxide (AlO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum pentoxide (Ta2O5), yttrium trioxide (Y2O3), strontium titanate (SrTiO3, STO), barium titanate (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium zirconium oxide (HfZrO), hafnium lanthanum oxide (HfLaO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), barium strontium titanate ((Ba,Sr)TiO3, BST), aluminum oxide (Al2O3), etc.), a metal silicide (e.g., hafnium silicon oxide (HfSiO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), etc.), a metal nitride or semiconductor nitride, a metal oxynitride or semiconductor oxynitride, combinations thereof, and / or other suitable materials. In a specific example, the thickness of the high-k dielectric layer 254 ranges from about to approximately The range between.

[0119] In operation 118, method 100 ( Figure 2B ) First, a capping layer 260 is formed to cover the gate dielectric layers 250a, 250b, and 250c, as shown in FIG. Figure 13 As shown. The thickness adjustment layer 260 may include one or more material layers. In the embodiment shown, the thickness adjustment layer 260 includes titanium nitride (TiN). In a further embodiment of this embodiment, the cap layer 260 includes metal-rich titanium nitride, for example, a titanium-nitrogen ratio (Ti:N ratio) of about 1.05:1 or about 2:1. The deposition method includes physical vapor deposition, chemical vapor deposition, atomic layer deposition or other suitable methods. Subsequently, operation step 120 forms a mask layer 261 covering the nanowires 220 of the fully wrapped gate core device structure 206a and the fully wrapped gate input-output device structure 206c, and removes the cap layer 260 from the fully wrapped gate core device structure 206b, as shown. Figure 14 As shown. The capping layer 260 can be removed by, for example, wet etching, dry etching, reactive ion etching, or other suitable etching methods. In some embodiments, the masking layer 261 is a photoresist layer, such as a bottom anti-reflective coating. After operation 120, the masking layer 261 can be removed by, for example, etching, ashing, or photoresist stripping. At this point, the capping layer 260 remains only on the gate dielectric layer 250a of the all-around gate core device structure 206a and the gate dielectric layer 250c of the all-around gate input / output device structure 206c.

[0120] In operation 120, method 100 ( Figure 2B ) annealing process (through Figure 15 2 (indicated by arrow 270 in FIG) to initiate oxide regrowth processes on the interface layer 252b. The annealing process includes a spike annealing process having a nitrogen-containing ambient with an initial temperature between about 500° C. and about 700° C. and a peak temperature between about 700° C. and about 900° C. In some embodiments, the thickness of the interface layer 252b may be increased by about 10% to about 20% by further silicon consumption. The cap layer 260 limits further growth of the interface layers 252a and 252c by blocking oxygen from the ambient. After operation step 120, the thickness TIL2 of the interface layer 252b is greater than the thickness TIL1 of the interface layer 252a, but is still less than the thickness TIL3 of the interface layer 252c. Since the annealing process is performed in a nitrogen-containing environment, high-k dielectric layer 254 b may absorb nitrogen, resulting in a nitrogen concentration in high-k dielectric layer 254 b being higher than that in high-k dielectric layer 254 a or 254 c .

[0121] In some other embodiments of method 100, capping layer 260 is a thickness adjustment layer, such as an oxygen-scavenging layer 260. Oxygen-scavenging layer 260 has a higher affinity for oxygen than the metal in the metal oxide (in the high-k gate dielectric layer) and the silicon (in the interfacial layer). Oxygen-scavenging layer 260 can include a metal or metal compound, such as titanium (Ti), hafnium (Hf), zirconium (Zr), tantalum (Ta), aluminum (Al), or combinations thereof, such as titanium aluminum (TiAl). Oxygen-scavenging layer 260 can also be formed from a metal nitride (e.g., tantalum nitride (TaN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN)) or a metal alloy nitride (e.g., titanium aluminum nitride (TiAlN)). In some embodiments, oxygen-scavenging layer 260 can be a silicon layer. In one specific example, oxygen-scavenging layer 260 includes a metal-rich titanium silicon nitride (e.g., having a Ti:N ratio of approximately 1.05:1 to approximately 2:1). The oxygen removal layer 260 has the function of removing oxygen from the interface layer 252a at high temperature. In some alternative embodiments, in operation step 120, the method 100 performs an annealing process (by Figure 16 The scavenging anneal may be performed using a spike anneal with a duration on the order of milliseconds, for example, between about 10 milliseconds and about 500 milliseconds. The temperature of each chip may be in a range of about 400° C. to about 1100° C. According to some exemplary embodiments, the temperature is in a range of about 700° C. to about 1,000° C.

[0122] The oxygen removal process strips oxygen from at least the bottom of the interfacial layers 252a and 252c, thereby retaining silicon in the interfacial layers 252a and 252c and forming another silicon layer on top of the crystalline silicon layer of the interfacial layers 252a and 252c of the nanowires 220. Figure 16An enlarged view of portion 272 is shown. Arrow 274 is shown to indicate the movement of oxygen atoms caused by the purge. As a result, an amorphous silicon layer 276 is formed. After oxygen is purged from the bottom of the interface layer 252a (252c), another silicon layer is formed from the silicon remaining in the interface layer 252a (252c). During the purge annealing process, the high-k dielectric layer 254a (254c) may mix with the oxygen purged from the top portion of the interface layer 252a (252c) and the bottom portion of the interface layer 252a (252c) to form an intermix compound, which may be a metal silicate. The intermix compound may have an increased oxygen content. For example, when the high-k dielectric layer 254a includes hafnium dioxide (HfO2), the intermix compound includes hafnium silicate (HfSiO4). When the high-k dielectric layer 254a includes zirconium dioxide (ZrO 2 ), the intermixed compound includes zirconium silicate (ZrSiO 4 ).

[0123] The oxygen removal process chemically reduces interfacial layers 252a and 252c. As a result, interfacial layer 252a has a reduced thickness (e.g., thinned by about 10% to about 50%), which is less than the thickness of interfacial layer 252b, or may even be eliminated (completely converted). Interfacial layer 252b may still grow due to oxide regrowth. Interfacial layer 252c also suffers a thickness loss, but remains greater than the thickness of interfacial layer 252b.

[0124] In operation 122, method 100 ( Figure 2A ) The capping layer 260 is removed in a selective etching process, and the gate dielectric layers 250a, 250b and 250c are exposed in the gate trench 246, as shown in FIG. Figure 17 As shown. The selective etching process may include dry etching, wet etching, reactive ion etching, and / or other suitable processes. Therefore, as the thickness of the interfacial layer changes, the gate dielectric layer 250a has a first capacitance equivalent thickness, which is the thinnest and suitable for high-speed applications; the gate dielectric layer 250b has a second capacitance equivalent thickness, which is moderate and suitable for low-power and low-leakage current applications; and the gate dielectric layer 250c has the thickest capacitance equivalent thickness and is suitable for high-voltage applications.

[0125] In operation 124, method 100 ( Figure 2B) A gate electrode layer 282 is formed in the gate trench, surrounding the gate dielectric layers 250a, 250b, and 250c in the core region and the input / output region. In the illustrated embodiment, the all-around gate core device structures 206a and 206b are adjacent and share the same gate electrode layer, while the all-around gate input / output device structure 206c has a separate gate electrode layer. The gate electrode layer 282 is a conductive layer that includes one or more metal layers, such as a work function metal layer, a conductive barrier layer, and a metal fill layer. The gate electrode layer 282 can be formed separately for n-type transistors and p-type transistors, wherein different metal layers may be used for the n-type transistors and the p-type transistors. The work function metal layer can be a p-type work function metal layer or an n-type work function layer. The p-type work function layer includes a metal with a sufficiently large effective work function, selected from, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or combinations thereof. This n-type work function layer includes a metal with a sufficiently low effective work function, which is selected from but not limited to titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicide nitride (TaSiN), titanium silicide nitride (TiSiN), or a combination thereof. The gate electrode layer 282 may include multiple work function metal layers, for example, a first metal layer and a second metal layer. As an example, the first metal layer may include titanium nitride, and the second metal layer may include titanium aluminum alloy (TiAl) or other combinations of titanium, tantalum, carbon, and aluminum, such as titanium aluminum carbide (TiAlC) or tantalum aluminum carbide (TaAlC). The gate electrode layer 282 also includes a metal fill layer. The metal fill layer may include aluminum (Al), tungsten (W), cobalt (Co), and / or other suitable materials. In various embodiments, the metal fill layer of the gate electrode layer 282 may be formed by plating, atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes. In various embodiments, a chemical mechanical polishing process may be performed to remove excess metal from the metal layer of the gate stack to provide a substantially planar top surface.

[0126] In method 100( Figure 2B), the semiconductor device 200 may be further processed to form various components and regions known in the art. For example, subsequent processing may form contact openings, contact metal, and various contacts / vias / conductors and multi-layer interconnect components (e.g., metal layers and interlayer dielectrics) configured to connect the various components to form functional circuits, which may include one or more multi-gate devices. In a further refinement of this example, the multi-layer interconnects may include vertical interconnects and horizontal interconnects, where the vertical interconnects may be, for example, vias or contacts, and the horizontal interconnects may be, for example, metal lines. The various interconnect components may be made of various conductive materials, including copper, tungsten, and / or silicide. In one example, damascene and / or dual damascene processes are used to form copper-related multi-layer interconnect structures. Furthermore, additional process steps may be provided before, during, and after method 100, and some of the process steps described may be replaced or omitted according to various embodiments of method 100.

[0127] Although not intended to be limiting, one or more embodiments of the present disclosure provide numerous advantages for semiconductor devices and their formation. For example, embodiments of the present disclosure provide fully wrapped gate high-speed devices, fully wrapped gate low-power / low-leakage current devices, and fully wrapped gate high-voltage devices on the same substrate and in the same integrated circuit. The fully wrapped gate high-speed devices and fully wrapped gate low-power / low-leakage current devices are located in the core area of ​​the integrated circuit, for example, for high-speed or low-power circuits, while the fully wrapped gate high-voltage devices are located in the input / output area of ​​the integrated circuit, for implementing input / output circuits or electrostatic discharge circuits. The fully wrapped gate high-speed devices, the fully wrapped gate low-power / low-leakage current devices, and the fully wrapped gate high-voltage devices have different gate dielectric thicknesses, resulting in performance differences among the three types of devices. This embodiment enables circuit designers to optimize circuits located in different areas of the integrated circuit by selecting different types of devices.

[0128] In some exemplary embodiments, an integrated circuit is provided. The integrated circuit includes: a substrate having a first region and a second region; a first wraparound gate device located in the first region, wherein the first wraparound gate device includes: a first channel member extending longitudinally in a first direction; and a first gate structure wrapping the channel region of the first channel member, wherein the first gate structure includes a first interface layer, wherein the first interface layer has a first thickness measured in a second direction substantially perpendicular to the first direction; a second wraparound gate device located in the first region, wherein the second wraparound gate device includes: a second channel member extending longitudinally in the first direction; and a second gate structure , wrapping the channel region of the above-mentioned second channel member, wherein the above-mentioned second gate structure includes a second interface layer, the above-mentioned second interface layer has a second thickness measured in the above-mentioned second direction, and the above-mentioned second thickness is greater than the above-mentioned first thickness; and a third all-around gate device, located in the above-mentioned second region, wherein the above-mentioned third all-around gate device includes: a third channel member, extending longitudinally in the above-mentioned first direction; and a third gate structure, wrapping the channel region of the above-mentioned third channel member, wherein the above-mentioned third gate structure includes a third interface layer, the above-mentioned third interface layer has a third thickness measured in the above-mentioned second direction, and the above-mentioned third thickness is greater than the above-mentioned second thickness. In some embodiments, the ratio of the above-mentioned second thickness to the above-mentioned first thickness is between about 1.1 and about 1.2. In some embodiments, the above-mentioned first thickness is about and In some embodiments, the third thickness is about and In some embodiments, each of the first interface layer, the second interface layer, and the third interface layer comprises silicon dioxide. In some embodiments, the first gate structure further comprises a first dielectric layer encapsulating the first interface layer, the second gate structure further comprises a second dielectric layer encapsulating the second interface layer, the third gate structure further comprises a third dielectric layer encapsulating the third interface layer, and the thicknesses of the first dielectric layer, the second dielectric layer, and the third dielectric layer measured in the second direction are substantially equal. In some embodiments, each of the first dielectric layer, the second dielectric layer, and the third dielectric layer comprises a material selected from the group consisting of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxynitride carbide (SiCON), silicon oxycarbide (SiOC), hafnium dioxide (HfO2), and aluminum oxide (Al2O3). In some embodiments, the second dielectric layer has a higher nitrogen concentration than the first dielectric layer and the third dielectric layer. In some embodiments, the first wraparound gate device and the second wraparound gate device are core devices of the integrated circuit, and the third wraparound gate device is an input / output device of the integrated circuit. In some embodiments, the first wraparound gate device comprises a first amorphous silicon layer positioned between the first interface layer and the first channel member, the second interface layer is in direct contact with the second channel member, and the third wraparound gate device comprises a second amorphous silicon layer positioned between the third interface layer and the third channel member.

[0129] In other exemplary embodiments, an integrated circuit device is provided, comprising: a core device including: a first channel member; a first gate structure engaged with the first channel member, wherein the first gate structure includes a first interfacial layer, wherein the first interfacial layer surrounds a channel region of the first channel member; a second channel member; and a second gate structure engaged with the second channel member, wherein the second gate structure includes a second interfacial layer, wherein the second interfacial layer surrounds the channel region of the second channel member, wherein the second interfacial layer has a thickness substantially perpendicular to a longitudinal axis of the second channel member that is greater than a thickness of the first interfacial layer in a direction substantially perpendicular to the longitudinal axis of the first channel member; and an input / output device including: a third channel member; and a third gate structure engaged with the third channel member, wherein the third gate structure includes a third interfacial layer, wherein the third interfacial layer surrounds the channel region of the third channel member, wherein the third interfacial layer has a thickness substantially perpendicular to the longitudinal axis of the third channel member that is greater than the thickness of the second interfacial layer. In some embodiments, the ratio of the thickness of the second interface layer to the thickness of the first interface layer is between about 1.1 and about 1.2. In some embodiments, the thickness of the first interface layer is between about and In some embodiments, the longitudinal axes of the first channel member, the second channel member, and the third channel member are parallel to each other. In some embodiments, the first interface layer, the second interface layer, and the third interface layer comprise silicon dioxide.

[0130] In some other exemplary embodiments, a method for manufacturing an integrated circuit device is provided. The manufacturing method includes: providing a substrate, wherein the substrate has a first channel component, a second channel component, and a third channel component, wherein the first channel component and the second channel component are located in a core region of the integrated circuit device, and the third channel component is located in an input / output region of the integrated circuit device; forming a first oxide layer and a second oxide layer by a first process, wherein the first oxide layer wraps the channel region of the first channel component, and the second oxide layer wraps the channel region of the second channel component; forming a third oxide layer by a second process different from the first process to wrap the channel region of the first channel component. The invention also provides a method for fabricating a channel region of a third channel member; forming a first dielectric layer, a second dielectric layer, and a third dielectric layer on the first oxide layer, the second oxide layer, and the third oxide layer, respectively; forming a first capping layer, a second capping layer, and a third capping layer on the first dielectric layer, the second dielectric layer, and the third dielectric layer, respectively; removing the second capping layer to expose the second dielectric layer, wherein after removing the second capping layer, the first capping layer and the third capping layer remain on the first dielectric layer and the third dielectric layer, respectively; and performing an annealing process after removing the second capping layer to increase the thickness of the second oxide layer. In some embodiments, the ratio of the thickness of the second oxide layer to the thickness of the first oxide layer is between approximately 1.1 and approximately 1.2, and the thickness of the third oxide layer is greater than the thickness of the second oxide layer. In some embodiments, the second process is performed before the first process, and before the first process, the manufacturing method further includes: forming a third oxide layer to encapsulate the channel region of the first channel member and the channel region of the second channel member through the second process; forming an etch mask to cover the input / output region of the integrated circuit device; removing the third oxide layer from the channel region of the first channel member and the channel region of the second channel member while the etch mask covers the input / output region of the integrated circuit device; and removing the etch mask to expose the channel region of the third channel member encapsulated by the third oxide layer. In some embodiments, the first process includes treating the first and second channel members with hydrogen peroxide, sulfuric acid, or a combination thereof. In some embodiments, the annealing process includes a spike annealing process, wherein the spike annealing process has a nitrogen-containing ambient, an initial temperature between approximately 500°C and approximately 700°C, and a peak temperature between approximately 700°C and approximately 900°C.

[0131] The foregoing text summarizes the components of numerous embodiments to provide those skilled in the art with a comprehensive understanding of the embodiments of the present invention. Those skilled in the art will appreciate that they can readily design or modify other processes and structures based on the embodiments of the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that these equivalent structures do not depart from the inventive concept and scope of the present invention. Various changes, substitutions, and modifications may be made to the present invention without departing from the inventive concept and scope of the present invention.

[0132] Although the present invention has been disclosed above with respect to several preferred embodiments, they are not intended to limit the present invention. Any person skilled in the art may make any changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. An integrated circuit comprising: A substrate having a first area and a second area; A first all-around gate device is located in the first region, wherein the first all-around gate device comprises: a first channel member extending longitudinally in a first direction; and a first gate structure wrapping a channel region of the first channel member, wherein the first gate structure comprises a first interfacial layer having a first thickness measured in a second direction perpendicular to the first direction; a second all-around gate device located in the first region, wherein the second all-around gate device comprises: a second channel member extending longitudinally in the first direction; and a second gate structure wrapping a channel region of the second channel member, wherein the second gate structure comprises a second interfacial layer having a second thickness measured in the second direction, and the second thickness is greater than the first thickness; and a third all-around gate device located in the second region, wherein the third all-around gate device comprises: a third channel member extending longitudinally in the first direction; and A third gate structure wraps a channel region of the third channel member, wherein the third gate structure includes a third interface layer having a third thickness measured in the second direction, and the third thickness is greater than the second thickness. 2 . The integrated circuit of claim 1 , wherein a ratio of the second thickness to the first thickness is between 1.1 and 1.

2.

3. The integrated circuit of claim 1 , wherein the first thickness is and between.

4. The integrated circuit of claim 1 , wherein the third thickness is and between. 5 . The integrated circuit of claim 1 , wherein each of the first interface layer, the second interface layer, and the third interface layer comprises silicon dioxide.

6. The integrated circuit of claim 1 , wherein the first gate structure further comprises a first dielectric layer wrapping the first interface layer, wherein the second gate structure further comprises a second dielectric layer wrapping the second interface layer, wherein the third gate structure further comprises a third dielectric layer wrapping the third interface layer, and wherein the thicknesses of the first dielectric layer, the second dielectric layer, and the third dielectric layer measured in the second direction are substantially equal.

7. The integrated circuit of claim 6 , wherein each of the first dielectric layer, the second dielectric layer, and the third dielectric layer comprises a material selected from the group consisting of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide nitride (SiCON), silicon oxycarbide (SiOC), hafnium oxide (HfO 2 ), and aluminum oxide (Al 2 O 3 ). 8 . The integrated circuit of claim 6 , wherein the second dielectric layer has a higher nitrogen concentration than the first dielectric layer and the third dielectric layer.

9. The integrated circuit of claim 1, wherein the first and second wrap-around gate devices are core devices of the integrated circuit, and wherein the third wrap-around gate device is an input / output device of the integrated circuit.

10. The integrated circuit according to claim 1, The first all-around gate device includes a first amorphous silicon layer located between the first interface layer and the first channel member. wherein the second interface layer is in direct contact with the second channel member, and The third all-around gate device includes a second amorphous silicon layer located between the third interface layer and the third channel component.

11. An integrated circuit device comprising: A core device, comprising: a first channel member; a first gate structure engaged with the first channel member, the first gate structure comprising a first interface layer wrapping a channel region of the first channel member; a second channel member; and a second gate structure engaged with the second channel member, the second gate structure comprising a second interfacial layer wrapping a channel region of the second channel member, wherein a thickness of the second interfacial layer in a direction perpendicular to a longitudinal axis of the second channel member is greater than a thickness of the first interfacial layer in a direction perpendicular to the longitudinal axis of the first channel member; and An input / output device comprising: a third channel member; and A third gate structure is engaged with the third channel component, and the third gate structure includes a third interface layer, which wraps a channel region of the third channel component, wherein the thickness of the third interface layer in a direction perpendicular to the longitudinal axis of the third channel component is greater than the thickness of the second interface layer. 12 . The integrated circuit device of claim 11 , wherein a ratio of the thickness of the second interface layer to the thickness of the first interface layer is between 1.1 and 1.

2.

13. The integrated circuit device according to claim 11 , wherein the thickness of the first interface layer is and between. 14 . The integrated circuit device of claim 11 , wherein a longitudinal axis of the first channel member, a longitudinal axis of the second channel member, and a longitudinal axis of the third channel member are parallel to each other. 15 . The integrated circuit device of claim 11 , wherein the first interface layer, the second interface layer, and the third interface layer comprise silicon dioxide.

16. A method for manufacturing an integrated circuit device, comprising: A structure is provided, the structure having a first channel component, a second channel component, and a third channel component, wherein the first channel component and the second channel component are located in a core region of an integrated circuit device, and the third channel component is located in an input / output region of the integrated circuit device; forming a first oxide layer and a second oxide layer by a first process, wherein the first oxide layer surrounds a channel region of the first channel component, and the second oxide layer surrounds a channel region of the second channel component; forming a third oxide layer to encapsulate a channel region of the third channel member through a second process different from the first process; forming a first dielectric layer, a second dielectric layer and a third dielectric layer on the first oxide layer, the second oxide layer and the third oxide layer respectively; forming a first capping layer, a second capping layer and a third capping layer on the first dielectric layer, the second dielectric layer and the third dielectric layer respectively; removing the second capping layer to expose the second dielectric layer, wherein after removing the second capping layer, the first capping layer and the third capping layer remain on the first dielectric layer and the third dielectric layer, respectively; as well as After removing the second capping layer, an annealing process is performed to increase the thickness of the second oxide layer. 17 . The method for manufacturing an integrated circuit device according to claim 16 , wherein a ratio of the thickness of the second oxide layer to the thickness of the first oxide layer is between 1.1 and 1.2, and wherein a thickness of the third oxide layer is greater than the thickness of the second oxide layer.

18. The method for manufacturing an integrated circuit device according to claim 16, wherein the second process is performed before the first process, and before performing the first process, the method further comprises: By the second process, the third oxide layer is formed to wrap the channel region of the first channel component and the channel region of the second channel component; forming an etching mask to cover the input / output region of the integrated circuit device; removing the third oxide layer from the channel region of the first channel member and from the channel region of the second channel member when the etching mask covers the input / output region of the integrated circuit device; as well as The etching mask is removed to expose the channel region of the third channel member surrounded by the third oxide layer. 19 . The method for fabricating an integrated circuit device according to claim 16 , wherein the first process comprises treating the first channel member and the second channel member with sulfuric acid, hydrogen peroxide, or a combination thereof.

20. The method for fabricating an integrated circuit device according to claim 16, wherein the annealing process comprises a spike annealing process having a nitrogen-containing environment, an initial temperature between 500°C and 700°C, and a peak temperature between 700°C and 900°C.

21. A semiconductor device comprising: A substrate having a first area and a second area; a first transistor located in the first region, the first transistor comprising: a first channel layer; a first gate dielectric layer on the first channel layer, the first gate dielectric layer having a first thickness; and a first gate structure on the first gate dielectric layer; a second transistor located in the first region, the second transistor comprising: a second channel layer; a second gate dielectric layer on the second channel layer, the second gate dielectric layer having a second thickness greater than the first thickness; and a second gate structure on the second gate dielectric layer; and a third transistor located in the second region, the third transistor comprising: a third channel layer; a third gate dielectric layer on the third channel layer, the third gate dielectric layer having a third thickness, the third thickness being greater than the second thickness; and A third gate structure is formed on the third gate dielectric layer, wherein the first gate dielectric layer includes a first interfacial layer, the second gate dielectric layer includes a second interfacial layer, and the third gate dielectric layer includes a third interfacial layer, and wherein the first interfacial layer is thinner than the second interfacial layer, and the second interfacial layer is thinner than the third interfacial layer. 22 . The semiconductor device of claim 21 , wherein the first gate dielectric layer comprises a first high-k dielectric layer, the second gate dielectric layer comprises a second high-k dielectric layer, and the third gate dielectric layer comprises a third high-k dielectric layer. 23 . The semiconductor device of claim 22 , wherein the first high-k dielectric layer, the second high-k dielectric layer, and the third high-k dielectric layer have substantially the same thickness.

24. The semiconductor device of claim 23, wherein the first high-k dielectric layer, the second high-k dielectric layer, and the third high-k dielectric layer each have to The thickness between. 25 . The semiconductor device of claim 22 , wherein a thickness of the third interface layer is 2 to 4 times a thickness of the first interface layer. 26 . The semiconductor device of claim 22 , wherein a thickness of the second interface layer is 1.1 to 1.2 times a thickness of the first interface layer. 27 . The semiconductor device of claim 21 , wherein the second gate dielectric layer has a higher nitrogen concentration than the first gate dielectric layer and the third gate dielectric layer.

28. The semiconductor device of claim 21, wherein the first region is a core region, and the second region is an input / output region.

29. The semiconductor device of claim 21, wherein the first gate structure continuously extends to the second gate structure.

30. A semiconductor device comprising: a substrate; a first multi-gate transistor on the substrate, the first multi-gate transistor comprising: a first channel layer; a first interface layer on the first channel layer; and a first high-k dielectric layer on the first interface layer; a second multi-gate transistor on the substrate, the second multi-gate transistor comprising: a second channel layer; a second interface layer on the second channel layer; and a second high-k dielectric layer on the second interface layer; and a third multi-gate transistor on the substrate, the third multi-gate transistor comprising: a third channel layer; a third interface layer on the third channel layer; and a third high-k dielectric layer on the third interface layer; The thickness of the third interface layer is greater than that of the second interface layer, the thickness of the second interface layer is greater than that of the first interface layer, and the second high-k dielectric layer has a higher nitrogen concentration than that of the first high-k dielectric layer. 31 . The semiconductor device of claim 30 , wherein the first multi-gate transistor and the second multi-gate transistor are located in a core region. 32 . The semiconductor device of claim 31 , wherein a ratio of the thickness of the second interface layer to the thickness of the first interface layer is 1.1 to 1.

2.

33. The semiconductor device of claim 30, wherein the second interface layer is in direct contact with a crystalline silicon layer, and the first interface layer is in direct contact with an amorphous silicon layer.

34. A method for manufacturing a semiconductor device, comprising: A structure is provided, the structure having a first channel component, a second channel component, and a third channel component, wherein the first channel component and the second channel component are located in a core region of an integrated circuit device, and the third channel component is located in an input / output region of the integrated circuit device; forming a first oxide layer, a second oxide layer, and a third oxide layer, wherein the first oxide layer wraps the first channel component, the second oxide layer wraps the second channel component, and the third oxide layer wraps the third channel component; forming a first capping layer, a second capping layer and a third capping layer on the first oxide layer, the second oxide layer and the third oxide layer respectively; removing the second cover layer, wherein the first cover layer and the third cover layer remain; as well as After removing the second capping layer, an oxide growth process is performed to increase the thickness of the second oxide layer. 35 . The method for manufacturing a semiconductor device according to claim 34 , wherein after performing the oxide growth process, a thickness of the second oxide layer is greater than a thickness of the first oxide layer and less than a thickness of the third oxide layer. 36 . The method for manufacturing a semiconductor device according to claim 34 , wherein the first capping layer, the second capping layer, and the third capping layer comprise a metal nitride. 37 . The method for manufacturing a semiconductor device according to claim 36 , wherein the metal nitride is metal-rich such that a ratio between metal elements and nitrogen is 1.05 to 2.

38. The method for manufacturing a semiconductor device according to claim 34, wherein forming the first oxide layer, the second oxide layer, and the third oxide layer comprises: forming the third oxide layer to wrap the first channel component, the second channel component, and the third channel component; removing the third oxide layer from the first channel member and the second channel member; as well as The first oxide layer and the second oxide layer are formed to respectively wrap the first channel member and the second channel member.

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