Image sensor device and method of forming the same

Abstract

An image sensor device and a method for forming the same are disclosed. The device includes a plurality of pixels disposed above a first surface of a semiconductor layer. The device includes a device layer disposed above the first surface. The device includes a plurality of metallization layers disposed above the device layer. One of the metallization layers includes at least one conductive structure, the metallization layer being closer to the first surface than the other metallization layers. The device includes an oxide layer disposed above a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess, the recess extending through the semiconductor layer. The device includes a spacer layer disposed between a plurality of inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to physically contact the at least one conductive structure.

Description

Technical Field

[0001] The present disclosure relates to an image sensor device and a method of forming an image sensor device. Background Art

[0002] The present disclosure relates generally to semiconductor devices, and more particularly to image sensor devices and methods of forming the same.

[0003] Semiconductor image sensors are used to sense incident visible or invisible radiation, such as visible light, infrared light, etc. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors are used in various applications such as digital still cameras, mobile phones, tablet computers, goggles, etc. These image sensors utilize an array of pixels to absorb (e.g., sense) incident radiation and convert it into an electrical signal. Back side illuminated (BSI) image sensor devices are one example of image sensor devices. These BSI image sensor devices are operable to detect light from their back surface. Summary of the invention

[0004] The present disclosure provides an image sensor device. The image sensor device includes a semiconductor layer, a conductive structure, and a pad region. The semiconductor layer has a first surface and a second surface, the second surface being opposite to the first surface. The conductive structure is disposed on the first surface, wherein a dielectric layer is disposed between the conductive structure and the first surface. The pad region includes a recess extending through the semiconductor layer from the first surface to the second surface. The pad region includes a spacer layer, an oxide layer, and a pad structure. The spacer layer extends along a plurality of inner sidewalls of the recess. The oxide layer lines the recess above the spacer layer. The pad structure extends through the oxide layer and the dielectric layer to physically contact the conductive structure.

[0005] The present disclosure provides an image sensor device. The image sensor device includes a plurality of pixels, a device layer, a plurality of metallization layers, an oxide layer, a spacer layer, and a pad structure. The plurality of pixels are disposed above a first surface of a semiconductor layer. The device layer is disposed above the first surface. A plurality of metallization layers are disposed above the device layer, wherein one of the metallization layers includes at least one conductive structure, and the one of the metallization layers is closer to the first surface than the other of the metallization layers. An oxide layer is disposed above a second surface of the semiconductor layer, the second surface is opposite to the first surface, and the oxide layer is also lined with a recess, and the recess extends through the semiconductor layer. The spacer layer is disposed between a plurality of inner sidewalls of the recess and the oxide layer. The pad structure extends through the oxide layer and the device layer so that the pad structure is in physical contact with the at least one conductive structure.

[0006] The present disclosure provides a method for forming an image sensor device, comprising the following operations. A plurality of pixels are formed above a first surface of a semiconductor layer, the pixels being configured to absorb radiation from a second surface of the semiconductor layer, the second surface of the semiconductor layer being opposite to the first surface of the semiconductor layer. A device layer is formed above the first surface of the semiconductor layer. A metallization layer is formed above the device layer. The second surface of the semiconductor layer is etched to form a recess, the recess being laterally separated from the pixels. A spacer layer is formed extending along a plurality of inner sidewalls of the recess. An oxide layer is formed above the second surface, wherein the spacer layer is sandwiched between the inner sidewalls and the oxide layer. A portion of the oxide layer and the device layer is etched to expose a portion of the metallization layer. A conductive material is deposited to form a pad structure electrically connected to the exposed portion of the metallization layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A and Figure 1B a flow chart illustrating an example method for manufacturing an image sensor device according to some embodiments;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 and Fig.15 Description According to some embodiments Figure 1A to Figure 1B Cross-sectional views of an example image sensor device manufactured by the method at various stages of manufacturing;

[0010] Fig.16 Description of some embodiments Figures 2 to 15 A top view of the example image sensor device illustrated in FIG.

[0011]

Explanation of symbols

[0012] 100: Method

[0013] 102: Operation

[0014] 104: Operation

[0015] 106: Operation

[0016] 108: Operation

[0017] 110: Operation

[0018] 112: Operation

[0019] 114: Operation

[0020] 116: Operation

[0021] 118: Operation

[0022] 120: Operation

[0023] 122: Operation

[0024] 124: Operation

[0025] 200:BSI image sensor device

[0026] 202:Semiconductor substrate

[0027] 202B: Rear surface

[0028] 202F: front surface

[0029] 203A: Pixel area

[0030] 203B: Pad area

[0031] 204A: Pixel

[0032] 204B: Pixel

[0033] 204C: Pixel

[0034] 302:Isolated area

[0035] 304:Isolated area

[0036] 400: device layer

[0037] 402: Nitride layer / etching stop layer

[0038] 404:Semiconductor device

[0039] 406: Conductive structure

[0040] 408: Dielectric layer

[0041] 410: Metallization layer

[0042] 410A: Metallization layer

[0043] 410B: Metallization layer

[0044] 410C: Metallization layer

[0045] 410D: Metallization layer

[0046] 412: Horizontal conductive structure

[0047] 414: Dielectric layer

[0048] 416: Vertical conductive structure

[0049] 418: Dielectric layer

[0050] 420: Silicon on Wafer

[0051] 422:Joint structure

[0052] 504:Isolated Area

[0053] 506: passivation layer

[0054] 600: concave part

[0055] 600B: Bottom surface

[0056] 600S: Inner wall

[0057] 602: Patternable layer

[0058] 700: First oxide layer

[0059] 800: Spacer layer

[0060] 802: Etching process

[0061] 900: Arc profile

[0062] 1000: Small faceted profile

[0063] 1000A: Small

[0064] 1000B: Small noodles

[0065] 1100: Second oxide layer

[0066] 1200: Opening

[0067] 1300: Pad structure

[0068] 1400: Dielectric layer

[0069] 1500: Opening

[0070] 1602: Pixel array

[0071] 1604: Pad array DETAILED DESCRIPTION

[0072] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0073] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature(s), as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0074] The terms "about" and "substantially" may indicate that a value of a given number varies within 5% of that value (eg, ±1%, ±2%, ±3%, ±4%, ±5% of that value).

[0075] Typically, a back side illuminated (BSI) image sensor device includes a semiconductor substrate (e.g., a silicon substrate) in which pixels or radiation sensing regions are formed. As disclosed herein, the terms "radiation sensing region" and "pixel" are used interchangeably. A BSI image sensor device may include a pixel array configured within a semiconductor substrate. The pixel array is configured vertically relative to multiple metallization layers (e.g., one or more interconnect structures) formed on a first surface of the semiconductor substrate. The first surface of the semiconductor substrate is referred to herein as the "front side" or "front" surface of the semiconductor substrate. The pixel array extends into the semiconductor substrate and is used to receive radiation (e.g., light) from or through a second surface of the semiconductor substrate opposite to the front surface of the semiconductor substrate. The second surface of the semiconductor substrate that receives radiation (opposite to the front surface of the semiconductor substrate) is referred to herein as the "back side" or "back" surface of the semiconductor substrate.

[0076] The pixels in the semiconductor substrate are electrically isolated by an isolation structure such as a deep trench isolation (DTI) structure. Respective grid structures are aligned with the isolation structures (and formed on the back surface of the semiconductor substrate), which provide optical isolation between adjacent pixels. Adjacent grid structures together form a cell. In addition, the cells together form a composite grid structure for receiving a color filtering material. Based on the above description, the composite grid structure is formed on the back surface of the semiconductor substrate.

[0077] Color filter materials may be disposed between adjacent grid structures to form color filters. The color filter materials may be selected so that light having a desired wavelength passes through the filter materials, while light having other wavelengths is absorbed by the filter materials. For example, a green light filter material receiving unfiltered natural light will allow the green portion (wavelengths between about 495 nm and about 570 nm) to pass through the filter, but will absorb all other wavelengths. The filters are aligned with respective pixels to provide filtered light to the corresponding pixels.

[0078] Components of a BSI sensor device (e.g., pixels, transistors, capacitors, memory structures, other chips attached to the BSI sensor device, etc.) can be electrically coupled to an external device (e.g., an external circuit) via a wire connector attached to a pad structure formed on the back surface of the semiconductor substrate. To this end, the pad structure of the BSI sensor device physically extends from the back surface of the semiconductor substrate to the front surface of the semiconductor substrate and is electrically connected to the multi-layer metallization layer of the BSI sensor. Therefore, the multi-layer metallization layer of the BSI sensor device that provides electrical signal connections to the BSI sensor device can be electrically coupled to an external device or circuit via the pad structure. The pad structure can be disposed at the periphery of the BSI sensor device around the pixels or radiation sensing area.

[0079] In existing techniques for forming pad structures in BSI image sensor devices, an opening (or recess) is typically formed that extends from at least the back side to the front side of a semiconductor substrate thereof. The opening is characterized by a depth of up to several microns. Such deep openings often result in the formation of one or more pores in the dielectric layer above and below the pad structure. For example, due in part to their deep depth, pores may form at the corners of the opening. The pores may adversely facilitate the penetration of acids or etchants through the dielectric layer to the pad structure or the interconnect structure below, which may cause various interconnect problems (e.g., increased contact resistance, increased RC delay, electromigration effects). Therefore, the existing techniques for manufacturing BSI image sensor devices are not entirely satisfactory.

[0080] The present disclosure provides various embodiments of BSI image sensor devices and methods for manufacturing the same. As disclosed herein, a BSI image sensor device includes a spacer layer formed at least around the corners of a recess having a pad structure formed therein. In various embodiments, the spacer layer may have, for example, a tapered profile characterized in that a lower portion is wider than an upper portion. By forming such a spacer layer around the corners of a relatively deep recess, the profile of the recess may be effectively "rounded" or otherwise "raised." Thus, when a dielectric layer is deposited over the recess, the formation of voids, which are typically found in image sensor devices manufactured using prior art techniques, may be avoided. Therefore, when compared to existing BSI image sensor devices, the BSI image sensor device of the present disclosure may be characterized by a more reliable pad structure and interconnect structure.

[0081] Figure 1A and Figure 1B 1 and 1 , which are flowcharts of a method 100 for forming a BSI image sensor device according to one or more embodiments of the present disclosure. It should be noted that the method 100 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 100 may be used in Figure 1A to Figure 1BAdditional operations are provided before, during, and after method 100, and only some of the other operations are briefly described herein. In some embodiments, the operations of method 100 may be different from those in Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 and Fig.15 The cross-sectional views of a BSI image sensor device at various fabrication stages are shown in association with each other, which will be discussed in further detail below.

[0082] Briefly, method 100 begins with operation 102 of forming a plurality of pixels (or radiation sensing regions) over a front surface of a semiconductor substrate. Method 100 proceeds to operation 104 of forming one or more isolation regions over the front surface. Method 100 proceeds to operation 106 of forming a device layer and one or more metallization layers over the front surface. Method 100 proceeds to operation 108 of flipping the semiconductor substrate. Method 100 proceeds to operation 110 of forming an opening from a back surface of the semiconductor substrate. Method 100 proceeds to operation 112 of depositing a first oxide layer. Method 100 proceeds to operation 114 of forming a spacer layer using the first oxide layer. Method 100 proceeds to operation 116 of depositing a second oxide layer. Method 100 proceeds to operation 118 of exposing a portion of one of the metallization layers. Method 100 proceeds to operation 120 of forming one or more pad structures. Method 100 proceeds to operation 122 of depositing a dielectric layer over the one or more pad structures. The method 100 continues with operation 124 where respective portions of one or more pad structures are exposed.

[0083] As mentioned above, Figures 2 to 15 Each is illustrated in a cross-sectional view. Figure 1A and Figure 1B A portion of a BSI image sensor device 200 at various stages of manufacturing of the method 100 is shown. Figures 2 to 15 Although the drawings illustrate the BSI image sensor device 200, it should be understood that the BSI image sensor device 200 may include a number of other devices, such as inductors, fuses, capacitors, coils, etc., which are not shown in the drawings for the sake of clarity. Figures 2 to 15 In the description.

[0084] Corresponds to Figure 1A Operation 102 in Figure 2The cross-sectional view of a BSI image sensor device 200 at one of various manufacturing stages includes a plurality of pixels 204A, 204B, and 204C formed over a front surface 202F of a semiconductor substrate (or semiconductor layer) 202. Opposite to the front surface 202F (e.g., along the Z-axis), the semiconductor substrate 202 has a back surface 202B through which the BSI image sensor device 200 receives incident radiation.

[0085] The semiconductor substrate 202 may include a top layer of a bulk semiconductor wafer or a semiconductor on insulator wafer (SOI) having a thickness greater than about 6 μm (e.g., about 6.15 μm, about 6.30 μm, about 6.50 μm, or about 6.70 μm). For example, the semiconductor substrate 202 may include a semiconductor material such as silicon, germanium, a compound semiconductor, an alloy semiconductor, any other suitable semiconductor material, and / or a combination thereof. Additionally, the semiconductor substrate 202 may be an epitaxial material strained for performance enhancement, and / or may be doped with n-type dopants, p-type dopants, or a combination thereof. In various embodiments, the semiconductor substrate 202 may include a combination of p-type and n-type doped regions.

[0086] Pixels 204A-C are formed in a portion of semiconductor substrate 202, which is referred to herein as pixel region 203A. Figure 3 2 and the following cross-sectional views show three pixels 204A-C, but it should be understood that BSI image sensor device 200 may include any desired number of pixels while remaining within the scope of the present disclosure. In some embodiments, pixel region 203A is a central region of semiconductor substrate 202. For example, pixel region 203A may correspond to a region in which a pixel array is formed in BSI image sensor device 200, such as Fig.16 shown in top view.

[0087] Pixels 204A-C are each used to sense electromagnetic radiation, such as near infrared light. By way of example and not limitation, each pixel 204A-C includes a photodiode structure, such as a pinned layer photodiode, a photogate, a reset transistor, a source follower transistor, a transfer transistor, any other suitable structure, and / or a combination thereof. Additionally, pixels 204A-C may sometimes be referred to as "radiation detection devices" or "photosensors." In some embodiments, pixels 204A-C are formed by doping semiconductor substrate 202 from front surface 202F. For example, the doping process may include doping semiconductor substrate 202 with a p-type dopant such as boron or an n-type dopant such as phosphorus or arsenic. In some embodiments, pixels 204A-C are formed by a dopant diffusion process and / or an ion implantation process.

[0088] In some embodiments, the semiconductor substrate 202 includes a pad region 203B adjacent to the pixel region 203A. One or more pad structures may be formed in the pad region 203B. Such pad structures may be located at the periphery of the semiconductor substrate 202 to surround the pixel region 203A. For example, the pad region 203B corresponds to a region where one or more pad arrays are formed in the BSI image sensor device 200, such as Fig.16 As shown in the top view.

[0089] Corresponds to Figure 1A Operation 104, Figure 3 2 is a cross-sectional view of a BSI image sensor device 200 at one of various manufacturing stages, including one or more isolation regions 302 and 304 formed over a front surface 202F. In some embodiments, isolation regions 302 formed in pad region 203B of semiconductor substrate 202 may facilitate the formation of one or more pad structures. In some embodiments, one or more isolation regions 304 may be formed in pixel region 203A before, simultaneously with, or after forming isolation regions 302 in pad region 203B. Such isolation regions 304 may isolate pixels 204A-C from one another. By way of example and not limitation, isolation regions 302 and 304 may be formed on various portions of front surface 202F.

[0090] In some embodiments, the isolation regions 302 and 304 may be formed by performing at least some of the following processes: forming a patternable layer (e.g., a photoresist (PR) layer) using a pattern that defines respective locations of the isolation regions 302 and 304 in the semiconductor substrate 202; etching (e.g., dry etching) the semiconductor substrate 202 using the patternable layer as an etching mask to form a recess; removing (e.g., wet etching) the patternable layer; depositing one or more layers (including but not limited to silicon oxide, USG, PSG, BPSG, PEOX, FSG, a low-k dielectric material (e.g., with a k value less than about 3.9), or a combination) as a blanket layer to fill the recess; and planarizing (e.g., a chemical-mechanical polishing (CMP) process) the blanket layer.

[0091] Corresponds to Figure 1A Operation 106, Figure 4 4 is a cross-sectional view of semiconductor device 200 at one of various manufacturing stages, which includes device layer 400 and one or more metallization layers 410. According to some embodiments, device layer 400 and metallization layer 410 may be sequentially formed on or over front surface 202F of semiconductor substrate 202. For example, device layer 400 may contact a particular portion of front surface 202F.

[0092] The device layer 400 may include one or more semiconductor devices 404 (e.g., field effect transistors) formed according to the wafer layout on the front surface 202F of the semiconductor substrate 202. The device layer 400 may also include additional elements or structures such as doped regions, dummy regions, epitaxial layers, transistor structures, resistors, etc. For simplicity, these additional elements or structures of the device layer 400 are not shown in FIG. Figure 4 . In some embodiments, the BSI image sensor device 200 includes vertical conductive structures 406 (e.g., vias) that electrically connect the semiconductor device 404 and other elements of the device layer 400 to the upper metallization layer. The conductive structures 406 may form part of a middle of the line (MOL) wiring network. In some embodiments, the device layer 400 further includes a nitride layer 402 that is used as an etch stop layer (ESL) in a subsequent etching operation during the formation of the pad structure. In some embodiments, the ESL 402 is formed around the semiconductor device 404, but not between the semiconductor device 404 and the semiconductor substrate 202. The ESL 402, the semiconductor device 404, and the conductive structures 406 may be embedded or covered by corresponding dielectric layers 408.

[0093] The metallization layer 410 may include one or more metallization layers, such as metallization layers 410A, 410B, 410C, and 410D. Figure 4 . It should be understood that image sensor device 200 may include any desired number of metallization layers while remaining within the scope of the present disclosure. In some embodiments, along the Z-axis, metallization layer 410A is the first or bottommost metallization layer (sometimes referred to as the "M1" layer), and metallization layer 410D is the topmost metallization layer (sometimes referred to as the "top metal") (TM layer). Metallization layers 410 may form part of a back end of the line (BEOL) wiring network. Each metallization layer 410 (e.g., 410A-D) may include one or more lateral conductive structures 412 (e.g., wires) embedded in a corresponding dielectric layer 414. In some embodiments, one or more conductive structures and the dielectric layer in which the conductive structures are embedded may sometimes be collectively referred to as a metallization layer.

[0094] Across different metallization layers 410, one or more vertical conductive structures 416 (e.g., vias) may be extended through corresponding dielectric layers 418 to electrically connect adjacent metallization layers along the Z-axis. For example, lines 412 and vias 416 formed of copper may sometimes be referred to as copper interconnect structures. Although not shown, in some embodiments, each of the copper lines 412 and copper vias 416 may be surrounded by a (diffusion) barrier layer. The barrier layer may include a material selected from the group consisting of: tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium tungsten (TiW), and titanium (Ti). In some embodiments, such a barrier layer may sometimes be referred to as a portion of the corresponding metallization layer (or corresponding conductive structure).

[0095] Dielectric layer 408, dielectric layer 414, and dielectric layer 418 may electrically isolate components and / or structures therein. In some embodiments, each of dielectric layer 408, dielectric layer 414, and dielectric layer 418 is part of an interlayer dielectric (ILD) or inter-metal dielectric (IMD) layer. For example, such an ILD or IMD layer includes silicon oxide, USG, BPSG, a low-k dielectric (e.g., a dielectric constant less than 3.9), or a dielectric stack, such as a low-k dielectric and another dielectric: (i) a low-k dielectric (e.g., carbon-doped silicon oxide) and nitrogen-doped silicon carbide; (ii) a low-k dielectric (e.g., carbon-doped silicon oxide) and oxygen-doped silicon carbide; (iii) a low-k dielectric with silicon nitride (e.g., carbon-doped silicon oxide); (iv) a low-k dielectric with silicon oxide (e.g., carbon-doped silicon oxide).

[0096] In some other embodiments, the device layer 400 and / or the metallization layer 410 may be formed on a separate semiconductor substrate (eg, different from the semiconductor substrate 202 ) and subsequently attached to the front surface 202F of the semiconductor substrate 202 .

[0097] In certain applications of image sensor device 200, an application specific integrated circuit (ASIC) and silicon-on-chip (SoC) 420 may be attached to top metallization layer 410D. This structure may sometimes be referred to as a three-dimensional (3D) stack or 3D integrated circuit. In this regard, one or more bonding structures 422 may be used to electrically and mechanically bond ASIC / SoC 420 to top metallization layer 410D. ASIC / SoC 420 may add functionality to image sensor device 200 or may control the functions of image sensor device 200. In some embodiments, ASIC / SoC 420 includes metallization layers, semiconductor devices, memory devices, or may be a stack of chips, such as memory chips, central processing unit (CPU) chips, other functional chips (e.g., RF chips), or combinations thereof.

[0098] According to some embodiments, the fabrication of BSI image sensor device 200 may continue with forming additional structures in or on semiconductor substrate 202 from back surface 202B. In this regard, such partially fabricated BSI image sensor 200 may be rotated 180° (flipped) about the X-axis (e.g., Figure 5 ), which also corresponds to Figure 1A Operation 108.

[0099] After flipping the semiconductor substrate 202, one or more isolation regions 504 are formed to align with the isolation region 304 to further isolate the pixels 204A-C in the pixel region 203A. The isolation region 504 may include one or more dielectric materials and, for example, form a deep trench isolation (DTI) structure. The isolation region 504 may be formed by etching the semiconductor substrate 202 to form corresponding trenches between the pixels 204A-C. The trenches are then filled with one or more dielectric materials. Although in Figure 5 Although not illustrated in the figure, after forming the isolation region 504, one or more high-k (dielectric constant higher than 3.9) dielectric layers may be formed over the isolation region 504 as appropriate. For example, the high-k dielectric layers may each include a material selected from the following: Ta 2 O 5 , HfO 2 、Al 2 O 3 Such a high-k dielectric layer can be used to dissipate charges accumulated in the BSI image sensor device 200 .

[0100] In some embodiments, a dielectric layer (e.g., including a dielectric layer forming the isolation region 504 and an optional high-k dielectric layer) may cover both the pixel region 203A and the pad region 204B of the semiconductor substrate 200. Before forming the isolation region 504 on the back surface 202B, the semiconductor substrate 202 may be thinned to a desired thickness T 1 As an example and not limitation, depending on the application of the BSI image sensor device 200, the thickness T 1 The range of T may be in the range of about 2 μm to about 6 μm. Therefore, it should be understood that within the scope of the present disclosure, the thickness T 1 The thickness of the semiconductor substrate 202 may be within any suitable range of values. The thinning of the semiconductor substrate 202 may be performed by a planarization process (e.g., a CMP process), an etch-back process (e.g., a dry etching process), some other thinning process (e.g., grinding), or a combination thereof. The thinning of the semiconductor substrate 202 may facilitate the formation of the isolation region 504 and the subsequent formation of the liner structure.

[0101] After forming the isolation region 504 (and the optional high-k dielectric layer) on the back surface 202B, a passivation layer 506 may be deposited on the back surface 202B, such as Figure 5 As shown. The passivation layer 506 may be a dielectric layer, such as silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the passivation layer 506 is a protective layer or a hard mask (HM) layer grown or deposited on both the pixel region 203A and the pad region 203B.

[0102] Corresponds to Figure 1A Operation 110, Figure 6 FIG. 2 is a cross-sectional view of a BSI image sensor device 200 at one of various manufacturing stages, including a recess (opening or trench) 600. The recess 600 is formed in the pad region 203B to expose a portion of the dielectric layer 408. As shown, the recess 600 may extend through at least the passivation layer 506, the dielectric layer of the isolation region 504, the semiconductor substrate 202, the isolation region 302, and the ESL 402. The thinned semiconductor substrate 202 has a thickness T of about 6 μm. 1 In the example of FIG. 6 , the recess 600 is characterized by a depth T 2 , T 2 Substantially greater than 6 μm. It should be understood that the depth of the recess 600 may be between any suitable range of values ​​depending on the thickness of the thinned semiconductor substrate 202. Depending on the application for which the BSI image sensor device 200 is designed, the thickness of the thinned semiconductor substrate 202 (and the depth of the recess 600) may vary accordingly. For example, when the BSI image sensor device 200 is configured to absorb visible light, the thickness of the thinned semiconductor substrate 202 (and the depth of the recess 600) may be selected to be at least 2 μm.

[0103] The recess 600 may be formed by performing at least some of the following processes: forming a patternable layer (e.g., a photoresist (PR) layer) 602 over the passivation layer 506; patterning the patternable layer 602 in the pad region 203A to expose a portion of the passivation layer 506 aligned with the isolation region 302; etching (e.g., one or more dry etching processes) the passivation layer 506, the dielectric layer of the isolation region 504, the semiconductor substrate 202, the isolation region 302, and the ESL 402 to expose a portion of the dielectric layer 408; and removing the patternable layer 602.

[0104] Specifically, the dry etching process may use one or more different etching gases. For example, the material of the semiconductor substrate 202 (eg, silicon) may be etched using chlorine (Cl) gas in a first dry etching process. 2 ) and HBr gas mixture, which ends at the isolation region 302. In some embodiments, this first dry etching process etches about 200 angstroms (angstroms, ) to 300 angstroms. It should be understood that within the scope of the present disclosure, the first dry etching process can etch the isolation region 302 to any suitable depth. Subsequently, a second dry etching process, such as using tetrafluoromethane (CF 4 ) gas to remove the isolation region 302 and the endpoints on the ESL 402. The third dry overetching process, for example, uses octafluorocyclobutane (C 4 F 8 ) gas removes the ESL 402 to expose the dielectric layer 408 of the device layer 400, such as Figure 6 In other words, when at least a portion of the dielectric layer 408 of the device layer 400 in the pad region 203B is exposed through the recess 600 , the one or more etching processes may be terminated.

[0105] Corresponds to Figure 1A Operation 112, Figure 7 FIG. 2 is a cross-sectional view of a BSI image sensor device 200 at one of various manufacturing stages, including a first oxide layer 700. Figure 6 ), a first oxide layer 700 may be conformally deposited to line the recess 600 (eg, extending through the bottom surface 600B and the inner sidewalls 600S of the recess 600) and cover the exposed surfaces of the dielectric layer 408 and the passivation layer 506, as shown in FIG. Figure 7As shown. In some embodiments, the first oxide layer 700 is a silicon oxide dielectric, such as PEOX, with a thickness ranging from about 100 nm to about 700 nm. It should be understood that within the scope of the present disclosure, the thickness of the first oxide layer 700 can be between any suitable range of values. In some other embodiments, the first oxide layer 700 includes a material selected from USG, PSG, BPSG, FSG, a low-k dielectric material, and combinations thereof.

[0106] Corresponds to Figure 1A Operation 114, Figure 8 The cross-sectional view of the BSI image sensor device 200 at one of various manufacturing stages includes a spacer layer 800. In some embodiments, the spacer layer 800 (composed of a Figure 8 ). The etching process 802 may be an anisotropic etching process (eg, a reactive ion etching (RIE) process). Thus, the etching process 802 may remove respective portions of the first oxide layer 700 covering the passivation layer 506 and a portion of the bottom surface 600B.

[0107] For example, the remaining first oxide layer 700 (i.e., the spacer layer 800) may be formed to extend along at least a portion of the inner sidewall 600S and cover a portion of the bottom surface 600B. As shown, a portion of the inner sidewall 600S and the bottom surface 600B are coupled to each other, so that the corner of the recess 600 is covered by the spacer layer 800, while causing a portion of the bottom surface 600B to be exposed. Such an exposed portion of the bottom surface 600B (i.e., the exposed portion of the dielectric layer 408) may facilitate the formation of one or more liner structures thereon, which will be discussed below.

[0108] Each inner sidewall 600S may be defined by (e.g., constituted by) at least one of the following: a sidewall of the ESL 402, a sidewall of the semiconductor substrate 202 in the pad region 203B, a sidewall of a layer forming the isolation region 504, or a sidewall of the passivation layer 506. For example, Figure 8 The illustrated embodiment of (and the following cross-sectional views) depicts that a portion of the inner sidewall 600S along which the spacer layer 800 extends includes a sidewall of the ESL 402, a sidewall of the semiconductor substrate 202, and a portion of the sidewall of the layer forming the isolation region 504. However, it should be understood that the spacer layer 800 may extend across any combination of the sidewall of the ESL 402, the semiconductor substrate 202, the layer forming the isolation region 504, the passivation layer 506, and the layer between the isolation region 504 and the passivation layer 506 while remaining within the scope of the present disclosure.

[0109] According to various embodiments, the spacer layer 800 may be characterized as having a tapered profile. For example, the "tapered" spacer layer 800 may be formed to include a lower portion and an upper portion, wherein the lower portion is much wider (along the X-axis) than the upper portion. The width of the spacer layer 800 may gradually increase from the upper portion toward the lower portion. In some embodiments, the ratio of the lateral width of the lower portion of the spacer layer 800 to the width of the upper portion may be between about 2 and 5, although this ratio may be in other ranges and still within the scope of the present disclosure. By forming such a tapered spacer layer 800 in the recess 600, respective corners of the recess 600 may be filled by at least the lower portion of the spacer layer 800, which may effectively round these corners. Thus, even though the recess 600 may present a profile having a relatively high aspect ratio, when one or more layers are formed over the recess 600 (e.g., to fill the recess), it may significantly prevent the formation of voids in the recess 600. As a non-limiting example, the sum of the lateral widths of each lower portion of the spacer layer 800 may occupy an optimal ratio of the lateral width of the recess 600, for example, from about 0.1 to about 0.7. When the ratio is too low, voids may still be formed in the subsequently formed layer. On the other hand, in the case where the ratio is too high, there may not be enough space for the subsequently formed liner structure.

[0110] Fig. 9 and Fig.10 The example outlines of the spacer layer 800 according to various embodiments are described respectively. Fig. 9 , the spacer layer 800 is characterized by an arc-based profile 900. For example, the profile 900 may present a circular upper surface that is continuous from a lower portion to an upper portion of the spacer layer 800. Fig.10 , the spacer layer 800 is characterized by a faceted profile 1000. For example, the profile 1000 may include one or more facets (edges or bevels) 1000A and 1000B connected to each other from a lower portion to an upper portion of the spacer layer 800.

[0111] Corresponds to Figure 1B Operation 116, Fig.11 1 is a cross-sectional view of a BSI image sensor device 200 at one of various manufacturing stages, including a second oxide layer 1100. In some embodiments, the second oxide layer 1100 may be conformally deposited to line the recess 600 (e.g., to cover at least the spacer layer 800) and to cover the exposed surfaces of the dielectric layer 408 and the passivation layer 506, as shown in FIG. Fig.11As shown. Thus, the spacer layer 800 is disposed (e.g., sandwiched) between the inner sidewall 600S and the second oxide layer 1100. In some embodiments, the second oxide layer 1100 is a silicon oxide dielectric, such as PEOX, with a thickness ranging from about 100nm to about 700nm. It should be understood that within the scope of the present disclosure, the thickness of the second oxide layer 1100 can be between any suitable numerical range. In some other embodiments, the second oxide layer 1100 includes a material selected from USG, PSG, BPSG, FSG, a low-k dielectric material, and a combination thereof. Within the scope of the present disclosure, the second oxide layer 1100 may include any other suitable dielectric material.

[0112] According to various embodiments, the first oxide layer 700 (spacer layer 800) and the second oxide layer 1100 may include the same oxide material, but the first oxide layer 700 may be characterized by greater resistance to various etchants than the second oxide layer 1100. For example, the oxide material of the first oxide layer 700 may have a greater density than the oxide material of the second oxide layer 1100. In another example, the oxide material of the first oxide layer 700 may have a higher dielectric constant than the oxide material of the second oxide layer 1100.

[0113] Corresponds to Figure 1B Operation 118, Fig.12 4 is a cross-sectional view of BSI image sensor device 200 at one of various manufacturing stages, wherein one or more portions of line 412 in metallization layer 410A are exposed. In some embodiments, one or more dry etching processes may be performed on second oxide layer 1100 and dielectric layer 408 based on the pattern formed in recess 600 to expose one or more portions of line 412. Thus, one or more openings 1200 may be formed according to the pattern. After forming opening 1200, the pattern (e.g., formed on a photoresist layer) may be removed. For example, according to the photoresist layer having the pattern, such as using tetrafluoromethane (CF 4 ) gas to remove one or more portions of the second oxide layer 1100 and one or more portions of the dielectric layer 408 and the end points on the line 412 to form the opening 1200. After the opening 1200 is formed, the photoresist layer may be removed by an acid or an etchant. According to various embodiments, when etching the second oxide layer 1100 and the dielectric layer 408, the spacer layer 800 may remain covered by the second oxide layer 1100 (e.g., intact).

[0114] Corresponds to Figure 1B Operation 120, Fig.131 is a cross-sectional view of a BSI image sensor device 200 at one of various manufacturing stages, which includes one or more pad structures 1300. Pad structures 1300 are formed to physically contact lines 412 in metallization layer 410A. In some embodiments, a metal layer may be deposited to fill opening 1200 and then patterned in recess 600 to form pad structures 1300. For example, patterning of the metal layer may be accomplished by one or more photolithography processes followed by one or more etching processes. In some embodiments, pad structures 1300 include a metal alloy, such as aluminum copper (AlCu). However, this is not limiting, and other suitable metals or metal alloys may be used to form pad structures 1300.

[0115] Corresponds to Figure 1B Operation 122, Fig.14 The cross-sectional view of BSI image sensor device 200 at one of various manufacturing stages includes dielectric layer 1400. In some embodiments, dielectric layer 1400 (e.g., a USG layer or another oxide) is deposited on pad structure 1300. The top surface of dielectric layer 1400 may be polished by a CMP process that polishes and removes the deposited amount of dielectric layer 1400 on second oxide layer 1100.

[0116] Corresponds to Figure 1B Operation 124, Fig.15 1 is a cross-sectional view of BSI image sensor device 200 at one of various manufacturing stages, including opening 1500 extending through dielectric layer 1400. In some embodiments, dielectric layer 1400 is patterned such that opening 1500 is formed to expose a portion of pad structure 1300. By way of example and not limitation, Fig.15 Wire connectors, solder balls and / or bonding bumps not shown in the figure may be formed in the opening 1500. According to some embodiments, such a connector structure electrically connects the wire 412 of the metallization layer 410A to one or more external components via the pad structure 1300.

[0117] refer to Fig.16 , providing a top view of BSI image sensor device 200 viewed from back surface 202B of semiconductor substrate 202 . Figures 2 to 15 1 corresponds to a cross-sectional view of BSI image sensor device 200 taken along line AA'. As shown, BSI image sensor device 200 may include other pixels and pad structures substantially similar to pixels 204A-C and pad structures 1300, respectively. According to various embodiments, such pixels may form a pixel array 1602 laterally surrounded by one or more pad arrays 1604, each pad array including one or more of pad structures 1300. In some embodiments, such pad arrays 1604 may be located around the perimeter of semiconductor substrate 202.

[0118] In one aspect of the present disclosure, an image sensor device is disclosed. The image sensor device includes a semiconductor layer having a first surface and a second surface, the second surface being opposite to the first surface. The image sensor device includes a conductive structure disposed on the first surface, wherein a dielectric layer is disposed between the conductive structure and the first surface. The image sensor device includes a pad region including a recess extending through the semiconductor layer from the first surface to the second surface. The pad region further includes: a spacer layer extending along an inner sidewall of the recess; an oxide layer lining the recess above the spacer layer; and a pad structure extending through the oxide layer and the dielectric layer to physically contact the conductive structure.

[0119] In some embodiments, at least a portion of the oxide layer is in direct contact with the dielectric layer. In some embodiments, the conductive structure is one of a plurality of lateral interconnect structures, the lateral interconnect structure being disposed at the lowest layer of a plurality of metallization layers above the first surface of the semiconductor layer. In some embodiments, further comprising a plurality of radiation sensing regions above the first surface, the radiation sensing regions being configured to absorb radiation from the second surface. In some embodiments, the radiation sensing regions form an array laterally surrounded by the pad region. In some embodiments, the spacer layer comprises an upper portion having a first lateral width and a lower portion having a second lateral width, the second lateral width being greater than the first lateral width. In some embodiments, the spacer layer comprises a first oxide material, and the oxide layer comprises a second oxide material, the first oxide material having a greater etching resistance than the second oxide material. In some embodiments, the spacer layer and the oxide layer comprise the same polyethyloxazoline (PEOX), but the spacer layer has a greater etching resistance than the oxide layer. In some embodiments, the spacer layer and the oxide layer include the same material selected from the group consisting of silicon oxide, undoped silicate glass (USG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), and combinations thereof, but the spacer layer has greater etching resistance than the oxide layer. In some embodiments, the depth of the recess is at least about 2 μm.

[0120] In another aspect of the present disclosure, an image sensor device is disclosed. The image sensor device includes a plurality of pixels disposed above a first surface of a semiconductor layer. The image sensor device includes a device layer disposed above the first surface. The image sensor device includes a plurality of metallization layers disposed above the device layer. One of the metallization layers includes at least one conductive structure, the one of the metallization layers being closer to the first surface than other of the metallization layers. The image sensor device includes an oxide layer disposed above a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess, the recess extending through the semiconductor layer. The image sensor device includes a spacer layer disposed between a plurality of inner sidewalls of the recess and the oxide layer. The image sensor device includes a pad structure extending through the oxide layer and the device layer such that the pad structure is in physical contact with the at least one conductive structure.

[0121] In some embodiments, the device layer includes a nitride layer, the nitride layer covering a first portion of the first surface where the pixel is disposed, but not covering a second portion of the first surface where the recess is formed. In some embodiments, each of the pixels is configured to absorb radiation from the second surface. In some embodiments, the spacer layer extends along some inner sidewalls of the recess and has a profile that gradually narrows from the first surface to the second surface of the semiconductor layer. In some embodiments, the spacer layer includes a first oxide material, and the oxide layer includes a second oxide material, the first oxide material having a greater etching resistance than the second oxide material. In some embodiments, the spacer layer and the oxide layer include the same polyethyloxazoline (PEOX), but the spacer layer has a greater etching resistance than the oxide layer. In some embodiments, the spacer layer and the oxide layer include the same material selected from the group consisting of silicon oxide, undoped silicate glass (USG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG) and a combination thereof, but the spacer layer has a greater etching resistance than the oxide layer. In some embodiments, the pad structure is one of a plurality of pad structures located at a periphery of the semiconductor layer, and the pixel is surrounded by the periphery.

[0122] In another aspect of the present disclosure, a method includes forming a plurality of pixels above a first surface of a semiconductor layer, the plurality of pixels being configured to absorb radiation from a second surface of the semiconductor layer. The second surface of the semiconductor layer is opposite to the first surface of the semiconductor layer. The method includes forming a device layer above the first surface of the semiconductor layer. The method includes forming a metallization layer above the device layer. The method includes etching the second surface of the semiconductor layer to form a recess, the recess being laterally separated from the plurality of pixels. The method includes forming a spacer extending along the inner sidewall of the recess. The method includes forming an oxide layer above the second surface, wherein the spacer layer is sandwiched between the plurality of inner sidewalls and the oxide layer. The method includes etching a portion of the oxide layer and the device layer to expose a portion of the metallization layer. The method includes depositing a conductive material to form a pad structure electrically connected to the exposed portion of the metallization layer.

[0123] In some embodiments, the spacer layer has a profile that gradually narrows from the first surface to the second surface of the semiconductor layer.

[0124] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made thereto without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensor device, It is characterized in that Include: A semiconductor layer having a first surface and a second surface, the second surface being opposite to the first surface; a conductive structure disposed on the first surface, wherein a dielectric layer is disposed between the conductive structure and the first surface; and A pad region including a recess extending through the semiconductor layer from the first surface to the second surface, the pad region including: a spacer layer extending along the inner sidewalls of the recess, wherein the spacer layer includes an upper portion having a first lateral width and a lower portion having a second lateral width, the second lateral width being greater than the first lateral width; an oxide layer lining the recess above the spacer layer; and A liner structure extends through the oxide layer and the dielectric layer to physically contact the conductive structure, wherein a portion of the oxide layer is below a portion of the liner structure and between the liner structure and the dielectric layer.

2. The image sensor device according to claim 1, It is characterized in that At least a portion of the oxide layer is in direct contact with the dielectric layer.

3. The image sensor device according to claim 1, It is characterized in that The conductive structure is one of a plurality of lateral interconnect structures, and the lateral interconnect structure is disposed at a bottommost layer of a plurality of metallization layers above the first surface of the semiconductor layer.

4. The image sensor device according to claim 1, It is characterized in that Further included are a plurality of radiation sensing regions above the first surface, the plurality of radiation sensing regions being configured to absorb radiation from the second surface.

5. The image sensor device according to claim 4, It is characterized in that The plurality of radiation sensing regions form an array laterally surrounded by the pad region.

6. The image sensor device according to claim 1, It is characterized in that The spacer layer includes a first oxide material, and the oxide layer includes a second oxide material. The first oxide material has a greater etching resistance than the second oxide material.

7. The image sensor device according to claim 1, It is characterized in that The spacer layer and the oxide layer include the same polyethyloxazoline (PEOX), but the spacer layer has a greater etching resistance than the oxide layer.

8. The image sensor device according to claim 1, It is characterized in that The spacer layer and the oxide layer comprise the same material selected from a group consisting of silicon oxide, undoped silicate glass (USG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG) and combinations thereof, and the spacer layer has greater etching resistance than the oxide layer.

9. The image sensor device according to claim 1, It is characterized in that A depth of the recess is at least about 2 μm.

10. An image sensor device, It is characterized in that Include: A plurality of pixels are disposed above a first surface of a semiconductor layer; a device layer disposed above the first surface; a plurality of metallization layers disposed over the device layer, wherein one of the plurality of metallization layers comprises at least one conductive structure, the one of the plurality of metallization layers being closer to the first surface than other of the plurality of metallization layers; an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess extending through the semiconductor layer; a spacer layer disposed between the inner sidewalls of the concave portion and the oxide layer, the spacer layer extending along the inner sidewalls of the concave portion and having a profile gradually narrowing from the first surface to the second surface of the semiconductor layer; and A pad structure extends through the oxide layer and the device layer such that the pad structure is in physical contact with the at least one conductive structure, wherein a portion of the oxide layer is below a portion of the pad structure and between the pad structure and the device layer.

11. The image sensor device according to claim 10, It is characterized in that The device layer includes a nitride layer, which covers a first portion of the first surface where the plurality of pixels are arranged, but does not cover a second portion of the first surface where the concave portion is formed.

12. The image sensor device according to claim 10, It is characterized in that Each of the plurality of pixels is configured to absorb radiation from the second surface.

13. The image sensor device according to claim 10, It is characterized in that The spacer layer includes a first oxide material, and the oxide layer includes a second oxide material. The first oxide material has a greater etching resistance than the second oxide material.

14. The image sensor device according to claim 10, It is characterized in that The spacer layer and the oxide layer comprise the same polyethyloxazoline (PEOX), and the spacer layer has a greater etching resistance than the oxide layer.

15. The image sensor device according to claim 10, It is characterized in that The spacer layer and the oxide layer comprise the same material selected from a group consisting of silicon oxide, undoped silicate glass (USG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG) and a combination thereof, but the spacer layer has a greater etching resistance than the oxide layer.

16. The image sensor device according to claim 10, It is characterized in that The pad structure is one of a plurality of pad structures located at a periphery of the semiconductor layer, and the plurality of pixels are surrounded by the periphery.

17. A method of forming an image sensor device, It is characterized in that The following steps are involved: forming a plurality of pixels over a first surface of a semiconductor layer, the plurality of pixels being configured to absorb radiation from a second surface of the semiconductor layer, the second surface of the semiconductor layer being opposite to the first surface of the semiconductor layer; forming a device layer over the first surface of the semiconductor layer; forming a metallization layer over the device layer; Etching the second surface of the semiconductor layer to form a concave portion, the concave portion being laterally separated from the plurality of pixels; forming a spacer layer extending along a plurality of inner sidewalls of the recess, wherein the spacer layer has a profile gradually narrowing from the first surface to the second surface of the semiconductor layer; forming an oxide layer over the second surface, wherein the spacer layer is sandwiched between the plurality of inner sidewalls and the oxide layer; etching the oxide layer and a portion of the device layer to expose a portion of the metallization layer; and A conductive material is deposited to form a pad structure electrically connected to the exposed portion of the metallization layer.

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