Frequency Locking Circuit, Switching Circuit and Switching Method

Abstract

A frequency locking circuit, a switching circuit and a switching method. The frequency locking circuit includes a frequency generation circuit, a first impedance circuit, a second impedance circuit and a switching circuit. The frequency generation circuit includes a positive terminal and a negative terminal. The frequency generation circuit outputs an output clock signal according to the voltage difference between the positive terminal and the negative terminal. The first impedance circuit and the second impedance circuit are electrically connected to a first impedance node and a second impedance node respectively. The second impedance circuit adjusts its impedance value according to the output clock signal. The switching circuit is used to periodically conduct the negative terminal to one of the first impedance node or the second impedance node, and periodically conduct the positive terminal to the other of the first impedance node or the second impedance node. Accordingly, the jitter problem caused by noise can be eliminated.

Description

Technical Field

[0001] The present disclosure relates to a frequency locking circuit, particularly a circuit for outputting a clock signal. Background Art

[0002] In various electronic products, a clock generator is an indispensable component. A clean clock signal is usually generated by a quartz oscillator and then multiplied in frequency through a phase-locked loop. In order to save the quartz oscillator and still generate a clean clock signal, a low-noise frequency locked loop circuit (FLL) is adopted to replace the quartz oscillator to ensure the correctness and stability of the clock signal. Summary of the Invention

[0003] The present disclosure relates to a frequency locking circuit, including a frequency generating circuit, a first impedance circuit, a second impedance circuit, and a switching circuit. The frequency generating circuit includes a positive terminal and a negative terminal. The negative terminal is electrically connected to a first current source. The positive terminal is electrically connected to a second current source. The frequency generating circuit is configured to output an output clock signal according to the voltage difference between the positive terminal and the negative terminal. The first impedance circuit is electrically connected to a first impedance node. The second impedance circuit is electrically connected to a second impedance node. The second impedance circuit is configured to adjust the impedance value of the second impedance circuit according to the output clock signal. The switching circuit is electrically connected to the first impedance node, the second impedance node, the positive terminal, and the negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and is configured to periodically conduct the positive terminal to the other of the first impedance node and the second impedance node.

[0004] In one embodiment, the frequency generating circuit is further configured to generate a first clock signal and a second clock signal according to the output clock signal, and provide the first clock signal and the second clock signal to the second impedance circuit.

[0005] In one embodiment, the frequency generating circuit is further configured to generate a first control signal and a second control signal according to the output clock signal, and provide the first control signal and the second control signal to the switching circuit.

[0006] In one embodiment, the switching circuit further includes a plurality of switching units, the plurality of switching units including a first switching unit and a second switching unit. The first switching unit is electrically connected to the first impedance node, the second impedance node, and the negative terminal. The first switching unit is configured to conduct the negative terminal to one of the first impedance node and the second impedance node according to the first control signal and the second control signal. The second switching unit is electrically connected to the first impedance node, the second impedance node, and the positive terminal. The second switching unit is configured to conduct the positive terminal to the other of the first impedance node and the second impedance node according to the first control signal and the second control signal.

[0007] In one embodiment, the frequency of each of the first control signal and the second control signal is less than the frequency of each of the first clock signal and the second clock signal, and the first clock signal and the second clock signal are generated by a frequency generation circuit according to an output clock signal.

[0008] In one embodiment, the first control signal and the second control signal are opposite to each other.

[0009] In one embodiment, each of the plurality of switching units includes a first transistor switch and a second transistor switch. The first transistor switch is electrically connected to the first impedance node and the second impedance node, and is electrically connected to one of the positive terminal and the negative terminal. The first transistor switch is used to be turned on or off according to one of the first control signal and the second control signal. The second transistor switch is electrically connected to the first impedance node and the second impedance node, and is electrically connected to one of the positive terminal and the negative terminal. The second transistor switch is used to be turned on or off according to the other of the first control signal and the second control signal.

[0010] In one embodiment, the second impedance circuit includes a plurality of impedance units and a first capacitor, and the plurality of impedance units are electrically connected between the second impedance node and the reference voltage. The first capacitor is electrically connected between the second impedance node and the reference voltage.

[0011] In one embodiment, each of the plurality of impedance units includes a first impedance switch, a second impedance switch and a second capacitor. The first impedance switch is electrically connected to the second impedance node, and is used to be turned on or off according to the output clock signal. The second impedance switch is electrically connected to the first impedance node and the reference voltage, and is used to be turned on or off according to the output clock signal. The on - time of the first impedance switch and the second impedance switch are staggered from each other. The second capacitor is connected in parallel with the second impedance switch.

[0012] In one embodiment, the frequency generation circuit includes a chopper amplifier and a low - pass filter. The chopper amplifier is used to receive the voltage difference between the positive terminal and the negative terminal to output an operational voltage signal. The low - pass filter is electrically connected to the output terminal of the chopper amplifier to receive the operational voltage signal, and is used to filter the high - frequency signals in the operational voltage signal.

[0013] In one embodiment, the frequency generation circuit further includes a frequency conversion circuit. The frequency conversion circuit is used to receive the output signal from the low - pass filter, and is used to generate an output clock signal.

[0014] In one embodiment, the frequency generation circuit further includes a frequency divider. The frequency divider is electrically connected to the frequency conversion circuit and is configured to generate a first clock signal and a second clock signal based on the output clock signal, and to provide the first clock signal and the second clock signal to the second impedance circuit.

[0015] In one embodiment, a current mirror is further included. The current mirror includes a first current source and a second current source. The switching circuit further includes a first switching unit and a second switching unit. The first switching unit is electrically connected to the first current source through the negative terminal of the frequency generation circuit. The second switching unit is electrically connected to the second current source through the positive terminal of the frequency generation circuit.

[0016] The present disclosure also relates to a switching circuit, including a first switching unit and a second switching unit. The first switching unit is electrically connected to the first current source through the negative terminal of the frequency generation circuit, and is electrically connected to the first impedance circuit through a first impedance node and to the second impedance circuit through a second impedance node. The first switching unit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node. The second switching unit is electrically connected to the second current source through the positive terminal of the frequency generation circuit, and is electrically connected to the first impedance circuit through the first impedance node and to the second impedance circuit through the second impedance node. The second switching unit is configured to periodically conduct the positive terminal to the other of the first impedance node and the second impedance node.

[0017] In one embodiment, the first switching unit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node based on a first control signal and a second control signal. The second switching unit is configured to periodically conduct the positive terminal to the other of the first impedance node and the second impedance node based on the first control signal and the second control signal.

[0018] In one embodiment, either the first switching unit or the second switching unit includes a first transistor switch and a second transistor switch. The first transistor switch is electrically connected to one of the second impedance node, the positive terminal, and the negative terminal, and is configured to be turned on or off based on one of the first control signal and the second control signal. The second transistor switch is electrically connected to one of the first impedance node, the positive terminal, and the negative terminal, and is configured to be turned on or off based on the other of the first control signal and the second control signal, wherein the first control signal and the second control signal are opposite to each other.

[0019] In one embodiment, the first control signal and the second control signal are output by the frequency generation circuit.

[0020] The present disclosure also relates to a switching method, comprising the following steps: electrically connecting a switching circuit to a first impedance circuit, a second impedance circuit, the positive terminal of a frequency generating circuit, and the negative terminal of the frequency generating circuit; adjusting the impedance value of the second impedance circuit according to an output clock signal output by the frequency generating circuit; periodically conducting the negative terminal to one of the first impedance circuit and the second impedance circuit through a first switching unit in the switching circuit; and periodically conducting the positive terminal to the other of the first impedance circuit and the second impedance circuit through a second switching unit in the switching circuit.

[0021] In one embodiment, the method of periodically conducting the negative terminal to one of the first impedance circuit and the second impedance circuit comprises: conducting or turning off a first transistor switch in the first switching unit according to a first control signal; and conducting or turning off a second transistor switch in the first switching unit according to a second control signal, wherein the first control signal and the second control signal are opposite to each other.

[0022] In one embodiment, the method of periodically conducting the positive terminal to the other of the first impedance circuit and the second impedance circuit comprises: conducting or turning off a first transistor switch in the first switching unit according to the second control signal; and conducting or turning off a second transistor switch in the first switching unit according to the first control signal.

[0023] The present disclosure reduces the jitter problem caused by noise from a current source and a frequency generating circuit by periodically switching the negative terminal and the positive terminal to conduct to a first impedance node or a second impedance node. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of a frequency locking circuit according to some embodiments of the present disclosure;

[0025] Figure 2 Schematic diagram of a switching circuit according to some embodiments of the present disclosure;

[0026] Figure 3 Flowchart of a switching method according to some embodiments of the present disclosure;

[0027] Figure 4A Schematic diagram of the operating state of a frequency locking circuit according to some embodiments of the present disclosure;

[0028] Figure 4B Schematic diagram of the operating state of a frequency locking circuit according to some embodiments of the present disclosure.

[0029] SYMBOL DESCRIPTION

[0030] 100: Frequency locking circuit

[0031] 110: Frequency generation circuit

[0032] 111: Chopper amplifier

[0033] 111a: Chopper switch unit

[0034] 112: Low-pass filter

[0035] 113: Frequency conversion circuit

[0036] 114: Frequency divider

[0037] 115: Non-overlapping signal circuit

[0038] 120: First impedance circuit

[0039] 130: Second impedance circuit

[0040] 131: Impedance unit

[0041] 140: Switching circuit

[0042] 141: First switching unit

[0043] 142: Second switching unit

[0044] 150: Current mirror

[0045] CS1: First current source

[0046] CS2: Second current source

[0047] Sc: Output clock signal

[0048] Tp: Positive terminal

[0049] Tn: Negative terminal

[0050] N1: First impedance node

[0051] N2: Second impedance node

[0052] S1: First clock signal

[0053] S2: Second clock signal

[0054] PY1: First control signal

[0055] PY2: Second control signal

[0056] S0: Operational voltage signal

[0057] OP1: First operational amplifier

[0058] OP2: Second operational amplifier

[0059] Sh: High-frequency signal

[0060] T11: First transistor switch

[0061] T12: Second transistor switch

[0062] T21: First transistor switch

[0063] T22: Second transistor switch

[0064] W1: First impedance switch

[0065] W2: Second impedance switch

[0066] C1: First capacitor

[0067] C2: Second capacitor

[0068] S301 - S304: Steps Detailed implementation manners

[0069] The following will disclose multiple implementation manners of the present invention with the accompanying drawings. For the sake of clear illustration, many practical details will be described together in the following narration. However, it should be understood that these practical details are not used to limit the present invention. That is to say, in some implementation manners of the present invention, these practical details are not necessary. In addition, for the purpose of simplifying the accompanying drawings, some well-known conventional structures and elements will be shown in a simple schematic manner in the drawings.

[0070] In this article, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" can also be used to indicate the mutual cooperation operation or interaction between two or more elements. In addition, although terms such as "first", "second",... are used in this article to describe different elements, these terms are only used to distinguish the elements or operations described with the same technical terms. Unless clearly specified in the context, these terms do not particularly refer to or imply an order or sequence, nor are they used to limit the present invention.

[0071] Please refer to Figure 1 as shown Figure 1Schematic diagram of a frequency-locking circuit 100 according to some embodiments of the present disclosure. The frequency-locking circuit 100 includes a frequency generation circuit 110, a first impedance circuit 120, a second impedance circuit 130, and a switching circuit 140. The frequency-locking circuit 100 is used to form a loop that can lock the output clock signal Sc. The operation of the frequency-locking circuit 100 is briefly described below. During operation, a plurality of current mirrors 150 (such as a first current source CS1 and a second current source CS2) are used to generate a plurality of currents, and the plurality of currents will be converted by the first impedance circuit 120 to generate corresponding input voltages. The first impedance circuit 120 provides the corresponding input voltages to the frequency generation circuit 110. The frequency generation circuit 110 is used to convert the corresponding input voltages into corresponding frequencies, which are represented by the output clock signal Sc here. The output clock signal Sc is used to generate a plurality of control signals to feedback and control its operation, and is also used to adjust the impedance value of the second impedance circuit 130. Accordingly, a loop for locking the frequency of the output clock signal Sc can be formed.

[0072] The frequency generation circuit 110 includes a positive terminal Tp and a negative terminal Tn. The negative terminal Tn is electrically connected to the first current source CS1. The positive terminal Tp is electrically connected to the second current source CS2. The frequency generation circuit 110 is used to output an output clock signal Sc according to the voltage difference between the positive terminal Tp and the negative terminal Tn.

[0073] The first impedance circuit 120 is electrically connected to a first impedance node N1. The first impedance circuit 120 may include at least one impedance element, such as including a resistor and a capacitor connected in parallel with it. The second impedance circuit 130 is electrically connected to a second impedance node N2. In some embodiments, the impedance value of the second impedance circuit 130 is adjusted by the frequency generation circuit 110 according to at least one feedback signal. As Figure 1 shown, the second impedance circuit 130 is used to adjust the impedance value of the second impedance circuit 130 according to the output clock signal Sc. In other words, the impedance value of the second impedance circuit 130 is variable, and the details will be described in the following paragraphs. The change in the impedance value of the second impedance circuit 130 is generated according to the feedback signal provided by the signal generation circuit 110. Through the difference between the impedance value of the second impedance circuit 130 and the impedance value of the first impedance circuit 120, a voltage difference between the first impedance node N1 and the second impedance node N2 will be further generated. Accordingly, a loop for locking the frequency of the output clock signal S can be formed.

[0074] The switching circuit 140 is electrically connected to the first impedance node N1, the second impedance node N2, the positive terminal Tp, and the negative terminal Tn. The switching circuit 140 is configured to periodically connect the negative terminal Tn to one of the first impedance node N1 and the second impedance node N2, and periodically connect the positive terminal Tp to the other of the first impedance node N1 and the second impedance node N2. By operating the switching circuit 140, the jitter generated by the current source 150 and the frequency generation circuit 110 can be reduced.

[0075] The output clock signal Sc is generated by the frequency generation circuit 110, and the frequency of the output clock signal Sc is locked according to the voltage difference between the positive terminal Tp and the negative terminal Tn. However, the signals transmitted by the current sources CS1 and CS2 may still have noise and generate jitter. On the other hand, the transistor switches (such as the transistors in the operational amplifier) in the frequency generation circuit 110 may also generate noise when processing signals. The present disclosure reduces the jitter generated by the noise from the current source 150 and the frequency generation circuit 110 by periodically switching the negative terminal Tn and the positive terminal Tp to conduct to the first impedance node N1 or the second impedance node N2.

[0076] In addition, the switching circuit 140 is periodically electrically connected between the "negative terminal Tn / positive terminal Tp" and the "first impedance node N1 / second impedance node N2". Therefore, the noise generated by either the current sources CS1 and CS2 or the frequency generation circuit 110 can be weakened or removed through the switching operation of the switching circuit 140. Specifically, the switching circuit 140 and the chopper amplifier 111 in the frequency generation circuit 110 perform the switching operation simultaneously to completely eliminate the noise, so the output clock signal Sc generated by the frequency locking circuit 100 will not have jitter.

[0077] In some embodiments, the frequency generation circuit 110 is further configured to generate a first clock signal S1 and a second clock signal S2 according to the output clock signal Sc, and provide the first clock signal S1 and the second clock signal S2 to the second impedance circuit 130. The first clock signal S1 and the second clock signal S2 are used to control the switches in the second impedance circuit 130 to adjust the impedance value of the second impedance circuit 130. In other embodiments, the first clock signal S1 and the second clock signal S2 can be generated by other circuits or processors in addition to being generated by the frequency generation circuit 110. In other words, the first clock signal S1 and the second clock signal S2 are not limited to being generated through a feedback path.

[0078] In some embodiments, the frequency generation circuit 110 is further configured to generate a first control signal PY1 and a second control signal PY2 according to the output clock signal Sc, and provide the first control signal PY1 and the second control signal PY2 to the switching circuit 140. The first control signal PY1 and the second control signal PY2 are used to control the switches in the switching circuit 140 to adjust the conduction mode of the switching circuit 140.

[0079] Please refer to Figure 1 , Figure 1 FIG. is a schematic circuit diagram of the frequency generation circuit 110 according to some embodiments of the present disclosure. In some embodiments, the frequency generation circuit 110 further includes a chopper amplifier 111, a low-pass filter 112, and a frequency conversion circuit 113. The frequency generation circuit 110 includes a frequency divider 114. The chopper amplifier 111 is configured to receive (or detect) the voltage difference between the positive terminal Tp and the negative terminal Tn and output an operational voltage signal S0. For example, within a preset time, the chopper amplifier 111 first receives the input signal of the frequency generation circuit 110 through the positive terminal Tp and the negative terminal Tn. Then, the chopper amplifier 111 can perform averaging on the received input signal. Accordingly, the low-frequency noise in the signal output by the chopper amplifier 111 can be filtered.

[0080] In operation, the switching circuit 140 and the chopper amplifier 111 can modulate or shift the low-frequency components (such as flicker noise) in the noise generated by the current source 150 and the frequency generation circuit 110 to a high-frequency band. The low-pass filter 112 can then filter the high-frequency noise (such as the modulated flicker noise). Since the low-frequency components of the flicker noise are the main components of the noise, most of the noise effects can be reduced as long as these low-frequency components are filtered out. In other words, the switching operations performed synchronously by the switching circuit 140 and the chopper amplifier 111 can completely eliminate the noise in the output clock signal Sc.

[0081] As Figure 1As shown, in some embodiments, the chopper amplifier 111 includes a first operational amplifier OP1, a chopper switch unit 111a, and a second operational amplifier OP2. The chopper switch unit 111a is electrically connected to the output terminal of the first operational amplifier OP1 and periodically switches any one of the output terminals of the first operational amplifier OP1 to be coupled between the input terminals of the second operational amplifier OP2. The switching operation synchronously performed by the switching circuit 140 and the chopper amplifier 111 is used to eliminate the noise of the output clock signal Sc. Specifically, the switching circuit 140 can modulate the signal to a high frequency band. At the same time, if the noise originates from the first operational amplifier OP1 in the current source 150 and the frequency generation circuit 110, the noise will be in the low frequency band. Then, the operation of the chopper switch unit 111a can modulate the signal back and modulate the noise to a high frequency. Thereafter, the low-pass filter 112 can filter or eliminate the noise shifted to the high frequency band. Since those skilled in the art can understand the circuit structure and principle of the chopper amplifier 111, it will not be repeated here.

[0082] The low-pass filter 112 is electrically connected to the output terminal of the chopper amplifier 111 to receive the operational voltage signal S0 and is used to filter the high-frequency signal Sh in the operational voltage signal S0.

[0083] The frequency conversion circuit 113 is used to receive the output signal of the low-pass filter 112 (i.e., the high-frequency signal Sh) and generate the output clock signal Sc. The output clock signal Sc can be used as the locked-frequency clock signal output by the frequency generation circuit 110.

[0084] The shunt 114 is electrically connected to the frequency conversion circuit 113. The shunt 114 is used to generate a first clock signal S1, a second clock signal S2, a first control signal PY1, and a second control signal PY2 according to the output clock signal Sc. The first clock signal S1 and the second clock signal S2 are used to control the second impedance circuit 130. The first control signal PY1 and the second control signal PY2 are used to control the switching circuit 140. The shunt 114 provides the first clock signal S1 and the second clock signal S2 to the second impedance circuit 130 and provides the first control signal PY1 and the second control signal PY2 to the switching circuit 140.

[0085] In some embodiments, the shunt 114 generates the first control signal PY1 and the second control signal PY2 through a non-overlapping signal circuit 115. The non-overlapping signal circuit 115 is used to ensure that the first control signal PY1 and the second control signal PY2 are not simultaneously turned on or simultaneously turned off.

[0086] Please refer to Figure 1 and Figure 2 , Figure 2Schematic diagram of a switching circuit 140 according to some embodiments of the present disclosure. The switching circuit 140 includes a plurality of switching elements. In some embodiments, the plurality of switching elements include switching elements such as a first switching element 141 and a second switching element 142. As Figure 2 shown, the first switching unit 141 is electrically connected to a first impedance node N1, a second impedance node N2, and a negative terminal Tn. The first switching unit 141 is configured to conduct the negative terminal Tn to one of the first impedance node N1 and the second impedance node N2 according to a first control signal PY1 and a second control signal PY2.

[0087] The second switching unit 142 is electrically connected to the first impedance node N1, the second impedance node N2, and a positive terminal Tp. The second switching unit 142 is configured to conduct the positive terminal Tp to the other one of the first impedance node N1 and the second impedance node N2 according to the first control signal PY1 and the second control signal PY2.

[0088] The first switching unit 141 and the second switching unit 142 periodically conduct the negative terminal Tn (or the positive terminal Tp) to the first impedance node N1 or the second impedance node N2 according to the first control signal PY1 and the second control signal PY2. In some embodiments, the frequency of each of the first control signal PY1 and the second control signal PY2 is less than the frequency of each of the first clock signal S1 and the second clock signal S2. The first control signal PY1 and the second control signal PY2 are opposite to each other (e.g., opposite voltage levels).

[0089] In some embodiments, each switching element 141, 142 includes a two-transistor switch to periodically conduct the negative terminal Tn (or the positive terminal Tp) to the first impedance node N1 or the second impedance node N2. As Figure 2 shown, the first switching unit 141 includes a first transistor switch T11 and a second transistor switch T12. The first transistor switch T11 is electrically connected to the second impedance node N2 and the negative terminal Tn. The first transistor switch T11 is configured to conduct or turn off according to the first control signal PY1. The second transistor switch T12 is electrically connected to the first impedance node N1 and the negative terminal Tn. The second transistor switch T12 is configured to conduct or turn off according to the second control signal PY2.

[0090] Similarly, the second switching unit 142 includes a first transistor switch T21 and a second transistor switch T22. The first transistor switch T21 is electrically connected to the second impedance node N2 and the positive terminal Tp. The first transistor switch T21 is configured to conduct or turn off according to the second control signal PY2. The second transistor switch T22 is electrically connected to the first impedance node N1 and the positive terminal Tp. The second transistor switch T22 is configured to conduct or turn off according to the first control signal PY1.

[0091] Continuing from above, the impedance value of the second impedance circuit 130 can be adjusted according to the first clock signal S1 and the second clock signal S2. The change in the impedance value of the second impedance circuit 130 is based on the feedback signal of the signal generation circuit 110, and can cause the impedance value of the second impedance circuit 130 to differ from the impedance value of the first impedance circuit 120, thereby forming a voltage difference at the two impedance nodes N1 and N2, forming a loop for locking the frequency of the output clock signal Sc.

[0092] Please refer to Figure 1 , in some embodiments, the second impedance circuit 130 includes a plurality of impedance elements 131, 132 and a first capacitor C1. Each of the impedance elements 131, 132 is electrically connected to the second impedance node N2 and a reference voltage (such as: ground potential). The first capacitor C1 is electrically connected between the second impedance node N2 and the reference voltage, and is used to stabilize the voltage of the second impedance node N2.

[0093] Taking the impedance unit 131 as an example, the impedance unit 131 includes a first impedance switch W1, a second impedance switch W2 and a second capacitor C2. The first impedance switch W1 is electrically connected to the second impedance node N2, and is used to be controlled to conduct or turn off according to the output clock signal Sc (such as: the first clock signal S1). The second impedance switch W2 is electrically connected between the first impedance switch W1 and the reference voltage. The second impedance switch W2 is used to be controlled to conduct or turn off according to the output clock signal Sc (such as: the second clock signal S2). The conduction times of the first impedance switch W1 and the second impedance switch W2 are staggered from each other. In other words, the voltage levels of the first clock signal S1 and the second clock signal S2 are opposite to each other. The second capacitor C2 is connected in parallel with the second impedance switch W2.

[0094] When the first clock signal S1 is at the enable level and the second clock signal S2 is at the disable level, the first impedance switch W1 is turned on and the second impedance switch W2 is turned off. At this time, the second capacitor C2 will be charged through the second impedance node N2. On the other hand, when the first clock signal S1 is at the disable level and the second clock signal S2 is at the enable level, the first impedance switch W1 is turned off, and the second impedance switch W2 is turned on. At this time, the second capacitor C2 is discharged through the second impedance switch W2. Then, as the first clock signal S1 and the second clock signal S2 change, the impedance value of the impedance unit 131 will also change accordingly.

[0095] The circuit of the impedance unit 132 is similar to that of the impedance unit 131, but the first impedance switch W1 of the impedance unit 132 is used to be controlled according to the second clock signal S2, and the second impedance switch W2 of the impedance unit 132 is used to be controlled according to the first clock signal S1. Accordingly, the second capacitor C2 in the impedance unit 131 and the second capacitor C2 in the impedance unit 132 will not be charged or discharged simultaneously.

[0096] In addition, in some embodiments, the frequency-locking circuit 100 further includes a current mirror 150. The current mirror 150 includes a first current source CS1 and a second current source CS2. The second switching unit 141 is electrically connected to the first current source CS1 through the negative terminal Tn of the frequency generation circuit 110, and is electrically connected to the second impedance circuit 130 through the second impedance node N2. The first switching unit 141 is configured to periodically conduct the negative terminal Tn to the first impedance node N1 or the second impedance node N2.

[0097] The second switching unit 142 is electrically connected to the second current source CS2 through the positive terminal Tp of the frequency generation circuit 110, and is electrically connected to the second impedance circuit 130 through the second impedance node N2. The second switching unit 142 is configured to periodically conduct the positive terminal Tp to the first impedance node N1 or the second impedance node N2.

[0098] Please refer to Figure 3 , Figure 3 FIG. is a flowchart of a switching method according to some embodiments of the present disclosure. In step S301, the switching circuit 140 is electrically connected to the first impedance circuit 120, the second impedance circuit 130, the positive terminal Tp, and the negative terminal T. Then, the frequency generation circuit 110 outputs the output clock signal Sc according to the voltage difference between the positive terminal Tp and the negative terminal Tn, and generates a first clock signal S1, a second clock signal S2, a first control signal PY1, and a second control signal PY2 according to the output clock signal Sc.

[0099] In step S302, the second impedance circuit 130 adjusts the impedance value of the second impedance circuit 130 according to the output clock signal Sc. In step S303, the second switching unit 141 in the switching circuit 140 periodically conducts the negative terminal Tn to one of the first impedance circuit 120 and the second impedance circuit 130.

[0100] In step S304, the second switching unit 142 of the switching circuit 140 periodically conducts the positive terminal Tp to the other one of the first impedance circuit 120 and the second impedance circuit 130.

[0101] Please refer to Figure 1 and Figure 4AAs shown, in the first week, the first control signal PY1 is an enabling level, and the second control signal PY2 is a disabling level. In other words, the first control signal PY1 and the second control signal PY2 are opposite to each other. Therefore, both the first transistor switch T11 and the second transistor switch T22 are turned on. The second transistor switch T12 and the first transistor switch T21 are both turned off. At this time, the second switching unit 141 conducts the negative terminal Tn to the second impedance circuit 130 through the first transistor switch T11. The second switching unit 142 conducts the positive terminal Tp to the first impedance circuit 120 through the second transistor switch T22.

[0102] Similarly, please refer to Figure 1 and Figure 4B As shown, in the second cycle, the first control signal PY1 is a disabling level, and the second control signal PY2 is an enabling level. Therefore, the second transistor switch T12 and the first transistor switch T21 are turned on. The first transistor switch T11 and the second transistor switch T22 are turned off. At this time, the second switching unit 141 conducts the negative terminal Tn to the first impedance circuit 120 through the second transistor switch T12. The second switching unit 142 conducts the positive terminal Tp to the second impedance circuit 130 through the first transistor switch T21.

[0103] As described in the foregoing embodiments, the switching circuit is used to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other of the first impedance node and the second impedance node. Through the synchronous switching operation of the switching circuit and the chopper amplifier in the frequency generation circuit, the elimination of noise can be achieved. Therefore, due to the noise in the current source and the frequency generation circuit, the jitter phenomenon of the output clock signal output by the frequency locking circuit can be reduced.

[0104] The various elements, method steps or technical features in the foregoing embodiments can be combined with each other, and are not limited by the order of text description or the order of illustration in this disclosure.

[0105] Although this disclosure has been disclosed in the above embodiments, it is not intended to limit this disclosure. Any person skilled in this art can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the protection scope of this disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A frequency locking circuit, characterized in that: Include: a frequency generating circuit comprising a positive terminal and a negative terminal, wherein the negative terminal is electrically connected to a first current source and the positive terminal is electrically connected to a second current source, and the frequency generating circuit is configured to output an output clock signal according to a voltage difference between the positive terminal and the negative terminal; a first impedance circuit electrically connected to a first impedance node; a second impedance circuit electrically connected to a second impedance node, wherein the second impedance circuit is configured to adjust an impedance value of the second impedance circuit according to the output clock signal; as well as a switching circuit electrically connected to the first impedance node, the second impedance node, the positive terminal, and the negative terminal, wherein the switching circuit is configured to periodically connect the negative terminal to one of the first impedance node and the second impedance node, and to periodically connect the positive terminal to the other of the first impedance node and the second impedance node; The second impedance circuit includes a plurality of impedance units and a first capacitor. The plurality of impedance units are electrically connected between the second impedance node and a reference voltage. The first capacitor is electrically connected between the second impedance node and the reference voltage.

2. The frequency locking circuit according to claim 1, wherein: The frequency generating circuit is further configured to generate a first clock signal and a second clock signal according to the output clock signal, and provide the first clock signal and the second clock signal to the second impedance circuit.

3. The frequency locking circuit according to claim 1, wherein: The frequency generating circuit is further configured to generate a first control signal and a second control signal according to the output clock signal, and provide the first control signal and the second control signal to the switching circuit.

4. The frequency locking circuit according to claim 1, wherein: The switching circuit further includes a plurality of switching units, wherein the plurality of switching units include: a first switching unit electrically connected to the first impedance node, the second impedance node, and the negative terminal, wherein the first switching unit is configured to conduct the negative terminal to one of the first impedance node and the second impedance node according to a first control signal and a second control signal; as well as A second switching unit is electrically connected to the first impedance node, the second impedance node and the positive terminal, wherein the second switching unit is used to conduct the positive terminal to the other of the first impedance node and the second impedance node according to the first control signal and the second control signal.

5. The frequency locking circuit according to claim 4, characterized in that: The frequency of each of the first control signal and the second control signal is lower than the frequency of each of a first clock signal and a second clock signal, which are generated by the frequency generating circuit according to the output clock signal.

6. The frequency locking circuit according to claim 4, characterized in that: The first control signal and the second control signal are opposite to each other.

7. The frequency locking circuit according to claim 4, characterized in that: Each of the plurality of switching units includes: a first transistor switch electrically connected to the first impedance node and the second impedance node, and electrically connected to one of the positive terminal and the negative terminal, wherein the first transistor switch is configured to be turned on or off according to one of the first control signal and the second control signal; and A second transistor switch is electrically connected to the first impedance node and the second impedance node, and is electrically connected to one of the positive terminal and the negative terminal, wherein the second transistor switch is used to be turned on or off according to the other of the first control signal and the second control signal.

8. The frequency locking circuit according to claim 1, wherein: Each of the plurality of impedance units comprises: a first impedance switch electrically connected to the second impedance node and configured to be turned on or off according to the output clock signal; a second impedance switch electrically connected to the first impedance node and the reference voltage, and configured to be turned on or off according to the output clock signal, wherein the on-times of the first impedance switch and the second impedance switch are staggered; and A second capacitor is connected in parallel to the second impedance switch.

9. A frequency locking circuit, comprising: a frequency generating circuit comprising a positive terminal and a negative terminal, wherein the negative terminal is electrically connected to a first current source and the positive terminal is electrically connected to a second current source, and the frequency generating circuit is configured to output an output clock signal according to a voltage difference between the positive terminal and the negative terminal; a first impedance circuit electrically connected to a first impedance node; a second impedance circuit electrically connected to a second impedance node, wherein the second impedance circuit is configured to adjust an impedance value of the second impedance circuit according to the output clock signal; and a switching circuit electrically connected to the first impedance node, the second impedance node, the positive terminal, and the negative terminal, wherein the switching circuit is configured to periodically connect the negative terminal to one of the first impedance node and the second impedance node, and to periodically connect the positive terminal to the other of the first impedance node and the second impedance node; It is characterized in that The frequency generating circuit comprises: a chopper amplifier for receiving a voltage difference between the positive terminal and the negative terminal to output a calculation voltage signal; and A low-pass filter is electrically connected to an output terminal of the chopper amplifier to receive the operation voltage signal and filter a high-frequency signal in the operation voltage signal.

10. The frequency locking circuit according to claim 9, characterized in that: The frequency generating circuit further includes a frequency converting circuit. The frequency converting circuit is used to receive an output signal from the low-pass filter and to generate the output clock signal.

11. The frequency locking circuit according to claim 10, wherein: The frequency generating circuit further includes a frequency divider electrically connected to the frequency conversion circuit and configured to generate a first clock signal and a second clock signal according to the output clock signal, and to provide the first clock signal and the second clock signal to the second impedance circuit.

12. The frequency locking circuit according to claim 9, wherein: It also includes a current mirror, which includes the first current source and the second current source; the switching circuit also includes a first switching unit and a second switching unit, the first switching unit is electrically connected to the first current source through the negative terminal of the frequency generating circuit; the second switching unit is electrically connected to the second current source through the positive terminal of the frequency generating circuit.

13. A switching method, characterized in that: Include: A switching circuit is electrically connected to a first impedance circuit, a second impedance circuit, a positive terminal of a frequency generating circuit, and a negative terminal of the frequency generating circuit, wherein the first impedance circuit is electrically connected to a first impedance node, and the second impedance circuit is electrically connected to a second impedance node; adjusting an impedance value of the second impedance circuit according to an output clock signal output by the frequency generating circuit, wherein the second impedance circuit comprises a plurality of impedance units and a first capacitor, the plurality of impedance units being electrically connected between the second impedance node and a reference voltage, and the first capacitor being electrically connected between the second impedance node and the reference voltage; The negative terminal is periodically connected to one of the first impedance node and the second impedance node through a first switching unit in the switching circuit; as well as The positive terminal is periodically conducted to the other of the first impedance node and the second impedance node through a second switching unit in the switching circuit.

14. The switching method according to claim 13, wherein: The method of periodically conducting the negative terminal to one of the first impedance node and the second impedance node includes: Turning on or off a first transistor switch in the first switching unit according to a first control signal; and A second transistor switch in the first switching unit is turned on or off according to a second control signal, wherein the first control signal and the second control signal are opposite to each other.

15. The switching method according to claim 14, characterized in that: The method of periodically conducting the positive terminal to the other of the first impedance node and the second impedance node includes: Turning on or off a first transistor switch in the first switching unit according to a second control signal; and A second transistor switch in the first switching unit is turned on or off according to a first control signal.

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