Image sensor driving circuit including power switch and image sensor

Abstract

A driver circuit of an image sensor is provided. The driver circuit includes: a row decoder that decodes an address indicating a target row of a pixel array and generates an operation instruction signal corresponding to the target row; a digital logic circuit including: a target row logic circuit that generates a pixel control signal based on the operation instruction signal; a power switch that is configured to connect a power supply voltage to the target row logic circuit during a first time period based on the operation instruction signal and to isolate the power supply voltage from the target row logic circuit during a second time period; an output circuit that is configured to output a default signal during the second time period; and a row driver that is configured to drive the target row based on the pixel control signal during the first time period and to drive the target row based on the default signal during the second time period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0175243 filed on December 26, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Apparatuses and methods according to example embodiments relate to a driving circuit of an image sensor, and more particularly, to an image sensor driving circuit including a power switch and an image sensor including the driving circuit. Background Art

[0004] Various electronic devices such as smart phones, personal computers (PCs), digital cameras, or digital camcorders are equipped with image sensors for obtaining and processing images. The image sensor may include a pixel array that converts external light into electrical signals and obtains an image. The pixel array may include a plurality of pixels arranged in two dimensions, and the image sensor may include a driving circuit for controlling the operation of the pixel array.

[0005] When the driving circuit of the image sensor operates, leakage current is generated at the driving circuit. The amount of leakage current at the driving circuit increases due to the following reasons: the manufacturing technology applied to the reduced scale of the driving circuit; the increase in the number of internal components of the driving circuit according to high-resolution image acquisition and various additional functions; and the increase in operating temperature according to the reduction in size of the electronic device. The increase in the amount of leakage current of the driving circuit may cause the power consumption of the electronic device to increase and the temperature of the electronic device to increase, thereby reducing the image quality. Therefore, a method for reducing the leakage current of the driving circuit is needed. Summary of the invention

[0006] One or more example embodiments provide an image sensor driving circuit including a power switch capable of reducing leakage current and preventing increases in temperature and power consumption, and an image sensor including the same.

[0007] According to an example embodiment, a driver circuit of an image sensor includes: a row decoder configured to decode an address indicating a target row of a pixel array and generate an operation indication signal corresponding to the target row; a digital logic circuit including: a target row logic circuit configured to generate a pixel control signal corresponding to the target row based on the operation indication signal; a power switch configured to connect a power supply voltage to the target row logic circuit during a first time period based on the operation indication signal, and to isolate the power supply voltage from the target row logic circuit during a second time period; and an output circuit configured to output a default signal during a second time period based on the operation indication signal; and a row driver configured to drive the target row of the pixel array based on the pixel control signal during the first time period, and to drive the target row of the pixel array based on the default signal during the second time period.

[0008] According to an example embodiment, a driver circuit of an image sensor includes: a row decoder configured to decode an address and generate an operation indication signal having an enable level during a first time, the operation indication signal indicating an operation of a target row of a pixel array; a latch including: a target row latch configured to detect the operation indication signal at a first time, and generate an operation signal having an enable level during a second time after the first time based on the operation indication signal at the first time; a power gating control circuit configured to generate a power gating signal based on the operation indication signal; and a first power switch configured to connect a power supply voltage to the target row latch during a first time and a second time based on the power gating signal; and a digital logic circuit including: a target row logic circuit configured to generate a pixel control signal corresponding to the target row based on the operation signal; and a second power switch configured to connect the power supply voltage to the target row logic circuit during the first time and the second time based on the power gating signal.

[0009] According to an example embodiment, an image sensor includes: a pixel array including a plurality of pixels; a driver circuit connected to rows of the pixel array through row lines, the driver circuit configured to control a first operation and a second operation of each row; and a conversion circuit connected to columns of the pixel array through column lines, the conversion circuit configured to receive an image signal from the pixel array through the column lines according to the first operation and the second operation of the pixel array, and convert the received image signal into a digital image signal. The driver circuit includes: a row decoder configured to decode an address indicating a target row of the pixel array and generate an operation indication signal corresponding to the target row, wherein the first operation and the second operation are performed in the target row of the pixel array; a digital logic circuit including: a target row logic circuit configured to generate a pixel control signal corresponding to the target row based on the operation indication signal; and a power switch configured to connect a power supply voltage to the target row logic circuit based on the operation indication signal when the target row logic circuit generates the pixel control signal corresponding to the first operation and the second operation; and a row driver configured to control the first operation and the second operation of the target row based on the pixel control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features will become apparent from the following description of example embodiments with reference to the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of an image sensor according to example embodiments.

[0012] Figure 2 is a circuit diagram of a pixel according to example embodiments.

[0013] Figure 3 is a timing diagram for describing the operation of an image sensor according to example embodiments.

[0014] Figure 4 is a timing diagram of shutter time and read time according to example embodiments.

[0015] Figure 5 is a block diagram of a driver circuit according to an example embodiment.

[0016] Figure 6 is a block diagram of a driver circuit according to an example embodiment.

[0017] Figure 7 is a timing diagram of signals input to the front buffer according to example embodiments.

[0018] Figure 8 is a timing diagram of signals generated by a first row decoder and a second row decoder according to an example embodiment.

[0019] Fig. 9is a circuit diagram of a digital logic circuit according to an example embodiment.

[0020] Fig.10 is a timing diagram of digital logic circuit signals according to an example embodiment.

[0021] Fig.11 is a block diagram of a driver circuit according to an example embodiment.

[0022] Fig.12 is a timing diagram of signals input to the front buffer according to example embodiments.

[0023] Fig.13 is a timing diagram of signals generated by a latch according to an example embodiment.

[0024] Fig.14 is a circuit diagram of a digital logic circuit and a latch according to an example embodiment.

[0025] Fig.15 is a timing diagram of latch signals according to an example embodiment.

[0026] Fig.16 is a timing diagram of digital logic circuit signals according to an example embodiment.

[0027] Fig.17 is a block diagram of a driver circuit according to an example embodiment.

[0028] Fig.18 is a block diagram of an electronic system according to an example embodiment. DETAILED DESCRIPTION

[0029] By describing the example embodiments in detail with reference to the accompanying drawings, the above and other aspects and features will become clearer. It will be understood that when an element or layer is referred to as being "above", "above", "on", "connected to" or "coupled to" another element or layer, it can be directly above, above, on, directly connected to or coupled to the other element or layer, or there can be an intermediate element or layer. On the contrary, when an element is referred to as being "directly on" another element or layer "above", "above", "on", "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer. Throughout the accompanying drawings, the same reference numerals represent the same elements.

[0030] Figure 1 is a block diagram of an image sensor according to example embodiments. Figure 1, the image sensor 1000 may include a pixel array 100, a driver circuit 200, a conversion circuit 300, an output buffer 400, and a timing controller 500. The image sensor 1000 may be implemented in various electronic devices (e.g., digital cameras, smart phones, tablet PCs, and wearable devices). The image sensor 1000 may be implemented with an integrated circuit (IC), a system on chip (SoC), and the like.

[0031] The pixel array 100 includes a plurality of pixels PX arranged in two dimensions. Each of the plurality of pixels PX may convert a light signal sensed from the outside into a pixel signal as an electrical signal. For example, the plurality of pixels PX may generate an electrical signal based on the amount of light incident on each corresponding pixel PX. The pixel array 100 may generate an image signal IS as an analog signal including pixel signals generated by the plurality of pixels PX. The pixel array 100 may be controlled by a pixel control signal provided from the driver circuit 200, and may generate an image signal IS. The image signal IS may be provided to the conversion circuit 300 through a plurality of column lines.

[0032] The driver circuit 200 may select a row of one or more pixels of the pixel array 100. The pixels included in the selected row may generate pixel signals, which are provided to the conversion circuit 300. To this end, the driver circuit 200 may generate pixel control signals corresponding to the selected row, and may provide the pixel control signals to the pixel array 100. The pixel control signals may be provided to the pixel array 100 via row lines. For example, the pixel control signals may include a transmission control signal TG provided to a transmission transistor of each pixel PX, a reset control signal RG provided to a reset transistor of each pixel PX, and a selection signal SEL provided to a selection transistor of each pixel PX. The pixel control signals will be described in more detail later.

[0033] The conversion circuit 300 may convert the analog image signal IS into a digital image signal IDAT. The conversion circuit 300 may receive pixel signals generated by pixels of a row selected by the driver circuit 200 in parallel through column lines, and may convert the received pixel signals into digital signals. The conversion circuit 300 may perform various operations for converting analog signals into digital signals. For example, the conversion circuit 300 may perform correlated double sampling (CDS) for extracting effective signal components.

[0034] The output buffer 400 may store the digital image signal IDAT generated by the conversion circuit 300. The output buffer 400 may output the digital image signal IDAT to an image signal processor (ISP).

[0035] The timing controller 500 may control the overall operation of the image sensor 1000. The timing controller 500 may provide control signals TC1, TC2, and TC3 to the driver circuit 200, the conversion circuit 300, and the output buffer 400, respectively, and may drive the image sensor 1000. The driver circuit 200 may generate a pixel control signal based on the first control signal TC1. The conversion circuit 300 may convert the image signal IS into a digital image signal IDAT based on the second control signal TC2. Based on the third control signal TC3, the output buffer 400 may temporarily store the digital image signal IDAT, and may output the temporarily stored digital image signal IDAT to the outside.

[0036] Figure 2 is a circuit diagram of a pixel according to an example embodiment. For example, Figure 2 The circuit diagram can be compared with Figure 1 The pixels correspond to the reference Figure 2 , the pixel PX may include a photoelectric conversion element PD, a floating diffusion region FD, a transfer transistor TX, a reset transistor RX, a selection transistor SX, and a drive transistor DX. Figure 2 The structure shown is an example, and other pixel structures may be Figure 1 For example, the pixel PX may further include a storage transistor connected between the transfer transistor TX and the floating diffusion region FD. In this case, Figure 1 The driver circuit 200 may also generate a storage control signal for controlling the storage transistor.

[0037] The photoelectric conversion element PD generates and accumulates charges according to the amount of incident light or the intensity of incident light. For example, the photoelectric conversion element PD can be implemented by (but not limited to) a photodiode including InGaAs for sensing light in the infrared band. For example, the photoelectric conversion element PD can be a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof.

[0038] The transfer transistor TX can transfer the charge generated and accumulated by the photoelectric conversion element PD to the floating diffusion area FD. The transfer transistor TX can be connected between the photoelectric conversion element PD and the floating diffusion area FD. The transfer transistor TX can be turned on or off by the transfer control signal TG. Figure 1 The driver circuit 200 provides a transfer control signal TG. When the transfer transistor TX is turned on, the charge generated and accumulated by the photoelectric conversion element PD can be transferred to the floating diffusion area FD. When the transfer transistor TX is turned off, the photoelectric conversion element PD can accumulate the charge.

[0039] The floating diffusion region FD may accumulate charges transferred from the photoelectric conversion element PD through the transfer transistor TX. The drive transistor DX may be controlled according to the amount of charges accumulated at the floating diffusion region FD.

[0040] The reset transistor RX may reset the charge accumulated at the floating diffusion region FD. The reset transistor RX may be connected between the floating diffusion region FD and the pixel power supply voltage VPIX. The reset transistor RX may be turned on or off by a reset signal RG. The reset signal RG may be Figure 1 The driver circuit 200 is provided. When the reset transistor RX is turned on, the pixel power supply voltage VPIX may be transmitted to the floating diffusion region FD. In this case, the charges accumulated at the floating diffusion region FD may be released, and thus the floating diffusion region FD may be reset.

[0041] The driving transistor DX may be a source follower buffer amplifier that generates a source-drain current proportional to the amount of charge of the floating diffusion region FD input to the gate terminal of the driving transistor DX. The driving transistor DX may amplify the potential change of the floating diffusion region FD and may output the amplified signal to the column line CL through the selection transistor SX. The signal thus output may be a pixel signal.

[0042] The selection transistor SX is used to select the pixel PX to be read in units of rows. The selection transistor SX can be turned on or off by the selection signal SEL. Figure 1 The driver circuit 200 provides a selection signal SEL. When the selection transistor SX is turned on, the pixel signal output from the driving transistor DX can be output to the column line CL.

[0043] Figure 3 is a timing diagram for describing the operation of an image sensor according to an example embodiment. For example, Figure 3 The timing diagram can describe Figure 1 The operation of the image sensor. Figure 3 , the horizontal axis indicates time, and the vertical axis indicates rows of the pixel array 100. The pixel array 100 may be operated in units of rows under the control of the driver circuit 200. For ease of description, reference will be made to Figure 1 Reference numerals / symbol pairs Figure 3 Give a description.

[0044] The shutter time advances sequentially from row 0 to the last row. The shutter time can be used to reset the Figure 2The shutter time is the operation time of the driver circuit 200 for the charge accumulated at the photoelectric conversion element PD of the driver circuit 200. The shutter time can be determined according to the operation mode of the driver circuit 200, and how to determine the shutter time will be described later. Through the shutter time, the charge generated and accumulated at the pixel PX of each row is removed. After the shutter time, the photoelectric conversion element PD of each pixel PX can regenerate and accumulate charge. The charge can be accumulated until the reading time.

[0045] After the charge is generated and accumulated at each pixel PX, the read time advances sequentially from the 0th row to the last row. The read time may be an operation time of the driver circuit 200 for generating and reading a pixel signal based on the accumulated charge. The read time may be determined depending on the operation mode of the driver circuit 200, and how to determine the read time will be described later. Through the read time, the charge accumulated at the photoelectric conversion element PD is transferred to the floating diffusion region FD, and a pixel signal is generated based on the charge accumulated at the floating diffusion region FD. The pixel signal may be output to the conversion circuit 300 during the read time. During one frame time, the read operation is sequentially performed from the 0th row to the last row.

[0046] according to Figure 3 In the rolling shutter method of the pixel array 100, the charge reset operation can be sequentially performed on each row of the pixel array 100. However, the example embodiment is not limited thereto. For example, a global shutter method can be used, in which the charge reset operation is performed on all rows of the pixel array 100 at the same shutter time (or simultaneously during the shutter time). In addition, in addition to the shutter time and the read time, an additional operation time can be provided depending on the circuit structure of the pixel PX. The power gating of the driver circuit of the example embodiment described later can be applied to the global shutter method, without being limited to Figure 3 A rolling shutter mode can be used and additional operating time can be applied.

[0047] Figure 4 is a timing diagram for implementing shutter time and read time according to example embodiments. Figure 4 The timing diagram is in Figure 3 The timing diagram of the pixel control signal in the time TT. Figure 4 , the horizontal axis indicates time, and the vertical axis indicates levels of a transfer control signal TG, a reset control signal RG, and a selection signal SEL included in the pixel control signal.

[0048] The transmission control signal TG, the reset control signal RG and the selection signal SEL are Figure 1 The driver circuit 200 generates. Figure 1 and Figure 2 The transmission control signal TG is provided to Figure 2The transfer transistor TX, the reset control signal RG is provided to Figure 2 The reset transistor RX, and the selection signal SEL is provided to Figure 2 Assume that a high level pixel control signal turns on the transistor.

[0049] During at least a portion of the shutter time, the transfer control signal TG turns on the transfer transistor TX. During the shutter time, because the reset control signal RG turns on the reset transistor RX, the accumulated charge can be released from the photoelectric conversion element PD through the transfer transistor TX and the reset transistor RX. After the transfer transistor TX is turned off, the photoelectric conversion element PD can sense light and can generate and accumulate charge. The charge can be accumulated until the accumulation time.

[0050] During at least a portion of the read time, the transfer control signal TG turns on the transfer transistor TX. During the at least a portion of the read time, because the reset control signal RG turns off the reset transistor RX, the accumulated charge can be transferred from the photoelectric conversion element PD to the floating diffusion region FD through the transfer transistor TX. In this way, a pixel signal can be generated. During the at least a portion of the read time, because the selection signal SEL turns on the selection transistor SX, the pixel signal can be output to the conversion circuit 300 through the column line.

[0051] In the driving time for generating an image signal, the remaining time in the driving time except the shutter time and the reading time can be referred to as an idle time. During the idle time, the pixel control signal can maintain a default level. For example, in the case of the transmission control signal TG and the selection signal SEL, the low level can be the default level; in the case of the reset control signal RG, the high level can be the default level. The idle time can be determined according to the operation mode of the driver circuit 200, and how to determine the idle time will be described later. In order to reduce the leakage current of the driver circuit 200, during the idle time when the default level is maintained, power supply to some components of the driver circuit 200 can be blocked.

[0052] Figure 5 is a block diagram of a driver circuit according to an example embodiment. For example, Figure 5 The driver circuit can be connected with Figure 1 The driver circuit corresponds to Figure 5 , the driver circuit 200 may include a front buffer 210, a row decoder 220, a digital logic circuit 230, and a row driver 240. The driver circuit 200 may operate based on a control signal TC1 of the timing controller 500.

[0053] The front buffer 210 may receive and temporarily store a signal for generating a pixel control signal. For example, the signal for generating a pixel control signal may include an address ADDR and operation information TRT. The front buffer 210 may output the stored address ADDR to the row decoder 220, and may output the stored operation information TRT to the digital logic circuit 230.

[0054] The address ADDR may indicate a row of the pixel array 100 on which a specific operation is performed. For example, the address ADDR may indicate a row of the pixel array 100 on which a shutter operation is performed. For example, the address ADDR may indicate a row of the pixel array 100 on which a read operation is performed. The address ADDR may be generated within the driver circuit 200. However, example embodiments are not limited thereto. For example, the address ADDR may be included in the control signal TC1, or may be generated by an external device of the image sensor 1000.

[0055] The operation information TRT may include information about a pattern of pixel control signals for performing a specific operation. For example, the operation information TRT may include a pattern of a transmission control signal TG, a reset control signal RG, and a selection signal SEL used in a shutter time or a read time. The operation information TRT may be generated within the driver circuit 200. However, example embodiments are not limited thereto. For example, the operation information TRT may be included in the control signal TC1, or may be generated by an external device of the image sensor 1000.

[0056] The row decoder 220 can decode the address ADDR and generate an operation instruction signal indicating a specific operation of the row. When the address ADDR indicates a target row, the operation instruction signal of the target row can have an enable level. For example, the idle time and the driving time of a specific operation can be distinguished by the operation instruction signal. Figure 5 The operation indication signal described in the above may have an enable level within a time range for performing a specific operation. However, the operation indication signal may be a signal that is latched to generate an operation signal indicating a time range for performing a specific operation, which will be referred to as Fig.11 Give a description.

[0057] For example, the operation instruction signal may include shutter signals S0, S1, S2, and SI from row 0 to row 1, each shutter signal indicating a time range for performing a specific operation. For example, the operation instruction signal may include read signals R0, R1, R2, and RI from row 0 to row 1, each read signal indicating a time range for performing a read operation. Although not shown, in the presence of other operations for the pixel array 100, the row decoder 220 may decode the address ADDR and may also generate an operation instruction signal indicating a time range for performing the other operation.

[0058] The time when a specific operation is performed but not indicated by the operation indication signal can be referred to as idle time. Figure 3 As described above, the time to perform a specific operation on each row may be different, and therefore, the idle times respectively corresponding to the rows may be different.

[0059] The digital logic circuit 230 may generate a pixel control signal based on the operation instruction signal and the operation information TRT. For example, the pixel control signal may include transmission control signals TG0, TG1, TG2, and TGI applied to a plurality of rows, reset control signals RG0, RG1, RG2, RGI, and selection signals SEL0, SEL1, SEL2, and SELI. The digital logic circuit 230 may apply various modes of the transistor control signal included in the operation information TRT to the execution time of a specific operation controlled by the operation instruction signal, and may generate a pixel control signal.

[0060] The digital logic circuit 230 may include row logic circuits corresponding to a plurality of rows, respectively. Each of the row logic circuits may generate a pixel control signal corresponding to a corresponding row. During an idle time, a power supply voltage may not be supplied to each of the row logic circuits. To this end, power switches corresponding to the row logic circuits, respectively, may be provided. The power switch may isolate the power supply voltage from the row logic circuit during the idle time based on an operation indication signal, and connect the power supply voltage to the row logic circuit during the time when a specific operation is performed.

[0061] Compared with any other component of the driver circuit 200 (e.g., the front buffer 210, the row decoder 220, and the row driver 240), more leakage current may flow at the digital logic circuit 230. Unlike the front buffer 210, the row decoder 220, and the row driver 240, the digital logic circuit 230 may be composed of digital elements, and most of the leakage current may occur at the digital elements. When compared with the front buffer 210, the row decoder 220, and the row driver 240, the number of elements of the digital logic circuit 230 may be significantly higher. For example, row by row, the number of elements included in the front buffer 210 may be minimal, and the row decoder 220 and the row driver 240 may include about 20 elements. However, row by row, the number of elements included in the digital logic circuit 230 may exceed 300. Therefore, even if only the digital logic circuit 230 is powered off during the idle time, the leakage current of the driver circuit 200 can be significantly reduced.

[0062] The row driver 240 drives each row of the pixel array 100 based on the pixel control signal generated by the digital logic circuit 230. For example, the row driver 240 may adjust the level of the pixel control signal so as to be suitable for the characteristics of the transistors of the pixel array 100, and may output the pixel control signal after the level adjustment to the row line.

[0063] Figure 6 is a block diagram of a driver circuit according to an example embodiment. For example, Figure 6 The block diagram can be compared with Figure 1 The driver circuit corresponds to Figure 6 , the driver circuit 200a may include a front buffer 210a, a first row decoder 221a, a second row decoder 222a, a digital logic circuit 230a, and a row driver 240a. Figure 5 The same components, additional description will be omitted to avoid redundancy. A description will be given on the assumption that the driver circuit 200a operates to drive the above-described shutter operation and reading operation.

[0064] The front buffer 210a can receive and temporarily store the shutter address SA, the read address RA, the transfer transistor operation information OTX, the reset transistor operation information ORX and the selection transistor operation information OSX. It can be understood that the shutter address SA and the read address RA are included in Figure 5 The address ADDR, and the transmission transistor operation information OTX, the reset transistor operation information ORX and the selection transistor operation information OSX are included in Figure 5 The operation information TRT.

[0065] The first row decoder 221a can decode the shutter address SA to generate shutter signals S0, S1, S2 and SI. The second row decoder 222a can decode the read address RA to generate read signals R0, R1, R2 and RI. In the case where the pixel array 100 requires additional operations other than the shutter operation and the read operation, an additional row decoder may be further included in the driver circuit 200a. In this case, addresses for the additional operations may also be provided to the driver circuit 200a.

[0066] The digital logic circuit 230a may apply the transmission transistor operation information OTX, the reset transistor operation information ORX, and the selection transistor operation information OSX to the shutter time indicated by the shutter signals S0, S1, S2, and SI and the read time indicated by the read signals R0, R1, R2, and RI. As a result of the application, the transmission control signals TG0, TG1, TG2, and TGI, the reset control signals RG0, RG1, RG2, RGI, and the selection signals SEL0, SEL1, SEL2, and SELI may be generated. During the idle time determined based on the shutter signals S0, S1, S2, and SI and the read signals R0, R1, R2, and RI, power may not be supplied to the digital logic circuit 230a. The row driver 240a drives each row of the pixel array 100 based on the pixel control signal generated by the digital logic circuit 230a.

[0067] Figure 7 is a timing diagram of signals input to the front buffer according to an example embodiment. For example, Figure 7 The timing diagram can indicate the input to Figure 6 signal of the front buffer. Figure 7 The shutter address SA, the read address RA, the transfer transistor operation information OTX, the reset transistor operation information ORX, and the selection transistor operation information OSX are shown over time. Figure 7 The input signal is used to execute Figure 3 operation.

[0068] The shutter address SA sequentially indicates the rows where the shutter operation is performed. The shutter address SA indicates the rows where the shutter operation is performed in units of horizontal time HT. Figure 3 As shown, the shutter address SA may indicate rows sequentially starting from row 0.

[0069] The read address RA sequentially indicates the rows where the read operation is to be performed. The read address RA indicates the rows where the read operation is to be performed in units of horizontal time HT. Figure 3 As shown, when the shutter address SA indicates the third row, the read address RA may indicate the 0th row during the horizontal time HT. The read address RA may indicate rows sequentially from the 0th row.

[0070] The transmission transistor operation information OTX, the reset transistor operation information ORX, and the selection transistor operation information OSX may have a waveform that repeats in a cycle of the horizontal time HT. Figure 4 The pattern of the transmission control signal TG, the reset control signal RG and the selection signal SEL in the shutter time or the reading time corresponds to the pattern of the transmission transistor operation information OTX, the reset transistor operation information ORX and the selection transistor operation information OSX can be used to generate the pixel control signal in the shutter time or the reading time.

[0071] Figure 8 is a timing diagram of signals generated by a first row decoder and a second row decoder according to an example embodiment. Figure 8 The timing diagram can indicate the Figure 6 The first row decoder and the second row decoder generate signals. Figure 8 Shutter signals S0, S1, S2, S3, and S4 and read signals R0, R1, R2, R3, and R4 are shown over time. The first row decoder 221a may decode the shutter address SA to generate shutter signals S0, S1, S2, S3, and S4, and the second row decoder 222a may decode the read address RA to generate read signals R0, R1, R2, R3, and R4.

[0072] refer to Figure 8 , when the shutter address SA indicates a target row, the shutter signal corresponding to the target row may have an enable level (or a high level). When the read address RA indicates a target row, the read signal corresponding to the target row may have an enable level. Because the shutter address SA and the read address RA indicate one row during the horizontal time HT, the time interval during which each of the shutter signals S0, S1, S2, S3, and S4 and the read signals R0, R1, R2, R3, and R4 has an enable level may be equal to the time interval of the horizontal time HT.

[0073] The time when each of the shutter signals S0, S1, S2, S3, and S4 has an enable level may be referred to as a shutter time. The time when each of the read signals R0, R1, R2, R3, and R4 has an enable level may be referred to as a read time. The shutter time and the read time may be determined in units of a horizontal time HT. The shutter time and the read time may be determined differently for each row.

[0074] In one embodiment, as described above, the power switch PS is turned on based on the power gating signal PG of the enable level and turned off based on the power gating signal PG of the disable level. Since the power gating signal PG can have an enable level during the shutter time and the read time, the power switch PS can be configured to maintain its current state during the horizontal time HT.

[0075] and Figure 8The time corresponding to the shaded portion of indicates the idle time of each row. In the case where the operation for driving the pixel array 100 includes only a shutter operation and a read operation, the idle time may correspond to the remaining time in the drive time of the image sensor 1000 except the shutter time and the read time, row by row. However, in the case where an additional operation of the pixel array 100 is performed row by row, the idle time may correspond to the remaining time in the drive time of the image sensor 1000 except the shutter time and the read time and the time for the additional operation. Like the shutter time and the read time, the idle time of the row may be determined to be different from each other. Therefore, the power supply voltage may not be supplied to the row logic circuit included in the digital logic circuit 230a at different times. In other words, the row logic circuit included in the digital logic circuit 230a may be isolated from the power supply voltage at different times. For example, when the row logic circuit corresponding to the second row may be connected to the power supply voltage, the row logic circuit corresponding to the first row may be isolated from the power supply voltage.

[0076] Fig. 9 is a circuit diagram of a digital logic circuit according to an example embodiment. For example, Fig. 9 The circuit diagram can be compared with Figure 6 corresponding to the digital logic circuit. Fig. 9 The digital logic circuit 230a can be understood as a structure that generates a pixel control signal corresponding to a target row (for example, the first row). Because the digital logic circuit 230a generates pixel control signals corresponding to multiple rows, multiple digital logic circuits 230a can be provided so that a digital logic circuit 230a is provided for each row. Fig. 9 , the digital logic circuit 230a may include a row logic circuit (or a first row logic circuit) 231a, a power gating control circuit 232a, a power gating circuit 233a, and an output circuit 234a.

[0077] The row logic circuit 231a may apply operation information corresponding to the shutter time and the read time indicated by the shutter signal S1 and the read signal R1, respectively, and may generate a pixel control signal. The operation information may include transfer transistor operation information OTX, reset transistor operation information ORX, and selection transistor operation information OSX. The pixel control signal may include a transfer control signal TG, a reset control signal RG, and a selection signal SEL.

[0078] The power gating control circuit 232a may generate a power gating signal PG based on the shutter signal S1 and the read signal R1. The power gating control circuit 232a may include a NOR gate NOR and an inverter Inv. In this case, the power gating signal PG may be the same as the result of performing an "OR" operation on the shutter signal S1 and the read signal R1. That is, the power gating signal PG may have an enable level during the shutter time and the read time, and may have a disable level during the idle time.

[0079] The power gating circuit 233a may transmit the power supply voltage VDD to the row logic circuit 231a based on the power gating signal PG. The power gating circuit 233a may include a power switch PS that is turned on based on the power gating signal PG of the enable level and turned off based on the power gating signal PG of the disable level. The power switch PS may transmit the power supply voltage VDD to the row logic circuit 231a during the shutter time and the read time. During the idle time, the power switch PS may not transmit the power supply voltage VDD to the row logic circuit 231a.

[0080] The output circuit 234a may transmit the pixel control signal to the row driver 240a based on the power gating signal PG. To this end, the output circuit 234a may include a first output switch SS, a second output switch RS, and a third output switch TS. The first to third output switches SS, RS, and TS may operate based on the power gating signal PG. During the shutter time and the read time, the row logic circuit 231a may generate a selection signal SEL1, a reset control signal RG1, and a transmission control signal TG1. The selection signal SEL1 may be output through the first output switch SS, the reset control signal RG1 may be output through the second output switch RS, and the transmission control signal TGI may be output through the third output switch TS.

[0081] During the idle time, since the power supply voltage VDD is not supplied to the row logic circuit 231a, the row logic circuit 231a does not generate a pixel control signal. In order to transmit a signal corresponding to the level of the pixel control signal to the row driver 240a, the output circuit 234a may further include a first default switch SDS, a second default switch RDS, and a third default switch TDS. The first default switch SDS, the second default switch RDS, and the third default switch TDS may operate based on an inverted power gating signal.

[0082] During the idle time, the first default switch SDS, the second default switch RDS, and the third default switch TDS may transmit a default signal to the row driver 240a. The default signal may include a default signal SELd having a default level of the selection signal SEL1, a default signal RGd having a default level of the reset control signal RG1, and a default signal TGd having a default level of the transmission control signal TG1. Even if the power supply voltage VDD is not supplied to the row logic circuit 231a to reduce leakage current, the driver circuit 200 may stably drive the pixel array 100 by using the default signal during the idle time.

[0083] Fig.10 is a timing diagram of signals input to a digital logic circuit according to an example embodiment. For example, Fig.10 The timing diagram can indicate the input to Figure 6 A digital logic circuit or Figure 6 The signals generated by digital logic circuits. Fig.10 An operation indication signal, a power gate signal PG, operation information, and a pixel control signal are shown over time. For ease of description, a signal for generating a pixel control signal corresponding to a target row (e.g., the first row) is shown. In addition, for ease of description, only a shutter operation and a read operation are shown herein. Although additional operations other than the shutter operation and the read operation are not shown, example embodiments are not limited thereto.

[0084] The power gating signal PG is generated based on the shutter signal S1 and the read signal R1. The power gating signal PG may be generated by performing an OR operation on the shutter signal S1 and the read signal R1. That is, the power gating signal PG may have an enable level during the shutter time and the read time, and may have a disable level during the idle time.

[0085] During the shutter time, the row logic circuit 231a can generate a transfer control signal TG1 based on the transfer transistor operation information OTX. During the read time, the row logic circuit 231a can generate a transfer control signal TG1, a reset control signal RG1, and a selection signal SEL1 based on the transfer transistor operation information OTX, the reset transistor operation information ORX, and the selection transistor operation information OSX. That is, a pixel control signal corresponding to a specific operation can be generated by using the operation information repeated in the horizontal time (HT).

[0086] During the idle time, power is not supplied to the row logic circuit 231a based on the power gating signal PG. Therefore, the row logic circuit 231a may not output a pixel control signal of any level. However, the output circuit 234a may provide a default level of the pixel control signal to the row driver 240a, so that the pixel control signal remains at the default level during the idle time.

[0087] Fig.11 is a block diagram of a driver circuit according to an example embodiment. For example, Fig.11 The block diagram can be compared with Figure 1 The driver circuit corresponds to Fig.11 The driver circuit 200b includes a front buffer 210b, a row decoder 221b, a digital logic circuit 230b, a row driver 240b, and a latch 250b. Figure 6 Compared with the driver circuit 200a, according to the additional operation of the pixel array 100, Fig.11 The driver circuit 200b may not require an additional row decoder. Figure 5 The driver circuit 200 and Figure 6 The same description is given of the driver circuit 200a to avoid redundancy. A description will be given on the assumption that the driver circuit 200b operates to drive the above-mentioned shutter operation and reading operation.

[0088] The front buffer 210b can receive and temporarily store the address VA, the transmission transistor operation information OTX, the reset transistor operation information ORX, the selection transistor operation information OSX and the latch information. The latch information includes the latch set signal LSET, the shutter set signal SSET, the read set signal RSET and the latch reset signal LRST, and is used for the operation of the latch 250b. The latch information will be described in more detail later.

[0089] The address VA may indicate a row of the pixel array 100 on which a shutter operation is performed and a row of the pixel array 100 on which a read operation is performed. Unlike the shutter address SA and the read address RA described above, the address VA may indicate both a target row of the shutter operation and a target row of the read operation in a time-division manner.

[0090] The row decoder 221b can decode the address VA and generate an operation indication signal DVA, which indicates the shutter operation and the read operation of each row. For example, the operation indication signal corresponding to the first row can indicate the start of the shutter operation of the first row and the start of the read operation of the first row. Because the address VA indicates all rows for (or performing) the shutter operation and the read operation during one horizontal time, the timing of the address VA indicating the start of the shutter operation or the read operation can be less than the horizontal time. In other words, both the time when the address VA indicates the start of the shutter operation and the time when the address VA indicates the start of the read operation can be within one horizontal time.

[0091] The latch 250b can generate shutter signals S0, S1, S2 and SI and read signals R0, R1, R2 and RI based on the operation indication signal DVA. The latch 250b can detect the operation indication signal DVA indicating the shutter operation by using the shutter set signal SSET. The latch 250b can detect the operation indication signal DVA indicating the read operation by using the read set signal RSET. After detecting the operation indication signal DVA indicating the shutter operation, the latch 250b can change the level of the shutter signal to an enable level by using the latch set signal LSET. After detecting the operation indication signal DVA indicating the read operation, the latch 250b can change the level of the read signal to an enable level by using the latch set signal LSET. During the time interval of the horizontal time, the shutter signals S0, S1, S2 and SI and the read signals R0, R1, R2 and RI can have an enable level.

[0092] The digital logic circuit 230b can apply the transfer transistor operation information OTX, the reset transistor operation information ORX and the selection transistor operation information OSX to the shutter signals S0, S1, S2 and SI and the read signals R0, R1, R2 and RI. As a result of the application, the transfer control signals TG0, TG1, TG2 and TGI, the reset control signals RG0, RG1, RG2, RGI and the selection signals SEL0, SEL1, SEL2 and SELI can be generated. The row driver 240b drives each row of the pixel array 100 based on the pixel control signal generated by the digital logic circuit 230b.

[0093] During the idle time, power may not be provided to the latch 250b and the digital logic circuit 230b. The idle time may be the remaining time of the driving time of the driver circuit 200 except the time for the shutter operation and the read operation (i.e., the shutter time and the read time). The shutter time for the shutter operation may be started by the operation indication signal DVA and may end when the shutter signals S0, S1, S2, and SI have a disable level. The read time for the read operation may be started by the operation indication signal DVA and may end when the read signals R0, R1, R2, and RI have a disable level. The latch 250b may generate a signal for distinguishing the idle time from the shutter time and the read time.

[0094] Fig.12 is a timing diagram of a signal input to a front buffer according to an example embodiment. For example, a timing diagram of a signal may be input to Fig.11 front buffer. Fig.12The address VA, the transfer transistor operation information OTX, the reset transistor operation information ORX, the selection transistor operation information OSX, the latch set signal LSET, the shutter set signal SSET, the read set signal RSET and the latch reset signal LRST are shown over time. Fig.12 The input signal is used to execute Figure 3 operation.

[0095] The address VA sequentially indicates the rows where the shutter operation and the read operation are performed. The address VA indicates the rows where the shutter operation and the read operation are performed within the horizontal time HT in a time division manner. Figure 3 As shown, the address VA may indicate rows sequentially starting from row 0. Figure 7 As described above, the transmission transistor operation information OTX, the reset transistor operation information ORX, and the selection transistor operation information OSX may have waveforms that are repeated at a period of the horizontal time HT.

[0096] The latch set signal LSET, the shutter set signal SSET, the read set signal RSET, and the latch reset signal LRST may have a waveform that repeats in the period of the horizontal time HT. The shutter set signal SSET may have an enable level in the time period of the address VA indicating the shutter operation to indicate that the shutter operation is indicated. The read set signal RSET may have an enable level in the time period of the address VA indicating the read operation to indicate that the read operation is indicated. Depending on the shutter set signal SSET or the read set signal RSET, the latch set signal LSET and the latch reset signal LRST may be used to generate a shutter signal or a read signal having an enable level during the period of the horizontal time HT.

[0097] Fig.13 is a timing diagram of a signal generated by a latch according to an example embodiment. For example, the timing diagram of the signal may be provided to Fig.11 of the latch. Fig.13 Shutter signals S0, S1, S2, S3 and S4 and read signals R0, R1, R2, R3 and R4 are shown over time. The row decoder 220b can decode the address VA and can generate operation instruction signals DVA corresponding to the rows respectively. For example, the operation instruction signal corresponding to the first row can have an enable level during the time of indicating the shutter operation of the first row in the second horizontal time HT, and can have an enable level during the time of indicating the read operation of the first row in the fifth horizontal time HT. The latch 250b can generate shutter signals S0, S1, S2, S3 and S4 and read signals R0, R1, R2, R3 and R4 by using the operation instruction signal DVA and latch information.

[0098] refer to Fig.13, when the address VA indicates the shutter operation of the target row, the shutter set signal SSET can detect the operation indication signal of the enable level. For example, the latch 250b can detect the shutter set signal SSET of the enable level. After the detection, each of the shutter signals S0 to S4 having the enable level can be generated in synchronization with the time when the latch set signal LSET has the enable level during the time interval of the horizontal time HT. When the address VA indicates the read operation of the target row, the read set signal RSET can detect the operation indication signal of the enable level. For example, the latch 250b can detect the read set signal RSET of the enable level. After the detection, each of the read signals R0 to R4 having the enable level can be generated in synchronization with the time when the latch set signal LSET has the enable level during the time interval of the horizontal time HT.

[0099] The time from the time point when each of the operation instruction signals DVA starts to indicate the shutter operation to the time point when the enable level of each of the shutter signals S0 to S4 ends can be referred to as the shutter time. The time from the time point when each of the operation instruction signals DVA starts to indicate the read operation to the time point when the enable level of each of the read signals R0 to R4 ends can be referred to as the read time. The shutter time and the read time can be determined differently for each row.

[0100] In each row, with Fig.13 The time corresponding to the shaded portion of represents the idle time. In the case where the operation for driving the pixel array 100 includes only the shutter operation and the read operation, the idle time may correspond to the remaining time except the shutter time and the read time in the driving time of the image sensor 1000 row by row. However, in the case where an additional operation of the pixel array 100 is performed row by row, the idle time may correspond to the remaining time except the shutter time and the read time and the time for the additional operation in the driving time of the image sensor 1000. Like the shutter time and the read time, the idle time of the rows may be determined to be different from each other.

[0101] Fig.14 is a circuit diagram of a digital logic circuit and a latch according to an example embodiment. For example, Fig.14 The circuit diagram can be compared with Fig.11 The digital logic circuit corresponds to the latch. Fig.14 The digital logic circuit 230b and latch 250b can be understood as a structure for generating a pixel control signal corresponding to a target row (e.g., the first row). Therefore, a plurality of digital logic circuits 230b and a plurality of latches 250b can be provided so that a digital logic circuit 230b and a latch 250b are provided for each row.

[0102] refer to Fig.14, the latch 250b may include a row latch (or a first row latch) 251b, a power gating control circuit (or a first power gating control circuit) 252b, and a first power gating circuit 253b. The digital logic circuit 230b may include a row logic circuit (or a first row logic circuit) 231b, a default level control circuit 232b, a second power gating circuit 233b, and an output circuit 234b.

[0103] The row latch 251b may generate a shutter signal S1 and a read signal R1 based on the operation instruction signal DVA1, the shutter set signal SSET, the read set signal RSET, the latch set signal LSET, and the latch reset signal LRST. Fig.13 The levels of the shutter signal S1 and the read signal R1 are described. Fig.15 It is described that the shutter signal S1 and the read signal R1 are generated by using the operation instruction signal DVA1 , the shutter set signal SSET, the read set signal RSET, the latch set signal LSET, and the latch reset signal LRST.

[0104] The power gating control circuit 252b may generate a power gating signal PG based on the operation indication signal DVA1, the shutter set signal SSET, the read set signal RSET, the latch set signal LSET, and the latch reset signal LRST. The power gating signal PG may have an enable level during the shutter time and the read time, and may have a disable level during the idle time. Fig.15 It is described that the power gating signal PG is generated by using the operation indication signal DVA1 , the shutter set signal SSET, the read set signal RSET, the latch set signal LSET, and the latch reset signal LRST.

[0105] The first power gating circuit 253b may transmit the power supply voltage VDD to the row latch 251b based on the power gating signal PG. The first power gating circuit 253b may include a first power switch PS1 that is turned on based on the power gating signal PG of the enable level and turned off based on the power gating signal PG of the disable level. The first power switch PS1 may transmit the power supply voltage VDD to the row latch 251b during the shutter time and the read time. The first power switch PS1 may not transmit the power supply voltage VDD to the row latch 251b during the idle time.

[0106] The row logic circuit 231b can generate a pixel control signal based on the shutter signal S1, the read signal R1 and the operation information. The operation information may include the transmission transistor operation information OTX, the reset transistor operation information ORX and the selection transistor operation information OSX. The pixel control signal may include the transmission control signal TG, the reset control signal RG and the selection signal SEL.

[0107] The second power gating circuit 233b can transmit the power supply voltage VDD to the row logic circuit 231b based on the power gating signal PG. The second power gating circuit 233b may include a second power switch PS2 that is turned on based on the power gating signal PG of the enable level and turned off based on the power gating signal PG of the disable level. Both the first power gating circuit 253b and the second power gating circuit 233b can operate based on the power gating signal PG generated by the power gating control circuit 252b.

[0108] The default level control circuit 232b may include an inverter Inv that inverts the power gating signal PG. The output circuit 234b may transmit the pixel control signal to the row driver 240b based on the power gating signal PG. To this end, the output circuit 234b may include a first output switch SS, a second output switch RS, and a third output switch TS. The output circuit 234b may further include a first default switch SDS, a second default switch RDS, and a third default switch TDS, so that the default signals SELd, RGd, and TGd are transmitted to the row driver 240b. The first default switch SDS, the second default switch RDS, and the third default switch TDS may operate based on the inverted power gating signal from the default level control circuit 232b.

[0109] Fig.15 is a timing diagram of latch signals according to an example embodiment. For example, Fig.15 The timing diagram of the signals in Fig.11 For example, a signal may be input to a latch or generated by a latch. Fig.15 An address VA (or an operation indication signal), latch information, a power gating signal PG, intermediate signals LS and LR, a shutter signal S1, and a read signal R1 are shown over time. It is assumed that no additional operation other than the shutter operation and the read operation is performed.

[0110] The shutter signal S1 is generated based on the shutter set signal SSET, the latch set signal LSET, the latch reset signal LRST and the operation indication signal. The operation indication signal indicating the shutter operation of the target row can be latched by using the shutter set signal SSET. In response to the shutter set signal SSET, the first intermediate signal LS can have an enable level. The first intermediate signal LS of the enable level can be latched by using the latch set signal LSET. In response to the latch set signal LSET, the shutter signal S1 can have an enable level. In response to the latch reset signal LRST, the first intermediate signal LS can be changed from the enable level to the disable level. The first intermediate signal LS of the disable level can be latched by using the latch set signal LSET. In response to the latch set signal LSET, the shutter signal S1 can have a disable level.

[0111] The read signal R1 is generated based on the read set signal RSET, the latch set signal LSET, the latch reset signal LRST and the operation indication signal. The operation indication signal indicating the read operation of the target row can be latched by using the read set signal RSET. In response to the read set signal RSET, the second intermediate signal LR can have an enable level. The second intermediate signal LR of the enable level can be latched by using the latch set signal LSET. In response to the latch set signal LSET, the read signal R1 can have an enable level. In response to the latch reset signal LRST, the second intermediate signal LR can be changed from the enable level to the disable level. The second intermediate signal LR of the disable level can be latched by using the latch set signal LSET. In response to the latch set signal LSET, the read signal R1 can have a disable level.

[0112] The power gating signal PG is generated based on the read set signal RSET, the shutter set signal SSET, the latch set signal LSET, the latch reset signal LRST and the operation indication signal. In response to the operation indication signal indicating the shutter operation or the read operation, the power gating signal PG may have an enable level. The operation indication signal indicating the shutter operation or the read operation of the target row may be latched by using the shutter set signal SSET or the read set signal RSET. In response to the shutter set signal SSET or the read set signal RSET, the first intermediate signal LS or the second intermediate signal LR may have an enable level. In response to the latch reset signal LRST, the first intermediate signal LS or the second intermediate signal LR may be changed from an enable level to a disable level. The first intermediate signal LS or the second intermediate signal LR of the disable level may be latched by using the latch set signal LSET. In this way, the power gating signal PG may have a disable level.

[0113] The time when the power gating signal PG has the disable level is referred to as an idle time. During the idle time, power is not supplied to the row latch 251b and the row logic circuit 231b based on the power gating signal PG.

[0114] Fig.16 Is input to Fig.11 A timing diagram of a digital logic circuit or a signal generated by a digital logic circuit. Fig.16 The power gate signal PG, the shutter signal S1, the read signal R1, the operation information and the pixel control signal are shown over time. For ease of description, the signal for generating the pixel control signal corresponding to the target row (e.g., the first row) is shown. It is assumed that other operations except the shutter operation and the read operation are not performed.

[0115] During the shutter time, the row logic circuit 231b can generate a transfer control signal TG1 based on the transfer transistor operation information OTX. During the read time, the row logic circuit 231b can generate a transfer control signal TG1, a reset control signal RG1, and a selection signal SEL1 based on the transfer transistor operation information OTX, the reset transistor operation information ORX, and the selection transistor operation information OSX.

[0116] During the idle time, power is not provided to the row logic circuit 231b based on the power gating signal PG. Therefore, the row logic circuit 231b may not output a pixel control signal of any level. However, the output circuit 234b may provide a default level of the pixel control signal to the row driver 240b so that the pixel control signal remains at the default level during the idle time. The power gating signal PG may be generated by the latch 250b and may be transmitted to the digital logic circuit 230b.

[0117] Fig.17 is a block diagram of a driver circuit according to an example embodiment. For example, Fig.17 The block diagram can be compared with Figure 1 The driver circuit corresponds to Fig.17 The driver circuit 200c includes a front buffer 210c, a row decoder 220c, a digital logic circuit 230c, a row driver 240c, and a binning control circuit 250c. With respect to the front buffer 210c, the row decoder 220c, the digital logic circuit 230c, and the row driver 240c, additional description will be omitted to avoid redundancy.

[0118] The merge control circuit 250c may merge the operation instruction information corresponding to the plurality of rows based on the operation instruction information decoded by the row decoder 220c. Thus, two or more rows may be operated at the same timing. The merge control circuit 250c may be applied to Figure 6 The driver circuit 200a and Fig.11 Driver circuit 200b.

[0119] Fig.18 is a block diagram of an electronic system according to an example embodiment. For example, Fig.18 Electronic systems can include Figure 1 Image sensor. Fig.18 The electronic system 2000 may be implemented in various ways using a desktop computer, a laptop computer, a tablet computer, a smart phone, a wearable device, or an electric vehicle. The electronic system 2000 may include an image system 2100, a communication system 2200, an audio processing system 2300, a display system 2400, a buffer memory 2500, a nonvolatile memory 2600, a user interface 2700, and a main processor 2800.

[0120] The image system 2100 may receive light through the lens 2105. The image sensor 2110 included in the image system 2100 may generate image data based on the received light, and the image signal processor 2120 included therein may process the image data for displaying the image data. The image sensor 2110 may be a reference Figures 1 to 16 The image sensor 1000 is described. For example, the image sensor 2110 may include the driver circuit 200, 200a, 200b, or 200c described above.

[0121] The communication system 2200 may exchange signals with an external device / system through an antenna 2210. A transceiver 2220 and a MODEM (modulator / demodulator) 2230 of the communication system 2200 may process signals exchanged with an external device / system according to various wireless communication protocols.

[0122] The audio processing system 2300 may play and output audio by processing sound information using the audio signal processor 2310. The audio processing system 2300 may receive audio input through the microphone 2320. The audio processing system 2300 may output the played audio through the speaker 2330.

[0123] The display system 2400 may receive data from an external device (eg, the main processor 2800 ), and may display an image through the display panel based on the received data. For example, the display system 2400 may display an image generated by the image signal processor 2120 .

[0124] The buffer memory 2500 may store data to be used for the operation of the electronic system 2000. In an example embodiment, the buffer memory 2500 may temporarily store data processed or to be processed by the main processor 2800. In an example embodiment, the buffer memory 2500 may include a volatile memory (e.g., a static random access memory (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM)) and / or a nonvolatile memory (e.g., a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM)).

[0125] The nonvolatile memory 2600 can store data regardless of whether power is supplied. In an example embodiment, the nonvolatile memory 2600 may include at least one of various nonvolatile memories (e.g., flash memory, PRAM, MRAM, ReRAM, and FRAM). In an example embodiment, the nonvolatile memory 2600 may include a removable memory (e.g., a secure digital (SD) card) and / or an embedded memory (e.g., an embedded multimedia card (eMMC)).

[0126] The user interface 2700 may perform communication arbitration between the user and the electronic system 2000. In an example embodiment, the user interface 2700 may include an input interface such as a keypad, a button, a touch screen, a touch pad, a gyro sensor, a vibration sensor, and an acceleration sensor. In an example embodiment, the user interface 2700 may include an output interface such as a motor and an LED light.

[0127] The main processor 2800 may control the overall operation of the components of the electronic system 2000. The main processor 2800 may process various operations for operating the electronic system 2000. For example, the main processor 2800 may be implemented with an operation processing device / circuit including one or more processor cores, such as a general-purpose processor, a dedicated processor, an application processor, or a microprocessor.

[0128] According to example embodiments, an image sensor driver circuit including a power switch and an image sensor including the driver circuit may prevent power from being supplied to a digital logic circuit during a time when a specific operation is not performed, thereby preventing increases in leakage current, power consumption, and temperature of the driver circuit.

[0129] According to an exemplary embodiment, Figure 1 , Figure 5 , Figure 6 , Fig. 9 , Fig.11 , Fig.14 , Fig.17 and Fig.18At least one of the driver circuit, conversion circuit, output buffer, timing controller, NOR gate, inverter, row logic, front buffer, row decoder, latch, digital logic, row driver, power gating control circuit, merge control circuit or other elements represented by the blocks shown in the figure can be implemented as various numbers of hardware, software and / or firmware structures that perform the above-mentioned corresponding functions. For example, at least one of the driver circuit, conversion circuit, output buffer, timing controller, NOR gate, inverter, row logic, front buffer, row decoder, latch, digital logic, row driver, power gating control circuit, merge control circuit or other elements can use a direct circuit structure, such as a memory, a processor, a logic circuit, a lookup table, etc., which can perform the corresponding functions under the control of one or more microprocessors or other control devices. In addition, the driver circuit, conversion circuit, output buffer, timing controller, NOR gate, inverter, row logic, front buffer, row decoder, latch, digital logic, row driver, power gating control circuit, merge control circuit or other elements can be specifically implemented by a module, a part of a program or a code (including executable instructions for performing a specified logical function) and executed by one or more microprocessors or other control devices. In addition, the driver circuit, conversion circuit, output buffer, timing controller, NOR gate, inverter, row logic, front buffer, row decoder, latch, digital logic, row driver, power gating control circuit, merge control circuit or other elements can also include a processor (e.g., a central processing unit (CPU)), a microprocessor, etc. that performs the corresponding function or can be implemented by it. Two or more of the driver circuit, conversion circuit, output buffer, timing controller, NOR gate, inverter, row logic, front buffer, row decoder, latch, digital logic, row driver, power gate control circuit, merge control circuit or other elements can be combined into a single component, element, module or unit, which performs all operations or functions of two or more driver circuits, conversion circuits, output buffers, timing controllers, NOR gates, inverters, row logic, front buffer, row decoder, latches, digital logic, row drivers, power gate control circuits, merge control circuits or other elements combined. In addition, at least a portion of the functions of at least one of the driver circuit, conversion circuit, output buffer, timing controller, NOR gate, inverter, row logic, front buffer, row decoder, latch, digital logic, row driver, power gate control circuit, merge control circuit or other elements can be performed by another of these components. In addition, although the bus is not shown in each of the above block diagrams, the communication between components can be performed by the bus. The functional aspects of the above example embodiments can be implemented as algorithms executed on one or more processors.In addition, the driver circuits, conversion circuits, output buffers, timing controllers, NOR gates, inverters, row logic, front buffers, row decoders, latches, digital logic, row drivers, power gating control circuits, merge control circuits or other elements represented by the boxes or processing steps can adopt any number of relevant technologies for electronic configuration, signal processing and / or control, data processing, etc.

[0130] Although example embodiments have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A driver circuit for an image sensor, comprising: a row decoder configured to decode an address indicating a target row of the pixel array and generate an operation indication signal corresponding to the target row; Digital logic circuits, including: a target row logic circuit configured to generate a pixel control signal corresponding to the target row based on a power supply voltage and the operation instruction signal; a power switch configured to connect the power supply voltage to the target row logic circuit during a first time and to isolate the power supply voltage from the target row logic circuit during a second time based on the operation indication signal; and an output circuit configured to output a default signal during the second time based on the operation indication signal; and A row driver is configured to drive the target row of the pixel array based on the pixel control signal during the first time, and to drive the target row of the pixel array based on the default signal during the second time.

2. The driver circuit according to claim 1, wherein: The digital logic circuit further includes: a power gating control circuit configured to generate a power gating signal having an enable level during the first time and a disable level during the second time based on the operation indication signal, and The power switch is configured to be turned on based on the enable level of the power gating signal, and to be turned off based on the disable level of the power gating signal.

3. The driver circuit according to claim 1, wherein: The address includes a first address and a second address, the first address indicating a first row of the pixel array, wherein a first operation is performed on the first row, and the second address indicating a second row of the pixel array, wherein a second operation is performed on the second row, Wherein, the row decoder comprises: a first row decoder configured to decode the first address and generate a first operation indication signal, the first operation indication signal indicating the first operation to be performed on the target row; and a second row decoder configured to decode the second address and generate a second operation indication signal, wherein the second operation indication signal indicates the second operation to be performed on the target row, and The first time includes a first operation time when the first operation indication signal has an enable level and a second operation time when the second operation indication signal has an enable level.

4. The driver circuit according to claim 3, wherein: The first operation indication signal and the second operation indication signal have an enable level during a time interval, and During the time interval, the power switch is configured to maintain a current state.

5. The driver circuit according to claim 3, wherein: The first operation includes a shutter operation for resetting charges accumulated by a light sensing operation of the pixel array, and the second operation includes an operation of reading a pixel signal generated by the light sensing operation of the pixel array after the charges are reset by the first operation.

6. The driver circuit according to claim 1, further comprising: a latch configured to output an operation signal to the target row logic circuit based on the operation instruction signal, wherein the target row logic circuit is further configured to generate the pixel control signal based on the operation signal received from the latch, and Wherein, the latch comprises: a power gating control circuit configured to generate, based on the operation indication signal, a power gating signal having an enable level during the first time and having a disable level during the second time; a target row latch configured to latch the operation indication signal and generate the operation signal having an enable level during a portion of the first time; and A second power switch is configured to connect the power supply voltage to the target row latch during the first time and isolate the power supply voltage from the target row latch during the second time based on the power gating signal.

7. The driver circuit according to claim 6, wherein: The row decoder is further configured to decode the address and generate the operation indication signal having an enable level during a third time and during a fourth time, the operation indication signal indicating a first operation to be performed on the target row during the third time and indicating a second operation to be performed on the target row during the fourth time, The target row latch is further configured to: detect the enable level of the operation indication signal, and generate a first operation signal having an enable level during a fifth time period after the third time, and generate a second operation signal having an enable level during a sixth time period after the fourth time, and Among them, the first time includes the third to sixth time.

8. A driver circuit for an image sensor, comprising: a row decoder configured to decode the address and generate an operation indication signal having an enable level during a first time, the operation indication signal indicating an operation of a target row of the pixel array; Latches, including: a target row latch configured to detect the operation indication signal at the first time and generate an operation signal having an enable level during a second time after the first time based on the operation indication signal at the first time; a power gating control circuit configured to generate a power gating signal based on the operation indication signal; and a first power switch configured to connect a power supply voltage to the target row latch during the first time and the second time based on the power gating signal; and Digital logic circuits, including: a target row logic circuit configured to generate a pixel control signal corresponding to the target row based on the power supply voltage and the operation signal; and A second power switch is configured to connect the power supply voltage to the target row logic circuit during the first time and the second time based on the power gating signal.

9. The driver circuit according to claim 8, wherein: The target row latch is further configured to generate the operation signal having an enable level during the second time of the horizontal time interval based on a latch set signal having a horizontal time interval period after detecting the operation indication signal at the first time.

10. The driver circuit according to claim 8, wherein: The target row latch is further configured to: latch the operation indication signal of the first time by using an operation setting signal to generate an intermediate signal having an enable level; latch the intermediate signal of the enable level by using a latch setting signal to change the level of the operation signal from a disable level to an enable level; changing the level of the intermediate signal from an enable level to a disable level based on a latch reset signal; and latching the intermediate signal of the disable level by using the latch set signal to change the operation signal from the enable level to the disable level.

11. The driver circuit according to claim 8, wherein: The power gating control circuit is further configured to: generate the power gating signal having an enable level based on the operation indication signal; latch the operation indication signal of the first time by using an operation set signal to generate an intermediate signal having an enable level; changing the level of the intermediate signal from an enable level to a disable level based on a latch reset signal; and latching the intermediate signal of the disable level by using a latch set signal to change the level of the power gating signal from an enable level to a disable level.

12. The driver circuit according to claim 8, wherein: The power gating control circuit is further configured to output the power gating signal having an enable level to the first power switch and the second power switch during a third time, the third time being a time from a start point of the first time to an end point of the second time.

13. The driver circuit according to claim 12, wherein: The power gating control circuit is further configured to turn off the first power switch and the second power switch during a fourth time different from the third time in a driving time of the pixel array driven based on the pixel control signal.

14. The driver circuit according to claim 12, further comprising: a row driver configured to drive the pixel array based on the pixel control signal, The digital logic circuit further includes an output circuit, which is configured to provide the pixel control signal to the row driver during the third time based on the power gating signal, and to provide a default signal to the row driver during a fourth time different from the third time based on the power gating signal.

15. The driver circuit according to claim 8, wherein: The row decoder is further configured to decode the address to generate the operation indication signal having an enable level during a third time and during a fourth time, the operation indication signal indicating a first operation to be performed on the target row during the third time and indicating a second operation to be performed on the target row during the fourth time, The target row latch is further configured to: detect the operation indication signal at the third time based on the first set signal, and detect the operation indication signal at the fourth time based on the second set signal, Wherein, the first time includes the third time and the fourth time, The third time and the fourth time are shorter than the horizontal time interval. wherein the first setting signal and the second setting signal have a period corresponding to the horizontal time interval, and The phase of the first setting signal is different from the phase of the second setting signal.

16. An image sensor, comprising: a pixel array comprising a plurality of pixels; a driver circuit connected to the rows of the pixel array via row lines, the driver circuit being configured to control a first operation and a second operation for each row; as well as a conversion circuit connected to the columns of the pixel array through column lines, the conversion circuit being configured to receive image signals from the pixel array through the column lines according to the first operation and the second operation of the pixel array, and convert the received image signals into digital image signals, Wherein, the driver circuit comprises: a row decoder configured to decode an address indicating a target row of the pixel array and generate an operation indication signal corresponding to the target row, wherein the first operation and the second operation are performed on the target row of the pixel array; Digital logic circuits, including: a target row logic circuit configured to generate a pixel control signal corresponding to the target row based on a power supply voltage and the operation instruction signal; and a power switch configured to connect the power supply voltage to the target row logic circuit based on the operation instruction signal when the target row logic circuit generates the pixel control signal corresponding to the first operation and the second operation; and A row driver is configured to control the first operation and the second operation of the target row based on the pixel control signal.

17. The image sensor according to claim 16, wherein: The address includes: a first address indicating a first row of the pixel array, the first operation is performed on the first row of the pixel array; and a second address indicating a second row of the pixel array, the second operation is performed on the second row of the pixel array, Wherein, the row decoder comprises: a first row decoder configured to decode the first address and generate a first operation indication signal having an enable level during a first time, the first operation indication signal indicating the first operation of the target row; and a second row decoder configured to decode the second address and generate a second operation indication signal having an enable level during a second time, the second operation indication signal indicating the second operation of the target row, and The driver circuit further includes: a power gating control circuit configured to turn on the power switch during the first time period and the second time period based on the first operation instruction signal and the second operation instruction signal.

18. The image sensor according to claim 16, wherein: The row decoder is further configured to decode the address and generate the operation indication signal having an enable level during a first time period and a second time period, the operation indication signal indicating the first operation of the target row during the first time period and indicating the second operation of the target row during the second time period, Wherein, the driver circuit further includes: a target row latch configured to: detect the operation indication signal at the first time, generate a first operation signal having an enable level during a third time after the first time, and generate a second operation signal having an enable level during a fourth time after the second time; a power gating control circuit configured to generate a power gating signal based on the operation indication signal; and a latch power switch configured to connect the power supply voltage to the target row latch during the first time to the fourth time based on the power gating signal, and The power switch and the latch power switch are turned on or off based on the power gating signal.

19. The image sensor according to claim 18, wherein: The first operation includes a shutter operation for resetting charges accumulated by a light sensing operation of the pixel array, and the second operation includes an operation of reading a pixel signal generated by the light sensing operation of the pixel array after the charges are reset by the first operation, and Wherein, the pixel control signal includes: a transfer control signal configured to turn on a transfer transistor of each pixel of the target row in the first operation and the second operation so that the accumulated charges are provided to a floating diffusion region; a reset control signal configured to turn off a reset transistor of each pixel of the target row in the second operation so that the provided charge is accumulated at the floating diffusion region; and A selection signal is configured to turn on a selection transistor of each pixel of the target row in the second operation so that a pixel signal generated based on the charge accumulated at the floating diffusion region is transmitted to the conversion circuit.

20. The image sensor according to claim 16, wherein: The driver circuit also includes: a merging control circuit configured to merge the operation instruction signal corresponding to the target row and another operation instruction signal corresponding to another row of the pixel array so that the target row and the another row perform the first operation and the second operation together.

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