Semiconductor packaging anti-magnetic structure

Abstract

A semiconductor package antimagnetic structure, characterized in that it includes: a substrate, a first chip, a first wire, an adhesive layer, a second chip, a metal film, and a second wire, wherein the substrate has an upper surface and a lower surface and a plurality of electrical connection structures extending through the upper and lower surfaces, and a window is provided between the upper and lower surfaces. The first chip has an active surface and a back surface, the active surface being arranged downward on the upper surface of the substrate, while a portion of the active surface of the first chip is exposed in the window, the portion of the active surface exposed in the window being electrically connected to the electrical connection structure of the substrate, and the first wire electrically connects the active surface to the lower surface of the substrate through the portion exposed in the window. Next, the adhesive layer is arranged on the back surface of the first chip, and then the second chip is arranged on the adhesive layer, and the second chip is fixed to the back surface of the first chip by the adhesive layer. The metal film is arranged on the second chip, and the second wire is electrically connected to the upper surface of the metal film and the upper surface of the substrate at the same time.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging structure, and in particular to a semiconductor packaging antimagnetic structure. Background Art

[0002] Small-scale integrated circuit packages are typically constructed in batches on a single matrix substrate. This matrix substrate is pre-defined with multiple packaging areas, each of which is used to construct a package unit. After the encapsulation process is completed, a singulation process can be performed to separate the overall package unit structure constructed on the matrix substrate into individual package units. Package units manufactured in this manner include Thin & Fine Ball Grid Array (TFBGA) packages and Quad Flat No-Lead (QFN) packages, for example.

[0003] Electromagnetic interference (EMI) is an electromagnetic phenomenon in which electromagnetic waves generated by some electrical and electronic equipment can easily interfere with other nearby devices, causing malfunctions or impacting signal transmission. Furthermore, excessive EMI can lead to electromagnetic pollution, potentially harming the health of nearby users. As devices and structures evolve, achieving a state of compatibility—one where they can operate normally without causing electromagnetic interference that could alter performance or damage the equipment—is becoming increasingly challenging. To achieve overall EMI, the overall electromagnetic environment must be considered as a guide. Each device must not generate electromagnetic emissions exceeding certain limits, while also possessing a certain level of interference immunity. Only by implementing these two constraints and improvements on each device can full EMI be achieved. Summary of the Invention

[0004] In view of the problems disclosed in the prior art, the design of the magnetic shielding structure of the semiconductor package of the present invention can prevent electromagnetic waves and improve the electrical properties of the entire package structure.

[0005] The main purpose of the present invention is to provide a semiconductor package antimagnetic structure that can prevent electromagnetic waves and improve the electrical properties of the entire package structure.

[0006] In accordance with the above objectives, the present invention provides a semiconductor package antimagnetic structure, characterized by comprising: a substrate, a first chip, a first conductive wire, an adhesive layer, a second chip, a metal film, and a second conductive wire, wherein the substrate further comprises an upper surface and a lower surface, and a plurality of electrical connection structures extending through the upper and lower surfaces, and a window is provided between the upper and lower surfaces. Furthermore, the first chip has an active surface and a back surface, the active surface of the first chip being disposed downwardly on the upper surface of the substrate, and a portion of the active surface of the first chip being exposed in the window. The portion of the active surface exposed in the window is electrically connected to the electrical connection structure of the substrate, and the first conductive wire electrically connects the active surface of the first chip to the lower surface of the substrate through the portion exposed in the window. Subsequently, an adhesive layer is disposed on the back surface of the first chip, and then a second chip is disposed on the adhesive layer, with the adhesive layer securing the second chip to the back surface of the first chip. The metal film is disposed on the second chip, and the second conductive wire electrically connects the upper surface of the metal film and the upper surface of the substrate.

[0007] In accordance with the above-mentioned objectives, the present invention further provides a semiconductor package antimagnetic structure, characterized in that it comprises: a substrate, a first chip, a first wire, a glue layer, a second chip, a metal film, a second wire and a packaging structure, wherein the substrate further comprises an upper surface and a lower surface and a plurality of electrical connection structures penetrating the upper surface and the lower surface. In addition, the first chip is provided with an active surface and a back surface, the back surface of the first chip is arranged downward on the upper surface of the substrate, and the active surface of the first chip also comprises a plurality of solder pads, and the first wire is electrically connected to the plurality of solder pads on the active surface of the first chip and the upper surface of the substrate respectively. Next, the glue layer is arranged on the active surface of the first chip and covers the first wire, and then the second chip is arranged on the glue layer, and then the metal film is arranged on the second chip, and then the second wire is electrically connected to the upper surface of the metal film and the upper surface of the substrate at the same time. The packaging structure is arranged on the upper surface of the substrate and covers part of the upper surface of the substrate, the metal film and the second wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 1 is a schematic diagram showing a first embodiment of a magnetic shielding structure for a semiconductor package according to the technology disclosed in the present invention;

[0009] Figure 2 is a schematic diagram showing a second embodiment of a magnetic shielding structure for a semiconductor package according to the technology disclosed in the present invention;

[0010] Figure 3 is a schematic diagram showing a third embodiment of a magnetic shielding structure for a semiconductor package according to the technology disclosed in the present invention;

[0011] Figure 4 is a schematic diagram showing a fourth embodiment of a magnetic shielding structure for a semiconductor package according to the technology disclosed in the present invention;

[0012] Figure 5 is a schematic diagram showing a fifth embodiment of a magnetic shielding structure for a semiconductor package according to the technology disclosed in the present invention; DETAILED DESCRIPTION

[0013] In order to make the objectives, technical features, and advantages of the present invention more understandable to those skilled in the art and to enable the present invention to be implemented, the technical features and implementation methods of the present invention are specifically explained with reference to the accompanying drawings, and further illustrated with reference to preferred embodiments. The drawings compared below are for illustration purposes only and are not necessarily drawn in full according to actual circumstances. The technical content familiar to those skilled in the art in the description of the implementation methods of this case will not be further described.

[0014] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a first embodiment of a semiconductor package antimagnetic structure. Figure 1As shown, the semiconductor package magnetic shielding structure 1 of the present invention includes a substrate 10, a first chip 20, a first conductive line 30, an adhesive layer 40, a second chip 50, a metal film 60, and a second conductive line 70. The substrate 10 further has an upper surface 101 and a lower surface 102, as well as a plurality of electrical connection structures 80 extending through the upper and lower surfaces 101 and 102. A window 103 is also defined between the upper and lower surfaces 101 and 102. It should be noted that the plurality of electrical connection structures 80 within the substrate 10 are formed using an interconnection process. The formation method and function of the electrical connection structures are the same as those of the prior art and are not the primary technical features of the present invention, so they will not be further elaborated. In addition, the first chip 20 has an active surface 201 and a back surface 202, and a plurality of bonding pads (not shown in the figure) are provided on the active surface 201. The active surface 201 of the first chip 20 is arranged on the upper surface 101 of the substrate 10 in a flip-chip manner with the active surface 201 facing downward, and a portion of the active surface 201 of the first chip 20 is also exposed in the window 103. The portion of the active surface 201 exposed in the window 103 is electrically connected to the electrical connection structure 80 of the substrate 10. At the same time, the first wire 30 electrically connects the active surface 201 of the first chip 20 to the lower surface 102 of the substrate 10 through the portion exposed in the window 103. Specifically, one end of the first wire 30 is connected to a bonding pad (not shown in the figure) on the active surface 201 of the first chip 20, and the other end of the first wire 30 is connected to the lower surface 102 of the substrate 10 through the window 103. Next, an adhesive layer 40 is disposed on the back surface 202 of the first chip 20, and then a second chip 50 is disposed on the adhesive layer 40, securing the second chip 50 to the back surface 202 of the first chip 20 via the adhesive layer 40. A metal film 60 is disposed on the second chip 50, and a second conductive wire 70 electrically connects the upper surface of the metal film 60 and the upper surface 101 of the substrate 10.

[0015] Please continue to refer to Figure 1In another embodiment, the semiconductor package antimagnetic structure 1 of the present invention includes a substrate 10, a first chip 20, a first wire 30, a glue layer 40, a second chip 50, a metal film 60, a second wire 70 and a packaging structure 90, wherein the substrate 10 further has an upper surface 101 and a lower surface 102 and a plurality of electrical connection structures 80 penetrating the upper surface 101 and the lower surface 102, and a window 103 is provided between the upper surface 101 and the lower surface 102. In addition, the first chip 20 is a functional chip having an active surface 201 and a back surface 202. The active surface 201 of the first chip 20 is disposed face down on the upper surface 101 of the substrate 10 in a flip-chip manner, and a portion of the active surface 201 of the first chip 20 is also exposed in the window 103. The portion of the active surface 201 exposed in the window 103 is electrically connected to the electrical connection structure 80 of the substrate 10. At the same time, the first wire 30 electrically connects the active surface 201 of the first chip 20 to the lower surface 102 of the substrate 10 through the portion exposed in the window 103. In addition, the lower surface 102 of the substrate 10 also has multiple electrical connection structures, among which the electrical connection structures on the lower surface 102 of the substrate 10 are solder balls or wafer bumps. Next, an adhesive layer 40 is disposed on the back surface 202 of the first chip 20. A second chip 50 is then disposed on the adhesive layer 40, securing the second chip 50 to the back surface 202 of the first chip 20 via the adhesive layer 40. The size of the second chip 50 can be larger, smaller, or equal to that of the first chip 20, and the second chip 50 can be a bare semiconductor die or a silicon chip. A metal film 60 is disposed on the second chip 50, and second conductive lines 70 are electrically connected to the upper surface of the metal film 60 and the upper surface 101 of the substrate 10, respectively. The package structure 90 covers a portion of the upper surface 101 of the substrate 10, the second conductive lines 70, the metal film 60, the first conductive lines 30 within the window 103, and the lower surface 102 of the substrate 10 exposed at the window 103. In the present invention, the second chip 50 and the metal film 60 above it enhance the electrical properties of the overall semiconductor package magnetic shielding structure 1 and prevent electromagnetic interference, thereby improving the operating efficiency of the semiconductor package magnetic shielding structure 1.

[0016] Please refer to Figure 2 , Figure 2 FIG2 is a schematic diagram of a second embodiment of the semiconductor package antimagnetic structure of the present invention. Figure 2As shown, the semiconductor package magnetic shielding structure 2 of the present invention includes a substrate 12, a first chip 22, a first conductive wire 32, an adhesive layer 42, a second chip 52, a metal film 62, a second conductive wire 72, and a packaging structure 90. The substrate 12 further has an upper surface 121 and a lower surface 122, and a plurality of electrical connection structures 82 extending through the upper and lower surfaces 121, 122. Furthermore, the first chip 22 has an active surface 221 and a back surface 222. The first chip 22 is disposed on the upper surface 121 of the substrate 12 with the active surface 221 facing upward and the back surface 222 facing downward. The active surface 221 of the first chip 22 also has a plurality of bonding pads (not shown in the figure). The first conductive wires 32 are electrically connected to the plurality of bonding pads (not shown in the figure) on the active surface 221 of the first chip 22 and the upper surface 121 of the substrate 12. Next, the adhesive layer 42 is disposed on the active surface 221 of the first chip 22 and covers the first conductive wires 32. The second chip 52 is then disposed on the adhesive layer 42. The metal film 62 is then disposed on the second chip 52. The second conductive wires 72 are then electrically connected to the upper surface of the metal film 62 and the upper surface 121 of the substrate 12. The package structure 90 is disposed on the upper surface 121 of the substrate 12 and covers a portion of the upper surface 121 of the substrate 12, the metal film 62, and the second conductive wires 72.

[0017] Please continue to refer to Figure 2In another embodiment, the semiconductor package antimagnetic structure 2 of the present invention includes a substrate 12, a first chip 22, a first wire 32, a glue layer 42, a second chip 52, a metal film 62, a second wire 72 and a packaging structure 90, wherein the substrate 12 further has an upper surface 121 and a lower surface 122 and a plurality of electrical connection structures 82 penetrating the upper surface 121 and the lower surface 122. In addition, the first chip 22 is a functional chip having an active surface 221 and a back surface 222. The back surface 222 of the first chip 22 is disposed downward on the upper surface 121 of the substrate 12, and the active surface 221 of the first chip 22 also has a plurality of bonding pads (not shown in the figure). At the same time, the first wire 32 is electrically connected to the plurality of bonding pads (not shown in the figure) on the active surface 221 of the first chip 22 and the upper surface 121 of the substrate 12. In addition, the lower surface 122 of the substrate 12 also has a plurality of electrical connection structures (not shown in the figure), wherein the electrical connection structures on the lower surface 122 of the substrate 12 are solder balls or wafer bumps. Next, an adhesive layer 42 is disposed on the active surface 221 of the first chip 22 and covers the first conductive wire 32. A second chip 52 is then disposed on the adhesive layer 42. A metal film 62 is then disposed on the second chip 52. The size of the second chip 52 can be larger, smaller, or equal to that of the first chip 22, and the second chip 52 can be a bare semiconductor die or a silicon chip. Second conductive wires 72 are then electrically connected to both the upper surface of the metal film 62 and the upper surface 121 of the substrate 12. The package structure 90 is disposed on the upper surface 121 of the substrate 12 and covers a portion of the upper surface 121 of the substrate 12, the metal film 62, and the second conductive wires 72, thereby enhancing the electrical properties of the overall semiconductor package shielding structure 2.

[0018] Please also refer to Figure 2 and Figure 3 , Figure 3 FIG3 is a schematic diagram of a third embodiment of the semiconductor package antimagnetic structure of the present invention. Figure 3 As shown, the semiconductor package anti-magnetic structure 2 of the present invention includes a substrate 12, a first chip 22, a first wire 32, a glue layer 42, a second chip 52, a metal film 62, a second wire 72 and a package structure 90, wherein Figure 3 The third embodiment of Figure 2 The second embodiment differs in that Figure 3In the third embodiment, the adhesive layer 42 is disposed on the active surface 221 of the first chip 22, and then the second chip 52 is disposed on the adhesive layer 42. Next, the metal film 62 is disposed on the second chip 52, wherein the size of the second chip 52 is smaller than that of the first chip 22. Then, one end of the first wire 32 is electrically connected to multiple pads (not shown in the figure) on the active surface 221 of the first chip 22, and the other end of the first wire 32 is electrically connected to the upper surface 121 of the substrate 12. One end of the second wire 72 is electrically connected to the upper surface of the metal film 62, and the other end is electrically connected to the upper surface 121 of the substrate 12.

[0019] Please also refer to Figure 2 and Figure 4 , Figure 4 FIG4 is a schematic diagram of a fourth embodiment of the semiconductor package antimagnetic structure of the present invention. Figure 4 As shown, the semiconductor package anti-magnetic structure 2 of the present invention includes a substrate 12, a first chip 22, a first wire 32, a glue layer 42, a second chip 52, a metal film 62, a second wire 72 and a package structure 90, wherein Figure 4 The fourth embodiment and Figure 2 The second embodiment differs in that Figure 4 In the fourth embodiment, the adhesive layer 42 is disposed on the active surface 221 of the first chip 22, and then the second chip 52 is disposed on the adhesive layer 42. Next, the metal film 62 is disposed on the second chip 52, wherein the size of the second chip 52 is smaller than that of the first chip 22. Then, one end of the first wire 32 is electrically connected to the metal film 62 and the other end is electrically connected to multiple bonding pads (not shown in the figure) on the active surface 221 of the first chip 22 that are not covered by the adhesive layer 42. One end of the second wire 72 is electrically connected to multiple bonding pads of the first chip 22 and the other end is electrically connected to the upper surface 121 of the substrate 12.

[0020] Please also refer to Figure 2 and Figure 5 , Figure 5 FIG. 5 is a schematic diagram of a fifth embodiment of the semiconductor package antimagnetic structure of the present invention. Figure 5 As shown, the semiconductor package anti-magnetic structure 2 of the present invention includes a substrate 12, a first chip 22, a first wire 32, a glue layer 42, a second chip 52, a metal film 62, a second wire 72 and a package structure 90, wherein Figure 5 The fifth embodiment and Figure 2 The second embodiment differs in that Figure 5In the fifth embodiment, the adhesive layer 42 is disposed on the active surface 221 of the first chip 22, and then the second chip 52 is disposed on the adhesive layer 42. Next, the metal film 62 is disposed on the second chip 52, wherein the size of the second chip 52 is smaller than that of the first chip 22. Then, on one side of the first chip 22 and the second chip 52 (such as Figure 5 One end of the first wire 32 is electrically connected to the active surface 221 of the first chip 22 and a plurality of pads (not shown in the figure) that are not covered by the adhesive layer 42, and the other end is electrically connected to the upper surface 121 of the substrate 12. Figure 5 On the left side, the second wires 72 are electrically connected to the upper surface of the metal film 62 and the upper surface 121 of the substrate 12, while the first wires 32 are electrically connected to the plurality of pads on the active surface 221 of the first chip 22 that are not covered by the adhesive layer 42 and the upper surface 121 of the substrate 12. Figure 5 In the structure of the first wire 32 and the second wire 72 and the substrate 12, the first chip 22 and the metal film 62 are connected in the manner described above. Figure 3 and Figure 4 integrated structure.

[0021] Although the present invention is disclosed above with reference to the preferred embodiments, they are not intended to limit the present invention. Anyone skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, other equivalent changes or modifications that do not depart from the spirit disclosed by the present invention should be included in the claims.

Claims

1. A semiconductor package antimagnetic structure, characterized in that: Include: A substrate having an upper surface and a lower surface, wherein the substrate has a plurality of electrical connection structures penetrating the upper surface and the lower surface and a window between the upper surface and the lower surface; a first chip having an active surface and a back surface, wherein the active surface of the first chip is disposed downward on the upper surface of the substrate, a portion of the active surface of the first chip is exposed to the window, and a portion of the active surface is electrically connected to the electrical connection structure; a first wire electrically connecting the active surface of the first chip to the lower surface of the substrate through a portion exposed in the window; an adhesive layer, disposed on the back surface of the first chip; a second chip disposed on the adhesive layer, wherein the second chip is fixed to the back surface of the first chip by the adhesive layer; a metal film, disposed on the second chip; a second wire electrically connected to the upper surface of the metal film and the upper surface of the substrate; as well as The packaging structure is used to cover a portion of the upper surface of the substrate, the second wire, the metal film, the first wire in the window and the lower surface of the substrate exposed to the window.

2. A semiconductor package antimagnetic structure comprising: A substrate having an upper surface and a lower surface, wherein the substrate has a plurality of electrical connection structures penetrating the upper surface and the lower surface; A first chip having an active surface and a back surface, wherein a plurality of bonding pads are provided on the active surface and the back surface of the first chip is arranged toward the upper surface of the substrate; first wires electrically connecting the bonding pads on the active surface of the first chip and the upper surface of the substrate respectively; an adhesive layer, disposed on the active surface of the first chip and covering the first wire; a second chip, disposed on the adhesive layer; a metal film, disposed on the second chip; a second wire electrically connecting the upper surface of the metal film and the upper surface of the substrate; as well as The packaging structure is arranged on the upper surface of the substrate to cover a portion of the upper surface of the substrate, the metal film and the second wire.

3. A semiconductor package antimagnetic structure comprising: A substrate having an upper surface and a lower surface, wherein the substrate has a plurality of electrical connection structures penetrating the upper surface and the lower surface; A first chip having an active surface and a back surface, wherein a plurality of bonding pads are provided on the active surface and the back surface of the first chip is disposed toward the upper surface of the substrate; an adhesive layer, disposed on the active surface of the first chip; a second chip, disposed on the adhesive layer; a metal film, disposed on the second chip; a first conductive wire electrically connecting an upper surface of the first chip and the upper surface of the substrate respectively; a second conductive wire electrically connecting the upper surface of the metal film and the upper surface of the substrate respectively; as well as A packaging structure is disposed on the upper surface of the substrate to cover a portion of the upper surface of the substrate, the metal film, the first chip, the first wire, and the second wire.

4. A semiconductor package antimagnetic structure comprising: A substrate having an upper surface and a lower surface, wherein the substrate has a plurality of electrical connection structures penetrating the upper surface and the lower surface; A first chip having an active surface and a back surface, wherein a plurality of bonding pads are provided on the active surface and the back surface of the first chip is disposed toward the upper surface of the substrate; an adhesive layer, disposed on the active surface of the first chip; a second chip, disposed on the adhesive layer; a metal film, disposed on the second chip; a first conductive wire electrically connecting an upper surface of the first chip and the upper surface of the substrate respectively; a second wire electrically connecting the upper surface of the metal film and the upper surface of the first chip respectively; as well as A packaging structure is disposed on the upper surface of the substrate to cover a portion of the upper surface of the substrate, the metal film, a portion of the upper surface of the first chip, the first wire, and the second wire.

5. A semiconductor package antimagnetic structure comprising: A substrate having an upper surface and a lower surface, wherein the substrate has a plurality of electrical connection structures penetrating the upper surface and the lower surface; A first chip having an active surface and a back surface, wherein a plurality of bonding pads are provided on the active surface and the back surface of the first chip is arranged toward the upper surface of the substrate; an adhesive layer, disposed on the active surface of the first chip; a second chip, disposed on the adhesive layer; a metal film, disposed on the second chip; a first conductive wire disposed on both sides of the first chip, the second chip, and the metal film, for electrically connecting the upper surface of the first chip; a second wire, disposed on one side of the first chip, the second chip, and the metal film, electrically connecting the upper surface of the metal film and the upper surface of the substrate, and disposed on the other side of the first chip, the second chip, and the metal film, electrically connecting the upper surface of the metal film and the bonding pad on the first chip that is not covered by the adhesive layer; as well as A packaging structure is disposed on the upper surface of the substrate to cover a portion of the upper surface of the substrate, the metal film, a portion of the upper surface of the first chip, the first wire, and the second wire.

6. The semiconductor package antimagnetic structure according to claim 1 or 2, wherein: The size of the second chip is larger than, smaller than, or equal to that of the first chip.

7. The semiconductor package antimagnetic structure according to any one of claims 1 to 5, wherein: The first chip is a functional chip and the second chip is a semiconductor bare chip.

8. The semiconductor package antimagnetic structure according to any one of claims 1 to 5, wherein: The semiconductor die is a silicon chip.

9. The semiconductor package antimagnetic structure according to any one of claims 1 to 5, wherein: The lower surface of the substrate also has a plurality of electrical connection structures.

10. The semiconductor package antimagnetic structure according to claim 9, wherein: The electrical connection structure is a solder ball or a wafer solder bump.

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