Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor packaging device and a manufacturing method thereof. The semiconductor packaging device comprises a redistribution layer including at least one redistribution line, a first chip and a second chip located on an upper surface of the redistribution layer, and a height variation in a vertical direction of the redistribution line between the first chip and the second chip. The semiconductor packaging device and the manufacturing method thereof increase the total length and surface area of the redistribution line, improve the stress resistance of the redistribution line, effectively avoid the fracture of the redistribution line between the first chip and the second chip, and further improve the product yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging apparatus technology, and more specifically to semiconductor packaging apparatus and its manufacturing method. Background Technology

[0002] FOCoS (Fan Out Chip on Substrate) packaging technology achieves this by using a fan-out composite chip on a typical ball grid array substrate. It offers a lower-cost solution and, in practice, provides better electrical and thermal performance than silicon interposer structures.

[0003] In FOCoS packaging devices, different materials have different coefficients of thermal expansion (CTE), resulting in varying degrees of deformation when temperatures change. During thermal cycling, the overall structure cannot directly release the stress caused by these inconsistent CTEs. Since the wiring between the ASIC (Application Specific Integrated Circuit) chip and the HBM (High Bandwidth Memory) chip is located in a stress concentration area, it is prone to fracture under the aforementioned stress.

[0004] Therefore, it is necessary to propose a new technical solution for FOCoS packaging. Summary of the Invention

[0005] This disclosure provides a semiconductor packaging apparatus and a method for manufacturing the same.

[0006] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising:

[0007] A redistribution layer, including at least one redistribution layer;

[0008] The first chip and the second chip are located on the upper surface of the redistribution layer;

[0009] The rewiring lines between the first chip and the second chip have a vertical height variation.

[0010] In some alternative implementations, the longitudinal cross-section of the rewiring line between the first chip and the second chip includes at least one inclined segment.

[0011] In some alternative implementations, the longitudinal section of the rewiring line between the first chip and the second chip includes a wavy portion, the wavy portion including at least one high point, at least one low point, and a sloping segment between the high point and the low point.

[0012] In some alternative implementations, the first chip and the second chip are located on the upper surface of the uppermost redistribution line in the redistribution layer.

[0013] In some optional implementations, the wave-shaped portion extends into the vertical projection area corresponding to the first chip; or

[0014] The wave-shaped portion extends into the vertical projection area corresponding to the second chip.

[0015] In some alternative implementations, the redistribution layer further includes a dummy line at the bottom layer, the dummy line being used to form the height variation of the redistribution line between the first chip and the second chip.

[0016] In some alternative implementations, the dummy line includes at least two dummy units, the longitudinal cross-sections of which correspond to at least two different widths; or

[0017] The longitudinal sections of the at least two dummy units correspond to at least two different thicknesses.

[0018] In some optional embodiments, the dummy unit includes a smaller dummy unit and a larger dummy unit, wherein the width of the longitudinal cross-section of the smaller dummy unit is greater than 2 micrometers and less than 10 micrometers, and the width of the longitudinal cross-section of the larger dummy unit is greater than 10 micrometers and less than 50 micrometers; and

[0019] The thickness of the longitudinal section of the smaller dummy unit is greater than 2 micrometers and less than 5 micrometers, and the thickness of the longitudinal section of the larger dummy unit is 2 micrometers greater than the thickness of the longitudinal section of the smaller dummy unit.

[0020] In some alternative implementations, the minimum distance between adjacent dummy units in the dummy circuit is 2 micrometers.

[0021] In some alternative embodiments, a first dielectric layer is provided between the dummy line and the adjacent rewiring line, the thickness of the longitudinal cross-section of the first dielectric layer being greater than 2 micrometers and less than 8 micrometers.

[0022] In some alternative implementations, the length of the wave-shaped portion is greater than 10 micrometers and less than 4 millimeters.

[0023] In some alternative implementations, the rewiring lines between the first chip and the second chip are electrically connected to the first chip and the second chip, respectively.

[0024] In some alternative implementations, the first chip is an application-specific integrated circuit (ASIC) chip, and the second chip is a high-bandwidth memory chip.

[0025] In some alternative implementations, the rewiring line has at least one bend in the horizontal plane.

[0026] In some alternative implementations, the rewiring lines have a zigzag pattern in the horizontal plane.

[0027] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging device, comprising:

[0028] A virtual circuit is formed on the carrier, wherein the virtual circuit has a vertical height variation;

[0029] A first dielectric layer is formed on the dummy line;

[0030] At least one redistribution layer is formed on the first dielectric layer to obtain the redistribution layer.

[0031] In some alternative embodiments, after forming at least one redistribution layer on the first dielectric layer to obtain the redistribution layer, the method further includes:

[0032] A first chip and a second chip are disposed on the surface of the redistribution layer, wherein the redistribution lines are at least partially located between the first chip and the second chip.

[0033] In some alternative implementations, forming a dummy circuit on the carrier includes:

[0034] A second dielectric layer is disposed on the carrier;

[0035] At least two dummy units are formed on the bottom second electrical layer by electroplating to obtain the dummy circuit, wherein the longitudinal cross-section of the at least two dummy units corresponds to at least two different thicknesses.

[0036] In some alternative implementations, forming a dummy circuit on the carrier includes:

[0037] At least two dummy units are formed on the carrier by electroplating to obtain the dummy circuit, wherein the longitudinal cross-section of the at least two dummy units corresponds to at least two different thicknesses; and

[0038] After forming at least one redistribution layer on the first dielectric layer to obtain the redistribution layer, the method further includes:

[0039] The semiconductor packaging device is flipped over, and a second dielectric layer is formed on the dummy line.

[0040] In the semiconductor packaging apparatus and manufacturing method disclosed herein, the rewiring lines between the first chip and the second chip have a vertical height variation, which increases the total length and surface area of ​​the rewiring lines, improves the stress resistance of the rewiring lines, effectively avoids breakage of the rewiring lines between the first chip and the second chip, and thus improves product yield. Attached Figure Description

[0041] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0042] Figure 1A and Figure 1B This is a schematic diagram of a semiconductor packaging device in the prior art;

[0043] Figures 2-6 These are first to fifth schematic diagrams of a semiconductor packaging apparatus according to embodiments of the present invention;

[0044] Figure 7 and Figure 8 This is a schematic diagram of a method for manufacturing a semiconductor packaging device according to an embodiment of the present invention.

[0045] Symbol explanation:

[0046] 11. ASIC chip; 12. HBM chip; 13. Substrate; 14. Circuit section; 100. First chip; 200. Second chip; 240. First conductive pad; 300. Rewiring line; 301. Left end of wavy section; 302. Right end of wavy section; 310. Inclined section; 320. High point; 330. Low point; 340. Second conductive pad; 400. Solder; 500. First dielectric layer; 510. First conductive via; 600. Dummy line; 610. Larger dummy unit; 620. Smaller dummy unit; 700. Second dielectric layer; 710. Second conductive via; 800. Carrier. Detailed Implementation

[0047] The specific embodiments of the present invention will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present invention and the resulting technical effects from the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0048] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the invention. They are not intended to limit the scope of the invention and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and objectives of the invention, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity and not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0049] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0050] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0051] Figure 1A and Figure 1B This is a schematic diagram of a semiconductor packaging device in the prior art. For example... Figure 1A As shown, in existing semiconductor packaging devices, both the ASIC chip 11 and the HBM chip 12 are located on the substrate 13, and the wiring portion 14 is located between the ASIC chip 11 and the HBM chip 12, electrically connecting them. Because the coefficients of thermal expansion of different parts of the semiconductor packaging device (such as the chip, underfill material, and packaging material) are different, the deformation generated during temperature changes varies, causing the overall structure to bend and thus inducing internal stress. The wiring portion 14 between the ASIC chip 11 and the HBM chip 12 is located in a stress concentration area and is prone to breakage. Figure 1B The dashed area in the diagram shows the breakage of section 14.

[0052] Figures 2-6 These are first to fifth schematic diagrams of a semiconductor packaging apparatus according to embodiments of the present invention.

[0053] Figure 2 A longitudinal cross-section of the semiconductor packaging device in this embodiment is shown. For example... Figure 2 As shown, the semiconductor packaging device in this embodiment includes a redistribution layer, a first chip 100, and a second chip 200.

[0054] In this embodiment, the redistribution layer includes at least one layer of redistribution lines 300 for rearranging electrical connection points. The redistribution lines 300 can be made of metallic materials, such as copper, gold, or silver.

[0055] In this embodiment, the first chip 100 and the second chip 200 are located on the upper surface of the redistribution layer. The first chip 100 is, for example, an application-specific integrated circuit (ASIC) chip, and the second chip 200 is, for example, a high-bandwidth memory chip. When the redistribution layer includes multiple redistribution lines 300, the first chip 100 and the second chip 200 are located on the upper surface of the uppermost redistribution line 300 in the redistribution layer.

[0056] In one example, the first conductive pad 240 on the second chip 200 is connected to the second conductive pad 340 on the redistribution line 300 via solder 400. Similarly, the corresponding conductive pads on the first chip 100 and the redistribution line 300 are also connected via solder 400. Thus, the redistribution line 300 between the first chip 100 and the second chip 200 is electrically connected to both the first chip 100 and the second chip 200.

[0057] In this embodiment, the rewiring line 300 between the first chip 100 and the second chip 200 has a vertical height variation.

[0058] Figure 3 The top-middle image is a top view of rewiring line 300. Figure 3 The lower center figure shows the longitudinal cross-section of rewire line 300. Figure 3 The dashed lines in the diagram show the correspondence between the top view and the longitudinal section. For example... Figure 3 As shown, the longitudinal section of the rewiring line 300 between the first chip 100 and the second chip 200 includes at least one inclined segment 310. The inclined segment 310 is located between a high point 320 and a low point 330. Multiple high points 320 and multiple low points 330 are staggered and connected by the inclined segment 310, thus forming a wave-like section as a whole. It should be noted that the wave-like section in the illustration has angles, while the wave-like section in the actual structure has a smooth transition.

[0059] In the semiconductor packaging apparatus of this embodiment, the rewiring line 300 between the first chip 100 and the second chip 200 has a vertical height variation, which increases the total length and surface area of ​​the rewiring line 300, improves the stress resistance of the rewiring line 300, and can effectively prevent the rewiring line 300 between the first chip 100 and the second chip 200 from breaking, thereby improving the product yield.

[0060] In one example, such as Figure 2As shown, the wavy portion extends into the vertical projection area corresponding to the first chip 100, with the left end 301 of the wavy portion exceeding the right edge of the first chip 100. The wavy portion also extends into the vertical projection area corresponding to the second chip 200, with the right end 302 exceeding the left edge of the second chip 200. This ensures that all rewiring lines 300 between the first chip 100 and the second chip 200 are wavy, avoiding weak points and further reducing the possibility of breakage of the rewiring lines 300 between the first chip 100 and the second chip 200.

[0061] In one example, such as Figure 5 As shown, the redistribution layer also includes a dummy line 600 located at the bottom layer, which is used to form a height variation of the redistribution line 300 between the first chip 100 and the second chip 200. The dummy line 600 includes at least two dummy units, such as a larger dummy unit 610 and a smaller dummy unit 620. The longitudinal cross-sections of the larger dummy unit 610 and the smaller dummy unit 620 correspond to different widths, and the longitudinal cross-sections of the larger dummy unit 610 and the smaller dummy unit 620 correspond to different thicknesses. The different units in the dummy line 600 can be separated from each other. The dummy line 600 is used to provide multiple surfaces with different heights, thereby forming a height variation of the redistribution line 300.

[0062] In one example, such as Figure 5 As shown, a first dielectric layer 500 may be provided between the dummy line 600 and the adjacent rewiring line 300. A first conductive via 510 is provided on the first dielectric layer 500. The first conductive via 510 connects the end unit (e.g., ...) of the dummy line 600. Figure 5 The left or right end unit (of the dummy line 600) is electrically connected to the redistribution line 300. During the manufacturing process, the first dielectric layer 500 can vary with the height of the dummy line 600, thus forming a wave-like surface. Based on this, the redistribution line 300 can be formed on the surface of the first dielectric layer 500, thereby achieving height variation of the redistribution line 300.

[0063] A second dielectric layer 700 may be disposed below the dummy line 600. A second conductive via 710 is disposed on the second dielectric layer 700. The second conductive via 710 is electrically connected to the end unit of the dummy line 600. Through the first conductive via 510 and the second conductive via 710, the redistribution line 300 can be electrically connected to other line structures located below the second dielectric layer 700.

[0064] In one example, such as Figure 6As shown, the width A of the longitudinal section of the smaller dummy unit 620 can be greater than 2 micrometers and less than 10 micrometers. The width C of the longitudinal section of the larger dummy unit 610 can be greater than 10 micrometers and less than 50 micrometers. The thickness E of the longitudinal section of the smaller dummy unit 620 can be greater than 2 micrometers and less than 5 micrometers. The thickness F of the longitudinal section of the larger dummy unit 610 can be 2 micrometers greater than the thickness of the longitudinal section of the smaller dummy unit 620. The minimum distance B between adjacent larger dummy units 610 and smaller dummy units 620 can be 2 micrometers. The thickness G of the longitudinal section of the first dielectric layer 500 can be greater than 2 micrometers and less than 8 micrometers. The length D of the wavy portion can be greater than 10 micrometers and less than 4 millimeters.

[0065] Figure 4 A top view of redistribution line 300 in an example is shown. (See example...) Figure 4 As shown, the redundancy line 300 has at least one bend in the horizontal plane. More specifically, the redundancy line 300 has a zigzag structure in the horizontal plane. Therefore, Figure 4 The rewiring line 300 has both vertical height variation and horizontal bending, which helps to further increase the total length and surface area of ​​the rewiring line 300 and reduce the possibility of breakage of the rewiring line 300 between the first chip 100 and the second chip 200.

[0066] This embodiment also provides a method for manufacturing a semiconductor packaging device.

[0067] Figure 7 A first embodiment of a method for manufacturing a semiconductor packaging device is shown. (As...) Figure 7 As shown, firstly, a second dielectric layer 700 is formed on the carrier 800. Secondly, at least two dummy units are formed on the second dielectric layer by electroplating to obtain a dummy line 600, wherein the longitudinal cross-section of the at least two dummy units corresponds to at least two different thicknesses. Then, a first dielectric layer 500 is formed on the dummy line 600. Finally, at least one redistribution line 300 is formed on the first dielectric layer 500 to obtain a redistribution layer.

[0068] Figure 8 A second embodiment of a method for manufacturing a semiconductor packaging device is shown. (e.g.) Figure 8 As shown, firstly, at least two dummy units are formed on the carrier 800 by electroplating to obtain a dummy line 600, wherein the longitudinal cross-sections of the at least two dummy units correspond to at least two different thicknesses. Secondly, a first dielectric layer 500 is formed on the dummy line 600. Then, at least one redistribution line 300 is formed on the first dielectric layer 500 to obtain a redistribution layer. Finally, the semiconductor packaging device is flipped, and a second dielectric layer 700 is formed on the dummy line 600.

[0069] Please compare Figure 7 and Figure 8 Because the order in which the second dielectric layer 700 is formed differs in the two embodiments, the aperture variation trends of the second conductive via 710 formed in the two embodiments are opposite. Figure 7 In this process, the aperture variation trend of the second conductive via 710 is the same as that of the first conductive via 510. Figure 8 In this process, the diameter variation trend of the second conductive via 710 is opposite to that of the first conductive via 510.

[0070] for Figure 7 and Figure 8 In the implementation method described above, after obtaining the redistribution layer, a first chip 100 and a second chip 200 can be disposed on the surface of the redistribution layer, wherein the redistribution lines 300 are at least partially located between the first chip 100 and the second chip 200. Thus, a complete FOCoS package device can be obtained.

[0071] The method for manufacturing a semiconductor packaging device in this embodiment can achieve similar technical effects to the semiconductor packaging device described above, and will not be repeated here.

[0072] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: A redistribution layer, including at least one redistribution layer; The first chip and the second chip are located on the upper surface of the redistribution layer; The rewiring lines between the first chip and the second chip have a vertical height variation. The redistribution layer further includes dummy lines located on the lower layer. The dummy lines are used to form the height variation of the redistribution lines between the first chip and the second chip. The dummy lines include at least two dummy units, and the longitudinal cross-section of the at least two dummy units corresponds to at least two different widths; or the longitudinal cross-section of the at least two dummy units corresponds to at least two different thicknesses.

2. The semiconductor packaging apparatus according to claim 1, wherein, The longitudinal cross-section of the rewiring line between the first chip and the second chip includes at least one inclined segment.

3. The semiconductor packaging apparatus according to claim 1, wherein, The longitudinal section of the rewiring line between the first chip and the second chip includes a wavy section, which includes at least one high point, at least one low point, and an inclined segment between the high point and the low point.

4. The semiconductor packaging apparatus according to claim 1, wherein, The first chip and the second chip are located on the upper surface of the uppermost rewiring line in the rewiring layer.

5. The semiconductor packaging apparatus according to claim 3, wherein, The wave-shaped portion extends into the vertical projection area corresponding to the first chip; or the wave-shaped portion extends into the vertical projection area corresponding to the second chip.

6. The semiconductor packaging apparatus according to claim 1, wherein, The dummy unit includes a smaller dummy unit and a larger dummy unit. The width of the longitudinal cross-section of the smaller dummy unit is greater than 2 micrometers and less than 10 micrometers, and the width of the longitudinal cross-section of the larger dummy unit is greater than 10 micrometers and less than 50 micrometers. The thickness of the longitudinal section of the smaller dummy unit is greater than 2 micrometers and less than 5 micrometers, and the thickness of the longitudinal section of the larger dummy unit is 2 micrometers greater than the thickness of the longitudinal section of the smaller dummy unit.

7. The semiconductor packaging apparatus according to claim 1, wherein, The minimum distance between adjacent virtual units in the virtual circuit is 2 micrometers.

8. The semiconductor packaging apparatus according to claim 1, wherein, A first dielectric layer is provided between the dummy line and the adjacent rewire line, wherein the thickness of the longitudinal cross-section of the first dielectric layer is greater than 2 micrometers and less than 8 micrometers.

9. The semiconductor packaging apparatus according to claim 5, wherein, The length of the wave-shaped portion is greater than 10 micrometers and less than 4 millimeters.

10. The semiconductor packaging apparatus according to any one of claims 1-9, wherein, The rewiring lines between the first chip and the second chip are electrically connected to the first chip and the second chip, respectively.

11. The semiconductor packaging apparatus according to any one of claims 1-9, wherein, The rewiring line has at least one bend in the horizontal plane.

12. The semiconductor packaging apparatus according to claim 11, wherein, The rewiring line has a sawtooth structure in the horizontal plane.

13. A method for manufacturing a semiconductor packaging device, comprising: A dummy circuit is formed on a carrier, wherein the dummy circuit has a vertical height variation. The process of forming the dummy circuit on the carrier includes: A second dielectric layer is disposed on the carrier; At least two dummy units are formed on the second dielectric layer by electroplating to obtain the dummy circuit, wherein the longitudinal cross-section of the at least two dummy units corresponds to at least two different thicknesses; A first dielectric layer is formed on the dummy line; At least one redistribution line is formed on the first dielectric layer to obtain a redistribution layer; Alternatively, the formation of a virtual circuit on the carrier includes: At least two dummy units are formed on the carrier by electroplating to obtain the dummy circuit, wherein the longitudinal cross-section of the at least two dummy units corresponds to at least two different thicknesses; and After forming at least one redistribution layer on the first dielectric layer to obtain the redistribution layer, the method further includes: The semiconductor packaging device is flipped over, and a second dielectric layer is formed on the dummy line.

14. The method according to claim 13, wherein, After forming at least one redistribution layer on the first dielectric layer to obtain the redistribution layer, the method further includes: A first chip and a second chip are disposed on the surface of the redistribution layer, wherein the redistribution lines are at least partially located between the first chip and the second chip.

Images