Semiconductor structure and method of manufacturing the same

Abstract

This invention provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate having first and second regions. It also includes an epitaxial layer above the substrate, a first element, and a second element located on the first and second regions of the substrate, respectively. The first element includes a first gate on the epitaxial layer, and a first source electrode and a first drain electrode located on opposite sides of the first gate, with a dielectric layer formed on the epitaxial layer and covering the first gate. The second element includes a second gate on the dielectric layer, and a second source electrode and a second drain electrode located on opposite sides of the second gate, wherein the second source electrode is electrically connected to the first drain electrode. The semiconductor structure further includes an isolation structure disposed on the substrate to isolate the epitaxial layers in the first and second regions from each other. This invention avoids the noise caused by parasitic inductance and capacitance generated by conventional wire bonding of different elements.

Description

Technical Field

[0001] This invention relates to semiconductor structures and methods of manufacturing the same, and more particularly to a semiconductor structure and method of manufacturing the same suitable for high-voltage operation. Background Technology

[0002] In recent years, semiconductor structures have developed rapidly in fields such as computers and consumer electronics. Currently, semiconductor structure technology is widely accepted in the market for metal-oxide-semiconductor field-effect transistors (MOSFETs), holding a high market share. Semiconductor structures are used in various electronic applications, such as high-power devices, personal computers, mobile phones, digital cameras, and other electronic devices. These semiconductor structures are generally manufactured by depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, followed by patterning these material layers using photolithography. This allows circuit devices and components to be formed on the semiconductor substrate.

[0003] Among these devices, high-electron-mobility transistors (HEMTs) offer advantages such as high output power and high breakdown voltage, making them widely used in high-power applications. While existing semiconductor structures and their fabrication methods can meet their original intended uses, there are still challenges to be overcome in various aspects of their structure and fabrication techniques.

[0004] Taking System-in-a-Package (SiP) as an example, it involves directly packaging multiple functionally different chips into a single integrated circuit (IC) with complete functionality. Wire bonding is used to connect the different chips before further packaging to form the SiP semiconductor structure. While the SiP process is much simpler than integrating different functional ICs into a single system-on-a-chip (SoC), wire bonding between components introduces parasitic inductance and capacitance, leading to significant noise. For example, a rapid change rate of input current (L*di / dt) can cause spike current, limiting the operating frequency of the semiconductor structure. Furthermore, excessively large spike current fluctuations may exceed the component's critical voltage, damaging it. Summary of the Invention

[0005] Some embodiments of the present invention provide a semiconductor structure. The semiconductor structure includes a substrate, and the substrate has a first region and a second region. The semiconductor structure also includes an epitaxial layer located above the substrate. The semiconductor structure also includes a first element disposed on the first region of the substrate and a second element disposed on the second region of the substrate. In some embodiments, the first element includes a first gate located on the epitaxial layer, and a first source electrode and a first drain electrode located on opposite sides of the first gate, wherein a dielectric layer is formed on the epitaxial layer and covers the first gate. In some embodiments, the second element includes a second gate located on the dielectric layer, and a second source electrode and a second drain electrode located on opposite sides of the second gate, wherein the second source electrode is electrically connected to the first drain electrode. The semiconductor structure further includes an isolation structure disposed on the substrate, and the epitaxial layers in the first region and the second region are isolated from each other by the isolation structure.

[0006] According to some embodiments, the first gate in the semiconductor structure comprises p-type doped gallium nitride, and the second gate comprises metal or polysilicon.

[0007] According to some embodiments, the second gate of the second element in the semiconductor structure is electrically connected to the first source electrode of the first element.

[0008] According to some embodiments, the isolation structure in the semiconductor structure extends through the epitaxial layer and contacts the top surface of the substrate.

[0009] According to some embodiments, the semiconductor structure further includes a seed layer located on the substrate, wherein an epitaxial layer is located on the seed layer.

[0010] According to some embodiments, the isolation structure in the semiconductor structure penetrates the epitaxial layer and the seed layer, and the isolation structure contacts the top surface of the substrate.

[0011] According to some embodiments, the first source electrode in the semiconductor structure includes two first conductive portions that are electrically connected to each other, and the first element further includes a first through-hole that is electrically connected to one of the two first conductive portions, and the first through-hole passes through the epitaxial layer and contacts the seed layer.

[0012] According to some embodiments, the second source electrode in the semiconductor structure includes two second conductive portions that are electrically connected to each other, and the second element further includes a second via that is electrically connected to one of the two second conductive portions, and the second via passes through the epitaxial layer and contacts the seed layer.

[0013] According to some embodiments, the first element in the semiconductor structure is an enhanced-mode high-voltage transistor, and the second element is a depletion-mode high-voltage transistor.

[0014] According to some embodiments, the semiconductor structure further includes an interlayer dielectric layer located on the epitaxial layer and covering the first element and the second element, wherein the interlayer dielectric layer includes the aforementioned dielectric layer covering the first gate and another dielectric layer covering the second gate.

[0015] According to some embodiments, the semiconductor structure further includes a third element disposed on a second region of the substrate. The third element includes a third gate located on a dielectric layer, a third source electrode and a third drain electrode located on opposite sides of the third gate, wherein the third source electrode of the third element is electrically connected to the second drain electrode of the second element.

[0016] According to some embodiments, the third gate of the third element in the semiconductor structure is electrically connected to the second source electrode of the second element.

[0017] According to some embodiments, the semiconductor structure further includes another isolation structure disposed on the substrate, which isolates the epitaxial layers corresponding to the second and third elements from each other.

[0018] According to some embodiments, the first element in the semiconductor structure is an enhancement-mode high-voltage transistor, and the second and third elements are depletion-mode high-voltage transistors.

[0019] According to some embodiments, the substrate in the semiconductor structure includes a base and an insulating layer disposed on the base, with the epitaxial layer located above the insulating layer.

[0020] Some embodiments of the present invention provide a method for manufacturing a semiconductor structure, comprising providing a substrate having a first region and a second region. The manufacturing method also includes forming an epitaxial layer over the substrate and forming an isolation structure on the substrate, wherein the isolation structure isolates the epitaxial layers in the first region and the second region from each other. The manufacturing method further includes forming a first element in the first region of the substrate and forming a second element in the second region of the substrate. In some embodiments, the first element includes a first gate located on the epitaxial layer, and a first source electrode and a first drain electrode located on opposite sides of the first gate, wherein a dielectric layer is formed on the epitaxial layer and covers the first gate. In some embodiments, the second element includes a second gate located on the dielectric layer, and a second source electrode and a second drain electrode located on opposite sides of the second gate, wherein the second source electrode is electrically connected to the first drain electrode.

[0021] In some embodiments, the method of manufacturing the above-described semiconductor structure further includes electrically connecting a second gate of the second element to a first source electrode of the first element.

[0022] In some embodiments, in the above-described semiconductor structure manufacturing method, the formed isolation structure penetrates the epitaxial layer and contacts the top surface of the substrate.

[0023] In some embodiments, the method for manufacturing the above-described semiconductor structure further includes forming a seed layer on the substrate, wherein an epitaxial layer is formed on the seed layer.

[0024] In some embodiments, in the manufacturing method of the above semiconductor structure, the isolation structure penetrates through the epitaxial layer and the seed layer, and the isolation structure contacts the top surface of the substrate.

[0025] In some embodiments, in the method for manufacturing the above semiconductor structure, the first source electrode includes two first conductive portions that are electrically connected to each other, and the step of forming the first element further includes forming a first via that is electrically connected to one of the two first conductive portions, and the first via penetrates the epitaxial layer and contacts the seed layer.

[0026] In some embodiments, in the method for manufacturing the above semiconductor structure, the second source electrode includes two second conductive portions that are electrically connected to each other, and the step of forming the second element further includes forming a second via that is electrically connected to one of the two second conductive portions, and the second via penetrates the epitaxial layer and contacts the seed layer.

[0027] According to some embodiments, in the above-described semiconductor structure manufacturing method, the first element obtained is an enhancement-mode high-voltage transistor, and the second element is a depletion-mode high-voltage transistor.

[0028] According to some embodiments, in the above-described semiconductor structure manufacturing method, the semiconductor structure further includes an interlayer dielectric layer located on the epitaxial layer and covering the first element and the second element, wherein the interlayer dielectric layer includes a dielectric layer covering the first gate and another dielectric layer covering the second gate.

[0029] According to some embodiments, the method for manufacturing the above-described semiconductor structure further includes forming a third element on a second region of a substrate. The third element includes a third gate located on a dielectric layer, a third source electrode, and a third drain electrode located on opposite sides of the third gate. The third source electrode is electrically connected to the second drain electrode.

[0030] According to some embodiments, in the above-described semiconductor structure manufacturing method, the third gate of the third element is electrically connected to the second source electrode of the second element.

[0031] According to some embodiments, the method for manufacturing the above-described semiconductor structure further includes forming another isolation structure on a substrate, which isolates the epitaxial layers corresponding to the second element and the third element from each other.

[0032] According to some embodiments, in the above-described semiconductor structure manufacturing method, the first element obtained is an enhancement-mode high-voltage transistor, and the second and third elements are depletion-mode high-voltage transistors.

[0033] This invention avoids the noise caused by parasitic inductance and capacitance generated by the traditional method of connecting different components with wires, thereby reducing the peak current caused by high current change rate and making the components less prone to damage.

[0034] To make the features and advantages of the embodiments of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0035] Figures 1A-1G According to some embodiments of the present invention, the formation is shown Figure 1G A cross-sectional schematic diagram of the various intermediate stages of the semiconductor structure 100.

[0036] Figure 2 This is a cross-sectional schematic diagram of a semiconductor structure according to some embodiments of the present invention, wherein two depletion-type transistors are connected in series in a second region of the substrate.

[0037] Figure 3 This is a cross-sectional schematic diagram of a semiconductor structure according to some embodiments of the present invention, wherein n depletion-type transistors are connected in series in a second region of a substrate, where n is a positive integer greater than or equal to 3.

[0038] Figure 4 This is an equivalent circuit diagram of a semiconductor structure according to some embodiments of the present invention.

[0039] Figure 5 This is a cross-sectional schematic diagram of a semiconductor structure according to some other embodiments of the present invention, wherein each element has a through-hole for electrically connecting the source electrode and the seed layer.

[0040] Figure 6 This is a cross-sectional schematic diagram of a semiconductor structure according to some other embodiments of the present invention, wherein each element has a through-hole for electrically connecting the source electrode and the seed layer.

[0041] Attached icon number

[0042] 10, 20, 30, 40, 50, 60 ~ Semiconductor structure;

[0043] 100A – First Area;

[0044] 100B – Second Zone;

[0045] DE1 ~ First element;

[0046] DE2 ~ Second element;

[0047] DE3 – Third element;

[0048] 100~substrate;

[0049] 101 ~ Base;

[0050] 102 ~ Insulation layer;

[0051] 102a – Top surface;

[0052] 104 ~ Seed layer;

[0053] 106 ~ Buffer layer;

[0054] 108~Channel Layer;

[0055] 110~Barrier layer;

[0056] 111 ~ Epitaxial layer;

[0057] 112h ~ trench;

[0058] 112 ~ Isolation structure;

[0059] 113 ~ First gate;

[0060] 114 ~ First dielectric layer;

[0061] 115 ~ Second gate;

[0062] 115-2 ~ Third gate;

[0063] 115-n ~ the (n+1)th gate;

[0064] 116 ~ Second dielectric layer;

[0065] 118 ~ Third dielectric layer;

[0066] 121h, 123h, 125h, 127h ~ Opening;

[0067] 121 ~ First source electrode;

[0068] 1211 ~ First conductive part;

[0069] 1212 ~ Second conductive part;

[0070] 123 ~ First drain electrode;

[0071] 124, 129 – Connecting parts;

[0072] 125 ~ Second source electrode;

[0073] 1251 ~ Third conductive part;

[0074] 1252~Fourth conductive part;

[0075] 125-2 ~ Third source electrode;

[0076] 125-n ~ the (n+1)th source electrode;

[0077] 127 ~ Second drain electrode;

[0078] 127-2 ~ Third drain electrode;

[0079] 127-n ~ the (n+1)th drain electrode;

[0080] 125-21, 125-22, 125-n1, 125-n2 ~ Conductive parts;

[0081] 113V, 115V, 121V, 127V ~ guide hole;

[0082] S, G, D ~ endpoints;

[0083] 151 – First through hole;

[0084] 152 ~ Second through hole;

[0085] 152-n ~ the (n+1)th through hole. Detailed Implementation

[0086] The following disclosure provides numerous embodiments or examples of different elements for implementing the provided semiconductor structure. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, the embodiments of the invention may repeat reference numerals and / or letters in different examples. Such repetition is for brevity and clarity and is not intended to indicate a relationship between the different embodiments discussed.

[0087] Furthermore, spatially related terms such as "below," "under," "below," "above," "above," and other similar expressions may be used in the following description to simplify the statement of the relationship between an element or component and other elements or components as shown in the figure. These spatially related terms include not only the direction depicted in the figure but also the different orientations of the device during use or operation. The device may be positioned in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptions used herein may be interpreted accordingly.

[0088] The following describes some variations of the embodiments. In embodiments with different figures and descriptions, similar element symbols are used to identify similar elements. It is understood that additional steps may be provided before, during, or after the method, and some described steps may be replaced or omitted for other embodiments of the method.

[0089] The embodiments of this invention provide semiconductor structures and methods for manufacturing the same. In some embodiments, multiple cascaded elements are fabricated on the same substrate, and the epitaxial layers of corresponding different elements are isolated from each other using isolation structures and the substrate. According to the element cascading method proposed in some embodiments, the semiconductor structure can achieve high-voltage or ultra-high-voltage applications without forming a very thick epitaxial layer. The reduced thickness of the epitaxial layer not only reduces the epitaxial process time but also significantly reduces the weight of the epitaxial layer on the substrate, reducing the stress generated by the epitaxial layer on the substrate. Furthermore, the elements of the semiconductor structure proposed in some embodiments can be elements that withstand lower voltages, achieving high-voltage applications through the cascading method described above. In some embodiments, the semiconductor structure includes a cascaded enhancement-mode transistor and one or more depletion-mode transistors. Furthermore, the semiconductor structure proposed in some embodiments is manufactured using a system-on-a-chip (SoC) process. The resulting semiconductor structure avoids the noise caused by parasitic inductance and capacitance resulting from traditional wire bonding of different components, thereby reducing the spike current caused by high current change rate (di / dt) and further improving the electrical performance of the semiconductor structure. Therefore, the semiconductor structure and its manufacturing method proposed in some embodiments of the present invention have improved electronic characteristics and good reliability.

[0090] In some of the following embodiments, a high-electron mobility transistor (HEMT) is used as an example of a device structure in a semiconductor structure. However, the present invention is not limited thereto, and other types of semiconductor devices may be used in some other embodiments.

[0091] Figures 1A-1G According to some embodiments of the present invention, the formation is shown Figure 1G A cross-sectional schematic diagram of each intermediate stage of the semiconductor structure 10.

[0092] Reference Figure 1A According to some embodiments, a substrate 100 is provided. The substrate 100 includes a base 101 and an insulating layer 102 disposed on the base 101. The insulating layer 102 provides an insulating surface for the substrate 100. In some embodiments, the substrate 100 includes the base 101 and a composite material layer encapsulating the base 101. The composite material layer, for example, covers all surfaces of the base 101 (including the top and bottom surfaces and all sides) to provide, for example, an insulating surface. Figure 1AAn insulating layer 102 is shown on a substrate 101. In some embodiments, the substrate 101 comprises a ceramic material. The ceramic material comprises a metallic inorganic material. In some embodiments, the substrate 101 may be a material comprising silicon carbide (SiC), aluminum nitride (AlN), sapphire, or other suitable materials. The sapphire substrate is aluminum oxide. In some embodiments, the composite material layer surrounding the substrate 101 may comprise a single or multiple layers of insulating material and / or other suitable material layers, wherein the insulating material layers are, for example, oxides, nitrides, or other suitable insulating materials. Additionally, in some other embodiments, the substrate 101 may be formed, for example, of silicon (Si), silicon carbide, gallium nitride (GaN), silicon dioxide (SiO2), sapphire, or a combination thereof. For example, the substrate 100 is a silicon-on-insulator (SOI) substrate, i.e., the substrate 100 comprises a silicon substrate and an insulating layer formed on the silicon substrate. For simplicity, only a portion of the insulating layer 102 above the substrate 101 is shown in the diagram of substrate 100. In some embodiments, substrate 100 may be a single-layer substrate or a multi-layer substrate. Substrate 100 is not limited to a silicon-on-insulator (SOI) substrate, but may also be a silicon wafer or a ceramic substrate. Furthermore, substrate 100 includes a first region 100A and a second region 100B. According to some embodiments, the first region 100A is where the first element D will subsequently be formed. E1 The second region, 100B, is where the second element D will subsequently be formed. E2 The following embodiments illustrate the structure of the first region 100A and the second region 100B as elements formed in the first region 100A and the second region 100B. Furthermore, the positions of the first region 100A and the second region 100B can be arbitrarily adjusted according to the configuration requirements of the semiconductor structure. In some embodiments, the first region 100A is adjacent to the second region 100B.

[0093] Next, refer to Figure 1A A seed layer 104 is formed above the substrate 100, and an epitaxial layer 111 is formed above the seed layer 104.

[0094] In some embodiments, the seed layer 104 may be formed of silicon (Si) or other suitable materials. In some embodiments, the method of forming the seed layer 104 may include a selective epitaxy growth (SEG) process, a chemical vapor deposition (CVD) process, a molecular beam epitaxy process (MBE), a solid-phase epitaxial recrystallization (SPER) step after depositing a doped amorphous semiconductor (e.g., Si), a method of directly transferring a seed, or other suitable processes. The chemical vapor deposition process is, for example, a vapor-phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, an ultra-high vacuum chemical vapor deposition (UHV-CVD) process, or other suitable processes.

[0095] As Figure 1A shown, in some embodiments, taking the structure of a high electron mobility transistor as an example of the elements formed in the first region 100A and the second region 100B, the epitaxial layer 111 includes a buffer layer 106, a channel layer 108, and a barrier layer 110.

[0096] In some embodiments, the buffer layer 106 is epitaxially grown on the seed layer 104. The buffer layer 106 can help mitigate the strain of a subsequent channel layer 108 formed above the buffer layer 106 and prevent defects from forming in the upper channel layer 108. In some embodiments, the material of the buffer layer 106 is a III-V semiconductor, such as AlN, GaN, AlxGa1-xN (1 < x < 1), the foregoing combinations, or similar materials. In some embodiments, the buffer layer 106 may be formed by hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), combinations of the foregoing methods, or similar methods. Although in the embodiments Figure 1A shown, the buffer layer 106 is a single-layer structure, in some other embodiments, the buffer layer 106 may also be a multi-layer structure.

[0097] Next, a channel layer 108 is epitaxially formed on the buffer layer 106. In some embodiments, the channel layer 108 includes an undoped group III-V semiconductor material. For example, the channel layer 108 may be formed of undoped gallium nitride (GaN), but the present invention is not limited thereto. In some other embodiments, the channel layer 108 includes aluminum gallium nitride (AlGaN), aluminum nitride (AlN), gallium arsenide (GaAs), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable group III-V materials, or a combination of the above. In some embodiments, molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), metalorganic chemical vapor deposition (MOCVD), other suitable methods, or a combination of the above methods may be used to form the channel layer 108.

[0098] After that, a barrier layer 110 is epitaxially formed on the channel layer 108. In some embodiments, the barrier layer 110 includes an undoped group III-V semiconductor material. For example, the barrier layer 110 is formed of undoped aluminum gallium nitride (AlxGa1-xN, where 0 < x < 1), but the present invention is not limited thereto. In some other embodiments, the barrier layer 110 may also include gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), gallium indium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable group III-V materials, or a combination of the above. For example, molecular beam epitaxy, metalorganic chemical vapor deposition, hydride vapor phase epitaxy, other suitable methods, or a combination of the above methods may be used to form the barrier layer 110 on the channel layer 108.

[0099] In some embodiments, the channel layer 108 and the barrier layer 110 include different materials to form a heterojunction interface between the channel layer 108 and the barrier layer 110. Through the band gap of the heterojunction materials, a two-dimensional electron gas (2DEG) (not shown) can be formed on this heterojunction interface. According to the semiconductor structure formed according to some embodiments, such as a high electron mobility transistor (HEMT), the two-dimensional electron gas can be used as the conductive carrier.

[0100] Although, as in the above embodiment, the epitaxial layer 111 is a gallium nitride-containing composite layer, the present invention is not limited thereto. In addition to the buffer layer 106, the channel layer 108, and the barrier layer 110, the epitaxial layer 111 may also contain other layers; for example, in some other embodiments, a carbon-doped layer may be formed between the buffer layer 106 and the channel layer 108 to improve the breakdown voltage of the semiconductor structure.

[0101] Next, refer to Figure 1B In some embodiments, a trench 112h is formed that penetrates the epitaxial layer 111 and contacts the top surface of the substrate 100. For example... Figure 1B As shown, trench 112h passes through barrier layer 110, channel layer 108, buffer layer 106, and seed layer 104, and contacts insulating layer 102 on substrate 101. In this example, the top surface 102a of insulating layer 102 is considered the top surface of substrate 100. Furthermore, in some embodiments, viewed from above substrate 100, trench 112h is part of a connected closed trench that separates a first region 100A and a second region 100B of substrate 100.

[0102] The formation method of trench 112h may include forming a mask layer (not shown) on barrier layer 110. Then, the mask layer is patterned by performing a patterning process to form a patterned mask (not shown). The patterning process includes photolithography and etching processes. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, washing, and drying (e.g., hard baking). The etching process includes dry etching or wet etching. As a result, the patterned mask exposes a portion of barrier layer 110. Then, using the patterned mask as a mask, a dry etching process, a wet etching process, or a combination of both dry and wet processes is performed to form trench 112h.

[0103] Then, refer to Figure 1C In some embodiments, one or more insulating materials are filled into the trench 112h to form an isolation structure 112, and a first gate 113 is formed on the epitaxial layer 111 (e.g., on the barrier layer 110) in the first region 100A.

[0104] In some embodiments, the insulating material filled within the trench 112h comprises, for example, nitrides, oxides, or combinations thereof, to form the isolation structure 112. The material of the isolation structure 112 may be formed by atomic layer deposition (ALD), chemical vapor deposition, spin-on glass (SOG), flowable chemical vapor deposition (FCVD), high-density plasma chemical vapor deposition, or similar processes. In some other embodiments, the isolation structure 112 may include a liner on the sidewalls of the trench 112h. The liner material used, depending on the process and component requirements, includes metallic and / or dielectric materials.

[0105] Furthermore, in some embodiments, viewed from above the substrate 100, the isolation structure 112 is part of a connected closed structure, which separates the first region 100A and the second region 100B of the substrate 100. For example Figure 1C As shown, the leftmost isolation structure 112 and the middle isolation structure 112 are respectively part of the left and right side walls of the closed structure surrounding the first region 100A, while the middle isolation structure 112 and the rightmost isolation structure 112 are respectively part of the left and right side walls of the closed structure surrounding the second region 100B. In some embodiments, the top view shape of the closed structure is square, rectangular, or other suitable shape. The present invention does not particularly limit the top view shape of the closed structure and the area of ​​the region it surrounds (i.e., the size of the first region 100A and the second region 100B), and can be arbitrarily varied and adjusted according to the configuration requirements of the semiconductor structure in the actual application.

[0106] Then, refer to Figure 1C In some embodiments, a first gate 113 is formed on a barrier layer 110 in the first region 100A, and a first dielectric layer 114 is formed on the barrier layer 110. The first dielectric layer 114 conformally covers the isolation structure 112 and the first gate 113. Figure 1C As shown, the first gate 113 directly contacts the barrier layer 110.

[0107] In some embodiments, the first gate 113 may be made of p-type doped gallium nitride (p-GaN). In some other embodiments, the first gate 113 may comprise p-type doped aluminum gallium nitride (AlGaN), gallium nitride (GaN), aluminum nitride (AlN), gallium arsenide (GaAs), indium gallium phosphide (GaInP), aluminum gallium arsenide (AlGaAs), indium phosphide (InP), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), other suitable III-V materials, or combinations thereof. Furthermore, the method of forming the first gate 113 may include the aforementioned deposition or epitaxial processes, as well as ion implantation or in-situ doping processes.

[0108] In some embodiments, the first dielectric layer 114 may be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or other suitable dielectric materials, wherein the thickness of the first dielectric layer 114 is about 1 angstrom. ~ Approximately 1000 Anglo Furthermore, the first dielectric layer 114 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or a combination thereof.

[0109] Then, refer to Figure 1D In some embodiments, a second gate 115 is formed on a first dielectric layer 114 in the second region 100B, and a second dielectric layer 116 is formed on the first dielectric layer 114. The second gate 115 directly contacts the first dielectric layer 114. The second dielectric layer 116 conformally covers the isolation structure 112 and the second gate 115.

[0110] In some embodiments, the second gate 115 may comprise a metallic material, a metal silicide, polysilicon, other suitable conductive materials, or a combination thereof. Metallic materials include, for example, nickel (Ni), gold (Au), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), combinations thereof, or other suitable materials. In some embodiments, the second gate 115 may be formed by atomic layer deposition, chemical vapor deposition, physical vapor deposition (such as sputtering), or similar processes. Additionally, in some embodiments, the process and materials of the second dielectric layer 116 may be similar to or the same as those of the first dielectric layer 114, and will not be repeated here.

[0111] In some embodiments, the first gate 113 is a p-GaN gate, and the first gate 113 is connected to the first source electrode 121 and the first drain electrode 123 subsequently formed on both sides of the first gate 113. Figure 1FThis can form an enhanced-mode (E-mode) device. The second gate 115 is a metal gate, and the second gate 115, along with the second source electrode 125 and the second drain electrode 127 subsequently formed on both sides of the second gate 115, can form an enhanced-mode (E-mode) device. Figure 1F This can form a depletion-mode (D-mode) element.

[0112] Next, as Figure 1E As shown, in some embodiments, the aforementioned material layers including the second dielectric layer 116, the first dielectric layer 114, and the barrier layer 110 are patterned to form openings 121h and 123h in the first region 100A and openings 125h and 127h in the second region 100B.

[0113] In this example, openings 121h and 123h in the first region 100A are located on opposite sides of the first gate 113 for subsequent formation of the source and drain of the first element DE1. In this example, openings 125h and 127h in the second region 100B are located on opposite sides of the second gate 115 for subsequent formation of the source and drain of the second element DE2. In some embodiments, openings 121h, 123h, 125h, and 127h extend into the barrier layer 110 and expose the channel layer 108.

[0114] In some embodiments, openings 121h, 123h, 125h, and 127h can be formed simultaneously using a masking layer (not shown) and an etching process. The etching process includes, for example, dry etching processes such as reactive ion etching (RIE), electron cyclotron resonance (ERC) etching, inductively coupled plasma (ICP) etching, or similar dry etching processes.

[0115] In some embodiments, an etching apparatus including an etching chamber may be used to provide an etchant supply system for the etching process, a bias power generator capable of applying bias power to the etching chamber, a wafer stage, a spray head capable of uniformly dispersing the etchant, and an etching endpoint detector capable of real-time monitoring of the etching signal of the material layer to be removed during the etching process. During the etching process, the etchant is accelerated by a bias electric field in the etching chamber and, in the direction of the wafer stage, performs anisotropic etching on the second dielectric layer 116, the first dielectric layer 114, and the barrier layer 110.

[0116] After the openings are formed for 121h, 123h, 125h and 127h, an ashing process can be performed to remove the masking layer.

[0117] Next, as Figure 1F As shown, in some embodiments, suitable conductive materials are deposited in openings 121h, 123h, 125h and 127h, and a patterning step is performed to form the source electrode and drain electrode of the first element and the second element, respectively.

[0118] In some embodiments, the deposited conductive material is, for example, gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), tantalum nitride (TaN), titanium nitride (TiN), tungsten silicide (WSi2), combinations thereof, or similar materials, to form a first source electrode 121 and a first drain electrode 123 at openings 121h and 123h in the first region 100A, respectively, and a second source electrode 125 and a second drain electrode 127 at openings 125h and 127h in the second region 100B, respectively.

[0119] like Figure 1F As shown, in some embodiments, the first source electrode 121 and the first drain electrode 123 in the first region 100A are located on the channel layer 108 and are in electrical contact with the channel layer 108; the second source electrode 125 and the second drain electrode 127 in the second region 100B are located on the channel layer 108 and are in electrical contact with the channel layer 108.

[0120] In some embodiments, the conductive material may be deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electron beam evaporation, sputtering, or similar processes. In some embodiments, after depositing the material layers to form the source / drain electrodes, a high-temperature thermal process, such as rapid thermal annealing, is further included to form source-drain ohmic contacts.

[0121] like Figure 1FAs shown, the first element DE1 formed in the first region 100A includes, for example, a first gate 113, a first source electrode 121, and a first drain electrode 123, while the second element DE2 formed in the second region 100B includes, for example, a second gate 115, a second source electrode 125, and a second drain electrode 127. According to some embodiments, the first element DE1 is an enhancement-mode (E-mode, i.e., normally-off) high electron mobility transistor, and the second element DE2 is a depletion-mode (D-mode) high electron mobility transistor.

[0122] It is worth noting that, according to some embodiments of the present invention, the first drain electrode 123 of the first element DE1 (in the first region 100A) is electrically connected to the second source electrode 125 of the second element DE2 (in the second region 100B). In some embodiments, such as Figure 1F As shown, after depositing conductive material in openings 121h, 123h, 125h, and 127h, and following appropriate patterning steps, the first drain electrode 123 in the first region 100A and the second source electrode 125 in the second region 100B can be electrically connected via a connection portion 124. In some embodiments, the connection portion 124, the first drain electrode 123, and the second source electrode 125 have the same conductive material.

[0123] Then, refer to Figure 1G In some embodiments, a third dielectric layer 118 is formed on the second dielectric layer 116. For example... Figure 1G As shown, the third dielectric layer 118 compliantly covers the first element DE1 and the second element DE2. The first dielectric layer 114, the second dielectric layer 116, and the third dielectric layer 118 may constitute an interlayer dielectric (ILD) above the epitaxial layer 111. In some embodiments, the process and materials of the third dielectric layer 118 may be similar to or the same as those of the second dielectric layer 116 and the first dielectric layer 114, and will not be repeated here.

[0124] Next, as Figure 1G As shown, in some embodiments, vias 121V and 113V are formed on the first source electrode 121 and the first gate electrode 113 of the first element DE1, respectively, and vias 115V and 127V are formed on the second gate electrode 115 and the second drain electrode 127 of the second element DE2, respectively, wherein the second gate electrode 115 of the second element DE2 and the first source electrode 121 of the first element DE1 are electrically connected via a connection portion 129. It is worth noting that, although Figure 1GConnection portion 129 is shown, but connection portion 129 is not electrically connected to via 113V above the first gate 113. The process and materials of vias 121V, 113V, 115V, 127V and connection portion 129 may be similar to or the same as those of the aforementioned source electrode and drain electrode (filling the openings 121h, 123h, 125h and 127h) and connection portion 124, and will not be described again here.

[0125] According to some embodiments of the present invention, the second gate 115 of the second element DE2 in the second region 100B is electrically connected to the first source electrode 121 of the first element DE1 in the first region 100A. For example... Figure 1G As shown, the second gate 115 and the first source electrode 121 are electrically connected via the connection portion 129. In some embodiments, the vias 121V, 113V, 115V, 127V and the connection portion 129 have the same conductive material.

[0126] According to some embodiments, the semiconductor structure described above interconnects multiple components in a cascade manner to enable high-voltage applications. In some embodiments, the components formed in the first region 100A are, for example, enhancement-mode transistors (e.g., the first component DE1 is an enhancement-mode high electron mobility transistor), and the components formed in the second region 100B are, for example, depletion-mode transistors (e.g., the second component DE2 is a depletion-mode high electron mobility transistor), and the first drain electrode 123 of the first region 100A is electrically connected to the second source electrode 125 of the second region 100B. Furthermore, in some embodiments, the second gate 115 of the component in the second region 100B is electrically connected to the first source electrode 121 of the component in the first region 100A. Operation as follows... Figure 1G In the semiconductor structure 10 shown, voltages are applied to terminals S, G, and D respectively. For example, in some embodiments, a source voltage is applied to terminal S via via 121V to the first source electrode 121, a gate voltage is applied to terminal G via via 113V to the first gate 113, and a drain voltage is applied to terminal D via via 127V to the second drain electrode 127. Figure 1G In the semiconductor structure 10 shown, the first element DE1 serves as a switching element of the semiconductor structure 10, and the second element DE2 can be turned off (Vgs is less than 0) by the first element DE1.

[0127] According to some embodiments of the present invention described above, through the above-described... Figure 1GThe series connection shown in the semiconductor structure 10 requires only that the epitaxial layer 111 has the capability to withstand approximately 650V, and a first element DE1 capable of withstanding approximately 650V and a second element DE2 capable of withstanding approximately 650V can be fabricated on the same substrate to achieve a high-voltage application of 1200V. Furthermore, when 0V and 1200V are applied to the first source electrode 121 and the second drain electrode 127 respectively, the electrically connected first drain electrode 123 and second source electrode 125 will each be 600V.

[0128] Therefore, according to the series connection method of the semiconductor structure 10 proposed in some embodiments of the present invention, the semiconductor structure 10 can be used as a high-voltage device or ultra-high-voltage device without forming a very thick epitaxial layer 111. For example, connecting a first element DE1 in series with a second element DE2 can reduce the thickness of the epitaxial layer 111, which originally required about 5 to 10 micrometers (μm), to about 1 to 5 micrometers (μm). The reduced thickness of the epitaxial layer 111 not only reduces the epitaxial process time but also significantly reduces the weight of the epitaxial layer 111 borne by the substrate 100 and reduces the stress generated by the epitaxial layer 111 on the substrate, thereby preventing the epitaxial layer 111 from peeling off from the substrate. Therefore, the process of the semiconductor structure proposed in some embodiments of the present invention can reduce manufacturing costs and improve product reliability.

[0129] Furthermore, some embodiments of the present invention propose a process for a system-on-a-chip (SoC) semiconductor structure that is easy to implement and has low manufacturing costs. As described above... Figures 1A-1G The semiconductor structure manufacturing method shown involves fabricating a first element DE1 and a second element DE2 on the same substrate 100. An isolation structure 112 and an insulating layer 102 on the substrate are used to isolate the epitaxial layers of corresponding different elements from each other. Elements in different regions are connected in series using connection portions (e.g., metal wires) 124 and 129 in the aforementioned connection manner. Furthermore, compared to conventional methods that fabricate elements separately and then achieve electrical connections using wire bonding (i.e., System-on-Package, SiP), the semiconductor structure proposed in some embodiments of the present invention avoids the noise caused by parasitic inductance and capacitance resulting from conventional wire bonding of different elements (e.g., transistor elements), thereby reducing the spike current caused by high current change rate (di / dt). The smaller the swing of the spike current, the less likely the element is to be damaged. Therefore, the semiconductor structure proposed in some embodiments of the present invention has improved electronic characteristics and good reliability.

[0130] According to some embodiments of the present invention, multiple depletion-mode (D-mode) transistors can be connected in series in the second region 100B, so that the semiconductor structure formed by the series connection can realize high-voltage or ultra-high-voltage operation.

[0131] Figure 2 This is a cross-sectional schematic diagram of a semiconductor structure according to some embodiments of the present invention. Figure 2 The semiconductor structure 20 and the above Figure 1G The difference in semiconductor structure 10 is that two depletion-type transistors are connected in series in the second region 100B of semiconductor structure 20, which can reduce the voltage that each transistor needs to withstand or increase the voltage that semiconductor structure 20 can be applied to. Figure 2 The same as the above Figures 1A-1G The components use the same or similar designations and their descriptions are omitted.

[0132] like Figure 2 As shown, in some embodiments, the semiconductor structure 20 includes an enhancement-mode (E-mode) transistor, such as a first element DE1, disposed in a first region 100A, and two depletion-mode (D-mode) transistors, such as a second element DE2 and a third element DE3, disposed in a second region 100B. The semiconductor structure 20 further includes another isolation structure 112 on the substrate 100, and this isolation structure 112 isolates the epitaxial layers 111 corresponding to the second element DE2 and the third element DE3 from each other. In some embodiments, the first element DE1 is an enhancement-mode high electron mobility transistor (E-mode HEMT), and the second element DE2 and the third element DE3 are depletion-mode high electron mobility transistors (D-mode HEMTs).

[0133] In some embodiments, the third element DE3 includes a third gate 115-2, a third source electrode 125-2, and a third drain electrode 127-2. The third gate 115-2 is located on the first dielectric layer 114, while the third source electrode 125-2 and the third drain electrode 127-2 are located on opposite sides of the third gate 115-2, extending into the barrier layer 110 and contacting the channel layer 108. The components, materials, and related processes of the third element DE3 are the same as or similar to those of the aforementioned second element DE2, and will not be repeated here.

[0134] Furthermore, the series connection between the three components is similar to the series connection method in the example above. For example, in some embodiments, the first drain electrode 123 of the first component DE1 is electrically connected to the second source electrode 125 of the second component DE2, and the second drain electrode 127 of the second component DE2 is electrically connected to the third source electrode 125-2 of the third component DE3.

[0135] Furthermore, the gate of a component (e.g., a depletion-type transistor) located on the second region 100B of the substrate 100 is electrically connected to the source electrode of the next transistor. For example, in some embodiments, the second gate 115 of the second component DE2 is electrically connected to the first source electrode 121 of the first component DE1, and the third gate 115-2 of the third component DE3 is electrically connected to the second source electrode 125 of the second component DE2. The operation is as follows... Figure 2 In the semiconductor structure 20 shown, a source voltage is applied to the first source electrode 121 at terminal S, a gate voltage is applied to the first gate electrode 113 at terminal G, and a drain voltage is applied to the third drain electrode 127-2 at terminal D. Figure 2 In the semiconductor structure 20 shown, the first element DE1 serves as a switching element of the semiconductor structure 20, and the second element DE2 and the third element DE3 can be turned off through the first element DE1.

[0136] according to Figure 2 The semiconductor structure 20, as described above Figure 2 In the series connection shown, if a high-voltage application of 1200V is required, the epitaxial layer 111 only needs to have the capability to withstand approximately 450V. Furthermore, a first element DE1 capable of withstanding approximately 450V, a second element DE2 capable of withstanding approximately 450V, and a third element DE3 capable of withstanding approximately 450V can be fabricated on the same substrate to achieve a high-voltage application of 1200V. Additionally, when 0V and 1200V are applied to the first source electrode 121 and the third drain electrode 127-2 respectively, the electrically connected first drain electrode 123 and second source electrode 125 are each 800V, while the electrically connected second drain electrode 127 and third source electrode 125-2 are each 400V.

[0137] Furthermore, in some embodiments of the semiconductor structure, n depletion-mode (D-mode) transistors are connected in series in the second region 100B, where n is a positive integer greater than or equal to 3. Figure 3 This is a cross-sectional schematic diagram of a semiconductor structure according to some embodiments of the present invention. Figure 3 The same as the foregoing embodiments Figures 1A-1G and Figure 2 The components use the same or similar designations, and their descriptions are omitted.

[0138] like Figure 3 As shown, in some embodiments, the semiconductor structure 30 includes an enhancement transistor, such as a first element DE1, disposed in the first region 100A, and n depletion transistors, such as a second element DE2, a third element DE3, ... and an (n+1)th element DE... (n+1)The components are located in the second region 100B, where n is a positive integer greater than or equal to 3. The semiconductor structure 30 includes a plurality of isolation structures 112 to isolate the epitaxial layers 111 corresponding to these components from each other. In some embodiments, the first component DE1 is, for example, an enhancement-mode high electron mobility transistor (E-mode HEMT), the second component DE2, the third component DE3, ..., and the (n+1)th component DE... (n+1) For example, a depletion-mode high electron mobility transistor (D-mode HEMT).

[0139] Furthermore, in some embodiments, multiple elements disposed in the second region 100B have similar components and configurations. For example, the (n+1)th element DE (n+1) It includes an (n+1)th gate 115-n, an (n+1)th source electrode 125-n, and an (n+1)th drain electrode 127-n. The (n+1)th gate 115-n is located on the first dielectric layer 114, while the (n+1)th source electrode 125-n and the (n+1)th drain electrode 127-n are located on opposite sides of the (n+1)th gate 115-n and extend into the barrier layer 110, contacting the channel layer 108. The structure, materials used, and related processes of the second element DE2 in the second region 100B are the same as or similar to those of the second element DE2 in the aforementioned embodiment, and will not be repeated here.

[0140] Furthermore, the series connection between the three components is similar to the series connection method in the example above. For example, in some embodiments, the first drain electrode 123 of the first component DE1 is electrically connected to the second source electrode 125 of the second component DE2, the second drain electrode 127 of the second component DE2 is electrically connected to the third source electrode 125-2 of the third component DE3, and the nth component DE... n The nth drain electrode 127-(n-1) is electrically connected to the (n+1)th element DE. (n+1) The (n+1)th source electrode 125-n, and so on.

[0141] Furthermore, the gate of a component (e.g., a depletion-type transistor) located on the second region 100B of the substrate 100 is electrically connected to the source electrode of the next transistor. For example, in some embodiments, the second gate 115 of the second component DE2 is electrically connected to the first source electrode 121 of the first component DE1, the third gate 115-2 of the third component DE3 is electrically connected to the second source electrode 125 of the second component DE2, and the (n+1)th component DE... (n+1) The (n+1)th gate 115-n is electrically connected to the nth element DE. n The nth source electrode is 125-(n-1), and so on.

[0142] Operation as follows Figure 3In the semiconductor structure 30 shown, a source voltage is applied to the first source electrode 121 at terminal S, a gate voltage is applied to the first gate electrode 113 at terminal G, and a drain voltage is applied to the (n+1)th drain electrode 127-n at terminal D. Figure 3 In the semiconductor structure 30 shown, the first element DE1 serves as a switching element of the semiconductor structure 20. By using the first element DE1, the second element DE2, the third element DE3, ... and the (n+1)th element DE on the second region 100B can be turned off. (n+1) .

[0143] according to Figure 3 The semiconductor structure 30, as described above Figure 3 In the cascading configuration shown, if a high-voltage application of 1200V is required, the epitaxial layer 111 only needs to have a capacity slightly greater than (1200 / (n+1))V. For example, when n=4, there is one enhancement-mode and four depletion-mode transistors on the substrate. The epitaxial layer 111 only needs to have a capacity of approximately 280V to 300V (1200 / 5=240V) to stably operate the semiconductor structure 30. Furthermore, first elements DE1 to fifth elements DE5, each capable of withstanding approximately 280V to 300V, can be fabricated on the same substrate and cascaded to achieve a high-voltage application of 1200V.

[0144] Figure 4 The diagram below shows an equivalent circuit of a semiconductor structure 40 according to some embodiments of the present invention, wherein the semiconductor structure 40 consists of one enhancement-mode transistor (first region 100A) and five depletion-mode transistors (second region 100B) connected in series. The structure of each component of the semiconductor structure 40 is described in the examples above. Figure 1G , Figure 2 , Figure 3 The first element DE1, the second element DE2, and the third element DE3 are shown.

[0145] Furthermore, while connecting more components in series on the substrate 100 can reduce the thickness of the epitaxial layer 111 and lower the voltage each component needs to withstand, it also increases the area of ​​the substrate 100. Therefore, in practical applications, a trade-off must be made considering factors such as the reduction in epitaxial layer thickness due to the increased number of components, the increased substrate area, and the size of the application product to determine the number of components to be connected in series on the substrate.

[0146] Furthermore, the present invention is not limited to the semiconductor structure proposed in the above embodiments. In some other embodiments, the semiconductor structure may include other components to further improve the electrical performance of the semiconductor structure.

[0147] For example, parasitic charges may be generated and accumulated in the seed layer 104 below the epitaxial layer 111 due to the plasma etching process. These accumulated parasitic charges in the seed layer 104 cause an increase in dynamic on-resistance (dynamic R-on), leading to a decrease in current (I-on), which in turn causes circuit failure and affects the electrical properties of the semiconductor structure. The following presents some other embodiments of semiconductor structures to address the problem of parasitic charges accumulated in the seed layer 104.

[0148] Figure 5 This is a cross-sectional schematic diagram of a semiconductor structure according to some other embodiments of the present invention. Figure 5 The same as the above Figure 1G The components use the same or similar designations, and their related structures, materials, processes and connection methods are described in the above embodiments, which will not be repeated here.

[0149] Figure 5 The semiconductor structure 50 and the above Figure 1G The difference in semiconductor structure 10 is that the source electrode of each element of semiconductor structure 50 includes two electrically connected conductive portions, and one of the conductive portions is electrically connected to the seed layer 104 through an additionally formed through-hole to release parasitic charges generated, for example, by plasma etching process and accumulated in the seed layer 104.

[0150] like Figure 5 As shown, in some embodiments, the first source electrode 121 of the first element DE1 includes a first conductive portion 1211 and a second conductive portion 1212 that are electrically connected to each other, and the first conductive portion 1211 and / or the second conductive portion 1212 pass through the epitaxial layer 111 and contact the seed layer 104.

[0151] Similarly, in some embodiments, the second source electrode 125 of the second element DE2 includes two third conductive portions 1251 and a fourth conductive portion 1252 electrically connected to each other, and the third conductive portion 1251 and / or the fourth conductive portion 1252 passes through the epitaxial layer 111 and contacts the seed layer 104. In this example, the third conductive portion 1251 passes through the epitaxial layer 111 and contacts the seed layer 104 to release parasitic charges accumulated in the seed layer 104.

[0152] In high-voltage operation (e.g., operating voltage above 600V) Figure 5 In the semiconductor structure 50, since the conductive material filled in the through holes 151 and 152 of the epitaxial layer 111 provides a release path for the parasitic charge accumulated in the seed layer 104, the problem of parasitic charge moving arbitrarily under high voltage and affecting the electrical performance of the semiconductor structure can be further solved.

[0153] In some other embodiments of the semiconductor structure, two or more depletion transistors may be connected in series in the second region 100B. Figure 6 This is a cross-sectional schematic diagram of a semiconductor structure according to some other embodiments of the present invention. Figure 6 The same as the foregoing embodiments Figure 3 and Figure 5 The components use the same or similar designations, and their descriptions are omitted.

[0154] like Figure 6 As shown, n depletion-type transistors can be connected in series in the second region 100B of the semiconductor structure 60, where n is, for example, a positive integer greater than or equal to 3. Furthermore, in some embodiments, the source electrodes of each element of the semiconductor structure 60 include two electrically connected conductive portions (e.g., first conductive portion 1211 and second conductive portion 1212, third conductive portion 1251 and fourth conductive portion 1252, conductive portions 125-21 and 125-22, ..., conductive portions 125-n1 and 125-n2). One of the conductive portions of each source electrode can be electrically connected to the seed layer 104 via vias (e.g., 151, 152, 152-2, ..., 152-n) through the epitaxial layer 111.

[0155] Therefore, in high-voltage operation (e.g., operating voltage above 600V) such as Figure 6 When the semiconductor structure 60 is used, it not only has the aforementioned advantages such as reducing the thickness of the epitaxial layer, reducing the voltage that each component needs to withstand, and allowing components to be fabricated on the same substrate, enabling high-voltage or ultra-high-voltage applications, but the conductive material filling the through-holes of each component also provides a release path for parasitic charges accumulated in the seed layer 104. Therefore, high-voltage operation, such as Figure 6 When the semiconductor structure 60 is shown, parasitic charges can be prevented from moving freely under high voltage, further improving the electrical performance of the semiconductor structure.

[0156] In summary, the semiconductor structure proposed in some embodiments of the present invention has multiple series-connected transistor elements. According to the element series connection method proposed in some embodiments, the semiconductor structure can achieve high-voltage or ultra-high-voltage applications without forming a very thick epitaxial layer. The reduced epitaxial layer thickness not only reduces the epitaxial process time but also significantly reduces the weight of the epitaxial layer on the substrate, lowering the stress exerted by the epitaxial layer on the substrate. Furthermore, each element in the semiconductor structure proposed in some embodiments can be a low-voltage-bearing element, achieving high-voltage applications through the series connection method described above. Additionally, the semiconductor structure proposed in some embodiments uses a system-on-a-chip (SoC) process that is easy to implement and has low manufacturing costs. Multiple elements, such as an enhancement-mode transistor and one or more depletion-mode transistors, are fabricated on the same substrate and connected in series, with the epitaxial layers of corresponding different elements isolated from each other using isolation structures and insulating layers on the substrate. Through the element series connection method as described in the above embodiments, noise caused by parasitic inductance and parasitic capacitance generated by conventional wire bonding of different elements (e.g., transistor elements) can be avoided, thereby reducing the spike current caused by high current change rate (di / dt). The smaller the peak current swing, the less susceptible the device is to damage. Furthermore, the semiconductor structure proposed in some other embodiments may include additional components, such as conductive portions connecting the source electrodes of each component in vias, to provide a release path for parasitic charges accumulated in the seed layer, thereby further improving the electrical performance of the semiconductor structure. Therefore, the semiconductor structure and its manufacturing method proposed in some embodiments of the present invention have improved electronic properties and good reliability.

[0157] While the embodiments and advantages of the present invention have been disclosed above, it should be understood that any person skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of the invention. Furthermore, the scope of protection of the present invention is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Any person skilled in the art can understand, from the disclosure of some embodiments of the present invention, current or future developed processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of the present invention. Therefore, the scope of protection of the present invention includes the above-described processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of the present invention also includes combinations of various claims and embodiments.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, comprising a first region and a second region; An epitaxial layer is located above the substrate; A seed layer is located on the substrate, wherein the epitaxial layer is located on the seed layer; A first element is disposed on the first region of the substrate, the first element comprising: A first gate is located on the epitaxial layer, and a dielectric layer is formed on the epitaxial layer and covers the first gate; A first source electrode and a first drain electrode are respectively located on opposite sides of the first gate; wherein the first source electrode includes two first conductive portions that are electrically connected to each other; A first through hole is electrically connected to one of the two first conductive portions mentioned above, and the first through hole passes through the epitaxial layer and contacts the seed layer; A second element is disposed on the second region of the substrate, wherein both the first element and the second element are high electron mobility transistors, and the second element includes: A second gate is located on the dielectric layer; A second source electrode and a second drain electrode are respectively located on opposite sides of the second gate electrode, wherein the second source electrode is electrically connected to the first drain electrode; and An isolation structure is disposed on the substrate, and the epitaxial layer in the first region and the second region are isolated from each other by the isolation structure.

2. The semiconductor structure as described in claim 1, characterized in that, The second gate of the second element is electrically connected to the first source electrode of the first element.

3. The semiconductor structure as described in claim 1, characterized in that, The isolation structure extends through the epitaxial layer and contacts the top surface of the substrate.

4. The semiconductor structure as described in claim 1, characterized in that, The isolation structure penetrates the epitaxial layer and the seed layer and contacts the top surface of the substrate.

5. The semiconductor structure as described in claim 1, characterized in that, The second source electrode includes two second conductive portions that are electrically connected to each other. The second element further includes a second through hole that is electrically connected to one of the two second conductive portions, and the second through hole passes through the epitaxial layer and contacts the seed layer.

6. The semiconductor structure as described in claim 1, characterized in that, The first gate contains p-type doped gallium nitride, and the second gate contains metal or polysilicon.

7. The semiconductor structure as described in claim 1, characterized in that, The first element is an enhancement-mode high electron mobility transistor, and the second element is a depletion-mode high electron mobility transistor.

8. The semiconductor structure as described in claim 1, characterized in that, It further includes an inter-dielectric layer located on the epitaxial layer and covering the first element and the second element, wherein the inter-dielectric layer includes the dielectric layer covering the first gate and another dielectric layer covering the second gate.

9. The semiconductor structure as described in claim 1, characterized in that, Including: A third element is disposed on the second region of the substrate, the third element comprising: A third gate is located on the dielectric layer; A third source electrode and a third drain electrode are located on opposite sides of the third gate electrode, respectively. The third source electrode of the third element is electrically connected to the second drain electrode of the second element.

10. The semiconductor structure as described in claim 9, characterized in that, The third gate of the third element is electrically connected to the second source electrode of the second element.

11. The semiconductor structure as described in claim 9, characterized in that, Including: Another isolation structure is disposed on the substrate to isolate the epitaxial layers corresponding to the second element and the third element from each other.

12. The semiconductor structure as claimed in claim 9, characterized in that, The first element is an enhancement-mode high electron mobility transistor, and the second and third elements are depletion-mode high electron mobility transistors.

13. The semiconductor structure as claimed in claim 1, characterized in that, The substrate includes a base and an insulating layer disposed on the base, with the epitaxial layer located above the insulating layer.

14. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, and the substrate includes a first region and a second region; An epitaxial layer is formed on top of the substrate; A seed layer is formed on the substrate, wherein the epitaxial layer is formed on the seed layer; An isolation structure is formed on the substrate, which isolates the epitaxial layer in the first region and the second region from each other; A first element is formed on the first region of the substrate, the first element comprising: A first gate is located on the epitaxial layer, and a dielectric layer is formed on the epitaxial layer and covers the first gate; A first source electrode and a first drain electrode are respectively located on opposite sides of the first gate; wherein the first source electrode includes two first conductive portions that are electrically connected to each other; A first via is electrically connected to one of the aforementioned two first conductive portions, and the first via penetrates the epitaxial layer and contacts the seed layer; and A second element is formed on the second region of the substrate, wherein both the first element and the second element are high electron mobility transistors, and the second element includes: A second gate is located on the dielectric layer; A second source electrode and a second drain electrode are located on opposite sides of the second gate, wherein the second source electrode is electrically connected to the first drain electrode.

15. The method for manufacturing a semiconductor structure as described in claim 14, characterized in that, The second gate of the second element is electrically connected to the first source electrode of the first element.

16. The method for manufacturing a semiconductor structure as described in claim 14, characterized in that, The isolation structure extends through the epitaxial layer and contacts the top surface of the substrate.

17. The method for manufacturing a semiconductor structure as described in claim 14, characterized in that, The isolation structure penetrates the epitaxial layer and the seed layer and contacts the top surface of the substrate.

18. The method for manufacturing a semiconductor structure as described in claim 14, characterized in that, The second source electrode includes two second conductive portions that are electrically connected to each other. The second element further includes forming a second via, which is electrically connected to one of the two second conductive portions and penetrates the epitaxial layer and contacts the seed layer.

19. The method for manufacturing a semiconductor structure as described in claim 14, characterized in that, The first element is an enhancement-mode high electron mobility transistor, and the second element is a depletion-mode high electron mobility transistor.

20. The method for manufacturing a semiconductor structure as described in claim 14, characterized in that, The semiconductor structure further includes an inter-dielectric layer located on the epitaxial layer and covering the first element and the second element, wherein the inter-dielectric layer includes the dielectric layer covering the first gate and another dielectric layer covering the second gate.

21. The method for manufacturing a semiconductor structure as described in claim 14, characterized in that, Including: A third element is formed on the second region of the substrate, the third element comprising: A third gate is located on the dielectric layer; A third source electrode and a third drain electrode are located on opposite sides of the third gate electrode, respectively. The third source electrode is electrically connected to the second drain electrode.

22. The method for manufacturing a semiconductor structure as described in claim 21, characterized in that, The third gate of the third element is electrically connected to the second source electrode of the second element.

23. The method for manufacturing a semiconductor structure as described in claim 21, characterized in that, Furthermore, another isolation structure is formed on the substrate, so that the epitaxial layers corresponding to the second element and the third element are isolated from each other.

24. The method for manufacturing a semiconductor structure as described in claim 21, characterized in that, The first element is an enhancement-mode high electron mobility transistor, and the second and third elements are depletion-mode high electron mobility transistors.

Images