Semiconductor Structure and Method of Manufacturing the Same

Abstract

The semiconductor structure includes: a metal gate structure (MG) formed above a substrate; a first gate spacer formed on a first sidewall of the MG; a second gate spacer formed on a second sidewall of the MG opposite the first sidewall, wherein the second gate spacer is shorter than the first gate spacer; a source / drain (S / D) contact (MD) adjacent to the MG, wherein sidewalls of the MD are defined by the second gate spacer; and a contact component configured to electrically connect the MG to the MD. Embodiments of the present invention also relate to a method of manufacturing a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods of manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, with each generation having smaller and more complex circuits than the previous one. During the development of ICs, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometric size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling process typically provides benefits by increasing production efficiency and reducing associated costs. This scaling also increases the complexity of processing and manufacturing ICs.

[0003] For example, in memory devices (e.g., static random access memory or SRAM devices), as the component size continues to decrease, the fabrication of butt contacts and interconnect components becomes more challenging. At smaller length scales, the configuration of the butt contacts can be altered to improve the connection between the metal gate structure and the adjacent source / drain contacts. Additionally, the interconnect components formed above the butt contacts can benefit from an enlarged contact area in an effort to reduce contact resistance and increase device density. At least for these reasons, improvements in the fabrication of butt contacts and interconnect components are desired. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor structure, comprising: a metal gate structure (MG) disposed above a semiconductor substrate; a first gate spacer disposed on a first sidewall of the metal gate structure; a second gate spacer disposed on a second sidewall of the metal gate structure opposite to the first sidewall, wherein the second gate spacer is shorter than the first gate spacer; a source / drain (S / D) contact (MD) disposed adjacent to the metal gate structure, wherein a sidewall of the source / drain contact is defined by the second gate spacer; and a contact component configured to electrically connect the metal gate structure to the source / drain contact.

[0005] Another embodiment of the present invention provides a semiconductor structure, comprising: a metal gate structure disposed above a semiconductor substrate; a source / drain (S / D) component disposed adjacent to the metal gate structure; a source / drain contact (MD) disposed on the source / drain component; and a conductive component configured to contact the metal gate structure and the source / drain contact, wherein a bottom of the conductive component is embedded between a sidewall of the metal gate structure and a sidewall of the source / drain contact.

[0006] Another embodiment of the present invention provides a method of fabricating a semiconductor structure, comprising: forming a semiconductor device including a metal gate structure (MG) disposed over a semiconductor layer, gate spacers disposed on sidewalls of the metal gate structure, and source / drain (S / D) components disposed in the semiconductor layer and adjacent to the metal gate structure; forming a source / drain (S / D) contact (MD) over the source / drain components, wherein the gate spacers separate the source / drain contact from the metal gate structure; forming an interlayer dielectric (ILD) layer over the metal gate structure and the source / drain contact; forming an opening to expose the metal gate structure, the source / drain contact, and the gate spacers; removing a top portion of the gate spacers exposed to the opening; forming a metal layer over the remaining portions of the gate spacers; and planarizing the metal layer to form a contact component such that the contact component electrically couples the metal gate structure to the source / drain contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A flowchart of a method of fabricating a semiconductor device in accordance with various aspects of the present invention is shown.

[0009] Figure 2A is a three-dimensional perspective view of an embodiment of a semiconductor device in accordance with various aspects of the present invention.

[0010] Figure 2B is a top plan view of an embodiment of a semiconductor device in accordance with various aspects of the present invention.

[0011] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F , Figure 11G , Figure 12A and Figure 12B are in accordance with various aspects of the present invention at Figure 1During an intermediate step of an embodiment of the method, along line LL’ Figure 2A and / or Figure 2B Cross-sectional view of an embodiment of a semiconductor device.

[0012] Figure 13A 、 Figure 13B 、 Figure 13C 、 Figure 13D 、 Figure 13E 、 Figure 13F 、 Figure 13G 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 15C 、 Figure 15D 、 Figure 16A 、 Figure 16B 、 Figure 16C 、 Figure 16D 、 Figure 16E 、 Figure 16F and Figure 16G are, according to various aspects of the present invention, during an intermediate step of an embodiment of the method, along line MM’ Figure 1 Cross-sectional view of an embodiment of a semiconductor device. Figure 2A and / or Figure 2B Cross-sectional view of an embodiment of a semiconductor device.

[0013] Figure 17A are, according to various aspects of the present invention Figure 13G 、 Figure 14B 、 Figure 15C and / or Figure 15D Planar top view of an embodiment of a semiconductor device.

[0014] Figure 17B are, according to various aspects of the present invention Figure 16C 、 Figure 16D 、 Figure 16E and / or Figure 16F Planar top view of an embodiment of a semiconductor device. Detailed Description

[0015] Numerous different embodiments or examples are provided below for implementing the various features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of an element are not limited to the disclosed ranges or values, but may depend on the process conditions of the device and / or desired properties. Additionally, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components may not be in direct contact. Further, to facilitate the description of the relationship of one element or component to another, spatial relative terms such as "lower", "upper", "horizontal", "vertical", "above", "on top of", "below", "beneath", "upward", "downward", "top", "bottom", etc. and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.) are used. The spatial relative terms are intended to cover different orientations of the device including the components.

[0016] In addition, when describing a numerical value or numerical range with terms such as "about", "approximate", etc., the term is intended to cover values within a reasonable range including the recited value, such as within + / - 10% of the recited value or other values understood by those skilled in the art. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm. Further still, the present invention may repeat reference numerals and / or letters in the various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0017] The present invention generally relates to semiconductor devices, and more particularly to field effect transistors (FETs) such as planar FETs, three-dimensional finFETs, gate-all-around (GAA) FETs, or combinations thereof. Some embodiments of the present invention may be directed to memory devices in an IC, such as SRAM devices.

[0018] In FET fabrication, a butt contact is configured to electrically couple a metal gate structure (e.g., a high-k metal gate structure or HKMG) to a source / drain (S / D) contact. To ensure proper device performance, subsequent formed interconnect components (e.g., wires) above the butt contact are designed to be isolated from the butt contact to avoid electrical short circuits between the two components, as can be seen from a planar top view, which may limit one or more dimensions of the interconnect component. While existing methods for fabricating butt contacts and interconnect components are generally sufficient, they are not entirely satisfactory in all respects. In one example, the need to reduce the size of the butt contact to avoid short circuits may compromise the connection between the metal gate structure and the S / D contact. In another example, accommodating the separation distance between the butt contact and the interconnect component formed thereon at a small length scale may become challenging. In yet another example, an interconnect component with a reduced size may inadvertently increase the contact resistance of such a component and unnecessarily limit the performance of the device.

[0019] Figure 1 An embodiment of a method 100 for forming a semiconductor device 200 in accordance with various aspects of the present invention is shown. Method 100 is merely an example and is not intended to limit the present invention beyond what is expressly recited in the claims. Additional operations may be provided before, during, and after method 100, and for additional embodiments of the method, some of the operations described may be replaced, eliminated, or moved. The method 100 is described below in conjunction with Figures 2A to 17B describing method 100, Figures 2A to 17B shows a portion of the semiconductor device 200 during an intermediate step of method 100, wherein Figure 2A is a three-dimensional perspective view of the device 200; Figure 2B 、 Figure 17A and Figure 17B are planar top views of the device 200 as shown in Figure 2A ; Figures 3 to 12B is a cross-sectional view of the device 200 taken along the dashed line LL' as shown in Figure 2A 、 Figure 2B 、 Figure 17A and / or Figure 17B ; and Figures 13A to 16G is a cross-sectional view of the device 200 taken along the dashed line MM' as shown in Figure 2A 、 Figure 2B 、 Figure 17A and / or Figure 17B .

[0020] Device 200 can be an intermediate device fabricated during the processing of an IC or a portion thereof, which may include static random access memory (SRAM) and / or other logic circuits, passive components (such as resistors, capacitors, and inductors), and active components, such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, GAA FETs, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells. The present invention is not limited to any particular number of devices or device regions, nor to any particular device configuration. For example, although the illustrated device 200 is a three-dimensional FinFET device, embodiments for fabricating planar FET devices can also be provided by the present invention.

[0021] At operation 102, with reference to Figure 2A 、 Figure 2B and Figure 3 , method 100 provides device 200 including substrate 202 having a three-dimensional active region 204 (hereinafter referred to as fin 204) disposed thereon. Device 200 further includes: a high-k metal gate (HKMG) structure 210 disposed above fin 204, gate spacers 212 disposed on sidewalls of HKMG structure 210, S / D components 214 disposed in or above each fin 204, an isolation structure 208 disposed above substrate 202 to separate the various components of device 200; and an interlayer dielectric (ILD) layer 218 disposed above isolation structure 208 and S / D components 214. It should be noted that although two HKMG structures 210 are shown in the three-dimensional perspective view of Figure 2A , additional HKMG structures 210 may be present in device 200, such as those shown in Figures 2B to 17B .

[0022] Substrate 202 may include: elemental (single-element) semiconductors, such as silicon, germanium, and / or other suitable materials; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. Substrate 202 may be a single-layer material with a uniform composition. Optionally, substrate 202 may include multiple material layers with similar or different compositions suitable for IC device fabrication. In one example, substrate 202 may be a silicon-on-insulator (SOI) substrate having a silicon layer formed on a silicon oxide layer. In another example, substrate 202 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof.

[0023] In some embodiments where the substrate 202 includes FETs, various doped regions are formed in or on the substrate 202. Depending on the design requirements, the doped regions may be doped with an n-type dopant such as phosphorus or arsenic and / or a p-type dopant such as boron or BF2. The doped regions may be formed directly on the substrate 202, in a p-well structure, in an n-well structure, in a dual-well structure, or using a raised structure. The doped regions may be formed by implanting dopant atoms, epitaxial growth with in-situ doping, other suitable techniques, or a combination thereof.

[0024] Still referring to Figure 2A and Figure 2B and Figure 3 , the fin 204 may be adapted to form a p-type or n-type FinFET. Suitable processes including photolithography and etching processes may be used to fabricate the fin 204. The photolithography process may include forming a photoresist layer (resist) on the substrate 202, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a mask element (not shown) including the photoresist. Then, the mask element is used to etch a groove in the substrate 202, leaving the fin 204 on the substrate 202. The etching process may include dry etching, wet etching, reactive ion etching (RIE), other suitable processes, or a combination thereof.

[0025] Many other embodiments of methods for forming the fin 204 may be suitable. For example, double patterning or multiple patterning processes may be used to pattern the fin 204. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing for the generation of patterns with, for example, a pitch smaller than the pitch obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate, and the sacrificial layer is patterned using a photolithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. Then, the sacrificial layer is removed, and the remaining spacer or mandrel may then be used to pattern the fin 204.

[0026] The isolation structure 208 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectric materials, other suitable materials, or combinations thereof. The isolation structure 208 may include a shallow trench isolation (STI) component. In one embodiment, the isolation structure 208 is formed by etching trenches in the substrate 202 during the formation of the fins 204. Then, the trenches may be filled with the above isolation materials by a deposition process, followed by a chemical mechanical planarization / polishing (CMP) process. Other isolation structures (such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures) may also be implemented as the isolation structure 208. Optionally, the isolation structure 208 may include a multi-layer structure, for example, having one or more thermal oxide liner layers. The isolation structure 208 may be deposited by any suitable method, such as chemical vapor deposition (CVD), flowable CVD (FCVD), spin-on glass (SOG), other suitable methods, or combinations thereof.

[0027] Reference Figure 2A , the device 200 includes S / D components 214 disposed above the fins 204 and adjacent to the HKMG structure 210. The S / D components 214 may be formed by any suitable technique, such as an etching process followed by one or more epitaxial processes. In one example, one or more etching processes are performed to remove portions of the fins 204 to form recesses (not shown) therein. A cleaning process may be performed to clean the recesses with a hydrofluoric acid (HF) solution and / or other suitable solutions. Subsequently, one or more epitaxial growth processes are performed to grow epitaxial components in the recesses. Each S / D component 214 may be suitable for a p-type FinFET device (e.g., p-type epitaxial material), or alternatively, suitable for an n-type FinFET device (e.g., n-type epitaxial material). The p-type epitaxial material may include one or more epitaxial layers of silicon germanium (epitaxial SiGe) doped with p-type dopants such as boron, germanium, indium, and / or other p-type dopants. The n-type epitaxial material may include one or more epitaxial layers of silicon (epitaxial Si) or silicon carbide (epitaxial SiC) doped with n-type dopants such as arsenic, phosphorus, and / or other n-type dopants.

[0028] Still referring Figure 2A , Figure 2B and Figure 3, device 200 further includes at least one HKMG structure 210 disposed over a portion of fin 204 such that each HKMG structure 210 is interposed between S / D components 214 formed in each fin 204. The HKMG structure 210 may include a high-k dielectric layer (i.e., having a dielectric constant greater than that of silicon oxide; not shown) disposed over fin 204 and a metal gate electrode (not shown) disposed over the high-k dielectric layer. Although not shown herein, the metal gate electrode may further include at least one work function metal layer and a bulk conductive layer disposed over the at least one work function metal layer. The work function metal layer may be a p-type or n-type work function metal layer. Example work function materials include TiN, TaN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Ru, Mo, Al, WN, Mn, Zr, other suitable work function materials, or combinations thereof. The bulk conductive layer may include Cu, W, Ru, Al, Co, other suitable materials, or combinations thereof. The HKMG structure 210 may further include other layers (not shown), such as an interface layer, a hard mask layer, a capping layer, a barrier layer, a seed layer, other suitable layers, or combinations thereof disposed between fin 204 and the high-k dielectric layer. The various layers of the HKMG structure 210 may be deposited by any suitable method, such as chemical oxidation, thermal oxidation, atomic layer deposition (ALD), CVD, physical vapor deposition (PVD), plating, other suitable methods, or combinations thereof. A polishing process, such as CMP, may be performed to remove excess material from the top surface of the HKMG structure 210 to planarize device 200.

[0029] Device 200 further includes gate spacers 212 disposed on sidewalls of each HKMG structure 210. The gate spacers 212 may be a single-layer structure or a multi-layer structure. The gate spacers 212 may include aluminum oxide, aluminum oxynitride, hafnium oxide, titanium oxide, zirconium aluminum oxide, zinc oxide, tantalum oxide, lanthanum oxide, yttrium oxide, silicon carbonitride, tantalum carbonitride, silicon nitride, zirconium nitride, silicon carbonitride, silicon oxide, silicon carbon oxide, hafnium silicide, silicon, zirconium silicide, other suitable materials, or combinations thereof. It should be noted that the composition of the gate spacers 212 is different from that of the surrounding dielectric components such that there is an etch selectivity between the gate spacers 212 and the surrounding dielectric components during subsequent etching processes. The gate spacers 212 may be formed by first depositing a blanket layer of spacer material over device 200 and then performing an anisotropic etching process to remove portions of the spacer material to form the gate spacers 212 on the sidewalls of the HKMG structure 210.

[0030] In some embodiments, the HKMG structure 210 is formed after other components of the device 200 are fabricated, such as the S / D components 214. This process is generally referred to as a gate replacement process, which includes forming a dummy gate structure (not shown) as a placeholder for each HKMG structure 210, forming the S / D components 214 adjacent to the dummy gate structure, forming an ILD layer 218 over the dummy gate structure and the S / D components 214, planarizing the ILD layer 218 by, for example, CMP to expose the top surface of the dummy gate structure, removing the dummy gate structure in the ILD layer 218 to form a gate trench (not shown), the gate trench exposing the channel region of the fin 204, and forming the HKMG structure 210 in the gate trench to complete the gate replacement process. In some embodiments, the ILD layer 218 includes a dielectric material, such as a low-k dielectric material, tetraethyl orthosilicate (TEOS), silicon oxide, doped silicon oxide (such as borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG)), other suitable dielectric materials, or combinations thereof. The ILD layer 218 may include a multi-layer structure having multiple dielectric materials and may be formed by a deposition process such as CVD, FCVD, SOG, other suitable methods, or combinations thereof.

[0031] Reference Figure 4 and Figure 5 , method 100 forms a dielectric layer 232 over the HKMG structure 210 at operation 104. Reference Figure 4 , method 100 first removes a portion of the HKMG structure 210 to form a trench 230. In some embodiments, method 100 performs an etching process, such as a dry etching process, to form the trench 230. The etching process selectively removes the HKMG structure 210 relative to the ILD layer 218 such that the ILD layer 218 is not etched or is only minimally etched. Reference Figure 5 , method 100 then forms a dielectric layer 232 in the trench 230. In this embodiment, method 100 deposits a dielectric material by a suitable method such as CVD, FCVD, ALD, PVD, other suitable methods, or combinations thereof. The dielectric layer 232 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, hafnium oxide, other suitable materials, or combinations thereof. Thereafter, method 100 uses a suitable method such as CMP to planarize the top surface of the device 200 to expose the top surface of the ILD layer 218. In some embodiments, as Figure 5As shown, the CMP process results in the top surface of the dielectric layer 232 being substantially flush with the top surfaces of the ILD layer 218 and the gate spacers 212. In some embodiments, the dielectric layer 232 and the subsequently formed dielectric layer 242 are optional and may be omitted in the device 200.

[0032] Referring Figure 6 and Figure 7 , method 100 forms S / D contacts 220 above the S / D components 214 at operation 104. Referring Figure 6 , method 100 removes a portion of the ILD layer 218 disposed above the S / D components 214 to form trenches 234. Method 100 may implement any suitable etching process (e.g., dry etching, wet etching, RIE, etc.) to form the trenches 234. In some embodiments, the etching process is a dry etching process that uses one or more plasmas, such as C4F6, oxygen, hydrogen, other suitable gases, or combinations thereof. Referring Figure 7 , method 100 then deposits a conductive material in the trenches 234 and over a portion of the dielectric layer 232. The conductive material may include Co, W, Ru, Cu, Ta, Ti, Mo, Ni, other suitable materials, or combinations thereof. The conductive material may be deposited by any suitable method, such as CVD, PVD, ALD, plating, other suitable methods, or combinations thereof. In some embodiments, a barrier layer (not shown) is formed in the trenches 234 prior to depositing the conductive material. The barrier layer may include TiN, TaN, other suitable materials, or combinations thereof, and may be deposited by, for example, an ALD process. Thereafter, still referring Figure 7 , method 100 uses a suitable method such as CMP to planarize the conductive material to form S / D contacts 220 above the S / D components 214. In some embodiments, a portion of the conductive material formed above the dielectric layer 232 is removed by the CMP process such that the top surface of the S / D contact is substantially flush with the top surface of the dielectric layer 232.

[0033] Referring Figure 8 and Figure 9 , method 100 forms a dielectric layer 242 above the dielectric layer 232 and the HKMG structure 210. In some embodiments, referring Figure 8 , method 100 first removes a portion of the S / D contacts 220 to form trenches 240 that are disposed between the gate spacers 212. Method 100 may implement any suitable etching process (e.g., dry etching, wet etching, RIE, etc.) to form the trenches 240. In the present invention, the etching process may be a wet etching process that uses a mixture of an acid such as sulfuric acid (H2SO4) as an etchant. In some embodiments, the wet etching process is controlled by the duration of the etching process. Referring Figure 9, Method 100 then deposits a dielectric layer 242 in the trench 240 and over a portion of the dielectric layer 232 using any suitable method such as CVD, FCVD, ALD, PVD, other suitable methods, or combinations thereof. The dielectric layer 242 can include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, hafnium oxide, other suitable materials, or combinations thereof. It should be noted that in the present invention, the dielectric layer 242 has a different composition from the dielectric layer 232 such that when subjected to subsequent etching processes, they will exhibit etch selectivity, as will be discussed in detail below. Thereafter, still referring to Figure 9 , Method 100 planarizes the top surface of the device 200 to expose the top surfaces of the dielectric layer 232 and the gate spacers 212 such that the top surface of the dielectric layer 242 is substantially flush with the top surface of the dielectric layer 232.

[0034] Referring to Figure 10 , Method 100 forms an ESL 246 over the device 200 at operation 106 and then forms an ILD layer 250 (which can also be referred to as an intermetal dielectric or IMD layer) over the ESL 246. The ESL 246 can include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, hafnium oxide, other suitable materials, or combinations thereof. In some embodiments, Method 100 uses any suitable method (such as CVD, ALD, other suitable methods, or combinations thereof) to deposit the ESL 246. The ILD layer 250 can be similar to the ILD layer 218 and can be formed in a manner similar to those discussed above with respect to the ILD layer 218. Thereafter, Method 100 can continue to form an interconnect structure over the ILD layer 250 that includes: vertical interconnect components (hereinafter referred to as vias) configured to connect the HKMG structure 210 and the S / D contacts 220; and additional interconnect components such as horizontal interconnect components (hereinafter referred to as wires) and / or butt contacts (BCTs) configured to connect the HKMG structure 210 to the S / D contacts 220 of the same transistor.

[0035] Returning to the reference Figure 1, Path A including operations 108 - 114 generally illustrates the process flow for forming vias for interconnecting the HKMG structure 210 and the S / D contact 220, and path B including operations 116 - 124 generally illustrates the process flow for forming the BCT that connects the HKMG structure 210 to the S / D contact 220 of the same transistor (e.g., memory device). In this embodiment, path A will be discussed with reference to a cross-sectional view of device 200 taken along line L-L’, and path B will be discussed with reference to a cross-sectional view of device 200 taken along line M-M’, as shown respectively in Figure 2A , Figure 2B , Figure 17A and / or Figure 17B shown.

[0036] Regarding path A and with reference to Figures 11A to 11D , method 100 patterns a portion of device 200 at operation 108 to expose one of the HKMG structures 210 in trench 270 and one of the S / D contacts 220 in trench 272. In some embodiments, as shown herein, the exposed HKMG structure 210 and the exposed S / D contact 220 belong to separate transistors. With reference to Figure 11A and Figure 11B , method 100 first forms trench 270 by implementing a series of patterning and etching processes. For example, with reference to Figure 11A , method 100 first exposes mask element 264A to a radiation source (e.g., extreme ultraviolet or EUV source) through a patterned photomask, and then develops the exposed mask element 264A to form a patterned mask element 264A including an opening (corresponding to trench 270), thereby forming a patterned mask element 264A above the ILD layer 250. In some embodiments, the patterned mask element 264A at least includes a photoresist layer (not shown) disposed above one or more material layers. In one such example, the patterned mask element 264A can be a three-layer structure including a photoresist layer disposed above an intermediate layer, and the intermediate layer is disposed above an anti-reflective bottom layer. Additionally, although not shown, one or more hard mask layers can be formed between the patterned mask element 264A and the ILD layer 250 to accommodate any subsequent etching process. With reference to Figure 11B , using the patterned mask element 264A as an etch mask, method 100 then removes portions of the ILD layer 250, the ESL 246, and the dielectric layer 232 to expose the HKMG structure 210 in trench 270. Method 100 can remove portions of the ILD layer 250, the ESL 246, and the dielectric layer 232 in one or more etching processes such as a dry etching process and / or a RIE process. After that, the patterned mask element 264A is removed from device 200 by a suitable method such as photoresist stripping and / or plasma ashing.

[0037] Reference Figure 11C and Figure 11D , Method 100 forms trench 272 to expose S / D contact 220 by a series of patterning and etching processes similar to those discussed above with respect to forming trench 270. For example, method 100 first forms a patterned mask element 264B to expose portions of ILD layer 250, ESL 246, and dielectric layer 242 disposed above S / D contact 220, as a result filling trench 270. Subsequently, using patterned mask element 264B as an etch mask, portions of ILD layer 250, ESL 246, and dielectric layer 242 are removed to expose S / D contact 220. It should be noted that in terms of selecting a suitable etchant for etching dielectric layer 242, the process of forming trench 272 can be different from the process of forming trench 270, and dielectric layer 242 is different in composition from dielectric layer 232. Thereafter, patterned mask element 264B is removed from device 200 by a suitable method as described above to expose HKMG structure 210 and S / D contact 220.

[0038] Now refer to Figure 11E , Method 100 deposits conductive material 280 in trenches 270 and 272 and above portions of ILD layer 250 at operation 110. Conductive material 280 can include Co, W, Ru, Cu, Ta, Ti, Mo, Ni, other suitable materials, or combinations thereof. Conductive material 280 can be deposited by any suitable method, such as CVD, PVD, plating, other suitable methods, or combinations thereof. In some embodiments, a barrier layer (not shown) is formed in trenches 270 and 272 prior to depositing conductive material 280. The barrier layer can include TiN, TaN, other suitable materials, or combinations thereof, and can be deposited by, for example, an ALD process. Thereafter, refer to Figure 11F , Method 100 removes portions of conductive material 280 formed above ILD layer 250 at operation 112 to form via 282A above HKMG structure 210 and via 284A above S / D contact 220. In the present embodiment, method 100 performs one or more CMP processes along line AA' as shown in Figure 11E to planarize the top of device 200. As a result, as shown in Figure 11F , vias 282A and 284A can be defined by height H1.

[0039] Reference Figure 11G, Method 100 then forms an interconnect component 290 over the device 200 at operation 114. In some embodiments, the interconnect component 290 is a horizontal interconnect component, such as a wire, and the horizontal interconnect component is configured to provide routing for the vias 282A and / or 284A according to various design requirements. In this way, the interconnect component 290 electrically couples the vias 282A and / or 284A to one or more subsequently formed interconnect components. The interconnect component 290 may include Co, W, Ru, Cu, Ta, Ti, Mo, Ni, other suitable materials, or combinations thereof, and may be formed by any suitable process, such as a damascene process or a series of deposition (by plating) and patterning processes. In an exemplary embodiment, the interconnect component 290 is formed by first depositing a conductive layer over the ILD layer 250 by a suitable method such as plating, and then patterning the conductive layer using a patterned mask element to form the interconnect component 290. In some embodiments, a barrier layer (not shown) is formed over the device 200 before forming the interconnect component 290. The barrier layer may include TiN, TaN, other suitable materials, or combinations thereof, and may be deposited by, for example, an ALD process.

[0040] In some embodiments, referring back Figure 11E , method 100 optionally planarizes the top of the device 200 along line B-B' at operation 112 to form a via 282B over the HKMG structure 210 and a via 284B over the S / D contact 220, as Figure 12A shown, and thus, the ILD layer 250 and the ESL 246 are removed from the device 200. In this regard, the height H2 of the vias 282B and 284B is less than the height H1 of the vias 282A and 284A (see Figure 11F ). This reduction in height (or thickness) results in the contact resistance of the vias 282B and 284B being lower than the contact resistance of the vias 282A and 284A, respectively. Thereafter, referring Figure 12B , method 100 forms an interconnect component 290 over the vias 282B and 284B at operation 114 by a process similar to the process discussed above with reference to Figure 11G .

[0041] Now turning to path B and referring Figures 13A to 13C , method 100 patterns a portion of the device 200 at operation 116 to expose one of the HKMG structures 210 and its adjacent S / D contact 220 in the trench 274. Method 100 forms the trench 274 by a series of patterning and etching processes similar to those discussed above with respect to operation 108. For example, referring Figure 13A, Method 100 forms a patterned mask element 266A that includes an opening corresponding to the trench 274. The patterned mask element 266A can be similar in composition to the patterned mask element 246A and can be formed by a series of photolithography processes similar to those discussed above with respect to operation 108. Refer to Figure 13B , Method 100 then uses the patterned mask element 266A as an etch mask to remove portions of the ILD layer 250, the ESL 246, and the dielectric layer 232 that are exposed in the trench 274. Method 100 can remove portions of the ILD layer 250, the ESL 246, and the dielectric layer 232 in one or more etch processes such as a dry etch process and / or an RIE process. Thereafter, the patterned mask element 266A is removed from the device 200 by a suitable method such as photoresist stripping and / or plasma ashing.

[0042] Thereafter, refer to Figure 13C , Method 100 continues to pattern portions of the device 200 to expose the S / D contacts 220 that are disposed adjacent to the exposed HKMG structure 210 and the gate spacers 212 disposed therebetween. To this end, Method 100 employs a patterned mask element 266B having an opening 276 over the device 200, thereby partially filling the trench 274. In some examples, although not shown, the patterned mask element 266B can completely fill the trench 274. The patterned mask element 266B can be similar in composition to the patterned mask element 246A and can be formed by a series of photolithography processes similar to those discussed above with respect to operation 108. In the present embodiment, the opening 276 is defined by a width W that is at least equal to the width W1 from the sidewall of the S / D contact 220 to the sidewall of the gate spacer 212, but does not exceed the width W2 from the sidewall of the S / D contact 220 to the sidewall of the HKMG structure 210 that is partially exposed by the opening 276.

[0043] Using the patterned mask element 266B as an etch mask, refer to Figure 13D, Method 100 removes portions of the gate spacer 212, ILD layer 250, ESL 246, and dielectric layer 242 that are exposed in the opening 276 at operation 118. In this embodiment, Method 100 removes the exposed portions of the gate spacer 212, ILD layer 250, ESL 246, and dielectric layer 242 in one or more etching processes such as a dry etching process, a wet etching process, and / or an RIE process. In other words, after performing operation 118, the gate spacer 212A disposed on one of the sidewalls of the HKMG structure 210 (i.e., disposed between the HKMG structure 210 and the S / D contact 220 and exposed in the opening 276) is shorter than the gate spacer 212B disposed on the other sidewall of the HKMG structure 210 (i.e., not exposed in the opening 276). In this embodiment, Method 100 implements a dry etching process at operation 118, and the dry etching process utilizes a fluorine-containing etchant (e.g., CF4, SF6, CH2F2, CHF3, C2F6, other fluorine-containing etchants, or combinations thereof), H2, O2, other suitable etchants, or combinations thereof. It should be noted that the etchant for the one or more etching processes at operation 118 does not remove or substantially does not remove portions of the HKMG structure 210 and the S / D contact 220. Thereafter, still referring to Figure 13D , the patterned mask element 266B is removed from the device 200 by a suitable method such as photoresist stripping and / or plasma ashing, thereby expanding the opening 276 to fully expose the HKMG structure 210 and the S / D contact 220.

[0044] Then referring to Figure 13E , Method 100 deposits a conductive material 286 in the opening 276 and over a portion of the ILD layer 250 at operation 120. The conductive material 286 may include Co, W, Ru, Cu, Ta, Ti, Mo, Ni, other suitable materials, or combinations thereof. In some embodiments, the conductive material 286 is substantially the same as the conductive material 280. The conductive material 286 can be deposited by any suitable method, such as CVD, PVD, plating, other suitable methods, or combinations thereof. In some embodiments, the conductive material 286 is deposited by a process substantially the same as that of the conductive material 280. In some embodiments, a barrier layer (not shown) is formed in the opening 276 before depositing the conductive material 286. The barrier layer may include TiN, TaN, other suitable materials, or combinations thereof, and can be deposited by, for example, an ALD process. Thereafter, referring to Figure 13F , Method 100 planarizes the top surface of the device 200 at operation 122 to form a BCT 288A, which electrically couples the CTMG structure 210 to an adjacent S / D contact 220. In this embodiment, Method 100 is along as Figure 13EThe line AA’ shown performs one or more CMP processes to remove excessive conductive material 286 from the top surface of the ILD layer 250. Thus, as Figure 13F shown, the BCT 288A can be defined by a height H3.

[0045] Referring Figure 13G to, method 100 then forms a dielectric layer 292 over the device 200 at operation 124. Since the BCT 288A (commonly used as a docking contact) locally connects the gate (e.g., HKMG structure 210) to adjacent S / D contacts (e.g., S / D contact 220), the dielectric layer 292 is configured to isolate the BCT 288A from the interconnect components (e.g., wires) formed above it to avoid potential electrical short circuits between them. In some examples, the dielectric layer 292 can be a dielectric hard mask and can include any suitable dielectric material, such as silicon nitride, silicon carbide, silicon carbonitride, silicon oxide, silicon oxynitride, silicon carbon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, hafnium oxide, other suitable materials, or combinations thereof.

[0046] In some embodiments, referring back to Figure 13E , method 100 can optionally planarize the top of the device 200 along the line B-B’ at operation 122 to form a BCT 288B as shown in Figure 14A . As a result, the ILD layer 250 and the ESL 246 are removed from the device 200. In this regard, the height H4 of the BCT 288B is less than the height H3 of the BCT 288A as shown in Figure 13F , resulting in the BCT 288B having a lower contact resistance than the BCT 288A. However, if the top of the gate spacer 212 is not removed at operation 118 as shown by the dashed line, planarizing the device 200 along the line B-B’ will effectively split the BCT 288B into two unconnected parts, thus reducing the functionality of the BCT 288B. Therefore, removing the top of the gate spacer 212 relative to the HKMG structure 210 and the S / D contact 220 allows for reducing the height of the BCT to achieve a reduced contact resistance. Thereafter, referring to Figure 14B , method 100 forms a dielectric layer 292 over the BCT 288 at operation 124 in a process similar to the process discussed above with reference to Figure 13G .

[0047] In some embodiments, referring to Figure 15A, Method 100 further removes a portion of the gate spacer 212A at operation 118 to form an opening 294 in the opening 276 such that the top surface of the gate spacer 212A is below the top surfaces of the S / D contacts 220 and the HKMG structure 210 exposed in the opening 276. In other words, the opening 294 extends the opening 276 downward below the top surface of the HKMG structure 210 and the top surface of the S / D contacts 220. In this embodiment, Method 100 removes a portion of the gate spacer 212A without removing or substantially removing the HKMG structure 210 and the S / D contacts 220. In some embodiments, Method 100 selectively removes a portion of the gate spacer 212A in one or more etching processes such as a dry etching process, a wet etching process, and / or an RIE process. In some embodiments, the amount of the gate spacer 212A removed can be controlled by the duration of the etching process and / or the pressure of the etchant applied during the etching process. In this embodiment, the height H5 of the remaining gate spacer 212A is not limited to a specific value as long as the top surface of the remaining gate spacer 212A is below the HKMG structure 210 and the S / D contacts 220. In one such example, the height H5 can be 0, i.e., the gate spacer 212A exposed in the opening 276 can be completely removed from the device 200. Thereafter, the patterned mask element 266B is removed from the device 200 by a suitable method such as photoresist stripping and / or plasma ashing.

[0048] In some embodiments, the same etchant used to remove portions of the ILD layer 250, the ESL 246, and the dielectric layer 242 exposed in the opening 276 can be employed to form the opening 294. In other words, the opening 294 can be formed by increasing the duration of one or more etching processes used to form the opening 276. In an alternative embodiment, after forming the opening 276, a different etchant and / or a different etching process is employed to form the opening 294 as long as such an etchant does not etch or substantially does not etch portions of the HKMG structure 210 and the S / D contacts 220.

[0049] Subsequently, referring to Figure 15B , Method 100 deposits a conductive material 286 in the openings 276 and 294 in a process similar to the process discussed above with reference to Figure 13E . In this embodiment, when the conductive material 286 fills the opening 294, the conductive material 286 extends to contact the sidewalls of the HKMG structure 210 and the S / D contacts 220. Thereafter, referring to Figure 15C, Method 100 planarizes the top surface of device 200 to form BCT 288C, which electrically couples HKMG structure 210 to S / D contact 220. In this embodiment, the bottom of BCT 288C extends to contact the sidewalls of HKMG structure 210 and S / D contact 220. For embodiments where gate spacer 212 is completely removed to form opening 294, the bottom of conductive material 286 extends to contact fin 204. In other words, this embodiment provides a method of replacing at least part of gate spacer 212 with conductive material including BCT 288C. Compared with Figure 13G the BCT 288A shown in

[0050] , the bottom of BCT 288C provides an additional contact between HKMG structure 210 and S / D contact 220 to improve device performance. Figure 15B Device 200 can be planarized along the dashed line CC’ shown in Figure 15C (i.e., along the top surface of ILD layer 250) to obtain the structure shown in Figure 13G . Method 100 then forms dielectric layer 292 over BCT 288C using a process similar to the process discussed above with reference to Figure 15C . Alternatively, in the embodiment shown in Figure 15D , with reference to Figure 15B , device 200 can be planarized along the dashed line DD’ shown in

[0051] (i.e., along the top surface of dielectric layer 232 (or dielectric layer 242)) to remove ESL 246 and form BCT 288D at operation 122, and then dielectric layer 292 is formed over BCT 288D at operation 124. Similar to the comparison between BCT 288A and BCT 288B, the contact resistance of the height-reduced BCT 288D is lower than that of BCT 288C. Figure 16A, after performing operation 122, method 100 removes a portion of BCT 288A to form trench 279 such that the top surface of the remaining portion of BCT 288A is below the top surface of ILD layer 250. To this end, method 100 may form a patterned mask element 268 including an opening corresponding to trench 279. The patterned mask element 268 may be similar in composition to the patterned mask element 246A and may be formed by a series of photolithography processes similar to those discussed above with respect to operation 108. Method 100 then uses the patterned mask element 268 as an etch mask to remove a portion of BCT 288A to form trench 279. Method 100 may implement any suitable etch process, such as a dry etch process, a wet etch process, RIE, or a combination thereof, to form trench 279. For example, the etch process may be a dry etch process or RIE using a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3) as an etchant. Thereafter, the patterned mask element 268 is removed from device 200 by a suitable method, such as photoresist stripping and / or plasma ashing. In some examples where path B is employed alone, due to the compositional differences between ILD layer 250 and BCT 288A, method 100 may selectively remove the top of BCT 288A relative to ILD layer 250 in the etch process without the need to apply a patterned mask element 268. In other words, method 100 forms trench 279 in a self-aligned manner.

[0052] Reference Figure 16B , method 100 deposits a dielectric layer 296 in trench 279 and then planarizes the dielectric layer 296 in one or more CMP processes such that the top surface of the dielectric layer 296 is substantially flush with the top surface of ILD layer 250. The dielectric layer 296 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, hafnium oxide, other suitable materials, or a combination thereof. In some embodiments, the composition of the dielectric layer 296 is different from the composition of the adjacent dielectric components including ILD layer 250. Subsequently, reference Figure 16C , method 100 forms interconnect component 290 over device 200 by a process similar to the process discussed above with respect to operation 114.

[0053] As Figure 16C , Figure 16D , Figure 16E and Figure 16F shown, the dielectric layer 296 may be formed in correspondence with those respectively referenced above Figure 13G , Figure 14B , Figure 15C and Figure 15DThe various configurations of BCTs discussed above correspond to any suitable embodiments. It should be noted that in the absence of dielectric layer 296, interconnect component 290 must be electrically isolated from BCTs 288A, 288B, 288C, and 288D by dielectric layer 292. In other words, Figure 17A and Figure 17B compared to, Figure 17A Shown in Figure 13G , Figure 14B , Figure 15C or Figure 15D A plan top view of the device 200 is shown in FIG. Figure 17B Shows Figure 16C , Figure 16D , Figure 16E or Figure 16F , the presence of dielectric layer 296 allows the width of interconnect feature 290 to be expanded from T1 to T2, thereby reducing the contact resistance of interconnect feature 290. In this regard, dielectric layer 296 can essentially "bury" the BCT (e.g., BCT 288A), thereby providing greater design flexibility in the types of components formed above the BCT without causing short circuit issues. In some embodiments, the dielectric layer 296 can be used to form a plurality of BCTs, such as BCT 288A, and can be used to form a plurality of BCTs. Figure 16G and Figure 16C , a dielectric layer 292 is formed over the dielectric layer 296 instead of the interconnection feature 290. Of course, although not shown, in other configurations of the device 200, the dielectric layer 292 may be formed instead of the interconnection feature 290, such as Figure 16D , Figure 16E and / or Figure 16F Those shown in .

[0054] In the present invention, path A and path B may be implemented simultaneously or sequentially, as no particular order is required for the purposes of the present invention. For example, trenches 270 and 272, opening 276, and / or trench 279 may be formed by the same series of patterning processes (e.g., using the same photomask during exposure), filled with the same conductive material (e.g., conductive material 280 or conductive material 286) by the same deposition process, and / or planarized along line AA' (i.e., at the top surface of ILD layer 250) or along line BB' (i.e., at the top surface of dielectric layers 232 and 242) by the same CMP process as discussed in detail above.

[0055] Although not intended to be limiting, one or more embodiments of the present invention provide many benefits for semiconductor devices and their formation. For example, embodiments of the present invention provide an improved structure for a butt contact and a method of manufacturing the same, the butt contact being configured to electrically couple a gate structure to an S / D contact. In some embodiments, such a method includes removing at least a portion of a gate spacer disposed between the gate structure and the S / D contact, resulting in better contact between the butt contact, the gate structure, and the S / D contact. In some embodiments, the gate spacer is etched such that the bottom of the butt contact extends to contact the sidewalls of the gate structure and the S / D contact, thereby further enlarging the contact area between the butt contact, the gate structure, and the S / D contact. Removing at least a portion of the gate spacer may allow for a reduction in the height of the butt contact through a CMP process, thereby reducing its contact resistance without compromising the function of the butt contact. Additionally, embodiments of the present invention also provide for re-etching a portion of the butt contact and forming a dielectric layer over the etched butt contact to electrically isolate the butt contact from a conductive component subsequently formed over the butt contact. The presence of such a dielectric layer allows for the formation of an interconnect component (e.g., a wire) directly over the butt contact, thereby increasing the width and reducing the contact resistance of the interconnect.

[0056] In one aspect, the present invention provides a semiconductor structure comprising: a metal gate structure (MG) formed over a substrate; a first gate spacer formed on a first sidewall of the MG; a second gate spacer formed on a second sidewall of the MG opposite the first sidewall, wherein the second gate spacer is shorter than the first gate spacer; an S / D contact (MD) adjacent to the MG, wherein the sidewall of the MD is defined by the second gate spacer; and a contact component configured to electrically connect the MG to the MD.

[0057] In the semiconductor structure described above, wherein the top surface of the second gate spacer is below the top surface of the source / drain contact or the top surface of the metal gate structure.

[0058] In the semiconductor structure described above, wherein the top surface of the second gate spacer is flush with the top surface of the source / drain contact or the top surface of the metal gate structure.

[0059] In the semiconductor structure described above, wherein the sidewall of the contact component is aligned with the first gate spacer.

[0060] In the semiconductor structure described above, further comprising an interlayer dielectric (ILD) layer disposed over the metal gate structure, wherein the top of the contact component is disposed in the interlayer dielectric layer.

[0061] In the above semiconductor structure, there is also an interlayer dielectric (ILD) layer disposed above the metal gate structure, wherein the top of the contact component is disposed in the interlayer dielectric layer, and there is also a conductive layer disposed above the interlayer dielectric layer and a dielectric layer disposed in the interlayer dielectric layer, wherein the sidewall of the dielectric layer is continuous with the sidewall of the contact component.

[0062] In another aspect, the present invention provides a semiconductor structure, which includes: an MG formed above a substrate; an S / D component adjacent to the MG; an MD in contact with the S / D component; and a conductive component configured to be in contact with the MG and the MD, wherein the bottom of the conductive component is embedded between the sidewalls of the MG and the sidewalls of the MD.

[0063] In the above semiconductor structure, wherein the bottom of the conductive component is in contact with the semiconductor substrate.

[0064] In the above semiconductor structure, there is also included: a gate spacer disposed between the sidewall of the metal gate structure and the sidewall of the source / drain contact, such that the bottom of the conductive component is in contact with the top surface of the gate spacer.

[0065] In the above semiconductor structure, wherein the conductive component is a first conductive component, and the semiconductor structure further includes a second conductive component, wherein the second conductive component is separated from the first conductive component by a dielectric layer, and wherein the sidewall of the dielectric layer is continuous with the sidewall of the first conductive component.

[0066] In the above semiconductor structure, wherein the conductive component is a first conductive component, and the semiconductor structure further includes a second conductive component, wherein the second conductive component is separated from the first conductive component by a dielectric layer, and wherein the sidewall of the dielectric layer is continuous with the sidewall of the first conductive component, and there is also an interlayer dielectric (ILD) layer disposed between the metal gate structure and the second conductive component, wherein the sidewall of the dielectric layer is defined by the interlayer dielectric layer.

[0067] In the above semiconductor structure, there is also included an interlayer dielectric (ILD) layer disposed above the metal gate structure and a dielectric layer disposed above the interlayer dielectric layer, wherein the conductive component extends through the interlayer dielectric layer to contact the dielectric layer.

[0068] In another aspect, the present invention provides a method that includes first forming a semiconductor device having an MG formed over a semiconductor layer, forming gate spacers on sidewalls of the MG, and forming S / D components adjacent to the MG in the semiconductor layer. The method further includes: forming an MD over the S / D components, wherein the gate spacers separate the MD from the MG; forming an ILD layer over the MG and the MD; and forming an opening to expose the MG, the MD, and the gate spacers. The method then includes: removing a top portion of the gate spacers exposed to the opening; forming a metal layer over the remaining portion of the gate spacers; and planarizing the metal layer to form a contact component such that the contact component is in electrical contact with the MG and the MD.

[0069] In the above method, wherein removing the top portion of the gate spacers causes the top surface of the remaining portion of the gate spacers to be flush with the top surface of the metal gate structure and the top surface of the source / drain contact.

[0070] In the above method, wherein removing the top portion of the gate spacers causes the top surface of the remaining portion of the gate spacers to be below the top surface of the metal gate structure and the top surface of the source / drain contact.

[0071] In the above method, wherein removing the top portion of the gate spacers causes the top surface of the remaining portion of the gate spacers to be below the top surface of the metal gate structure and the top surface of the source / drain contact, wherein forming the metal layer causes the bottom of the metal layer to extend to contact the sidewalls of the metal gate structure and the sidewalls of the source / drain contact.

[0072] In the above method, wherein removing the top portion of the gate spacers causes the top surface of the remaining portion of the gate spacers to be below the top surface of the metal gate structure and the top surface of the source / drain contact, wherein planarizing the metal layer includes removing a portion of the metal layer from the top surface of the interlayer dielectric layer.

[0073] In the above method, wherein removing the top portion of the gate spacers causes the top surface of the remaining portion of the gate spacers to be below the top surface of the metal gate structure and the top surface of the source / drain contact, wherein planarizing the metal layer includes removing a portion of the metal layer from the top surface of the interlayer dielectric layer, and further includes, after planarizing the metal layer: removing the top of the contact component to form a trench; forming a dielectric layer in the trench; and forming a conductive layer over the dielectric layer such that the dielectric layer separates the conductive layer from the remaining portion of the contact component.

[0074] In the above method, wherein planarizing the metal layer includes removing the interlayer dielectric layer.

[0075] In the above method, wherein planarizing the metal layer includes removing the interlayer dielectric layer, and further includes, after planarizing the metal layer: removing the top of the contact member to form a trench; forming a dielectric layer in the trench; and forming a conductive layer above the dielectric layer such that the dielectric layer separates the conductive layer from the remaining portion of the contact member.

[0076] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also realize that such equivalent configurations do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure, comprising: A metal gate structure (MG) disposed above a semiconductor substrate; A first gate spacer disposed on a first sidewall of the metal gate structure; A second gate spacer disposed on a second sidewall of the metal gate structure opposite to the first sidewall, wherein the second gate spacer is shorter than the first gate spacer; A source / drain (S / D) contact (MD) disposed adjacent to the metal gate structure, wherein a sidewall of the source / drain contact is defined by the second gate spacer; and A contact component configured to electrically connect the metal gate structure to the source / drain contact; Wherein a bottom of the contact component is embedded between a sidewall of the metal gate structure adjacent to the source / drain contact and a sidewall of the source / drain contact adjacent to the metal gate structure, and the contact component contacts the metal gate structure and the source / drain contact.

2. The semiconductor structure according to claim 1, wherein, A top surface of the second gate spacer is below a top surface of the source / drain contact or a top surface of the metal gate structure.

3. The semiconductor structure according to claim 1, wherein The top surface of the second gate spacer is flush with the top surface of the source / drain contact or the top surface of the metal gate structure.

4. The semiconductor structure according to claim 1, wherein, A sidewall of the contact component is aligned with the first gate spacer.

5. The semiconductor structure according to claim 1 further includes an interlayer dielectric (ILD) layer disposed above the metal gate structure, wherein, A top of the contact component is disposed in the interlayer dielectric layer.

6. The semiconductor structure according to claim 5 further includes a conductive layer disposed above the interlayer dielectric layer and a dielectric layer disposed in the interlayer dielectric layer, wherein, A sidewall of the dielectric layer is continuous with a sidewall of the contact component.

7. A semiconductor structure, comprising: A metal gate structure disposed above a semiconductor substrate; A source / drain (S / D) component disposed adjacent to the metal gate structure; A source / drain contact (MD) disposed on the source / drain component; And A conductive component configured to contact the metal gate structure and the source / drain contact, wherein a bottom of the conductive component is embedded between a sidewall of the metal gate structure adjacent to the source / drain contact and a sidewall of the source / drain contact adjacent to the metal gate structure.

8. The semiconductor structure according to claim 7, wherein, The bottom of the conductive component contacts the semiconductor substrate.

9. The semiconductor structure according to claim 7 further comprises: A gate spacer disposed between a sidewall of the metal gate structure and a sidewall of the source / drain contact such that the bottom of the conductive component contacts a top surface of the gate spacer.

10. The semiconductor structure according to claim 7, wherein, The conductive component is a first conductive component, and the semiconductor structure further includes a second conductive component, wherein the second conductive component is separated from the first conductive component by a dielectric layer, and wherein a sidewall of the dielectric layer is continuous with a sidewall of the first conductive component.

11. The semiconductor structure according to claim 10 further includes an interlayer dielectric (ILD) layer disposed between the metal gate structure and the second conductive component, wherein, The sidewall of the dielectric layer is defined by the interlayer dielectric layer.

12. The semiconductor structure according to claim 7 further includes an interlayer dielectric (ILD) layer disposed above the metal gate structure and a dielectric layer disposed above the interlayer dielectric layer, wherein, The conductive component extends through the interlayer dielectric layer to contact the dielectric layer.

13. A method of manufacturing a semiconductor structure, comprising: Forming a semiconductor device, the semiconductor device including a metal gate structure (MG) disposed above a semiconductor layer, a gate spacer disposed on a sidewall of the metal gate structure, and a source / drain (S / D) component disposed in the semiconductor layer and adjacent to the metal gate structure; A source / drain (S / D) contact (MD) is formed over the source / drain component, wherein the gate spacer separates the source / drain contact from the metal gate structure; An interlayer dielectric (ILD) layer is formed over the metal gate structure and the source / drain contact; An opening is formed to expose the metal gate structure, the source / drain contact, and the gate spacer; The top of the gate spacer exposed in the opening is removed; A metal layer is formed over the remaining portion of the gate spacer; and The metal layer is planarized to form a contact component such that the contact component electrically couples the metal gate structure to the source / drain contact; wherein the contact component contacts the metal gate structure and the source / drain contact, and the bottom of the contact component is embedded between the sidewall of the metal gate structure near the source / drain contact and the sidewall of the source / drain contact near the metal gate structure.

14. The method according to claim 13, wherein, Removing the top of the gate spacer causes the top surface of the remaining portion of the gate spacer to be flush with the top surface of the metal gate structure and the top surface of the source / drain contact.

15. The method according to claim 13, wherein, Removing the top of the gate spacer causes the top surface of the remaining portion of the gate spacer to be below the top surface of the metal gate structure and the top surface of the source / drain contact.

16. The method according to claim 15, wherein, Forming the metal layer causes the bottom of the metal layer to extend to contact the sidewalls of the metal gate structure and the source / drain contact.

17. The method according to claim 13, wherein, Planarizing the metal layer includes removing a portion of the metal layer from the top surface of the interlayer dielectric layer.

18. The method according to claim 17, further comprising, after planarizing the metal layer: Removing the top of the contact component to form a trench; Forming a dielectric layer in the trench; and Forming a conductive layer over the dielectric layer such that the dielectric layer separates the conductive layer from the remaining portion of the contact component.

19. The method according to claim 13, wherein, Planarizing the metal layer includes removing the interlayer dielectric layer.

20. The method according to claim 19, further comprising, after planarizing the metal layer: Removing the top of the contact component to form a trench; Forming a dielectric layer in the trench; and Forming a conductive layer over the dielectric layer such that the dielectric layer separates the conductive layer from the remaining portion of the contact component.

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