Semiconductor device and method for forming the same

Abstract

The semiconductor device according to the present invention includes a first source / drain epitaxial component and a second source / drain epitaxial component, each of which has an external liner layer and an internal filling layer; a plurality of channel components extending between the first source / drain epitaxial component and the second source / drain epitaxial component along a first direction; and a gate structure arranged above and around the plurality of channel components. The plurality of channel components are in contact with the external liner layer and are spaced apart from the internal filling layer. The external liner includes germanium and boron, and the internal filling layer includes germanium and gallium. Embodiments of the present application also relate to methods for forming semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while their geometry (i.e., the smallest component or line that can be manufactured using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology develops to smaller technology nodes, multi-gate metal oxide semiconductor field effect transistors (multi-gate MOSFETs, or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current and reducing short channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or a portion thereof disposed on more than one side of a channel region. Fin field effect transistors (FinFETs) and multi-bridge channel (MBC) transistors are examples of multi-gate devices, which have become popular and promising candidates in high-performance and low-leakage applications. FinFETs have elevated channels surrounded by gates on multiple sides (e.g., gates surround the top and sidewalls of a semiconductor material "fin" extending from a substrate). MBC transistors have a gate structure that can extend partially or completely around a channel region to provide access to a channel region on two or more sides. Since the gate structure of an MBC transistor surrounds the channel region, an MBC transistor may also be referred to as a surround gate transistor (SGT) or a full ring gate (GAA) transistor. The channel region of the MBC transistor may be formed of nanowires, nanosheets, other nanostructures, and / or other suitable structures.

[0004] Germanium has a greater hole mobility than silicon, and research has been conducted into using germanium to form the channel member of an MBC transistor. The fact that germanium has a greater dielectric constant than silicon presents challenges. Summary of the invention

[0005] Some embodiments of the present application provide a semiconductor device, including: a first source / drain epitaxial component and a second source / drain epitaxial component, respectively including an external lining layer and an internal filling layer; a plurality of channel components extending between the first source / drain epitaxial component and the second source / drain epitaxial component along a first direction; and a gate structure arranged above and around the plurality of channel components, wherein the plurality of channel components are in contact with the external lining layer and are spaced apart from the internal filling layer, wherein the external lining layer includes germanium and a first element, and wherein the internal filling layer includes germanium and a second element different from the first element.

[0006] Other embodiments of the present application provide a semiconductor device, including: a first source / drain component, including a first external epitaxial component and a first internal epitaxial component above the first external epitaxial component; a second source / drain component, including a second external epitaxial component and a second internal epitaxial component above the second external epitaxial component; a plurality of germanium-containing channel components, extending along a first direction between the first external epitaxial component and the second external epitaxial component and contacting the first external epitaxial component and the second external epitaxial component; and a gate structure, arranged above and around the plurality of germanium-containing channel components, wherein the plurality of germanium-containing channel components are spaced apart from the first internal epitaxial component and the second internal epitaxial component, wherein the first external epitaxial component and the second external epitaxial component include a first p-type dopant, and wherein the first internal epitaxial component and the second internal epitaxial component include a second p-type dopant different from the first p-type dopant.

[0007] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a stack above a substrate, wherein the stack includes a plurality of channel layers interlaced with a plurality of sacrificial layers; forming a fin-shaped structure from the stack and the substrate, the fin-shaped structure including a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin-shaped structure; depositing a gate spacer above the dummy gate stack; recessing the source / drain region to form a source / drain trench, the source / drain trench exposing the sidewalls of the plurality of channel layers and the plurality of sacrificial layers; selectively and partially recessing the plurality of sacrificial layers recessing to form a plurality of internal spacing grooves; forming a plurality of internal spacing members in the plurality of internal spacing grooves; depositing an outer epitaxial layer in the source / drain trench, the outer epitaxial layer comprising a first p-type dopant; depositing an inner epitaxial layer over the outer epitaxial layer, the inner epitaxial layer comprising a second p-type dopant, the second p-type dopant being different from the first p-type dopant; removing the pseudo gate stack; selectively removing a plurality of sacrificial layers in the channel region; and forming a gate structure around each of a plurality of channel layers in the channel region, wherein the plurality of channel layers comprise germanium and the plurality of sacrificial layers comprise silicon germanium. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 A flow chart of a method for forming a semiconductor device according to one or more aspects of the present invention is shown.

[0010] Figures 2A-16A , Figure 2B-Figure 10B and Figure 12B-Figure 14B It is shown that according to one or more aspects of the present invention, Figure 1 A partial cross-sectional view of a workpiece during a manufacturing process of the method.

[0011] Figure 17-Figure 19 A partial cross-sectional view of a semiconductor device including transistors of different types is shown according to one or more aspects of the present invention. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Moreover, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Furthermore, when "about," "approximately," and the like are used to describe a value or a range of values, unless otherwise stated, the term is intended to cover values ​​within + / - 10% of the stated value. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm.

[0014] The present invention relates generally to multi-gate transistors and methods of fabrication, and more particularly to p-type multi-gate transistors having germanium channel components and multi-layer source / drain features for improved performance.

[0015] The multi-gate device includes a transistor whose gate structure is formed on at least two sides of the channel region. Examples of multi-gate devices include a fin field effect transistor (FinFET) having a fin structure and an MBC transistor having multiple channel components. As described above, the MBC transistor may also be referred to as an SGT, a GAA transistor, a nanosheet transistor, or a nanowire transistor. The MBC transistor includes any device in which its gate structure or a portion thereof is formed on the 4 sides of the channel region (e.g., surrounding a portion of the channel region). The MBC device according to the present invention may have a channel region, which is arranged in a nanowire channel component, a strip channel component, a nanosheet channel component, a nanostructure channel component, a cylindrical channel component, a columnar channel component, and / or other suitable channel configurations. The MBC transistor may be n-type or p-type. Although silicon channel components may be applied to p-type MBC transistors, germanium channel components are being studied because the hole mobility in germanium is about 4 times that in silicon. In addition to the channel component formation process that must be changed to accommodate germanium, the fact that the dielectric constant of germanium (about 16, while silicon is about 12) is greater than that of silicon also poses challenges. The larger dielectric constant of germanium may lead to poor short channel effects (SCE) and increased leakage. In order to address or mitigate the short channel effect, it is expected to adopt a sudden junction dopant distribution between the channel component and the source / drain component. At the same time, a high dopant concentration is required in the source / drain component to reduce parasitic resistance. If the dopant in the source / drain component is allowed to diffuse too much into the channel component, the sudden junction dopant distribution may be eliminated, resulting in worse SCE and increased leakage.

[0016] The present invention provides an embodiment of a semiconductor device, wherein its source / drain component includes an external epitaxial layer, which is engaged with a channel component, and an internal epitaxial component, which is spaced apart from the channel component. The external epitaxial layer is used as a diffusion delay layer to reduce or prevent dopants from diffusing from the internal epitaxial component into the channel component. The internal epitaxial component and the external epitaxial layer can be formed by different semiconductor layers or by semiconductor materials doped with different dopants. In one embodiment, the external epitaxial layer is formed by germanium (Ge) doped with boron (B), and the internal epitaxial component is formed by germanium (Ge) doped with gallium (Ga). In other embodiments, the germanium (Ge) in the external epitaxial layer or the internal epitaxial layer can be replaced by germanium tin (GeSn) to introduce compressive stress. Because the diffusion rate of boron in germanium is lower than that of gallium, and the activation rate of gallium in germanium is higher, the semiconductor device according to the present invention can show good short channel control and reduced parasitic resistance.

[0017] Various aspects of the present invention will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 11 is a flow chart illustrating a method 100 for forming a semiconductor device from a workpiece according to an embodiment of the present invention. The method 100 is merely an example and is not intended to limit the present invention to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. For the sake of brevity, not all steps are described in detail herein. Figures 2A-16A , Figure 2B-Figure 10B and Figure 12B-Figure 14B Describing method 100, these figures are based on Figure 1 100, a partial cross-sectional view of a semiconductor device at different manufacturing stages. To better illustrate various aspects of the present invention, each figure ends with a capital letter A, such as Figures 2A-16A , showing a partial stereoscopic view of the workpiece 200 (or semiconductor device 200) along the Y direction or the gate length direction. Each figure ends with a capital letter B, such as Figure 2B-Figure 10B and Figure 12B-Figure 14B A partial cross-sectional view of the workpiece 200 along the X direction or the channel length direction is shown. Figures 2A-16A , Figure 2B-Figure 10B and Figure 12B-Figure 14B The X, Y and Z directions are perpendicular to each other.

[0018] refer to Figure 1 , Figure 2A and Figure 2B The method 100 includes a block 102 in which a stack 204 of alternating semiconductor layers is formed over a workpiece 200. Because the workpiece 200 will be fabricated into a semiconductor device, the workpiece 200 may be referred to herein as a semiconductor device 200 as the context requires. Figure 2A and Figure 2B As shown, workpiece 200 includes substrate 202. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon substrate. As known in the art, substrate 202 may include various doping structures according to design requirements. In embodiments where the semiconductor device is p-type, an n-type doping profile (i.e., an n-type well or n-type well) may be formed on substrate 202. In some embodiments, an n-type dopant for forming an n-type well may include phosphorus (P) or arsenide (As). Suitable doping may include ion implantation and / or diffusion processes of dopants. Substrate 202 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Optionally, substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Further, substrate 202 may optionally include an epitaxial layer (epi layer), may be strained to improve performance, may include a silicon on insulator (SOI) structure or a germanium on insulator (GOI) structure, and / or may have other suitable enhancement components.

[0019] In some embodiments, stack 204 includes sacrificial layers 206 having a first semiconductor composition interleaved with channel layers 208 having a second semiconductor composition. The first semiconductor composition and the second semiconductor composition can be different. In some embodiments, epitaxial layer 206 includes silicon germanium (SiGe) and epitaxial layer 208 includes germanium (Ge). In some optional embodiments, epitaxial layer 206 and epitaxial layer 208 both include silicon germanium and the germanium content of epitaxial layer 206 is greater than the germanium content of epitaxial layer 208. Note that the three (3) layers of sacrificial layer 206 and the three (3) layers of channel layer 208 are optionally as shown in FIG. Figure 2A and Figure 2B , the drawings are for illustrative purposes only and are not intended to limit the specific contents of the claims. It is understood that any number of epitaxial layers can be formed in the stack 204. The number of layers depends on the number of channel components expected in the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0020] In some embodiments, all sacrificial layers 206 may have a substantially uniform first thickness, and all channel layers 208 may have a substantially uniform second thickness. The first thickness and the second thickness may be the same or different. As described in more detail below, the channel layer 208 or a portion thereof may be used as a channel member for a subsequently formed multi-gate device, and the thickness of each channel layer 208 is selected based on device performance considerations. The sacrificial layer 206 in the channel region may be eventually removed and used to define the vertical distance between adjacent channel regions of a subsequently formed multi-gate device, and the thickness of each sacrificial layer 206 is selected based on device performance considerations.

[0021] The layers in stack 204 may be deposited using a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. As described above, in at least some instances, sacrificial layer 206 includes an epitaxially grown silicon germanium (SiGe) layer, and channel layer 208 includes an epitaxially grown germanium (Ge) layer. In some embodiments, sacrificial layer 206 and channel layer 208 are substantially free of dopants (i.e., have a non-intrinsic dopant concentration of about 0 cm-3 to about 1×1017 cm-3), where, for example, no intentional doping is performed during the epitaxial growth process of stack 204.

[0022] refer to Figure 1 , Figure 2A and Figure 2B, method 100 includes box 104, where a fin structure 210 is formed by a stack 204 and a substrate 202. Although not shown, a hard mask layer can be deposited over the stack 204 to form an etching mask. The hard mask layer can be a single layer or a multi-layer. For example, the hard mask layer can include a pad oxide layer and a pad nitride layer, the pad nitride layer being above the pad oxide layer. The fin structure 210 can be patterned from the stack 204 and the substrate 202 using a photolithography process and an etching process. The photolithography process can include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. In some embodiments, the etching process can include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. Reference Figure 2A and Figure 2B The etching process at block 104 forms a trench that extends through the stack 204 and a portion of the substrate 202. The trench defines a fin structure 210 ( Figure 2B In some embodiments, a double patterning or multiple patterning process can be used to define a fin structure having a pitch that is, for example, smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 210 by etching the stack 204. Figure 2A and Figure 2B As shown, the fin structure 210 , together with the sacrificial layer 206 and the channel layer 208 therein, extends longitudinally along the X direction.

[0023] The isolation component 212 is formed adjacent to the fin structure 210. In some embodiments, the isolation component 212 can be formed in a trench to isolate the fin structure 210 from an adjacent active area. The isolation component 212 may also be referred to as a shallow trench isolation (STI) component 212. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202 to fill the trench with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric layer, a combination thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, and / or other suitable processes. Then, the deposited dielectric material is thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by a dry etching process, a wet etching process, and / or a combination thereof to form the STI component 212. After being recessed, the fin structure 210 rises above the STI feature 212 .

[0024] refer to Figure 1 , Figure 3A , Figure 3B , Figure 4A and Figure 4B , the method 100 includes a block 106, wherein a dummy gate stack 218 is formed above the channel region 210C of the fin structure 210. In some embodiments, a gate replacement process (or a gate-last process) is used, wherein the dummy gate stack 218 ( Figure 4A ) is used as a placeholder to withstand various processes and will be removed and replaced by a functional gate structure. Other processes and structures are also possible. Figure 4A In some embodiments shown, a dummy gate stack 218 is formed above the fin structure 210, and the fin structure 210 can be divided into a channel region 210C, which is located below the dummy gate stack 218, and a source / drain region 210SD, which is not located below the dummy gate stack 218. The channel region 210C is adjacent to the source / drain region 210SD. Figure 4A As shown, the channel region 210C is disposed between two source / drain regions 210SD.

[0025] The formation of the dummy gate stack 218 may include deposition of layers in the dummy gate stack 218 and patterning of these layers. Figure 3A and Figure 3B, a dummy dielectric layer 214, a dummy electrode layer 216, and a gate top hard mask layer 220 can be deposited over the workpiece 200. In some embodiments, the dummy dielectric layer 214 can be deposited on the fin structure 210 using a chemical vapor deposition (CVD) process, an ALD process, or other suitable process. In some instances, the dummy dielectric layer 214 can include silicon oxide. Thereafter, the dummy electrode layer 216 can be deposited over the dummy dielectric layer 214 using a CVD process, an ALD process, or other suitable process. In some instances, the dummy electrode layer 216 can include polysilicon. For patterning purposes, the gate top hard mask layer 220 can be deposited on the dummy electrode layer 216 using a CVD process, an ALD process, or other suitable process. The gate top hard mask layer 220, the dummy electrode layer 216, and the dummy dielectric layer 214 can then be patterned to form a dummy gate stack 218, such as Figure 4A As shown. For example, the patterning process may include a lithography process (e.g., photolithography or electron beam lithography), which may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, the gate top hard mask layer 220 may include a silicon oxide layer and a silicon nitride layer. Figure 4B FIG. 2 shows a cross-sectional view of the workpiece 200 viewed along the X direction at the source / drain region 210SD. Figure 4B As shown, no dummy gate stack 218 is disposed over the source / drain region 210SD of the fin structure 210 .

[0026] refer to Figure 1 , Figure 5A and Figure 5B , the method 100 includes a block 108, wherein a gate spacer layer 224 is deposited over the dummy gate stack 218. In some embodiments, the gate spacer layer 224 is conformally deposited over the workpiece 200, including over the top surface and sidewalls of the dummy gate stack 218. For ease of describing a layer having a substantially uniform thickness over various regions, the term "conformal" may be used herein. The gate spacer layer 224 may have a single layer structure or include multiple layers. Figure 5A and Figure 5B In some embodiments shown, the gate spacer layer 224 may include silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. The gate spacer layer 224 may be deposited over the dummy gate stack 218 using a process such as a CVD process, a sub-atmospheric CVD (SACVD) process, an ALD process, or other suitable process. Figure 5A and Figure 5B, the gate spacer 224 may then be etched back in an anisotropic etching process to remove the gate top hard mask layer 220 and the gate spacer 224 above the top-facing surface of the fin structure 210. That is, the etch back remains behind the gate spacer 224 along the sidewalls of the dummy gate stack 218 and exposes the top surface of the source / drain region 210SD.

[0027] refer to Figure 1 , Fig. 6A and Figure 6B , the method 100 includes a frame 110, in which the source / drain region 210SD of the fin structure 210 is recessed to form a source / drain trench 222. In some embodiments, the source / drain region 210SD not covered by the dummy gate stack 218 and the gate spacer layer 224 is etched by dry etching or a suitable etching process to form the source / drain trench 222. For example, the dry etching process can be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases, and / or plasma and / or a combination thereof. Fig. 6A In some embodiments shown, the source / drain region 210SD of the fin structure 210 is recessed to expose sidewalls of the sacrificial layer 206 and the channel layer 208. In some implementations, the source / drain trenches 222 extend into the substrate 202 below the stack 204. Figure 6B FIG. 2 shows a cross-sectional view of the workpiece 200 viewed along the X direction at the source / drain region 210SD. Figure 6B As shown, the sacrificial layer 206 and the channel layer 208 in the source / drain region 210SD are removed at block 110 , thereby exposing the substrate 202 .

[0028] refer to Figure 1 , Fig. 7A and Figure 7B , the method 100 includes block 112, in which an internal spacer feature 226 is formed. Although not explicitly shown, the operations at block 112 may include selectively and partially removing the sacrificial layer 206 to form an internal spacer recess, depositing an internal spacer material over the workpiece, and etching back the internal spacer material to form the internal spacer feature 226 in the internal spacer recess. The sacrificial layer 206 ( Fig. 6A ) is selectively and partially recessed to form an inner spacer groove (shown in Fig. 7A206 occupies the inner spacer features 226 in the channel layer 208), while the gate isolation layer 224, the exposed portion of the substrate 202, and the channel layer 208 are substantially not etched. In an embodiment where the channel layer 208 is mainly composed of germanium (Ge) and the sacrificial layer 206 is mainly composed of silicon germanium (SiGe), a selective wet etching process or a selective dry etching process can be used to selectively recess the sacrificial layer 206. An example of a selective wet etching process may include using a TMAH (tetramethylammonium hydroxide) solution, and the process temperature is between about 90° C. and about 100° C.

[0029] The internal spacer material for the internal spacer component 226 may include metal oxide, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride or low-k dielectric material. The metal oxide herein may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide or other suitable metal oxides. Although not explicitly shown, the internal spacer material may be a single layer or multiple layers. In some implementations, the internal spacer material for the internal spacer component 226 may be deposited using CVD, PECVD, SACVD, ALD or other suitable methods. The internal spacer material for the internal spacer component 226 is deposited into the internal spacer groove and above the sidewall of the channel layer 208 exposed in the source / drain trench 222. Then the deposited internal spacer material is etched back to remove the internal spacer material from the sidewall of the channel layer 208 to form the internal spacer component 226 in the internal spacer groove. In frame 112, the internal spacer material may also be removed from the top surface and / or sidewall of the gate top hard mask layer 220, the gate spacer layer 224 and the isolation component 212. In some implementations, the etch back operation performed at block 112 may include using hydrogen fluoride (HF), fluorine (F2), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), or other fluorine-based etchants. Fig. 7A As shown, each inner spacing member 226 is in direct contact with the recessed sacrificial layer 206 and is disposed between two adjacent channel layers 208 .

[0030] refer to Figure 1 , Fig. 8A and Figure 8B, the method 100 includes a block 114, wherein a first outer epitaxial component 228 is formed in the source / drain trench 222. In some implementations, the first outer epitaxial component 228 can be epitaxially grown and selectively formed from the exposed sidewalls of the channel layer 208 and the exposed surface of the substrate 202. The sidewalls of the sacrificial layer 206 remain covered by the first outer epitaxial component 228. Suitable epitaxial processes of block 114 include CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process of block 112 can use gaseous and / or liquid precursors that interact with the components of the substrate 202 and the channel layer 208. In some embodiments, the parameters of the epitaxial growth process of block 112 are selected so that the first outer epitaxial component 228 is not epitaxially deposited on the inner spacer component 226. In some examples, the first external epitaxial component 228 includes germanium (Ge) doped with a first p-type dopant. The first external epitaxial component 228 serves as a diffusion barrier, and the diffusion rate of the first p-type dopant in germanium is less than the diffusion rate of gallium (Ga). The first p-type dopant may be boron (B). In other examples, the first external epitaxial component 228 includes germanium tin (GeSn) doped with a first p-type dopant. Since the lattice constant of tin is larger than that of germanium, the germanium atoms in the germanium tin alloy (GeSn) may be subjected to compressive strain, thereby increasing hole mobility. In some implementations, the first external epitaxial component 228 may have a thickness between about 1 nm and about 6 nm, and the doping concentration of the first p-type dopant may be about 5x10 19 Atom / cm 3 About 5x10 20 Atom / cm 3 When the doping concentration of the first p-type dopant is lower than 5x10 19 Atom / cm 3 When the first outer epitaxial component 228 is 200A, the impedance in the first outer epitaxial component 228 can prevent unexpected driving current (ie, conduction current). Moreover, the solubility of the first p-type dopant in germanium can prevent the doping concentration of the first p-type dopant from exceeding 5×10 20 Atom / cm 3 .like Fig. 8A As shown, first outer epitaxial feature 228 is allowed to bond and merge over inner spacing feature 226 so that first outer epitaxial feature 228 is continuous from one channel layer 208 to another channel layer 208. First outer epitaxial feature 228 may also be referred to as first outer epitaxial layer 228 or first outer liner 228.

[0031] exist Fig. 12A and Fig. 12BIn some optional embodiments shown, the second outer epitaxial component 230 is epitaxially grown from the exposed channel layer 208 and the substrate 202 instead of the first outer epitaxial component 228, but is not bonded to merge over the inner spacing component 226. The second outer epitaxial component 230 may also be referred to as a second outer epitaxial layer 230 or a second outer liner 230. Fig. 8A and Fig. 12A As shown, one of the differences between the first outer liner 228 and the second outer liner 230 is whether to allow overgrowth of the first outer liner 228 and the second outer liner 230 to cover the inner spacing member 226 .

[0032] refer to Figure 1 , Fig.9A and Fig. 9B , the method 100 includes a block 116, wherein a first inner epitaxial component 232 is formed over the first outer epitaxial component 228. In some embodiments, the first inner epitaxial component 232 may be epitaxially and selectively formed from the first outer epitaxial component 228. Suitable epitaxial processes of block 122 include CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process at block 116 may use gaseous and / or liquid precursors that interact with the composition of the first outer epitaxial component 228. In some embodiments, the parameters of the epitaxial growth process at block 116 are selected so that the first inner epitaxial component 232 is not epitaxially grown from the inner spacing component 226 even though the first inner epitaxial component 232 may overgrow to cover or contact the inner spacing component 226. In some examples, the first inner epitaxial component 232 includes germanium (Ge) doped with a second p-type dopant, which is different from the first p-type dopant. The first inner epitaxial component 232 is used as a low resistance layer (or a high conductivity layer), and the second p-type dopant has a larger dopant activation energy level in germanium than in boron (B). Here, the higher dopant activation energy level leads to reduced resistance and increased conductivity. The second p-type dopant can be gallium (Ga). In other examples, the first inner epitaxial component 232 includes germanium tin (GeSn) doped with a second p-type dopant. Since the lattice constant of tin is larger than that of germanium, the germanium atoms in the germanium tin alloy (GeSn) may be subjected to compressive strain, thereby increasing hole mobility. In some embodiments, the first inner epitaxial component 232 may have a thickness between about 1nm and about 6nm, and the doping concentration of the second p-type dopant may be about 3x10 20 Atom / cm 3 About 1x10 21 Atom / cm 3When the doping concentration of the second p-type dopant in the first inner epitaxial part 232 is lower than 3×10 20 Atom / cm 3 When the first inner epitaxial component 232 is less than 1×10 , the first inner epitaxial component 232 may not be sufficiently conductive to achieve a satisfactory drive current (ie, on-current). In addition, the solubility of the second p-type dopant in germanium may prevent the doping concentration of the second p-type dopant from exceeding 1×10 21 Atom / cm 3 .exist Fig.9A and Fig. 9B In some embodiments shown, the first inner epitaxial component 232 is separated or spaced apart from the channel layer 208, the inner spacer component 226, and the substrate 202 by the first outer epitaxial component 228. The first inner epitaxial component 232 may also be referred to as a first inner epitaxial layer 232 or a first inner filler 232. The first outer epitaxial component 228 and the first inner epitaxial component 232 may be collectively regarded as a first source / drain component 2310 disposed above the source / drain region 210SD.

[0033] Note that both boron (B) and gallium (Ga) are elements found in group IIIA of the element table. The atomic mass (or atomic weight) of boron (B) is 10.811u, and the atomic mass (or atomic weight) of gallium (Ga) is 67.723u. The atomic mass of gallium (Ga) is greater than the atomic mass of boron (B).

[0034] exist Fig.13A and Fig. 13B In some optional embodiments shown, when the second outer epitaxial component 230 is implemented in block 114, block 116 of method 100 can deposit the second inner epitaxial component 234 above the second outer epitaxial component 230. Fig.13A As shown, the second inner epitaxial component 234 may be in contact with the inner spacing component 226, but may be spaced apart from the channel layer 208 by the second outer epitaxial component 230. The second inner epitaxial component 234 may also be referred to as a second inner epitaxial layer 234 or a second inner filling paste 234. The second outer epitaxial component 230 and the second inner epitaxial component 234 may be collectively regarded as a second source / drain component 2320 disposed above the source / drain region 210SD. Fig.9A and Fig.13A As shown, one of the differences between the first inner filling glue 232 and the second inner filling glue 234 is that the second inner filling glue 234 is allowed to contact the inner spacer component 226, but the first inner filling glue 232 is not allowed. The second outer epitaxial component 230 and the second inner epitaxial component 234 can be collectively regarded as a second source / drain component 2320, which is disposed above the source / drain region 210SD.

[0035] Although not in Fig.9A , Fig. 9B , Fig.13A or Fig. 13B , in some optional embodiments, a top epitaxial component can be deposited above the first inner epitaxial component 232 or the second inner epitaxial component 234. In these optional embodiments, the top epitaxial component can have a similar composition to the first inner epitaxial component 232 or the second inner epitaxial component 234, but have a greater doping concentration than the first inner epitaxial component 232 or the second inner epitaxial component 234. The top epitaxial component can be used to further reduce contact resistance.

[0036] According to aspects of the present invention, first outer epitaxial feature 228 or second outer epitaxial feature 230 doped with a first p-type dopant acts as a diffusion barrier to prevent or block diffusion of a second p-type dopant, such as gallium (Ga), from first inner epitaxial feature 232 or second inner epitaxial feature 234 into channel layer 208 and substrate 202. Gallium has a higher diffusion rate in germanium than boron and is more likely to compromise short channel control and cause leakage.

[0037] refer to Figure 1 , Fig. 10A , Fig. 10B , Fig.14A and Fig. 14B , the method 100 includes a block 118, wherein the workpiece 200 is annealed in an annealing process 300 to activate the first p-type dopant and the second p-type dopant. In some implementations, the annealing process 300 may include a rapid thermal annealing (RTA) process, a laser pulse annealing process, a rapid annealing process, or a furnace annealing process. The annealing process 300 may include a peak annealing temperature between about 900° C. and about 1000° C. In these implementations, the peak annealing temperature may be maintained for a duration measured in seconds or microseconds. Through the annealing process 300, a desired electron contribution may be obtained from the first p-type dopant and the second p-type dopant in a semiconductor body, such as germanium (Ge) or germanium tin (GeSn). The annealing process 300 may generate vacancies that promote the movement of the first p-type dopant and the second p-type dopant from interstitial positions to alternative lattice positions and reduce damage or defects in the lattice of the semiconductor body.

[0038] refer to Figure 1 , Fig.11A and Fig.15AThe method 100 includes block 120, wherein further processing is performed. Such further processing may include, for example, depositing a contact etch stop layer (CESL) 236 over the workpiece 200, depositing an interlayer dielectric layer (ILD) 238 over the CESL 236, removing the dummy gate stack 218, selectively removing the sacrificial layer 206 in the channel region 210C to release the channel layer 208 as a channel member, forming a gate structure 250 over the channel region 210C, forming source / drain contact openings through the CESL 236 and the ILD layer 238, forming a germanide feature 240 and a source / drain contact 242. Now referring to Fig.11A and Fig.15A , a CESL 236 is formed before forming the ILD layer 238. In some examples, the CESL 236 includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art. The CESL 236 may be formed by an ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. Then, the ILD layer 238 is deposited over the CESL 236. In some embodiments, the ILD layer 238 includes a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), doped silica glass (BSG), and / or other suitable dielectric materials. The ILD layer 238 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 238, the workpiece 200 may be annealed to improve the integrity of the ILD layer 238. Reference Fig.11A and Fig.15A , the CESL 236 may be disposed directly on the top surface of the first inner epitaxial feature 232 or the second inner epitaxial feature 234 .

[0039] After the deposition of the CESL 236 and the ILD layer 238, the workpiece 200 may be planarized by a planarization process to expose the dummy gate stack 218 (at Fig. 10A and Fig.14A). For example, the planarization process may include a chemical mechanical planarization (CMP) process. The exposure of the dummy gate stack 218 allows the removal of the dummy gate stack 218 and the release of the channel layer 208. In some embodiments, the removal of the dummy gate stack 218 results in a gate trench above the channel region 210C. The removal of the dummy gate stack 218 may include one or more etching processes that are selective to the material of the dummy gate stack 218. For example, the removal of the dummy gate stack 218 may be performed using a selective wet etch, a selective dry etch, or a combination thereof that is selective to the dummy gate stack 218. After removing the dummy gate stack 218, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 210C are exposed in the gate trench.

[0040] After removing the dummy gate stack 218, the method 100 may include an operation for selectively removing the sacrificial layer 206 between the channel layers 208 in the channel region 210C. The selective removal of the sacrificial layer 206 releases the channel layer 208 to form the channel member 208. Note that for simplicity, the same reference numeral 208 is used to represent the channel member 208. The selective removal of the sacrificial layer 206 may be achieved by selective dry etching, selective wet etching, or other selective etching processes. An example of a selective wet etching process may include using a TMAH (tetramethylammonium hydroxide) solution, and the process temperature is between about 90°C and about 100°C.

[0041] The method 100 may include a further operation to form a gate structure 250 to surround each released channel layer 208. In some embodiments, the gate structure 250 is formed within the gate trench and into the space left by removing the sacrificial layer 206. In this aspect, the gate structure 250 surrounds each channel member 208. In various embodiments, the gate structure 250 includes an interfacial layer 252, a high-K gate dielectric layer 254 formed over the interfacial layer 252, and / or a gate electrode layer 256 formed over the high-K gate dielectric layer 254. As used and described herein, a high-K dielectric material includes a dielectric material having a high dielectric constant, such as a dielectric constant greater than that of thermal silicon oxide.

[0042] In some embodiments, the interfacial layer 252 of the gate structure 250 may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interfacial layer 252 may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-K gate dielectric layer 254 of the gate structure 250 may include hafnium oxide. Optionally, the high-K gate dielectric layer 254 of the gate structure 250 may include other high-K dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3, silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The high-K gate dielectric layer 254 may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0043] The gate electrode layer 256 of the gate structure 250 may include a single layer or a multi-layer structure, such as various combinations of metal layers with selected work functions to enhance device performance (work function metal layers), liner layers, wetting layers, adhesion layers, metal alloys, or metal silicides. For example, the gate electrode layer 256 of the gate structure 250 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer 256 of the gate structure 250 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In addition, gate electrode layers 256 may be formed separately for N-FET and P-FET transistors, which may use different metal layers (e.g., to provide different n-type and p-type work function metal layers). In various embodiments, a CMP process may be performed to remove excess metal, thereby providing a substantially flat top surface of the gate structure 250. The gate structure 250 includes a portion interposed between the channel members 208 in the channel region 210C.

[0044] In order to form Fig.11A The first source / drain feature 2310 or Fig.15A To electrically connect the second source / drain feature 2320 as shown, a source / drain opening is first formed through the ILD layer 238 and the CESL 236 to expose the first source / drain feature 2310 or the second source / drain feature 2320. A metal is then deposited over the exposed first source / drain feature 2310 or the second source / drain feature 2320. The workpiece 200 is annealed to induce a germanidation reaction between the deposited metal and the first source / drain feature 2310 or the second source / drain feature 2320 to form a germanide feature 240. In some implementations, the metal used for germanidation may include titanium, tantalum, nickel, cobalt, or tungsten, and the germanide feature 240 may include titanium germanide, tantalum germanium, nickel germanide, cobalt germanide, or tungsten germanide. After forming the germanide feature 240, tungsten (W), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Cu) may be deposited in the source / drain openings and planarized to form source / drain contacts 242. In some embodiments, a barrier layer may be deposited in the source / drain openings before depositing the source / drain contacts 242. Examples of barrier layers may include titanium nitride, tantalum nitride, titanium silicon nitride, or cobalt nitride.

[0045] like Fig.11A and Fig.15A As shown, a semiconductor device 200 is basically formed. Fig.11A , the semiconductor device 200 includes two first source / drain features 2310, a channel feature 208 extending between the two first source / drain features 2310, and a gate structure 250 surrounding each channel feature 208. The channel members 208 are also interleaved with internal spacing features 226. The internal spacing features 226 isolate the gate structure 250 from the two first source / drain features 2310. Each first source / drain feature 2310 includes a first outer epitaxial feature 228 and a first inner epitaxial feature 232. The channel member 208 is coupled to the first outer epitaxial feature 228, but is spaced apart from the first inner epitaxial feature 232. The first outer epitaxial feature 228 merges over the inner spacing features 226 and isolates the inner spacing features 226 from the first inner epitaxial feature 232. The first outer epitaxial component 228 serves as a diffusion barrier to prevent the second p-type dopant in the first inner epitaxial component 232 from diffusing into the channel member 208 or the substrate 202. As described above, the first p-type dopant in the first outer epitaxial component 228 may include boron (B), and the second p-type dopant in the first inner epitaxial component 232 may include gallium (Ga). The semiconductor device 200 is p-type. According to the size of the channel member 208, Fig.11AThe semiconductor device 200 in FIG. 2 may be referred to as a p-type MBC transistor, a p-type GAA transistor, a p-type SGT, a p-type nanowire transistor, and a p-type nanosheet transistor.

[0046] First reference Fig.15A , the semiconductor device 200 includes two second source / drain features 2320, a channel feature 208 extending between the two second source / drain features 2320, and a gate structure 250 surrounding each channel feature 208. The channel members 208 are also interleaved with internal spacing features 226. The internal spacing features 226 isolate the gate structure 250 from the two second source / drain features 2320. Each second source / drain feature 2320 includes a second outer epitaxial feature 230 and a second inner epitaxial feature 234. The channel member 208 is coupled to the second outer epitaxial feature 230, but is spaced apart from the second inner epitaxial feature 234. The second outer epitaxial feature 230 is not merged above the internal spacing features 226, and the internal spacing features 226 may be in contact with the second inner epitaxial feature 234. The second outer epitaxial component 230 serves as a diffusion barrier to prevent the second p-type dopant in the second inner epitaxial component 234 from diffusing into the channel member 208 or the substrate 202. As described above, the first p-type dopant in the second outer epitaxial component 230 may include boron (B), and the second p-type dopant in the second inner epitaxial component 234 may include gallium (Ga). The semiconductor device 200 is p-type. According to the size of the channel member 208, Fig.11A The semiconductor device 200 in FIG. 2 may be referred to as a p-type MBC transistor, a p-type GAA transistor, a p-type SGT, a p-type nanowire transistor, and a p-type nanosheet transistor.

[0047] exist Fig.16A In some alternative embodiments shown, although the second outer epitaxial features 230 are not merged over the inner spacing features 226, some lower outer epitaxial features 2300 are merged. This may be due to epitaxial growth from the exposed surface of the substrate 202. In these alternative embodiments, the lower outer epitaxial features 230 can be disposed over the inner spacing features 226 near the bottom surface of the gate structure 250.

[0048] Fig.17 , Fig.18 and Fig.19 An embodiment is shown, in which Fig.11A , Fig.15A and Fig.16A The p-type MBC transistor 200 and the n-type MBC transistor 300 are shown fabricated on a workpiece 400 to form a semiconductor device. Fig.17 , Fig.18 and Fig.19As shown, the n-type MBC transistor 300 shares a similar structure with the p-type MBC transistor 200 except for the n-type epitaxial component 310, the n-type gate structure 350 and the n-type channel member 308. Therefore, for the sake of simplicity, a detailed description of the n-type MBC transistor 300 is omitted. In some embodiments, the n-type channel member 308 is formed of silicon, and germanium is unintentionally included in the n-type channel member 308. The n-type gate structure 350 includes an n-type work function layer, while the gate structure 250 includes a p-type work function layer. Fig.11A , Fig.15A and Fig.16A Unlike the illustrated embodiment, the n-type epitaxial component does not have an internal filler / external liner structure and may include only a single n-type dopant species, such as phosphorus (P). In some implementations, the n-type epitaxial component may include a lower portion and an upper portion, the upper portion being above the lower portion. In these implementations, both the lower portion and the upper portion are doped with the same n-type dopant, but the upper portion may be more heavily doped than the lower portion.

[0049] Although not intended to be limiting, one or more embodiments of the present invention provide many benefits to semiconductor devices and their formation. For example, an embodiment of the present invention provides a p-type transistor, including a vertical stack of germanium channel components, which extend between two source / drain components. Each source / drain component includes an external epitaxial component and an internal epitaxial component. The germanium channel component is coupled to the external epitaxial component, but is spaced apart from the internal epitaxial component. The external epitaxial component includes a first p-type dopant, and the internal epitaxial component includes a second p-type dopant. The diffusion rate of the first p-type dopant in the germanium is less than the diffusion rate of the second p-type dopant in the germanium. The dopant activation energy level of the second p-type dopant in the germanium is greater than the dopant activation energy level of the first p-type dopant in the germanium. The external epitaxial component acts as a diffusion barrier to ensure abrupt junction dopant distribution, thereby improving short channel control and reducing leakage. The internal epitaxial component can reduce parasitic resistance.

[0050] In one exemplary aspect, the present invention relates to a semiconductor device. The semiconductor device includes a first source / drain epitaxial component and a second source / drain epitaxial component, each component including an external liner and an internal filling layer, a plurality of channel components extending between the first source / drain epitaxial component and the second source / drain epitaxial component along a first direction, and a gate structure disposed above and around the plurality of channel components. The plurality of channel components are in contact with the external liner and are spaced apart from the internal filling layer. The external liner includes germanium and a first element, and the internal filling layer includes germanium and a second element, the second element being different from the first element.

[0051] In some embodiments, the first element and the second element are located in Group IIIA of the periodic table. In some implementations, the atomic weight of the second element is greater than the atomic weight of the first element. In some implementations, at least one of the outer liner layer and the inner fill layer further comprises tin. In some embodiments, the semiconductor device may further comprise a plurality of inner spacer components, and the plurality of channel members are interlaced with the plurality of inner spacer components along a second direction perpendicular to the first direction. In some embodiments, the outer liner layer is merged above the plurality of inner spacer components, and the plurality of inner spacer components are spaced from the inner fill layer. In some instances, the outer liner layer is not merged above the plurality of inner spacer components, and the plurality of inner spacer components are in contact with the inner fill layer. In some embodiments, the outer liner layer comprises approximately 5x10 19 Atom / cm 3 About 5x10 20 Atom / cm 3 In some implementations, the inner fill layer includes about 3x10 20 Atom / cm 3 About 1x10 21 Atom / cm 3 The gallium doping concentration is between .

[0052] In another exemplary aspect, the present invention relates to a semiconductor device. The semiconductor device includes a first source / drain component, which includes a first outer epitaxial component and a first inner epitaxial component, the first inner epitaxial component is above the first outer epitaxial component, a second source / drain component, which includes a second outer epitaxial component and a second inner epitaxial component, the second inner epitaxial component is above the second outer epitaxial component, a plurality of germanium-containing channel components, which extend between the first outer epitaxial component and the second outer epitaxial component along a first direction and contact the first outer epitaxial component and the second outer epitaxial component; and a gate structure, which is disposed above and around the plurality of germanium-containing channel components. The plurality of germanium-containing channel components are spaced apart from the first inner epitaxial component and the second inner epitaxial component. The first inner epitaxial component and the second inner epitaxial component include a second p-type dopant, and the second p-type dopant is different from the first p-type dopant.

[0053] In some embodiments, the diffusion rate of the first p-type dopant in germanium is less than the diffusion rate of the second p-type dopant in germanium. In some embodiments, the conductivity of the first inner epitaxial component and the second inner epitaxial component is greater than the conductivity of the first outer epitaxial component and the second outer epitaxial component. In some implementations, the first outer epitaxial component and the second outer epitaxial component include germanium, and the first p-type dopant is boron, and the first inner epitaxial component and the second inner epitaxial component include germanium, and the second p-type dopant is gallium. In some implementations, at least one of the first outer epitaxial component and the second outer epitaxial component includes a plurality of parts separated from each other. In some instances, the semiconductor device may further include a top epitaxial component disposed on the first inner epitaxial component. In some embodiments, a plurality of germanium-containing channel members are spaced apart from each other by a plurality of inner spacing components along a second direction perpendicular to the first direction, and the first inner epitaxial component and the second inner epitaxial component are in contact with the plurality of inner spacing components. In some examples, the plurality of germanium-containing channel members are spaced apart from each other by a plurality of inner spacing members along a second direction perpendicular to the first direction, and the first and second inner epitaxial components are spaced apart from the plurality of inner spacing components along the first direction by the first and second outer epitaxial components, respectively.

[0054] In yet another exemplary aspect, the present invention relates to a method. The method includes forming a stack above a substrate, the stack including a plurality of channel layers, the plurality of channel layers being interlaced with a plurality of sacrificial layers, forming a fin-like structure from the stack and the substrate, the fin-like structure including a channel region and a source / drain region, forming a dummy gate stack above the channel region of the fin-like structure, depositing a gate isolation layer above the dummy gate stack, recessing the source / drain region to form a source / drain trench, the source / drain trench exposing sidewalls of the plurality of channel layers and the plurality of sacrificial layers, selectively and partially recessing the plurality of sacrificial layers, The invention relates to a method for forming a gate structure of a semiconductor device and a semiconductor device. The method comprises recessing a sacrificial layer to form a plurality of inner spacer grooves, forming a plurality of inner spacer members in the plurality of inner spacer grooves, depositing an outer epitaxial layer in the source / drain trenches, the outer epitaxial layer comprising a first p-type dopant, depositing an inner epitaxial layer over the outer epitaxial layer, the inner epitaxial layer comprising a second p-type dopant different from the first p-type dopant, removing the dummy gate stack, selectively removing the plurality of sacrificial layers in the channel region, and forming a gate structure around each of the plurality of channel layers in the channel region. The plurality of channel layers comprise germanium, and the plurality of sacrificial layers comprise silicon germanium.

[0055] In some embodiments, the first p-type dopant includes boron and the second p-type dopant includes gallium. In some implementations, depositing the outer epitaxial layer includes depositing the outer epitaxial layer over the plurality of inner spacer features.

[0056] The foregoing summarizes the features of several embodiments so that those of ordinary skill in the art can better understand the various aspects of the present invention. It will be appreciated by those skilled in the art that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. It will also be appreciated by those skilled in the art that this equivalent construction does not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: A first source / drain epitaxial component and a second source / drain epitaxial component, each comprising an outer liner layer and an inner fill layer; a plurality of channel members extending along a first direction between the first source / drain epitaxial component and the second source / drain epitaxial component; as well as a gate structure disposed above and around the plurality of channel components, wherein the plurality of channel members are in contact with the outer liner layer and are spaced apart from the inner filling layer, wherein the outer liner layer comprises germanium and a first element, The inner filling layer includes germanium and a second element different from the first element, and the first element and the second element are in Group IIIA of the periodic table.

2. The semiconductor device according to claim 1, wherein The first element has a lower diffusion rate in germanium than the second element.

3. The semiconductor device according to claim 1, wherein The atomic weight of the second element is greater than the atomic weight of the first element.

4. The semiconductor device according to claim 1, wherein: At least one of the outer liner layer and the inner fill layer further includes tin.

5. The semiconductor device according to claim 1, further comprising: A plurality of interior spacing components, wherein the plurality of channel members are staggered with the plurality of interior spacing components along a second direction perpendicular to the first direction.

6. The semiconductor device according to claim 5, wherein: The outer liner layer is merged over the plurality of inner spacing members, and the plurality of inner spacing members are spaced apart from the inner filling layer.

7. The semiconductor device according to claim 5, wherein: The outer liner layer is not merged over the plurality of inner spacing members, and the plurality of inner spacing members are in contact with the inner filling layer.

8. The semiconductor device according to claim 1, wherein The outer liner layer includes 5x10 19 Atom / cm 3 Up to 5x10 20 Atom / cm 3 The boron doping concentration is between .

9. The semiconductor device according to claim 1, wherein: The internal filling layer includes 3x10 20 Atom / cm 3 Up to 1x10 21 Atom / cm 3 The gallium doping concentration is between .

10. A semiconductor device comprising: a first source / drain feature including a first outer epitaxial feature and a first inner epitaxial feature over the first outer epitaxial feature; a second source / drain feature including a second outer epitaxial feature and a second inner epitaxial feature over the second outer epitaxial feature; a plurality of germanium-containing channel members extending along a first direction between and in contact with the first outer epitaxial component and the second outer epitaxial component; as well as a gate structure disposed above and around the plurality of germanium-containing channel components, wherein the plurality of germanium-containing channel members are spaced apart from the first inner epitaxial feature and the second inner epitaxial feature, wherein the first outer epitaxial component and the second outer epitaxial component include a first p-type dopant, Wherein, the first inner epitaxial component and the second inner epitaxial component include a second p-type dopant different from the first p-type dopant.

11. The semiconductor device according to claim 10, wherein: A diffusion rate of the first p-type dopant in germanium is less than a diffusion rate of the second p-type dopant in germanium.

12. The semiconductor device according to claim 10, wherein: The electrical conductivity of the first inner epitaxial component and the second inner epitaxial component is greater than the electrical conductivity of the first outer epitaxial component and the second outer epitaxial component.

13. The semiconductor device according to claim 10, in, the first outer epitaxial feature and the second outer epitaxial feature include germanium, and the first p-type dopant is boron, Wherein, the first inner epitaxial component and the second inner epitaxial component include germanium, and the second p-type dopant is gallium.

14. The semiconductor device according to claim 13, wherein: At least one of the first outer epitaxial member and the second outer epitaxial member includes a plurality of portions separated from each other. 15 . The semiconductor device of claim 10 , further comprising a top epitaxial feature disposed on the first inner epitaxial feature.

16. The semiconductor device according to claim 10, in, The plurality of germanium-containing channel members are spaced apart from one another along a second direction perpendicular to the first direction by a plurality of internal spacing features, and Wherein, the first inner epitaxial component and the second inner epitaxial component are in contact with the plurality of inner spacing components.

17. The semiconductor device according to claim 10, in, The plurality of germanium-containing channel members are spaced apart from one another along a second direction perpendicular to the first direction by a plurality of internal spacing features, and The first inner epitaxial component and the second inner epitaxial component are respectively separated from the plurality of inner spacing components by the first outer epitaxial component and the second outer epitaxial component along a first direction.

18. A method of forming a semiconductor device, comprising: forming a stack above the substrate, wherein the stack includes a plurality of channel layers interleaved with a plurality of sacrificial layers; forming a fin structure by the stack and the substrate, the fin structure comprising a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin structure; depositing a gate spacer over the dummy gate stack; recessing the source / drain region to form a source / drain trench, the source / drain trench exposing sidewalls of the plurality of channel layers and the plurality of sacrificial layers; selectively and partially recessing the plurality of sacrificial layers to form a plurality of inner spaced grooves; forming a plurality of internal spacing members in the plurality of internal spacing grooves; depositing an outer epitaxial layer in the source / drain trench, the outer epitaxial layer comprising a first p-type dopant; depositing an inner epitaxial layer over the outer epitaxial layer, the inner epitaxial layer comprising a second p-type dopant different from the first p-type dopant; removing the dummy gate stack; selectively removing the plurality of sacrificial layers in the channel region; and forming a gate structure around each of the plurality of channel layers in the channel region, The plurality of channel layers include germanium, and the plurality of sacrificial layers include silicon germanium.

19. The method according to claim 18, wherein: The first p-type dopant includes boron, and the second p-type dopant includes gallium.

20. The method according to claim 18, wherein: The depositing of the outer epitaxial layer includes depositing the outer epitaxial layer over the plurality of inner spacer features.

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