A calibration method and circuit structure of a Bluetooth clock

Abstract

The present invention relates to the field of Bluetooth technology, and in particular to a calibration method and circuit structure of a Bluetooth clock, the method comprising: calculating a high-frequency, high-precision, high-power consumption digital clock cycle corresponding to N low-frequency, low-precision, low-power consumption digital clock cycles through a calculation module, taking an average value and storing it in a register; Bluetooth devices interact with each other at regular intervals to implement the operation of sending and receiving packets, and during the interval between two interactions, the Bluetooth device enters a sleep state when there is no other task to be performed, the Bluetooth clock of the Bluetooth system stops when it is in the sleep state, and the sleep time is recorded using a low-frequency, low-precision, low-power consumption digital clock; the Bluetooth device automatically triggers a calculation module when it enters an activated state from the sleep state, calculates the absolute time corresponding to this sleep time, and compensates the absolute time to the Bluetooth clock. The present invention improves the accuracy of the Bluetooth clock and greatly reduces the power consumption of the Bluetooth chip in the sleep stage.

Description

Technical Field

[0001] The present invention relates to the technical field of Bluetooth, and in particular to a calibration method and circuit structure of a Bluetooth clock. Background Art

[0002] As a wireless link technology, Bluetooth has developed rapidly in the past decade, and the product forms have become more and more diverse. People have higher and higher requirements for the user experience of Bluetooth products, that is, they require stable links and long battery life. Each Bluetooth unit has an internal system clock, which determines the timing and frequency hopping of the transmitter and receiver. Therefore, maintaining the accuracy of the Bluetooth clock is of great significance to the stability of the Bluetooth link, but the power consumption paid in maintaining the accuracy of the Bluetooth clock is as low as possible to extend the battery life. The existing technology uses a low-frequency, low-precision, and low-power digital clock in the sleep state of the Bluetooth chip, which can consume very low power, but it is difficult to maintain the accuracy of the Bluetooth clock. If a high-frequency, high-precision, and high-power digital clock is used to ensure the accuracy of the Bluetooth clock, it will inevitably lead to a decrease in the battery life of the Bluetooth device. Summary of the invention

[0003] In order to solve the above problems, the present invention provides a calibration method and circuit structure of a Bluetooth clock.

[0004] The present invention provides a Bluetooth clock calibration method, comprising the following steps:

[0005] S1. For a Bluetooth device that is powered on for the first time, a hardware-specific circuit is used to calculate a high-frequency, high-precision, high-power consumption digital clock cycle corresponding to N low-frequency, low-precision, low-power consumption digital clock cycles. To reduce errors, the above operation is performed multiple times, and the average value of the corresponding high-frequency, high-precision, high-power consumption digital clock cycles is taken. The average value is saved in the third register as a global variable of the software.

[0006] S2. The link of the Bluetooth device interacts once at regular intervals to implement the operations of sending and receiving packets. During the interval between two interactions, if the Bluetooth device has no other tasks to perform, the Bluetooth device will enter a sleep state to ensure a long battery life. When the Bluetooth system is in a sleep state, the Bluetooth clock will stop. At this time, the system will run under a low-frequency, low-precision, and low-power digital clock. The period of this clock is used as a measure of the sleep time of the Bluetooth device, that is, a low-frequency, low-precision, and low-power digital clock is used to record the sleep time of the Bluetooth device.

[0007] S3. During the sleep process of the Bluetooth device system, when the low-frequency, low-precision, and low-power digital clock cycle reaches the sleep time cycle pre-set in the first register, the Bluetooth device is awakened, and the Bluetooth device enters the activated state from the sleep state. In the activated state, the Bluetooth system will run under the high-frequency, high-precision, and high-power digital clock. After the Bluetooth system enters the activated state, the calculation module in step S1 is automatically triggered to calculate the high-frequency, high-precision, and high-power digital clock cycle corresponding to N low-frequency, low-precision, and low-power digital clock cycles. At the same time, the software will calculate the absolute time corresponding to this sleep time based on the average value of the high-frequency, high-precision, and high-power digital clock cycles corresponding to the N low-frequency, low-precision, and low-power digital clock cycles calculated when the Bluetooth device was in the activated state last time, and compensate the absolute time to the Bluetooth clock to maintain the continuity and accuracy of the Bluetooth clock.

[0008] S4. After the calculation of the high-frequency, high-precision, and high-power consumption digital clock cycles corresponding to the N low-frequency, low-precision, and low-power consumption digital clock cycles is completed, in order to compensate for the error caused by the real-time change of the low-precision clock frequency, the number of high-frequency, high-precision, and high-power consumption digital clock cycles corresponding to the N low-frequency, low-precision, and low-power consumption digital clock cycles calculated this time is summed with the number of high-frequency, high-precision, and high-power consumption digital clock cycles corresponding to the N low-frequency, low-precision, and low-power consumption digital clock cycles previously saved in the third register, and the average value is taken. The average value is saved in the third register as a new global variable, and step S2 is executed.

[0009] A Bluetooth clock circuit structure comprises: a register for controlling the entire digital circuit module, a counter for calculating the number of cycles and a digital clock synchronizer, wherein the register provides a control interface and a software interface for the calculation module; the counter for calculating the number of cycles is used to calculate the number of high-frequency, high-precision and high-power consumption digital clock cycles corresponding to the low-frequency, low-precision and low-power consumption digital clock cycles, and save the calculated number of digital clock cycles into the register; and the digital clock synchronizer is used to synchronize the low-frequency, low-precision and low-power consumption digital clock with the high-frequency, high-precision and high-power consumption digital clock.

[0010] Further, the register includes a first register, a second register, a third register and an operation mode selection register,

[0011] The first register is readable and writable by software, and is used to store a register of a low-frequency, low-precision, low-power digital clock cycle N. When the Bluetooth device is in a sleep state, when the low-frequency, low-precision, low-power digital clock cycle reaches the sleep time cycle preset in the first register, the Bluetooth device is awakened, and the Bluetooth device enters an active state from the sleep state. The Bluetooth system runs under a high-frequency, high-precision, high-power digital clock, and automatically triggers the calculation module in step S1.

[0012] The second register is software readable, and an indication signal is stored in the second register, which is used to indicate whether the value calculated by the entire digital circuit module is valid, that is, whether the number of high-frequency, high-precision, high-power consumption digital clock cycles corresponding to the N low-frequency, low-precision, low-power consumption digital clock cycles stored in the third register is valid;

[0013] The third register is software readable, and is a register for storing the number of high-frequency, high-precision, high-power consumption digital clock cycles corresponding to N low-frequency, low-precision, low-power consumption digital clock cycles;

[0014] The operation mode selection register is readable and writable by software. The operation mode selection register includes a manual mode register and an automatic mode register, which are mainly used to control the operation mode of the module and select automatic trigger mode or manual trigger mode.

[0015] Furthermore, when the Bluetooth device is powered on for the first time, it operates in the manual trigger mode. When the Bluetooth device enters the active state from the sleep state, the Bluetooth device operates in the automatic trigger mode.

[0016] The present invention has the following beneficial effects:

[0017] 1. The Bluetooth chip of the present invention is in a sleep state except for the packet sending and receiving stage. The present invention adopts a low-frequency, low-precision, low-power digital clock, which greatly reduces the power consumption of the Bluetooth chip in the sleep stage.

[0018] 2. The inaccuracy of the Bluetooth clock caused by the sleep state is avoided by converting the digital clock cycle with high frequency, high precision and high power consumption, so that the Bluetooth chip can greatly increase the battery life of the Bluetooth device while ensuring the accuracy of the Bluetooth clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] Figure 1 It is a flow chart of a calibration method of a Bluetooth clock provided by the present invention;

[0021] Figure 2 The present invention is a schematic diagram of a Bluetooth clock circuit structure involved in the method of the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] This embodiment provides a Bluetooth clock calibration method, such as Figure 1 As shown, including but not limited to the following steps:

[0024] S1. For a Bluetooth device that is powered on for the first time, a high-frequency, high-precision, high-power consumption digital clock cycle corresponding to N low-frequency, low-precision, low-power consumption digital clock cycles is calculated through a calculation module in a hardware-specific Bluetooth clock digital circuit structure. To reduce errors, the above operation is performed multiple times, and an average value of the corresponding high-frequency, high-precision, high-power consumption digital clock cycles is taken, and the average value is saved as a global variable of the software.

[0025] S2. The link of the Bluetooth device interacts once at regular intervals to implement the operations of sending and receiving packets. During the interval between two interactions, if the Bluetooth device has no other tasks to perform, the Bluetooth device enters a sleep state to ensure long battery life. When the Bluetooth system is in a sleep state, the Bluetooth clock will stop. At this time, the system will run under a low-frequency, low-precision, and low-power digital clock, and the period of this clock is used as a measure of the system sleep time.

[0026] S3. In system sleep, after the low-frequency, low-precision, low-power digital clock cycle reaches a preset sleep time cycle, the Bluetooth device is awakened, and the Bluetooth device enters an active state from a sleep state. In the active state, the Bluetooth system runs under a high-frequency, high-precision, and high-power digital clock. After the Bluetooth system enters the active state, the calculation module in step S1 is automatically triggered to calculate the high-frequency, high-precision, and high-power digital clock cycle corresponding to N low-frequency, low-precision, and low-power digital clock cycles. At the same time, the software calculates the absolute time corresponding to this sleep time by multiplying the average value of the high-frequency, high-precision, and high-power digital clock cycles corresponding to the N low-frequency, low-precision, and low-power digital clock cycles calculated when the Bluetooth device was last in an active state by the time length of each cycle, and compensates the absolute time to the Bluetooth clock through the register in the Bluetooth device to maintain the continuity and accuracy of the Bluetooth clock.

[0027] Furthermore, the specific implementation process of compensating the absolute time to the Bluetooth clock through the register in the Bluetooth device includes: firstly dividing the absolute time by the Bluetooth slot (625us) to obtain the integer of the Bluetooth slot, and adding this multiple to the slot of the Bluetooth clock to maintain the continuity of Bluetooth.

[0028] S4. After the calculation of the high-frequency, high-precision, and high-power consumption digital clock cycles corresponding to the N low-frequency, low-precision, and low-power consumption digital clock cycles is completed, in order to compensate for the error caused by the real-time change of the low-precision clock frequency, the value calculated this time is summed with the previously saved value, and the average value is taken. This average value is saved as a new global variable, and step S2 is executed.

[0029] This embodiment also provides a digital circuit structure of a Bluetooth clock, which applies the above-mentioned Bluetooth clock calibration method to calculate the number of high-frequency, high-precision, and high-power consumption digital clock cycles corresponding to N low-frequency, low-precision, and low-power consumption digital clock cycles.

[0030] In a preferred embodiment, the digital circuit structure of the Bluetooth clock includes: a structure register for controlling the entire digital circuit structure, a counter for calculating the number of cycles, and a digital clock synchronizer.

[0031] In this embodiment, the register provides a control interface and a software interface for the digital circuit structure module of the Bluetooth clock. The register includes: a first register, a second register, a third register and an operation mode selection register.

[0032] The first register is readable and writable by software, and is used to store a register of a low-frequency, low-precision, low-power digital clock cycle N; that is, a threshold cycle number is set in the first register. When the Bluetooth device is in a sleep state, when the low-frequency, low-precision, low-power digital clock cycle reaches the sleep time cycle pre-set in the first register, the Bluetooth device is awakened, and the Bluetooth device enters an activated state from a sleep state. The Bluetooth system runs under a high-frequency, high-precision, and high-power digital clock, and automatically triggers the calculation module in step S1.

[0033] The second register is software readable and is used to store an indication signal, which is used to indicate that the attached Figure 2 Whether the value calculated by the entire digital circuit module in is valid, that is, whether the number of high-frequency, high-precision, high-power digital clock cycles corresponding to the N low-frequency, low-precision, low-power digital clock cycles stored in the third register is valid. Exemplarily, the initial value of the indication signal in the second register is 0, and the corresponding calculation process starts after the calculation module is triggered. When the calculation is completed, the indication signal value of the second register becomes 1. When the software reads the value of the second register as 1, the value stored in the third register is used for calculation.

[0034] The third register is software readable, and is used to store the number of high-frequency, high-precision, high-power digital clock cycles corresponding to N low-frequency, low-precision, low-power digital clock cycles. The value stored in the third register is dynamically updated, and is updated each time the Bluetooth device enters an activated state. The updating method includes: summing the number of high-frequency, high-precision, high-power digital clock cycles corresponding to the N low-frequency, low-precision, low-power digital clock cycles calculated in this activated state and the number of high-frequency, high-precision, high-power digital clock cycles corresponding to the N low-frequency, low-precision, low-power digital clock cycles previously stored in the third register, taking the average value, and storing the average value in the third register as a new global variable.

[0035] The operation mode selection register is readable and writable by software. The operation mode selection register includes a manual mode register and an automatic mode register, which are mainly used to control the operation mode of the module and select automatic trigger mode or manual trigger mode.

[0036] In this embodiment, the counter for calculating the number of cycles is mainly used to calculate the number of high-frequency, high-precision, high-power digital clock cycles corresponding to the low-frequency, low-precision, low-power digital clock cycles, and save the calculated number of digital clock cycles to the third register. Figure 2 The calculation module in the embodiment, therefore, the “calculation module” appearing in this embodiment may be equivalent to a counter.

[0037] In this embodiment, the digital clock synchronizer is used to synchronize a low-frequency, low-precision, low-power digital clock with a high-frequency, high-precision, high-power digital clock, and synchronize the signals between the two clock domains to reduce the occurrence of metastable states.

[0038] Exemplarily, this embodiment provides a specific digital circuit structure of a Bluetooth clock, such as Figure 2 The digital circuit structure of the Bluetooth clock includes input pin wakeup, input pin ref_clk, input pin rc_clk, input pin clknb, input pin auto / manual, output pin cal_done, output pin cal_result, register, synchronizer and counter (corresponding to the attached Figure 2 Module in the calculation).

[0039] In this embodiment, the registers are the above-mentioned first register, second register, third register and operation mode selection register. The synchronizer is a low-frequency, low-precision, low-power digital clock and a high-frequency, high-precision, high-power digital clock synchronizer, which is mainly used to synchronize the signals between the two clock domains to reduce the occurrence of metastable states. The counter is used to calculate the number of high-frequency, high-precision, high-power digital clock cycles corresponding to the low-frequency, low-precision, low-power digital clock cycle, and save it in the third register.

[0040] The digital circuit structure of the Bluetooth clock also includes various pins:

[0041] The wakeup pin is the input pin of the circuit structure, which is used to input the waku_up signal. The waku_up signal is a low-frequency, low-precision, low-power digital clock domain signal, which is used to indicate whether the system is in sleep mode at this time. One end of the wakeup pin is connected to the synchronizer, and the other end is connected to the wakeup module of the Bluetooth device.

[0042] The rc_clk pin is used to transmit the rc_clk signal, which is a low-frequency, low-precision, and low-power digital clock calculated by the calculation module. One end of the rc_clk pin is connected to the first register, and the other end is connected to the calculation module.

[0043] The ref_clk pin is used to transmit a ref_clk signal, which is a high-frequency, high-precision, high-power digital clock calculated by the calculation module. One end of the rc_clk pin is connected to the third register, and the other end is connected to the calculation module.

[0044] The clknb pin is used to transmit a clknb signal, which is a low-frequency, low-precision, low-power digital clock cycle N calculated by the calculation module. One end of the clknb pin is connected to the first register, and the other end is connected to the calculation module.

[0045] The auto / manul pin is used to transmit the auto / manul signal, which is used to control whether the operation mode of the module is automatically triggered or manually triggered. One end of the auto / manul pin is connected to the operation mode selection register, and the other end is connected to the calculation module.

[0046] The cal_done pin is used to transmit a cal_done signal, which is used to inform the software whether the final calculation result stored in the third register can be used at this time. One end of the cal_done pin is connected to the second register, and the other end is connected to the calculation module.

[0047] The cal_result pin is used to transmit the cal_result signal, which is the number of high-frequency, high-precision, and high-power consumption digital clock cycles corresponding to N low-frequency, low-precision, and low-power consumption digital clock cycles.

[0048] In this embodiment, the Bluetooth device that is powered on for the first time operates in the manual trigger mode, and when the Bluetooth device enters the active state from the sleep state, the Bluetooth device operates in the automatic trigger mode. That is to say, the manual trigger mode is mainly used when calculating the high-frequency, high-precision, high-power digital clock cycles corresponding to N low-frequency, low-precision, low-power digital clock cycles in S1; and the automatic trigger mode is mainly used when the high-frequency, high-precision, high-power digital clock cycles corresponding to N low-frequency, low-precision, low-power digital clock cycles are automatically performed in S3 each time the system wakes up from sleep.

[0049] In manual trigger mode, the software first configures the first register and then configures the manual mode register to start the attached Figure 2 The calculation process includes: recording the number of low-frequency, low-precision, and low-power digital clock cycles through a counter, stopping counting when the number of cycles is equal to the threshold number of cycles of the first register, and counting the number of high-frequency, high-precision, and high-power digital clock cycles contained in the time period, and finally saving the number of high-frequency, high-precision, and high-power digital clock cycles in the third register.

[0050] In automatic trigger mode Figure 2 The entire digital circuit module in the wakeup signal is used as a trigger source. Before the trigger source comes, the software must configure the first register in advance. The wakeup signal is a signal in the digital clock domain with low frequency, low precision and low power consumption. It needs to be processed by the synchronizer before entering the counter. The synchronizer is first used to convert the low frequency, low precision and low power consumption digital clock domain to the high frequency, high precision and high power consumption digital clock domain, and then input into the counter to participate in the logical operation of the high frequency, high precision and high power consumption digital clock domain to reduce the generation of metastable state. The calculation process includes: recording the number of low frequency, low precision and low power consumption digital clock cycles through the counter, and when the number of cycles is equal to the threshold number of cycles of the first register, stop counting, and count the number of high frequency, high precision and high power consumption digital clock cycles contained in the time period at the same time, and finally save the number of high frequency, high precision and high power consumption digital clock cycles to the third register.

[0051] It should be noted that a person skilled in the art can understand that all or part of the processes in the above method embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes in the above method embodiments. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0052] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The device embodiment described above is merely schematic, and the units and modules described as separate components may or may not be physically separated. In addition, some or all of the units and modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. A person of ordinary skill in the art can understand and implement it without paying creative work.

[0053] The above description is only a specific implementation mode of the present application. It should be pointed out that for ordinary technicians in this field, it can be understood that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A Bluetooth clock calibration method, characterized in that: The following steps are involved: S1. For a Bluetooth device that is powered on for the first time, a calculation module in the Bluetooth clock circuit structure is used to calculate a high-frequency, high-precision, high-power consumption digital clock cycle corresponding to N low-frequency, low-precision, low-power consumption digital clock cycles. To reduce errors, the above operation is performed multiple times, and an average value of the corresponding high-frequency, high-precision, high-power consumption digital clock cycles is taken. The average value is saved as a global variable of the software. S2. The Bluetooth devices interact with each other at regular intervals to implement the operations of sending and receiving packets. During the interval between two interactions, if the Bluetooth device has no other tasks to perform, the Bluetooth device enters a sleep state. When the Bluetooth device is in the sleep state, the Bluetooth clock stops, and a low-frequency, low-precision, and low-power digital clock is used to record the sleep time of the Bluetooth device. S3. During the sleep process of the Bluetooth device, when the low-frequency, low-precision, low-power digital clock cycle reaches a preset sleep time cycle, the Bluetooth device enters an activated state from the sleep state. In the activated state, the Bluetooth device runs under a high-frequency, high-precision, high-power digital clock. After the Bluetooth device enters the activated state, the calculation module in step S1 is automatically triggered to calculate the high-frequency, high-precision, high-power digital clock cycle corresponding to N low-frequency, low-precision, low-power digital clock cycles. At the same time, the absolute time corresponding to the current sleep time is calculated according to the average value of the high-frequency, high-precision, high-power digital clock cycle corresponding to the N low-frequency, low-precision, low-power digital clock cycles calculated when the Bluetooth device was in the activated state last time, and the absolute time is compensated to the Bluetooth clock, and step S4 is executed; S4. After the calculation of the high-frequency, high-precision, and high-power consumption digital clock cycles corresponding to the N low-frequency, low-precision, and low-power consumption digital clock cycles is completed, the number of high-frequency, high-precision, and high-power consumption digital clock cycles corresponding to the N low-frequency, low-precision, and low-power consumption digital clock cycles calculated this time is summed with the number of high-frequency, high-precision, and high-power consumption digital clock cycles corresponding to the N low-frequency, low-precision, and low-power consumption digital clock cycles saved previously, and the average value is taken, and the average value is saved as a new global variable, and step S2 is executed.

2. A Bluetooth clock circuit structure for implementing the Bluetooth clock calibration method according to claim 1, characterized in that: include: Control the registers of the entire digital circuit module, the counter for calculating the number of cycles, and the digital clock synchronizer, wherein the registers provide a control interface and a software interface for the calculation module; The counter for calculating the number of cycles is used to calculate the number of high-frequency, high-precision, and high-power consumption digital clock cycles corresponding to the low-frequency, low-precision, and low-power consumption digital clock cycles, and save the calculated number of digital clock cycles into a register; The digital clock synchronizer is used to synchronize a low-frequency, low-precision, low-power digital clock with a high-frequency, high-precision, high-power digital clock; The registers include a first register, a second register, a third register and an operation mode selection register. The first register is readable and writable by software, and is used to store a register of a low-frequency, low-precision, and low-power digital clock cycle N; The second register is software readable, and an indication signal is stored in the second register, which is used to indicate whether the value calculated by the entire digital circuit module is valid, that is, whether the number of high-frequency, high-precision, high-power consumption digital clock cycles corresponding to the N low-frequency, low-precision, low-power consumption digital clock cycles stored in the third register is valid; The third register is software readable, and is a register for storing the number of high-frequency, high-precision, high-power consumption digital clock cycles corresponding to N low-frequency, low-precision, low-power consumption digital clock cycles; The operation mode selection register is readable and writable by software. The operation mode selection register includes a manual mode register and an automatic mode register, which are mainly used to control the operation mode of the module and select automatic trigger mode or manual trigger mode.

3. A Bluetooth clock circuit structure according to claim 2, characterized in that: The first time a Bluetooth device is powered on, it operates in the manual trigger mode. When the Bluetooth device enters the active state from the sleep state, the Bluetooth device operates in the automatic trigger mode.

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