Error correction circuit, memory controller and memory system

Abstract

Error correction circuits, memory controllers, and memory systems are provided. A memory controller includes an error correction circuit and a central processing unit (CPU) to control the error correction circuit. The error correction circuit includes an error correction code (ECC) decoder and a memory to store a parity check matrix. The ECC decoder performs ECC decoding on a codeword read from a memory module to: (i) generate a first syndrome and a second syndrome, (ii) generate a decoding mode flag associated with a type of error in the codeword based on the first syndrome and the second syndrome, (iii) operate in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and (iv) selectively correct one or more symbol errors in the codeword or a chip error associated with one data chip of a plurality of data chips.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0172779, filed on December 23, 2019, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] Some example embodiments of the present disclosure relate to a memory, and more particularly, to a memory controller and a memory system including the same. BACKGROUND

[0003] Memory devices can be implemented using semiconductor materials such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. Memory devices are generally classified into volatile memory devices and non-volatile memory devices.

[0004] Volatile memory devices refer to memory devices in which stored data is lost when power is turned off. On the other hand, non-volatile memory devices refer to memory devices that retain stored data when power is turned off. Since a dynamic random access memory (DRAM) as a type of volatile memory has a high access speed, when used in a computing system, the DRAM is widely used as a working memory, a buffer memory, a main memory, etc. SUMMARY

[0005] Some example embodiments provide a memory controller capable of efficiently correcting errors occurring in a memory module.

[0006] Some example embodiments provide a memory system including a memory controller capable of efficiently correcting errors occurring in a memory module.

[0007] According to some example embodiments, a memory controller includes an error correction circuit and a central processing unit (CPU) for controlling the error correction circuit. The error correction circuit includes an error correction code (ECC) decoder and a memory for storing a parity check matrix. The ECC decoder performs ECC decoding on a codeword read from a memory module. Such ECC decoding includes: (i) generating a first syndrome and a second syndrome, (ii) generating a decoding mode flag associated with a type of error in the codeword based on the second syndrome and a decision syndrome, (iii) operating in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and (iv) selectively correcting one of one or more symbol errors in the codeword and a chip error associated with one data chip of a plurality of data chips.

[0008] According to some example embodiments, a memory system includes a memory module and a memory controller for controlling the memory module. The memory module includes a plurality of data chips, a first parity chip, and a second parity chip. The memory controller includes an error correction circuit and a central processing unit (CPU) for controlling the error correction circuit. The error correction circuit includes an error correction code (ECC) decoder and a memory for storing a parity check matrix. The ECC decoder performs ECC decoding on a codeword read from the memory module, thereby generating a first syndrome and a second syndrome, generates a decoding mode flag associated with a type of error in the codeword based on the second syndrome and a decision syndrome, operates in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and selectively corrects one of one or more symbol errors in the codeword and a chip error associated with one of the plurality of data chips.

[0009] According to some example embodiments, a memory controller for controlling a memory module having a plurality of data chips, a first parity chip, and a second parity chip includes an error correction circuit and a central processing unit (CPU) for controlling the error correction circuit. The error correction circuit includes an error correction code (ECC) encoder, an ECC decoder, and a memory for storing a parity generation matrix and a parity check matrix. The ECC encoder performs ECC encoding on a set of user data using the parity generation matrix to generate first parity data and second parity data, and provides a codeword including the set of user data, the first parity data, and the second parity data to the memory module. The ECC decoder performs ECC decoding on the codeword read from the memory module to: (i) generate a first syndrome and a second syndrome, (ii) generate a decoding mode flag associated with a type of error in the codeword based on the second syndrome and a decision syndrome, (iii) operate in one of a first decoding mode and a second decoding mode based on the decoding mode flag, and (iv) selectively correct one of one or more symbol errors in the codeword and a chip error associated with one of the plurality of data chips.

[0010] According to some example embodiments, an ECC decoder in a memory controller can perform ECC decoding on a codeword read from a memory module, thereby generating a first syndrome using a first check matrix of a parity check matrix and generating a second syndrome using a second check matrix of the parity check matrix. The decoder can determine a type of error in the codeword based on the first syndrome and the second syndrome, and can correct a plurality of errors in a plurality of chips or three or more symbol errors in one chip based on a decoding mode. Thus, the memory controller can efficiently correct various types of errors. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other features of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0012] Figure 1 is a block diagram illustrating a memory system according to an example embodiment.

[0013] Figure 2 is a block diagram illustrating a memory controller in the memory system of Figure 1 according to an example embodiment.

[0014] Figure 3 illustrates a data set corresponding to a plurality of burst lengths in the memory system of Figure 1 according to an example embodiment.

[0015] Figure 4 is a block diagram illustrating one of data chips in the memory module of Figure 1 according to an example embodiment.

[0016] Figure 5 illustrates a first memory bank array in the data chip of Figure 4 according to an example embodiment.

[0017] Figure 6 is a block diagram illustrating an example of an error correction circuit in Figure 2 according to an example embodiment.

[0018] Figure 7 illustrates a parity check generator matrix stored in a memory in the error correction circuit of Figure 6 according to an example embodiment.

[0019] Figure 8 illustrates a unit sub-matrix constituting a second check matrix in Figure 7 according to an example embodiment.

[0020] Figure 9 illustrates a unit matrix in Figure 8 according to an example embodiment.

[0021] Figure 10 illustrates a part of a Galois field sub-matrix in Figure 7 according to an example embodiment.

[0022] Figure 11 illustrates an example of an ECC encoder in the error correction circuit of Figure 6 according to an example embodiment.

[0023] Figure 12 illustrates a parity check generator matrix stored in a memory in the error correction circuit of Figure 6 according to an example embodiment.

[0024] Figure 13 illustrates an example of an error correction circuit in Figure 6Examples of an ECC decoder in an error correction circuit.

[0025] Figure 14A Examples of an ECC decoder according to example embodiments are shown. Figure 13 Examples of a syndrome generator circuit in an ECC decoder.

[0026] Figure 14B Examples of a first decoder in an ECC decoder according to example embodiments are shown. Figure 13 Examples of a second decoder in an ECC decoder according to example embodiments are shown.

[0027] Figure 14C Examples of a second decoder in an ECC decoder according to example embodiments are shown. Figure 13 Examples of a second decoder in an ECC decoder according to example embodiments are shown.

[0028] Figure 15 Operation of an ECC decoder according to example embodiments is shown. Figure 13

[0029] Various types of errors that an ECC decoder can correct according to example embodiments are shown. Figures 16A to 18

[0030] Table illustrating various types of errors that an ECC decoder determines based on a first syndrome and a second syndrome. Figure 19

[0031] Flowchart illustrating a method of correcting errors in a memory controller according to example embodiments. Figure 20

[0032] Flowchart illustrating a method of operating a memory system according to example embodiments, the memory system including a memory module and a memory controller for controlling the memory module. Figure 21

[0033] Block diagram illustrating a memory module that a memory system can employ according to example embodiments. Figure 22

[0034] Block diagram illustrating a memory system having a quad-rank memory module according to example embodiments. Figure 23

[0035] Block diagram illustrating a mobile system 900 including a memory module according to example embodiments. Figure 24 DETAILED DESCRIPTION

[0036] Example embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals can refer to like elements throughout the drawings.

[0037] Figure 1 ​is a block diagram illustrating a memory system according to an example embodiment. Referring to Figure 1 The memory system 20 can include a memory controller 100 and a memory module MM. The memory module MM includes a plurality of memory chips (or memory devices) 200a to 200k (where a and k are positive integers, and k is greater than a), 200pa, and 200pb. The plurality of memory chips 200a to 200k, 200pa, and 200pb includes a plurality of data chips 200a to 200k and first and second parity chips 200pa and 200pb.

[0038] The memory controller 100 can control overall operations of the memory system 20. The memory controller 100 can control overall data exchange between a host and the plurality of memory chips 200a to 200k, 200pa, and 200pb. For example, the memory controller 100 can write data into or read data from the plurality of memory chips 200a to 200k, 200pa, and 200pb in response to a request / command from the host. In addition, the memory controller 100 can issue operation commands to the plurality of memory chips 200a to 200k, 200pa, and 200pb to control the plurality of memory chips 200a to 200k, 200pa, and 200pb.

[0039] In an example embodiment, each of the plurality of memory chips 200a to 200k, 200pa, and 200pb includes a volatile memory unit such as a dynamic random access memory (DRAM). In other example embodiments, each of the plurality of memory chips 200a to 200k, 200pa, and 200pb includes a non-volatile memory unit such as a not-and (Nand) flash device. In this case, the memory system 20 can correspond to a solid state drive (SSD).

[0040] In an example embodiment, the number of data chips 200a to 200k can be 16, but the number of data chips 200a to 200k is not limited thereto. In an example embodiment, each of the data chips 200a to 200k can be referred to as a data memory, and each of the parity chips 200pa and 200pb can be referred to as an error-correcting code (ECC) memory or a redundant memory.

[0041] The memory controller 100 transmits an address ADDR and a command CMD to the memory module MM, and can exchange a codeword CW with the memory module MM.

[0042] The memory controller 100 may include an error correction circuit 130, which may use a parity generation matrix to perform error correction coding (ECC) encoding on the user dataset to generate a parity dataset, and may provide codewords including the user dataset and the parity dataset to the memory module MM during write operations of the memory system 20. The user dataset may be stored in data chips 200a to 200k, a first portion of the parity dataset may be stored in a first parity chip 200pa, and a second portion of the parity dataset may be stored in a second parity chip 200pb.

[0043] Furthermore, the error correction circuit 130 can use a parity check matrix to perform ECC decoding on the codeword CW read from the memory module MM to generate a first corrector and a second corrector. Based on the first and second correctors, it can generate a decoding mode flag associated with the type of error in the codeword CW. It can operate in one of the first and second decoding modes based on the decoding mode flag, and can selectively correct one or more symbol errors and chip errors in the codeword CW. Chip errors can be associated with one of the data chips 200a to 200k, and one or more symbol errors can be associated with symbols in the codeword CW. Therefore, the error correction circuit 130 can correct chip errors associated with errors in one data chip and multiple errors occurring in multiple data chips, and can correct various types of errors.

[0044] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of the memory controller in a memory system. (Refer to...) Figure 2 The memory controller 100 includes a central processing unit (CPU) 110, a host interface 120, a data register 125, an error correction circuit 130, a command buffer 190, and an address buffer 195. The error correction circuit 130 includes an ECC encoder 140, an ECC decoder 150, and an (ECC) memory 180.

[0045] Host interface 120 receives request REQ and user dataset SDQ from the host and provides user dataset SDQ to data register 125. Data register 125 provides user dataset SDQ to error correction circuitry 130. ECC encoder 140 can perform ECC encoding on user dataset SDQ using a parity generation matrix to generate a first codeword CW1. Conversely, ECC decoder 150 can perform ECC decoding on codeword CW2 provided from memory module MM using a parity matrix to correct errors in codeword CW2, providing one of user dataset SDQ and corrected user dataset C_SDQ to CPU 110, and providing CPU 110 with an error flag signal DSF associated with error correction. Memory 180 can store parity generation matrix and parity matrix.

[0046] CPU 110 receives user dataset SDQ or corrected user dataset C_SDQ, and controls error correction circuit 130, command buffer 190, and address buffer 195. Command buffer 190 stores command CMD corresponding to request REQ, and sends command CMD to memory module MM under the control of CPU 110. Address buffer 195 stores address ADDR, and sends address ADDR to memory module MM under the control of CPU 110.

[0047] Figure 3 The example embodiment is shown with Figure 1 The dataset corresponding to multiple burst lengths in the memory system. (Refer to...) Figure 3 Each of the data chips 200a to 200k and the parity chips 200pa and 200pb can perform a burst operation. Here, a burst operation refers to the operation of writing or reading a large amount of data by sequentially incrementing or decrementing an initial address provided from the memory controller 100. The basic unit of a burst operation may be referred to as the burst length BL.

[0048] Reference Figure 3 Each of the datasets DQ_BL1 to DQ_BLk, corresponding to multiple burst lengths, is input to or output from each of data chips 200a to 200k. Each of the datasets DQ_BL1 to DQ_BLk may include data segments DQ_BL_SG11 to DQ_BL_SG18 corresponding to each of the multiple burst lengths. Data sets DQ_BL1 to DQ_BL18 may correspond to the user dataset SDQ. Figure 3It is assumed that the burst length is eight (8), and it is assumed that the burst operation is performed once. When the burst operation is performed in each of the data chips 200a to 200k, first parity check data PRTR corresponding to a plurality of burst lengths is input to or output from the first parity check chip 200pa, and second parity check data PRTS corresponding to a plurality of burst lengths is input to or output from the second parity check chip 200pb. The second parity check data PRTS can include a first portion PRTS1 and a second portion PRTS2, and the first parity check data PRTR can include a first portion PRTR1 and a second portion PRTR2.

[0049] Figure 4 is a block diagram of one of the data chips in the memory module of Figure 1 According to an example embodiment. In Figure 4 , it is assumed that each of the data chips 200a to 200k in Figure 1 employs a volatile memory device. Referring to Figure 4 , the data chip 200a can include control logic 210, an address register 220, bank control logic 230, a row address multiplexer 240, a column address latch 250, a row decoder 260, a column decoder 270, a memory cell array 300, a sense amplifier unit 285, an input / output (I / O) gating circuit 290, a data input / output (I / O) buffer 295, and a refresh counter 245. The memory cell array 300 can include first to eighth bank arrays 310, 320, 330, 340, 350, 360, 370, and 380. The row decoder 260 can include first to eighth bank row decoders 260a to 260h coupled to the first to eighth bank arrays 310 to 380, respectively, the column decoder 270 can include first to eighth bank column decoders 270a to 270h coupled to the first to eighth bank arrays 310 to 380, respectively, and the sense amplifier unit 285 can include first to eighth bank sense amplifiers 285a to 285h coupled to the first to eighth bank arrays 310 to 380, respectively.

[0050] The first memory bank array 310 to the eighth memory bank array 380, the first memory bank row decoder 260a to the eighth memory bank row decoder 260h, the first memory bank column decoder 270a to the eighth memory bank column decoder 270h, and the first memory bank sense amplifier 285a to the eighth memory bank sense amplifier 285h can form the first memory bank to the eighth memory bank. Each of the first memory bank array 310 to the eighth memory bank array 380 can include a plurality of word lines WL, a plurality of bit lines BTL, and a plurality of memory cells MC formed at intersections of the plurality of word lines WL and the plurality of bit lines BTL.

[0051] Although the data chip 200a is shown as including eight memory banks in Figure 4 any number of memory banks. The address register 220 can receive an address ADDR including a memory bank address BANK ADDR, a row address ROW ADDR, and a column address COL ADDR from the memory controller 100. The address register 220 can provide the received memory bank address BANK ADDR to the memory bank control logic 230, can provide the received row address ROW ADDR to the row address multiplexer 240, and can provide the received column address COL ADDR to the column address latch 250.

[0052] The memory bank control logic 230 can generate memory bank control signals in response to the memory bank address BANK ADDR. One of the first memory bank row decoder 260a to the eighth memory bank row decoder 260h corresponding to the memory bank address BANK ADDR can be activated in response to the memory bank control signals, and one of the first memory bank column decoder 270a to the eighth memory bank column decoder 270h corresponding to the memory bank address BANK ADDR can be activated in response to the memory bank control signals.

[0053] The row address multiplexer 240 can receive the row address ROW ADDR from the address register 220 and can receive a refresh row address REF ADDR from the refresh counter 245. The row address multiplexer 240 can selectively output the row address ROW ADDR or the refresh row address REF ADDR as a row address RA. The row address RA output from the row address multiplexer 240 can be applied to the first memory bank row decoder 260a to the eighth memory bank row decoder 260h.

[0054] One of the first memory bank row decoder 260a to the eighth memory bank row decoder 260h activated can decode the row address RA output from the row address multiplexer 240 and can activate a word line WL corresponding to the row address RA. For example, the activated memory bank row decoder can generate a word line driving voltage and can apply the word line driving voltage to the word line WL corresponding to the row address RA.

[0055] The column address latch 250 can receive the column address COL_ADDR from the address register 220 and can temporarily store the received column address COL_ADDR. In an example embodiment of the inventive concept, in a burst mode, the column address latch 250 can generate a column address that is incremented from the received column address COL_ADDR. The column address latch 250 can apply the temporarily stored or generated column address to the first to eighth memory bank column decoders 270a to 270h.

[0056] An activated one of the first to eighth memory bank column decoders 270a to 270h can decode the column address COL_ADDR output from the column address latch 250 and can control the I / O gating circuit 290 to output data corresponding to the column address COL_ADDR. The I / O gating circuit 290 can include a circuit for gating input / output data. The I / O gating circuit 290 can further include a read data latch for storing data output from the first to eighth memory bank arrays 310 to 380 and a write control device for writing data to the first to eighth memory bank arrays 310 to 380.

[0057] Data read from one of the first to eighth memory bank arrays 310 to 380 can be combined to sensing of a sense amplifier of the one memory bank array from which data is to be read and can be stored in the read data latch. The data stored in the read data latch can be provided to the memory controller 100 via the data I / O buffer 295. A data set DQ_BL to be written into one of the first to eighth memory bank arrays 310 to 380 can be provided to the data I / O buffer 295 from the memory controller 100. The data I / O buffer 295 can provide the data set DQ_BL to the I / O gating circuit 290.

[0058] The control logic circuit 210 can control operations of the data chip 200a. For example, the control logic circuit 210 can generate a control signal for the data chip 200a to perform a write operation or a read operation. The control logic circuit 210 can include a command decoder 211 that decodes a command CMD received from the memory controller 100 and a mode register 212 that sets an operation mode of the data chip 200a. Figure 1 Each of the parity chips 200pa and 200pb in the parity chip 200p can have the same or substantially the same configuration as the data chip 200a. Each of the parity chips 200pa and 200pb can input / output corresponding parity data.

[0059] Figure 5Showing according to an example embodiment Figure 4 The first memory bank array in the data chip. (Refer to...) Figure 5 The first memory bank array 310 includes multiple word lines WL1 to WL2m (where m is a positive integer greater than two), multiple bit lines BTL1 to BTL2n (where n is a positive integer greater than two), and multiple memory cells MC disposed near the intersections of the word lines WL1 to WL2m and the bit lines BTL1 to BTL2n. In an exemplary embodiment of the inventive concept, each of the multiple memory cells MC may include a DRAM cell structure. The multiple word lines WL1 to WL2m to which the multiple memory cells MC are connected may be referred to as rows of the first memory bank array 310, and the multiple bit lines BL1 to BL2n to which the multiple memory cells MC are connected may be referred to as columns of the first memory bank array 310.

[0060] Figure 6 This illustrates an example embodiment. Figure 2 A block diagram of an example error correction circuit is shown. (Refer to...) Figure 6 The error correction circuit 130 includes an ECC encoder 140, an ECC decoder 150, and a memory 180. The memory 180 may be referred to as the ECC memory 180. The memory 180 is connected to the ECC encoder 140 and the ECC decoder 150, and can store the parity generation matrix PGM and the parity check matrix PCM. The ECC encoder 140 can perform ECC encoding on the user dataset SDQ using the parity generation matrix PGM to generate a parity check dataset SPRT including first parity check data PRTR and second parity check data PRTS, and can output a codeword CW1 including the user dataset SDQ, the first parity check data PRTR, and the second parity check data PRTS.

[0061] ECC decoder 150 can receive codeword CW2 from memory module MM, which includes user dataset SDQ, first parity data PRTR, and second parity data PRTS. ECC decoder 150 can perform ECC decoding on codeword CW2 using the first part of parity matrix PCM to generate a decoding status flag DSF indicating that user dataset SDQ includes correctable errors while outputting user dataset SDQ.

[0062] The ECC decoder 150 can perform ECC decoding on the codeword CW2 including the user data set SDQ, the first parity data PRTR, and the second parity data PRTS by using the parity check matrix PCM, can operate in one of a first decoding mode and a second decoding mode according to a type of error in the user data set SDQ, can selectively correct one of one or more symbol errors and chip errors in the user data set SDQ, and can output the user data set SDQ or the corrected user data set C_SDQ.

[0063] Figure 7 A parity check matrix stored in a memory in an error correction circuit of Figure 6 is illustrated. A parity generation matrix PGM can have a similar configuration as the parity check matrix PCM. Referring to Figure 7 , the parity check matrix PCM can include a first check matrix HS 21 and a second check matrix HS 22 . The first check matrix HS 21 may be generated based on a Reed-Solomon code, and can be used to generate a first syndrome. The second check matrix HS 22 may be generated based on a simple parity check code, and can be used to generate a second syndrome.

[0064] The first check matrix HS 21 includes a plurality of Galois field sub matrices RSM1 to RSM(k+1) corresponding to the data chips 200a to 200k and the first parity chip 200pa, and each of the plurality of Galois field sub matrices RSM1 to RSM(k+1) has p x p elements. Here, p is an integer greater than three. The second check matrix HS 22 includes (k+2) identity sub matrices ISM corresponding to the data chips 200a to 200k, the first parity chip 200pa, and the second parity chip 200pb, and each identity sub matrix ISM has p x p elements.

[0065] Figure 8 An identity sub matrix constituting the second check matrix in Figure 7 is illustrated. Referring to Figure 8 , the identity sub matrix ISM includes p / q identity matrices IM arranged in a diagonal direction. Here, q is an integer greater than 1 and less than p. Each identity sub matrix ISM has q x q elements. In the second check matrix HS 22 , other elements except the identity matrices IM have a value of "0".

[0066] Figure 9 The identity matrix in Figure 8 is shown. Referring to Figure 9 , q elements in a diagonal direction have a logic high level (i.e., a value "1"), and other elements except the q elements in the diagonal direction have a logic low level (i.e., a value "0").

[0067] Figure 10 A portion of a Galois field submatrix in Figure 7 is shown. Referring to Figure 10 , the Galois field submatrix RSM1 includes an identity matrix IM and α matrices α s , α 2s , and α 3s . Here, s is an integer in the range of 1 to 4. The Galois field submatrix RSM(k+1) includes α matrices α (4k-4)×s , α (4k-3)×2s , α (4k-2)×2s , and α (4k-1)×4s . Here, the α matrices can be obtained using a primitive polynomial of order q. α 2 can be obtained by involution of α. The matrix α (4k-1)×4s can be obtained by multiplying α by (4k-1)×4s times. The elements of the matrix can belong to a Galois field.

[0068] Figure 11 An example of an ECC encoder in an error correction circuit according to an example embodiment is shown. Figure 6 Referring to Figure 11 , the ECC encoder 140 includes a first parity generator 141, a second parity generator 143, and a buffer 147.

[0069] The first parity generator 141 performs ECC encoding on the user data set SDQ on a symbol basis using a first generator matrix HS 11 to generate first parity data PRTR, and provides the first parity data PRTR to the buffer 147. The first parity generator 141 can generate the first parity data PRTR by performing a matrix multiplication operation on the user data set SDQ and the first generator matrix HS 11 .

[0070] The second parity generator 143 performs ECC encoding on the user data set SDQ using a second generator matrix HS 12A simple parity check is performed on the user data set SDQ and the first parity check data PRTR based on data bits (cell indices) to generate second parity check data PRTS, and the second parity check data PRTS is provided to the buffer 147. The simple parity check is a code that sums data bits to be even or odd on a cell basis. The buffer 147 receives the user data set SDQ, the first parity check data PRTR, and the second parity check data PRTS, and provides a codeword CW1 including the user data set SDQ, the first parity check data PRTR, and the second parity check data PRTS to the memory module MM.

[0071] Figure 12 A parity check generation matrix stored in a memory in the error correction circuit of Figure 6 is illustrated. Referring to Figure 12 , the parity check generation matrix PGM can include a first generation matrix HS 11 and a second generation matrix HS 12 . The first generation matrix HS 11 includes a plurality of Galois submatrices RSM1 to RSM(k+1) corresponding to the data chips 200a to 200k and the first parity check chip 200pa, and each of the plurality of Galois submatrices RSM1 to RSM(k+1) has p x p elements. The first generation matrix HS 11 may be generated based on a Reed-Solomon code, and can be used to generate the parity check data PRTR.

[0072] The second generation matrix HS 12 includes (k+2) identity submatrices ISM corresponding to the data chips 200a to 200k, the first parity check chip 200pa, and the second parity check chip 200pb, and each identity submatrix ISM has p x p elements. The second generation matrix HS 12 may be generated based on a simple parity check code, and can be used to generate the second parity check data PRTS.

[0073] Figure 13 An example of an ECC decoder in the error correction circuit of Figure 6 according to an example embodiment is illustrated. Referring to Figure 13 , the ECC decoder 150 includes a syndrome generation circuit 160, a first decoder 170, a second decoder 175, and a selection circuit (MUX) 179. The ECC decoder 150 can further include a buffer 167. The buffer 167 receives the codeword CW2 and provides the codeword CW2 to the first decoder 170 and the second decoder 175.

[0074] The corrector generation circuit 160 can generate a first corrector RSDR based on codeword CW2 using the first parity check matrix (PCM), and a second corrector SSDR based on codeword CW2 using the second parity check matrix (PCM). It can also generate a decoding mode flag (DMFG) based on the first and second corrector RSDRs. The corrector generation circuit 160 can provide the first and second corrector RSDRs to the first decoder 170, the first corrector RSDR to the second decoder 175, and the decoding mode flag (DMFG) to the selection circuit 179.

[0075] The first decoder 170 can correct chip errors in codeword CW2 based on a first corrector RSDR and a second corrector SSDR to provide a first output dataset DOUT1. The first decoder 170 may correspond to a chip-kill decoder that performs chip-kill. The second decoder 175 can correct one or more symbol errors in codeword CW2 based on the first corrector RSDR to provide a second output dataset DOUT2. The second decoder 175 may correspond to a Reed-Solomon decoder that performs Reed-Solomon decoding. The selection circuit 179 may, in response to the decoding mode flag DMFG, provide the second output dataset DOUT2 as user dataset SDQ or corrected user dataset C_SDQ in the first decoding mode, or provide the first output dataset DOUT1 as user dataset SDQ or corrected user dataset C_SDQ in the second decoding mode.

[0076] Figure 14A Showing according to an example embodiment Figure 13 An example of a corrector generation circuit in an ECC decoder. (See also...) Figure 14A The corrector generation circuit 160 may include a first corrector generator 161, a second corrector generator 163, and a flag generator 165. The first corrector generator 161 can generate a flag by adjusting the codeword CW2 and the first parity check matrix HS. 21 The first corrector RSDR is generated by performing matrix multiplication. The second corrector generator 163 can generate the codeword CW2 and the second parity check matrix HS. 22 Matrix multiplication is performed to generate the second corrector SSDR. In one example, the second corrector generator 163 can generate the SSDR by using the second check matrix HS. 22 A simple parity check is performed on codeword CW2 to generate a second parity check (SSDR). Flag generator 165 can generate an error flag signal (DSF) and a decoding mode flag (DMFG) indicating the type of error in codeword CW2 based on the first parity check (RSDR) and the second parity check (SSDR). Flag generator 165 can provide the error flag signal DSF to... Figure 2The flag generator 165 can determine a logic level of the decode mode flag DMFG according to a type of error in the codeword CW2. For example, the flag generator 165 can output the decode mode flag DMFG having a first logic level specifying a first decode mode in response to the type of error in the codeword CW2 corresponding to one or two symbol errors. For example, the flag generator 165 can output the decode mode flag DMFG having a second logic level specifying a second decode mode in response to the type of error in the codeword CW2 corresponding to three or more symbol errors.

[0077] Figure 14B An example of a first decoder in the ECC decoder of FIG. 1 is shown according to an example embodiment. Referring to FIG. 1, Figure 13 Figure 14B The first decoder 170 can include a sub-syndrome generator 171, a syndrome comparator 172, and a data corrector 173. The sub-syndrome generator 171 can generate a plurality of sub-syndromes SBSDR corresponding to respective data chips in the plurality of data chips based on the second syndrome SSDR and the parity check matrix PCM. The sub-syndrome generator 171 can generate the plurality of sub-syndromes SBSDR by applying the second syndrome SSDR to the parity check matrix PCM. Each sub-syndrome SBSDR can indicate whether a respective one of the plurality of data chips has a symbol error.

[0078] The syndrome comparator 172 can compare the first syndrome RSDR with the sub-syndromes SBSDR corresponding to respective data chips in the plurality of data chips and can provide a comparison signal CS indicating a result of the comparison to the data corrector 173. The first syndrome RSDR can include a plurality of bits indicating locations at which one or more symbol errors occurred. The data corrector 173 receives the codeword CW2 and corrects three or more symbol errors (chip errors) that occurred in the data chips and outputs a first output data set DOUT1. Accordingly, the first decoder 170 can determine data chips in which chip errors occurred among the plurality of data chips based on the comparison of the sub-syndromes SBSDR and the first syndrome RSDR.

[0079] Figure 14C An example of a second decoder in the ECC decoder of FIG. 1 is shown according to an example embodiment. Referring to FIG. 1, Figure 13 Figure 14C ​​The second decoder 175 may include an error locator polynomial (ELP) calculator 176, a Chien search (CHS) block 177, and a data corrector 178. The ELP calculator 176 can calculate the error locator coefficients ELP (coefficients of the error locator polynomial) based on the first corrector RSDR, and can provide the error locator coefficients ELP to the Chien search block 177.

[0080] The Chan search block 177 can search for error locations based on the error location coefficients (ELP) and can provide the data corrector 178 with an error location signal (EPS) indicating the found error location. The data corrector 178 receives the codeword CW2, corrects one or two symbol errors based on the error location signal EPS, and outputs a second output dataset DOUT2.

[0081] Figure 15 Showing according to an example embodiment Figure 13 The operation of the ECC decoder. (Refer to...) Figures 13 to 15 The first decoder 170 and the second decoder 175 check the first corrector (RS corrector) RSDR and the second corrector (SPC corrector) SSDR (operation S110). The first decoder 170 and the second decoder 175 determine whether the codeword CW2 contains errors based on the results of checking the first corrector RSDR and the second corrector SSDR (operation S120).

[0082] When codeword CW2 does not contain errors ("No" in operation S120), ECC decoder 150 outputs user dataset SDQ. When codeword CW2 contains errors ("Yes" in operation S120), first decoder 170 and second decoder 175 determine whether a chip error has occurred by checking the first corrector RSDR and the second corrector SSDR (operation S130). When no chip error has occurred ("No" in operation S130), second decoder 175 corrects multiple errors in symbols in multiple data chips to output corrected user dataset C_SDQ (operation S140).

[0083] When a chip error occurs (Yes in operation S130), the first decoder 170 corrects a symbol error in one data chip (operation S150). If the first decoder 170 fails to correct a symbol error in one data chip (failure in operation S150), the ECC decoder 150 can output a flag signal DSF indicating that the symbol error is not corrected to the CPU 110. If the first decoder 170 corrects a symbol error in one data chip (success in operation S150), the ECC decoder 150 corrects a symbol error associated with another data chip (operation S160) and provides the flag signal DSF to the CPU 110.

[0084] Figures 16A to 18 Various types of errors that the ECC decoder according to an example embodiment can correct are shown. In Figures 16A to 18 , it is assumed that the chips CHIP1 to CHIP8 correspond to Figure 3 data chips 200a to 200k in Figures 16A to 18 , X denotes a symbol error occurring in data on a symbol basis.

[0085] Referring to Figure 16A , when the user data DQ_BL4 output from the chip CHIP4 includes a symbol error X, the second syndrome SSDR indicates one symbol error, and the first syndrome RSDR has a non-zero value. Accordingly, the second decoder 175 can correct one symbol error in the first decoding mode. Referring to Figure 16B , when the user data DQ_BL2 and DQ_BL4 output from the chips CHIP2 and CHIP4 include symbol errors X having the same pattern, the second syndrome SSDR indicates two symbol errors, and the first syndrome RSDR has a non-zero value. Accordingly, the second decoder 175 can correct two symbol errors in the first decoding mode.

[0086] Referring to Figure 16C , when the user data DQ_BL2 and DQ_BL5 output from the chips CHIP2 and CHIP5 include symbol errors X having a random pattern, the second syndrome SSDR indicates two symbol errors, and the first syndrome RSDR has a non-zero value. Accordingly, the second decoder 175 can correct two symbol errors in the first decoding mode. Referring to Figure 16DWhen the user data DQ_BL5 output from the chip CHIP5 includes two symbol errors X with a random pattern, the second syndrome SSDR indicates two symbol errors, and the first syndrome RSDR has a non-zero value. Accordingly, the second decoder 175 can correct two symbol errors in the first decoding mode.

[0087] Referring to Figure 17 When the user data DQ_BL4 output from the chip CHIP4 includes three symbol errors X, the second syndrome SSDR indicates three symbol errors, and the first syndrome RSDR has a non-zero value. Accordingly, the first decoder 170 can correct symbol errors in the user data from one data chip in the second decoding mode.

[0088] Referring to Figure 18 When the user data DQ_BL6 output from the chip CHIP6 includes one symbol error X after three symbol errors included in the user data DQ_BL4 output from the chip CHIP4 are corrected, the first decoder 170 can additionally correct one symbol error in the first decoding mode. The ECC decoder 150 can mark the chip CHIP4 as a marked chip after three symbols are corrected.

[0089] Figure 19 is a table illustrating various types of errors determined by the ECC decoder based on the first syndrome and the second syndrome. Referring to Figure 19 When symbol errors with the same pattern occur in two chips, the second syndrome has a zero value, and the first syndrome RSDR has a non-zero value. When one symbol error occurs in one chip or two symbol errors with a random pattern occur in two chips, the second syndrome SSDR indicates one symbol error or two symbol errors, and the first syndrome RSDR has a non-zero value.

[0090] When three or four symbol errors occur in one chip, the second syndrome SSDR indicates three or four symbol errors, and the first syndrome RSDR has a non-zero value. When one or two symbol errors occur, the ECC decoder 150 can operate in the first decoding mode (e.g., RS mode). When three or four symbol errors occur in one chip, the ECC decoder 150 can operate in the second decoding mode (e.g., chip deletion mode).

[0091] Figure 20 is a flowchart illustrating a method of correcting errors in a memory controller according to an example embodiment. Referring to Figures 1 to 20, a method of correcting an error in a memory controller 100 is provided. According to the method, the memory controller 100 reads a codeword CW2 including a user data set and a parity data set from a memory module MM including a plurality of data chips, a first parity chip, and a second parity chip (operation S210).

[0092] The ECC decoder 150 of the error correction circuit 130 in the memory controller 100 generates a first syndrome RSDR by performing a matrix multiplication operation on the read codeword CW2 and a first check matrix HS of the parity check matrix PCM 21 The matrix multiplication operation is performed to generate a second syndrome SSDR (operation S230). 22 The matrix multiplication operation (e.g., a simple parity check) is performed to generate a second syndrome SSDR (operation S230).

[0093] The ECC decoder 150 determines a type and a decoding mode of an error of the user data set in the codeword CW2 based on the first syndrome RSDR and the second syndrome SSDR (operation S240). The ECC decoder 150 selectively corrects one of a chip error and one or more symbol errors in the read codeword CW2 based on the decoding mode (operation S250).

[0094] Figure 21 is a flowchart illustrating a method of operating a memory system according to an example embodiment, the memory system including a memory module and a memory controller for controlling the memory module. Referring to Figures 1 to 18 and Figure 21 , a method of operating a memory system 20 is provided, the memory system 20 including a memory module MM and a memory controller 100 controlling the memory module MM, the memory module MM including a plurality of data chips, a first parity chip, and a second parity chip. According to the method, an ECC encoder 140 of an error correction circuit 130 in the memory controller 100 performs ECC encoding on a user data set based on a parity generation matrix to generate a parity data set including first parity data and second parity data (operation S310).

[0095] The memory controller 100 stores a codeword CW1 including the user data set and the parity data set in the plurality of data chips, the first parity chip, and the second parity chip (operation S320). The memory controller 100 reads a codeword CW2 including the user data set and the parity data set from the plurality of data chips, the first parity chip, and the second parity chip (operation S330). The ECC decoder 150 of the error correction circuit 130 generates a first syndrome RSDR by performing a matrix multiplication operation on the read codeword CW2 and a first check matrix HS of the parity check matrix PCM 21A matrix multiplication operation is performed to generate a first syndrome RSDR (operation S340).

[0096] The ECC decoder 150 determines a type and a decoding mode of an error of the user data set in the read codeword CW2 based on the first syndrome RSDR and the second syndrome SSDR (operation S360). The ECC decoder 150 selectively corrects one of a chip error and one or more symbol errors in the read codeword CW2 based on the decoding mode (operation S370). 22 A matrix multiplication operation (e.g., simple parity check) is performed to generate a second syndrome SSDR (operation S350). The ECC decoder 150 determines a type and a decoding mode of an error of the user data set in the read codeword CW2 based on the first syndrome RSDR and the second syndrome SSDR (operation S360). The ECC decoder 150 selectively corrects one of a chip error and one or more symbol errors in the read codeword CW2 based on the decoding mode (operation S370).

[0097] Figure 22 is a block diagram illustrating a memory module that a memory system according to an example embodiment can employ. Referring to Figure 22 , the memory module 500 includes a control device 590 (RCD, register clock driver), a plurality of semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d, a plurality of data buffers 541 to 545 and 551 to 555, module resistance units 560 and 570, a serial presence detect (SPD) chip 580, and a power management integrated circuit (PMIC) 585, which are disposed in or mounted on a circuit board 501.

[0098] The control device 590 can control the semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d, and the PMIC 585 under the control of the memory controller 100. For example, the control device 590 can receive an address ADDR, a command CMD, and a clock signal CK from the memory controller 100. The SPD chip 580 can be a programmable read-only memory (e.g., EEPROM). The SPD chip 580 can include device information DI or initial information of the memory module 100. In an example embodiment, the SPD chip 580 can include initial information or device information DI (such as a module form, a module configuration, a storage capacity, a module type, an execution environment, etc. of the memory module 500).

[0099] When the memory system including the memory module 500 is activated, the memory controller 100 can read the device information DI from the SPD chip 580, and can identify the memory module 500 based on the device information DI. The memory controller 100 can control the memory module 500 based on the device information DI from the SPD chip 580. For example, the memory controller 100 can identify the type of the semiconductor memory device included in the memory module 500 based on the device information DI from the SPD chip 580.

[0100] Here, the circuit board 501 as a printed circuit board can extend between the first edge portion 503 and the second edge portion 505 in a second direction D2 perpendicular to the first direction D1. The first edge portion 503 and the second edge portion 505 can extend in the first direction D1.

[0101] The control device 590 can be disposed on the center of the circuit board 501. The plurality of semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d can be arranged in a plurality of rows between the control device 590 and the first edge portion 503 and between the control device 590 and the second edge portion 505. In this case, the semiconductor memory devices 601a to 601e and 602a to 602e can be arranged along a plurality of rows between the control device 590 and the first edge portion 503. The semiconductor memory devices 603a to 603d and 604a to 604d can be arranged along a plurality of rows between the control device 590 and the second edge portion 505. The semiconductor memory devices 601a to 601d, 602a to 602d, 603a to 603d, and 604a to 604d can be referred to as data chips, and the semiconductor memory devices 601e and 602e can be referred to as a first parity chip and a second parity chip, respectively. Each of the plurality of semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d can be coupled to a corresponding one of the data buffers 541 to 545 and 551 to 554 through data transmission lines for receiving / transmitting data signals DQ and data mask signals DQS.

[0102] The control device 590 can provide command / address signals (e.g., CA) to the semiconductor memory devices 601a to 601e through the command / address transmission lines 561, and can provide the command / address signals to the semiconductor memory devices 602a to 602e through the command / address transmission lines 563. In addition, the control device 590 can provide the command / address signals to the semiconductor memory devices 603a to 603d through the command / address transmission lines 571, and can provide the command / address signals to the semiconductor memory devices 604a to 604d through the command / address transmission lines 573.

[0103] The command / address transmission lines 561 and 563 can be commonly connected to the module resistance unit 560 disposed adjacent to the first edge portion 503, and the command / address transmission lines 571 and 573 can be commonly connected to the module resistance unit 570 disposed adjacent to the second edge portion 505.

[0104] Each of the module resistance units 560 and 570 can include a terminal resistor Rtt / 2 connected to a terminal voltage Vtt. In this case, the arrangement of the module resistance units 560 and 570 can reduce the number of module resistance units, thereby reducing the area in which the terminal resistor is disposed. Further, each of the plurality of semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d can be a DRAM device.

[0105] The SPD chip 580 is disposed adjacent to the control device 590, and the PMIC 585 can be disposed between the semiconductor memory device 603d and the second edge portion 505. The PMIC 585 can generate a power supply voltage VDD based on an input voltage VIN, and can supply the power supply voltage VDD to the semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d. Although the PMIC 585 is shown as being disposed adjacent to the second edge portion 505 in Figure 22 , the PMIC 585 can be disposed in a center portion of the circuit board 501 to be adjacent to the control device 590 in an example embodiment.

[0106] Figure 23 is a block diagram illustrating a memory system having a quad-rank memory module according to an example embodiment. Referring to Figure 23 , the memory system 700 can include a memory controller 710 and at least one or more memory modules 720 and 730. The memory controller 710 can control the memory modules 720 and / or 730 to perform commands supplied from a processor or a host. The memory controller 710 can be implemented in the processor or the host, or can be implemented with an application processor or a system on chip (SoC).

[0107] For signal integrity, source termination can be implemented with a resistor RTT on a bus 740 of the memory controller 710. The resistor RTT can be incorporated into a power supply voltage VDDQ. The memory controller 710 can include a transmitter 711 for transmitting signals to the at least one or more memory modules 720 and 730, and a receiver 713 for receiving signals from the at least one or more memory modules 720 and 730. The memory controller 710 can include an error correction circuit 715, and the error correction circuit 715 can employ a low density parity check (LDPC) code.Figure 6 error correction circuit 130.

[0108] Accordingly, the error correction circuit 715 includes an ECC encoder and an ECC decoder, and the ECC decoder can perform ECC decoding on codewords from the at least one or more memory modules 720 and 730 to generate a first syndrome using a first parity check matrix of a parity check matrix and generate a second syndrome using a second parity check matrix of the parity check matrix, can determine a type and a decoding mode of errors in the codewords based on the first syndrome and the second syndrome, and can correct a plurality of errors in a plurality of chips or three or more symbol errors in one chip based on the decoding mode.

[0109] The at least one or more memory modules 720 and 730 can be referred to as a first memory module (MODULE1) 720 and a second memory module (MODULE2) 730. The first memory module 720 and the second memory module 730 can be coupled to the memory controller 710 through a bus 740. Each of the first memory module 720 and the second memory module 730 can correspond to a memory module MM in Figure 1 The first memory module 720 can include at least one or more memory ranks RK1 and RK2, and the second memory module 730 can include one or more memory ranks RK3 and RK4. Each of the first memory module 720 and the second memory module 730 can include a plurality of data chips, a first parity chip, and a second parity chip.

[0110] Figure 24 is a block diagram illustrating a mobile system 900 including a memory module according to an example embodiment. Referring to Figure 24 , the mobile system 900 can include an application processor (AP) 910, a connection module 920, a memory module 950, a non-volatile memory device (NVM) 940, a user interface 930, and a power supply 970. The application processor 910 can include a memory controller (MCT) 911. The application processor 910 can execute an application such as a web browser, a game application, a video player, etc. The connection module 920 can perform wired or wireless communication with an external device.

[0111] The memory module (MM) 950 can store data processed by the application processor 910 or operate as a working memory. The memory module 950 can include a plurality of semiconductor memory devices (MDs) 951, 952, 953, and 95q (where q is a positive integer greater than three) and a control device 961 (RCD).

[0112] The semiconductor memory devices 951, 952, 953,..., 95q can include a plurality of data chips, a first parity chip, and a second parity chip. Thus, the memory controller 911 can perform ECC decoding on a codeword from the memory module 950 to generate a first coset using a first parity check matrix of the parity check matrix and generate a second coset using a second parity check matrix of the parity check matrix, can determine a type and a decoding mode of errors in the codeword based on the first coset and the second coset, and can correct a plurality of errors in a plurality of chips or three or more symbol errors in one chip based on the decoding mode.

[0113] The non-volatile memory device 940 can store a boot image for booting the mobile system 900. The user interface 930 can include at least one input device (such as a keypad, a touch screen, etc.) and at least one output device (e.g., a speaker, a display device, etc.). The power supply 970 can provide operating voltages to the mobile system 900. The mobile system 900 or components of the mobile system 900 can be mounted using various types of packaging.

[0114] Example embodiments can be applied to various systems including a memory module and a memory controller including an error correction circuit.

[0115] While the disclosure has been particularly shown and described with reference to example embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the disclosure as defined by the following claims.

Claims

1. An error correction circuit, comprising: The error correction code decoder is configured as follows: The codewords read from the memory module are decoded using error correction codes to generate a first corrector and a second corrector. Based on the first and second correctors, a decoding mode flag is generated that is associated with the type of one or more errors in the codeword; Operates in one of the first and second decoding modes based on the decoding mode flag; as well as Selectively correct one or more symbol errors in a codeword or chip errors in a codeword, where the chip errors are associated with the data chip in the memory module. In response to the type of error in the codeword corresponding to one or two symbol errors, a decoding mode flag with a first logic level specifying the first decoding mode is output; In response to an error type in the codeword corresponding to three or more symbol errors, a decoding mode flag with a second logic level specifying the second decoding mode is output.

2. The error correction circuit according to claim 1, wherein, The error correction code decoder is also configured as follows: In response to the second corrector indicator codeword including a sign error and the first corrector being non-zero, operation is performed in the first decoding mode; and Correct the aforementioned symbol error.

3. The error correction circuit according to claim 1, wherein, The error correction code decoder is also configured as follows: In response to the second corrector indicator codeword including two symbol errors of the same pattern and the first corrector being nonzero, operation is performed in the first decoding mode; and Correct the two symbol errors mentioned above.

4. The error correction circuit according to claim 1, wherein, The error correction code decoder is also configured as follows: In response to the second corrector indicating codeword including two symbol errors with different and random patterns and the first corrector being non-zero, operation is performed in the first decoding mode; and Correct the two symbol errors mentioned above.

5. The error correction circuit according to claim 1, wherein, The error correction code decoder is also configured as follows: In response to the second corrector indicator codeword including three or more symbol errors and the first corrector being non-zero, operation is performed in the second decoding mode, which corresponds to the chip deletion mode; It was determined that the three or more symbol errors occurred in the first data chip within the memory module; as well as Correct the user data provided from the first data chip.

6. The error correction circuit as described in claim 5, wherein, When a symbol error occurs in a second data chip, which is different from the first data chip, within the memory module, the error correction code decoder operates in a first decoding mode to use a parity check matrix to correct the symbol error in the user data provided from the second data chip after the error correction code decoder has corrected the three or more symbol errors in the user data provided from the first data chip.

7. The error correction circuit according to any one of claims 1 to 6, wherein, The memory module includes multiple data chips, a first parity check chip, and a second parity check chip. The codewords include the user dataset, the first parity check data, and the second parity check data. User datasets are read from the multiple data chips; The first parity check data is read from the first parity check chip; and The second parity check data is read from the second parity check chip, and The parity check matrix in the memory of the error correction circuit includes: The first parity-check matrix, generated based on Reed-Solomon codes and used to generate the first corrector; and The second parity check matrix is ​​generated based on a simple parity check code and is used to generate the second corrector.

8. The error correction circuit according to claim 7, wherein, The error correction code decoder is also configured as follows: The first corrector is generated by performing matrix multiplication on the codeword and the first parity check matrix; and The second corrector is generated by performing a simple parity check on the codeword using the second parity check matrix.

9. The error correction circuit according to claim 7, wherein, The first parity check matrix includes multiple Galois submatrices corresponding to the multiple data chips and the first parity check chip, and each Galois submatrice in the multiple Galois submatrices has p×p elements, where p is an integer greater than 3; and The second parity check matrix includes multiple unit sub-matrices corresponding to the plurality of data chips, the first parity check chip, and the second parity check chip, and each of the plurality of unit sub-matrices has p×p elements.

10. The error correction circuit according to claim 9, wherein, Each of the plurality of identity submatrices comprises a plurality of identity matrices arranged diagonally, and each of the plurality of identity matrices has q×q elements, where q is an integer greater than 1 and less than p.

11. The error correction circuit according to any one of claims 1 to 6, wherein, Error correction code decoders include: The corrector generation circuit is configured to: generate a first corrector based on a codeword using a first parity check matrix, generate a second corrector based on a codeword using a second parity check matrix, and generate a decoding mode flag based on the first and second correctors; The first decoder is configured to correct chip errors in codewords based on a first and a second corrector to provide a first output dataset; The second decoder is configured to: correct one or more symbol errors in the codeword based on the first corrector to provide a second output dataset; and The selection circuit is configured to select one of the first and second output datasets to output the corrected user dataset.

12. The error correction circuit according to claim 11, wherein, The corrector generation circuit includes: The first corrector generator is configured to generate the first corrector by performing matrix multiplication on the codeword and the first parity check matrix; The second parity generator is configured to generate the second parity by performing a simple parity check on the codeword using the second parity check matrix; and The flag generator is configured to generate a decoding mode flag indicating the type of error based on the first and second correctors.

13. The error correction circuit according to claim 11, wherein, The memory module includes multiple data chips. The first decoder is configured as follows: Based on the second corrector and the parity check matrix, generate multiple sub-correctors corresponding to the corresponding data chips among the plurality of data chips; and Based on the comparison between the plurality of sub-correctors and the first corrector, the data chip among the plurality of data chips that has experienced a chip error is determined.

14. The error correction circuit according to any one of claims 1 to 6, further comprising: The error correction code encoder is configured as follows: The user dataset is encoded using a parity generation matrix to generate first and second parity data. as well as The memory module is provided with codewords that include the user dataset, the first parity data, and the second parity data.

15. The error correction circuit as described in claim 14, wherein, The parity check generation matrix includes a first parity check generation matrix and a second parity check generation matrix; wherein, the error correction code encoder is configured as follows: The first parity check data is generated by performing matrix multiplication on the user dataset and the first parity check generation matrix; and Second parity data is generated by performing a simple parity check on the user dataset and the first parity data using a second parity generation matrix.

16. A memory system, comprising: The memory module has multiple data chips, a first parity check chip, and a second parity check chip. as well as A memory controller, configured to control a memory module, includes: error correction circuitry containing an error correction code decoder and a memory configured to store a parity check matrix. The error correction code decoder is configured as follows: The codewords read from the memory module are decoded using error correction codes to generate a first corrector and a second corrector. A decoding mode flag is generated based on the first and second correctors, which is associated with the type of error in the codeword. Operating under one of the first and second decoding modes based on the decoding mode flag; and Selectively correct one or more symbol errors in a codeword or chip errors in a codeword, wherein the chip error is associated with one of the plurality of data chips. In response to an error type in the codeword corresponding to one or two symbol errors, a decoding mode flag with a first logic level specifying the first decoding mode is output; in response to an error type in the codeword corresponding to three or more symbol errors, a decoding mode flag with a second logic level specifying the second decoding mode is output.

17. The memory system according to claim 16, wherein, The error correction code decoder is configured as follows: In response to the second corrector indicator codeword including one or two symbol errors and the first corrector being non-zero, operation is performed in the first decoding mode; and Correct one or both of the aforementioned symbol errors to output the corrected user dataset.

18. The memory system according to claim 16, wherein, The error correction code decoder is configured as follows: In response to the second corrector indicator codeword including three or more symbol errors and the first corrector being non-zero, operation is performed in the second decoding mode, which corresponds to the chip deletion mode; It is determined that the three or more symbol errors occurred in the first data chip among the plurality of data chips; as well as Correct the user data provided from the first data chip.

19. The memory system according to any one of claims 16 to 18, wherein, The parity check matrix includes: The first parity-check matrix, generated based on Reed-Solomon codes and used to generate the first corrector; and The second parity check matrix is ​​generated based on a simple parity check code and is used to generate the second corrector. The error correction code decoder includes: The corrector generation circuit is configured to: generate a first corrector based on a codeword using a first parity check matrix, generate a second corrector based on a codeword using a second parity check matrix, and generate a decoding mode flag based on the first and second correctors; The first decoder is configured to correct chip errors in codewords based on a first and a second corrector to provide a first output dataset; The second decoder is configured to: correct one or more symbol errors in the codeword based on the first corrector to provide a second output dataset; and The selection circuit is configured to select one of the first and second output datasets to output the corrected user dataset.

20. A memory controller configured to control a memory module including a plurality of data chips, a first parity chip, and a second parity chip, the memory controller comprising: The error correction circuit includes an error correction code encoder, an error correction code decoder, and a memory, wherein the memory is configured to store a parity check generation matrix and a parity check matrix. The error correction encoder is configured as follows: Error-correcting coding is performed on the user dataset using a parity generation matrix to generate first and second parity data; and Provide the memory module with codewords including user dataset, first parity data, and second parity data; The error correction code decoder is configured as follows: The codewords read from the memory module are decoded using error correction codes to generate a first corrector and a second corrector. A decoding mode flag associated with the type of error in the codeword is generated based on the first and second correctors; Operating under one of the first and second decoding modes based on the decoding mode flag; and Selectively correct one or more symbol errors in a codeword or chip errors in a codeword, wherein the chip error is associated with one of the plurality of data chips. In response to an error type in the codeword corresponding to one or two symbol errors, a decoding mode flag with a first logic level specifying the first decoding mode is output; in response to an error type in the codeword corresponding to three or more symbol errors, a decoding mode flag with a second logic level specifying the second decoding mode is output.

Images