Method for forming semiconductor device

Abstract

A method for forming a semiconductor device includes: providing a target etching layer, sequentially forming an initial mask layer, an anti-reflection layer, and a patterned structure on the target etching layer; using the patterned structure as a mask, performing a first etching on the anti-reflection layer to remove a portion of the thickness of the anti-reflection layer; performing a surface treatment on the patterned structure; and performing a second etching on the anti-reflection layer until the surface of the initial mask layer is exposed. The method for forming a semiconductor device provided by the present invention can improve the line width roughness of the finally formed etching pattern, while ensuring that the etching pattern is consistent with the expected target size.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor device. Background Art

[0002] The process flow of semiconductor manufacturing technology includes two important process steps: photolithography and etching. In the photolithography process, the photoresist is first spin-coated on the substrate, and then the spin-coated photoresist is soft-dried to make it a solid film; then the photoresist is exposed and developed to form the desired photolithography pattern in the photoresist; then the substrate is etched using the photolithography pattern as a mask to transfer the photolithography pattern to the substrate.

[0003] With the advancement of semiconductor manufacturing technology, semiconductor devices are developing towards higher integration in order to achieve faster computing speeds, larger data storage capacity and more functions. The higher the integration of semiconductor chips, the smaller the critical dimension (CD) of semiconductor devices. The photolithography process, which plays an important role in CD control, has been challenged unprecedentedly. The distance between the edges of the lithography pattern formed after photolithography is called line width (LineWidth). Line width roughness (LWR, Line Width Roughness) and line edge roughness (LER, Line Edge Roughness) are one of the important indicators for measuring line width. Line width roughness determines the line width of CD to a certain extent, so the importance of LWR control is becoming increasingly apparent.

[0004] As line widths continue to shrink, current improvements in line width roughness may adversely affect the performance of semiconductor devices. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor device, which can improve the line width roughness of a patterned structure, thereby improving the performance of the semiconductor device.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor device, comprising: providing a target etching layer, and sequentially forming an initial mask layer, an anti-reflection layer, and a patterned structure on the target etching layer; using the patterned structure as a mask, performing a first etching on the anti-reflection layer to remove a portion of the thickness of the anti-reflection layer; performing surface treatment on the patterned structure; and performing a second etching on the anti-reflection layer until the surface of the initial mask layer is exposed.

[0007] Optionally, a plasma process is used to perform surface treatment on the patterned structure.

[0008] Optionally, the process gas of the plasma process includes HBr or H2 or Ar.

[0009] Optionally, when the process gas is HBr, the process parameters of the plasma process include a flow rate of 30 to 500 sccm of HBr gas, a pressure of 3 to 100 mTorr, and a power of 50 to 1000 watts.

[0010] Optionally, the anti-reflection layer is an inorganic anti-reflection layer or an organic anti-reflection layer.

[0011] Optionally, the thickness of the portion of the anti-reflection layer removed by the first etching accounts for 5% to 95% of the thickness of the anti-reflection layer.

[0012] Optionally, the first etching and the second etching are both dry etching.

[0013] Optionally, the process parameters of the first etching and the second etching are the same, and the process parameters include: the etching gas includes CH x F y A combination of one or more gases, wherein x is a natural number greater than or equal to 0, y is a natural number greater than or equal to 1, and x+y=4, the etching pressure is 5 to 100 mTorr, and the etching power is 100 to 1200 watts.

[0014] Optionally, the graphic structure has a first roughness; after surface treatment of the graphic structure, the first roughness of the graphic structure is changed to a second roughness, and the second roughness is smaller than the first roughness.

[0015] Optionally, after the surface of the initial mask layer is exposed, the method further includes: etching the initial mask layer using the patterned structure and the anti-reflection layer as masks to form a patterned mask layer.

[0016] Optionally, the method further includes: using the patterned mask layer as a mask to etch the target etching layer to form a target pattern layer.

[0017] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0018] Before surface treatment of the patterned structure, the anti-reflection layer is etched for the first time using the patterned structure as a mask to remove part of the thickness of the anti-reflection layer. Since the surface treatment process mainly makes the molecules of the patterned structure grow again and become smooth, the anti-reflection layer has little effect. Therefore, the spacing of the patterned structure is fixed by the anti-reflection layer at the bottom of the patterned structure to avoid the line width change of the patterned structure due to displacement after the surface treatment. When the morphology and size of the patterned structure after the surface treatment are subsequently transferred to the target etching layer, on the one hand, the line width roughness of the pattern formed by etching is improved; on the other hand, the size of the pattern formed by etching is guaranteed to be consistent with the expected target, thereby improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figures 1 to 3 is a structural schematic diagram of a semiconductor device forming process in one embodiment;

[0020] Figures 4 to 9 It is a schematic structural diagram corresponding to each step of a semiconductor device forming process in one embodiment of the present invention. DETAILED DESCRIPTION

[0021] As known from the background technology, the line width roughness of the photoresist layer is one of the important factors affecting the performance of semiconductor devices.

[0022] Figures 1 to 3 It is a structural schematic diagram of a semiconductor device forming process in one embodiment.

[0023] refer to Figure 1 , providing a layer to be etched 10 , an initial mask layer 20 located on the layer to be etched 10 , an anti-reflection layer 30 located on the initial mask layer 20 , and a patterned structure 40 located on the anti-reflection layer 30 .

[0024] refer to Figure 2 , performing surface treatment on the patterned structure 40 so that the first roughness of the patterned structure 40 is changed into a second roughness, and the second roughness is smaller than the first roughness.

[0025] refer to Figure 3 , using the patterned structure 40 as a mask, etching the anti-reflection layer 30 until the surface of the initial mask layer 20 is exposed.

[0026] Subsequently, the initial mask layer 20 is etched using the patterned structure 40 and the anti-reflection layer 30 as masks to form a patterned mask layer (not shown); and then the layer to be etched is etched using the patterned mask layer as a mask to form an etched layer (not shown).

[0027] The inventors have analyzed and found that in the above method for forming a semiconductor device, the patterned structure 40 is first subjected to surface treatment. When the patterned structure 40 is subjected to surface treatment, the surface treatment occurs not only on the sidewalls of the patterned structure 40, but also on the bottom of the patterned structure 40. Since the surface treatment causes the molecules on the surface of the patterned structure to grow again, thereby reducing the roughness of the patterned structure, after the molecules at the bottom of the patterned structure 40 grow again and become smooth, the patterned structure 40 is easily displaced, which changes the line width of the patterned structure (refer to Figure 1 and Figure 2 ), the morphology and size of the graphic structure 40 after surface treatment are subsequently transferred to the layer to be etched 10, which will cause the final pattern to be inconsistent with the target etching pattern, thereby affecting the performance of the semiconductor device.

[0028] In order to solve the above problems, the inventors have provided a method for forming a semiconductor device after research. First, a patterned structure is used as a mask to etch a partial thickness of an anti-reflection layer, and then the patterned structure is surface treated. On the one hand, surface treatment of the patterned structure is beneficial to improving the line width roughness. When the morphology of the patterned structure is subsequently transferred to the target etching layer, the line width roughness of the formed etched pattern can be improved. On the other hand, because the surface treatment has a smaller effect on the anti-reflection layer, the line width of the patterned structure is fixed by the partial thickness of the anti-reflection layer at the bottom of the patterned structure, thereby preventing the patterned structure from shifting during surface treatment. When the morphology and size of the patterned structure are transferred to the target etching layer, the change in the line width of the patterned structure can avoid a large size difference between the etched pattern and the target pattern, thereby improving the performance of the semiconductor device.

[0029] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0030] Figures 4 to 9 It is a schematic structural diagram corresponding to each step of a semiconductor device forming process in one embodiment of the present invention.

[0031] refer to Figure 4 , providing a target etching layer 100 , and sequentially forming an initial mask layer 101 , an anti-reflection layer 102 and a patterned structure 103 on the target etching layer 100 .

[0032] The material of the target etching layer 100 includes one or more combinations of a dielectric layer, a metal layer and a semiconductor substrate.

[0033] In this embodiment, the material of the target etching layer 100 is a low-K dielectric material (a low-K dielectric material refers to a dielectric material with a relative dielectric constant greater than or equal to 2.6 and less than 3.9) or an ultra-low-K dielectric material (an ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant less than 2.6). When the material of the target etching layer 200 is a low-K dielectric material or an ultra-low-K dielectric material, the material of the target etching layer 200 is SiOH, SiCOH, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), BPSG (boron-phosphorus-doped silicon dioxide), hydrogenated silsesquioxane (HSQ, (HSiO1.5)n) or methyl silsesquioxane (MSQ, (CH3SiO1.5)n). In this embodiment, the material of the target etching layer 200 is an ultra-low-K dielectric material, and the ultra-low-K dielectric material is SiCOH.

[0034] In other embodiments, the target etching layer 100 may also be a dielectric material such as silicon oxide, silicon nitride, or a conductive material such as titanium nitride.

[0035] The method of forming the initial mask layer 101 includes one or more combinations of spin coating, low-temperature chemical vapor deposition or atomic layer deposition.

[0036] In this embodiment, the initial mask layer 101 is formed by spin coating.

[0037] The anti-reflection layer 102 is used to eliminate the influence of reduced exposure accuracy caused by standing waves during the exposure process of forming the patterned structure 103.

[0038] In one embodiment, the anti-reflection layer 102 is a developer-soluble anti-reflection layer.

[0039] In another embodiment, the anti-reflective layer can also be a photosensitive soluble anti-reflective layer, also known as a photoimageable anti-reflective layer; in one type of photosensitive soluble anti-reflective layer, the anti-reflective layer 102 becomes soluble in a developer after exposure; in another type of photosensitive soluble anti-reflective layer, the anti-reflective layer 102 becomes insoluble in a developer after exposure.

[0040] The material of the anti-reflection layer 102 includes an inorganic anti-reflection material or an organic anti-reflection material.

[0041] When the material of the anti-reflection layer 102 is an inorganic anti-reflection material, it includes silicon dioxide, carbon-doped silicon dioxide, or nitrogen-doped silicon dioxide. In this embodiment, the material of the anti-reflection layer 102 is silicon dioxide.

[0042] When the material of the anti-reflection layer 102 is an organic anti-reflection material, it may be a silicon-containing anti-reflection layer, or an organic anti-reflection layer modified with other elements, or an unmodified organic anti-reflection layer.

[0043] In this embodiment, the anti-reflection layer 102 is formed by chemical vapor deposition. In other embodiments, when the anti-reflection layer 102 is an organic anti-reflection material, it can also be formed on the initial mask layer 101 by spin coating.

[0044] In this embodiment, the patterned structure 103 is a patterned photoresist layer, and the patterned photoresist layer has a first roughness.

[0045] In this embodiment, the first roughness is a first line width roughness.

[0046] The patterned photoresist layer includes positive photoresist or negative photoresist.

[0047] In this embodiment, the step of forming the patterned photoresist layer includes: forming an initial photoresist film (not shown) on the anti-reflection layer 102 by a spin coating process; and performing exposure and development treatment on the initial photoresist film to form a patterned photoresist layer.

[0048] In this embodiment, the patterned structure 103 defines the morphology and size of the target etching layer 100 to be subsequently etched, and the morphology and size of the patterned structure 103 are subsequently transferred to the target etching layer 100 .

[0049] refer to Figure 5 , using the patterned structure 103 as a mask, performing a first etching on the anti-reflection layer 102 to remove a portion of the thickness of the anti-reflection layer 102 .

[0050] In this embodiment, the thickness h of the portion of the anti-reflection layer 102 removed by the first etching accounts for 5% to 95% of the thickness H of the anti-reflection layer 102 .

[0051] In the present embodiment, the anti-reflection layer 102 is first etched away with a portion of its thickness, and then surface treatment is performed because: surface treatment will cause the molecules on the sidewalls and bottom of the patterned structure 103 to regrow, which may easily cause the patterned structure 103 to shift, but surface treatment has little effect on the molecules on the surface of the anti-reflection layer 102. A portion of the anti-reflection layer 102 is first etched away, and the line width of the patterned structure 103 is transferred to the anti-reflection layer 102. In the subsequent surface treatment, the line width is kept unchanged by the anti-reflection layer 102, and then transferred to the target etching layer 100, to ensure that the obtained pattern is consistent with the target pattern size.

[0052] If the thickness of the anti-reflection layer 102 removed by the first etching is too much, the remaining anti-reflection layer 102 is too thin, and after surface treatment, the morphology of the patterned structure 103 with improved line width roughness cannot be well transferred to the target etching layer, resulting in the line width roughness of the pattern formed after etching cannot be improved; if the thickness of the anti-reflection layer 102 removed by the first etching is too little, it is still possible to cause the patterned structure 103 to shift or change during the surface treatment process, and ultimately cause the pattern formed after etching to be inconsistent with the expected target size. Therefore, the thickness of the part of the anti-reflection layer 102 removed by the first etching accounts for 5% to 95% of the thickness of the anti-reflection layer 102.

[0053] In this embodiment, the first etching method is a dry etching process, and the process parameters of the dry etching process include: the etching gas includes CH x F y One or more combinations of the gases, the etching pressure is 5 to 100 mTorr, and the etching power is 100 to 1200 watts.

[0054] In this embodiment, x and y are natural numbers, and x+y=4, x=0, 1, 2 or 3, and the CH x F y Gases including CF 4 , CHF 3 , CH 2 F 2 , CH 3 F, the etching gas includes CF 4 , CHF 3 , CH 2 F 2 , CH 3 A combination of one or more gases in F.

[0055] Figure 6 yes Figure 5 A schematic diagram of the top view of the graphical structure shown, Figure 7 3 is a schematic diagram of a top view of the graphic structure after surface treatment.

[0056] refer to Figure 6 , the patterned structure 103 has a first roughness.

[0057] refer to Figure 7 After the anti-reflection layer 102 is etched for the first time, the patterned structure 103 is surface treated so that the first roughness of the patterned structure 103 is changed to a second roughness, and the second roughness is smaller than the first roughness.

[0058] In this embodiment, the patterned structure 103 is surface treated to improve the line width roughness of the patterned structure 103, and the morphology of the patterned structure 103 after the surface treatment is transferred to the target etching layer 100, which is beneficial to improve the line width roughness of the pattern after etching, thereby helping to improve the electrical performance of the semiconductor device.

[0059] In this embodiment, the surface treatment method is a plasma treatment process, which generates plasma and excites ultraviolet light and heat during the process of forming plasma.

[0060] The process gas of the plasma process includes HBr or H 2 or Ar.

[0061] In this embodiment, the process gas of the plasma process is HBr. In the plasma-generated HBr, the vacuum ultraviolet light can change the molecular structure on the surface of the patterned structure 103, thereby reducing the glass transition temperature of the patterned structure 103, causing the molecules on the surface of the patterned structure 103 to partially reflow and produce a flattening effect, thereby reducing the line width roughness.

[0062] In this embodiment, the process parameters of the plasma process include: a flow rate of HBr gas of 30 to 500 sccm, a pressure of 3 to 100 mTorr, and a power of 50 to 1000 watts.

[0063] refer to Figure 8 After the surface treatment is completed, the anti-reflection layer 102 is etched for the second time until the surface of the initial mask layer 101 is exposed.

[0064] In this embodiment, the second etching is dry etching, and the process parameters of the second etching are the same as those of the first etching, including: the etching gas includes CH x F y One or more combinations of the gases, the etching pressure is 5 to 100 mTorr, and the etching power is 100 to 1200 watts.

[0065] In this embodiment, after the patterned structure 103 is surface treated, the remaining anti-reflection layer 102 is further etched, and the patterned structure with improved line width roughness after the surface treatment is transferred to the remaining anti-reflection layer 102, and then further transferred to the target etching layer, thereby improving the line width roughness of the pattern finally formed by etching.

[0066] refer to Fig. 9After the surface of the initial mask layer 101 is exposed, the forming method further comprises: using the patterned structure 103 and the anti-reflection layer 102 as masks, etching the initial mask layer 101 to form a patterned mask layer 201.

[0067] In this embodiment, the method for etching the initial mask layer 101 is a dry etching process, and the process parameters of the dry etching process include: the etching gas includes sulfur dioxide and oxygen or sulfur dioxide and nitrogen, the gas flow rate is 10 to 500 sccm, the etching pressure is 10 to 50 mTorr, and the etching power is 100 to 1200 watts.

[0068] In this embodiment, after the patterned mask layer 201 is formed, the target etching layer 100 is etched using the patterned mask layer 210 as a mask to form a target patterned layer (not shown).

[0069] The etching process for etching the target etching layer 100 may be selected according to the material of the target etching layer 100 .

[0070] In one embodiment, when the material of the target etching layer 100 is silicon oxide or silicon nitride, the target etching layer 100 is etched by a dry etching process, and the process parameters of the dry etching process include: the etching gas includes CH x F y A combination of one or more gases, wherein x is a natural number greater than or equal to 0, y is a natural number greater than or equal to 1, and x+y=4, the etching pressure is 5 to 100 mTorr, and the etching power is 100 to 1200 watts.

[0071] In this embodiment, the morphology and line width of the patterned structure 103 are transferred to the target etching layer 100 through the anti-reflection layer 102 and the patterned mask layer 101, so that the line width roughness of the target graphic layer finally formed by etching is improved, and the line width is consistent with the preset line width, thereby improving the performance of the semiconductor device.

[0072] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, It is characterized in that include: Providing a target etching layer, and sequentially forming an initial mask layer, an anti-reflection layer, and a patterned structure on the target etching layer, wherein the patterned structure has a first roughness; Using the patterned structure as a mask, the anti-reflection layer is first etched to remove a portion of the anti-reflection layer, wherein the portion of the anti-reflection layer removed by the first etching accounts for 5% to 95% of the thickness of the anti-reflection layer; Performing surface treatment on the patterned structure so that the first roughness of the patterned structure changes to a second roughness, wherein the second roughness is smaller than the first roughness; The anti-reflection layer is etched for a second time until the surface of the initial mask layer is exposed, and the process parameters of the first etching and the second etching are the same, and the process parameters include: the etching gas includes CH x F y A combination of one or more gases, wherein x is a natural number greater than or equal to 0, y is a natural number greater than or equal to 1, and x+y=4, the etching pressure is 5~100 mTorr, and the etching power is 100~1200 watts.

2. The method for forming a semiconductor device according to claim 1, It is characterized in that The patterned structure is surface treated by a plasma process.

3. The method for forming a semiconductor device according to claim 2, It is characterized in that The process gas of the plasma process includes HBr or H 2 or Ar.

4. The method for forming a semiconductor device according to claim 3, It is characterized in that When the process gas is HBr, the process parameters of the plasma process include: a flow rate of HBr gas of 30-500 sccm, a pressure of 3-100 mTorr, and a power of 50-1000 watts.

5. The method for forming a semiconductor device according to claim 1, It is characterized in that The anti-reflection layer is an inorganic anti-reflection layer or an organic anti-reflection layer.

6. The method for forming a semiconductor device according to claim 1, It is characterized in that The first etching and the second etching are both dry etching.

7. The method for forming a semiconductor device according to claim 1, It is characterized in that After the surface of the initial mask layer is exposed, the method further includes: using the patterned structure and the anti-reflection layer as masks, etching the initial mask layer to form a patterned mask layer.

8. The method for forming a semiconductor device according to claim 7, It is characterized in that Also includes: The target etching layer is etched using the patterned mask layer as a mask to form a target pattern layer.

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