A packaging structure with an intermediate layer

Abstract

An embodiment of the present invention provides a packaging structure with an interposer, relating to the field of integrated circuit chip technology. The packaging structure includes: an active interposer; M small chips located above the active interposer and fixedly connected to the active interposer, and the M small chips are electrically connected to each other; a passive interposer located below the passive interposer and fixedly connected to the active interposer; a packaging substrate located below the passive interposer and fixedly connected to the passive interposer; wherein M is a positive integer greater than 1. The above scheme of the present invention combines the advantages of the passive interposer and the active interposer, which can not only save chip area, but also reduce production costs and improve production yield.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit chips, and in particular to a packaging structure with an intermediate layer. Background Art

[0002] With the slowdown of Moore's Law and the increase in semiconductor area costs, new architectures and packaging technologies have emerged, enabling system improvements through transistor process scaling. In recent years, multi-die integration has garnered significant attention. Unlike modern system-on-a-chip (SOC) systems, which are monolithically manufactured on a single large chip, chip-level integration integrates multiple semiconductor chips (each manufactured separately) into a single package.

[0003] Historically, multi-chip module (MCM) packaging has been used to integrate multiple chiplets onto a single substrate, providing a platform for chiplet integration. However, compared to on-chip interconnects, coarse-pitch substrate interconnects can only provide limited bandwidth, thereby reducing efficiency and increasing latency. However, these limitations can be addressed by using fine-pitch silicon interposers, which have been used in commercial products to integrate 3D high-bandwidth memory. Today, interposer technology is mainly divided into passive interposers and active interposers.

[0004] Traditionally, the Network on Chip (NOC) is deployed on the bare die within the chip, which creates two problems: on the one hand, the network bandwidth is related to the number and density of metal layers on the chiplet, and adding metal layers will increase chip cost and yield; on the other hand, the Network on Chip consumes a large amount of interconnection resources between chiplets.

[0005] If a passive interposer is used to deploy a NOC, the router component must be placed in the chiplet, which reduces the yield and increases the cost of chip area. If an active interposer is used, that is, active components (such as routers or repeaters) are deployed in the interposer, the manufacturing cost is several times that of a passive interposer. In addition, as the size of the active interposer silicon wafer increases, the production yield decreases, further increasing costs. Summary of the Invention

[0006] The present invention provides a packaging structure with an interposer, so as to solve, to a certain extent, the problem that deploying NOC in the existing interposer technology will reduce the yield and increase the manufacturing cost.

[0007] An embodiment of the present invention provides a package structure with an interposer, the package structure comprising:

[0008] Active interposer;

[0009] M small chips are located above the active interposer and fixedly connected to the active interposer, and the M small chips are electrically connected to each other;

[0010] a passive interposer, located below the active interposer and fixedly connected to the active interposer;

[0011] A packaging substrate, located below the passive interposer and fixedly connected to the passive interposer;

[0012] Wherein, M is a positive integer greater than 1.

[0013] Optionally, each of the M chiplets includes a first routing device, and the M chiplets are interconnected through the first routing device.

[0014] Optionally, each of the M chiplets is wrapped with a packaging material.

[0015] The first routing devices in different chiplets are interconnected by first conductive lines passing through the packaging material.

[0016] Optionally, when the number of first routing devices included in the target chiplet among the M chiplets is N, the N first routing devices are electrically connected;

[0017] Wherein, N is a positive integer greater than 1.

[0018] Optionally, the active interposer includes: a second routing device;

[0019] The second routing device is electrically connected to the first routing device.

[0020] Optionally, a through silicon via is provided in the active interposer;

[0021] The second routing device is electrically connected to the first routing device through the through-silicon via.

[0022] Optionally, there are multiple second routing devices, and the multiple second routing devices are electrically connected to each other.

[0023] Optionally, the passive interposer layer includes metal links, and the plurality of second routing devices are electrically connected via the metal links.

[0024] Optionally, the number of the second routing components is greater than or equal to the number of the first routing components.

[0025] Optionally, both the active interposer and the passive interposer are silicon interposers.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] In an embodiment of the present invention, M small chips are arranged above the active interposer and fixedly connected to the active interposer, and a passive interposer is arranged below the active interposer and fixedly connected to the active interposer. Combining the advantages of the passive interposer and the active interposer can not only save the chip area but also reduce production costs and improve production yield.

[0028] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for describing the embodiments.

[0030] Figure 1 This is a schematic diagram of the structure of deploying NOC using a passive intermediary layer in the existing technology;

[0031] Figure 2 This is a schematic diagram of the structure of deploying NOC using an active interposer in the prior art;

[0032] Figure 3 A schematic diagram of a packaging structure using an active interposer in the prior art;

[0033] Figure 4 Schematic diagram of a 3D structure of an on-chip network based on an active interposer in the prior art;

[0034] Figure 5 A schematic diagram of the packaging structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0036] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0037] When describing the embodiments of the present invention, some prior arts are first described in detail.

[0038] Existing technologies utilize fine-pitch silicon interposers, such as those used in the 65nm process node, and use fine-pitch microbumps (e.g., micro-bumps) to bond each chiplet. Leveraging interposer integration, the system can achieve the yield and flexibility advantages of multi-chiplet integration while maintaining the network-on-chip (NOC) structure used to connect modules in modern SOCs.

[0039] Today, the passive interposer used in interposer technology contains only metal interconnects but no active complementary metal-oxide-semiconductor (CMOS) transistors. Active interposer technology, used in interposer technology, is an alternative to passive interposers. In this interposer, the active interposer is manufactured using a standard CMOS process with the addition of die thinning and through-silicon via (TSV) insertion technology. Active interposers can provide high-speed relay links and move the NOC router to the interposer, providing more network bandwidth than is possible on a monolithic SOC.

[0040] Deploying NOC using a passive interposer can improve bandwidth, but the passive interposer only contains metal connections and does not contain active semiconductor devices such as routers, repeaters, or first-in-first-out (FIFO) queues. Therefore, it can only provide point-to-point connections between chiplets without relays. That is, the interconnection between chiplets uses metal traces embedded in the passive interposer, which is coupled to the microbumps of the two chiplets. Each microbump can be used to send a single signal, thus achieving high-bandwidth and low-latency connections.

[0041] For example: The structure of deploying NOC using passive intermediary layer is as follows: Figure 1As shown, chiplet A includes core A1, core A2, network card A1, network card A2, router A1, and router A2; wherein core A1 is electrically connected to core A2, network card A1 is electrically connected to network card A2, router A1 is electrically connected to router A2, network card A1 is electrically connected to core A1 and router A1 respectively, and network card A2 is electrically connected to core A2 and router A2 respectively. Chiplet B includes core B1, core B2, network card B1, network card B2, router B1, and router B2; wherein core B1 is electrically connected to core B2, network card B1 is electrically connected to network card B2, router B1 is electrically connected to router B2, network card B1 is electrically connected to core B1 and router B1 respectively, and network card B2 is electrically connected to core B2 and router B2 respectively. A passive interposer is used to deploy the NOC. Since the passive interposer does not contain transistors, it can only provide a point-to-point connection without relays between chiplet A and chiplet B. CLK is the on-chip synchronous clock, and the network card is the network interface card (NIC) that connects the core and the router. The interconnection between chiplet A and chiplet B uses metal traces embedded in the passive interposer. That is, the routers in chiplet A (router A1, router A2) and the routers in chiplet B (router B1, router B2) connect the microbumps on the two chiplets (that is, the electrical connection between the passive interposer and chiplet A or chiplet B) through the passive interposer. The router on one chiplet is coupled with the router on the other chiplet. Therefore, compared with data transmission between two chiplets directly connected, this connection method can achieve high-bandwidth, low-latency data transmission and reduce the consumption of microbumps.

[0042] The disadvantage of deploying NOC using a passive interposer is that the router components must be placed in the chiplet, which reduces the yield and increases the chip area cost. For long links, the delay time is quadratically related to the distance, which can easily lead to large delays and low transmission speeds. In addition, since clocks cannot be generated on the passive interposer and buffers cannot be deployed to drive low-jitter clock networks, it is difficult to implement high-frequency synchronous NOC on the passive interposer.

[0043] If an active interposer is used to deploy a NOC, active devices (such as routers or repeaters) are deployed on the active interposer. The router can be used to reduce transmission delay in the NOC link, and the delay of long links changes from a quadratic relationship with distance to a linear relationship. The reduced delay leads to higher NOC frequencies and longer transmission distances. In addition, deploying the router in the active interposer avoids the use of micro-bump capacitors and electrostatic discharge (ESD) protection circuit capacitors, thereby reducing delay. ESD protection circuits are required to protect the chiplet interface during bonding. However, the active interposer uses advanced process technology, and its manufacturing cost is several times that of the passive interposer. In addition, as the size of the active interposer silicon wafer increases, the production yield decreases, further increasing the cost.

[0044] For example: the structure of deploying NOC using active interposer is as follows: Figure 2 As shown, chiplet C includes core C1, core C2, network card C1, and network card C2; core C1 is electrically connected to core C2, network card C1 is electrically connected to network card C2, network card C1 is electrically connected to core C1, and network card C2 is electrically connected to core C2. Chiplet D includes core D1, core D2, network card D1, and network card D2; core D1 is electrically connected to core D2, network card D1 is electrically connected to network card D2, network card D1 is electrically connected to core D1, and network card D2 is electrically connected to core D2. The active interposer is equipped with routers C1, C2, D1, and D2 that are electrically connected to each other. Router C1 is electrically connected to the network card C1 in the chiplet C using microbumps, and router C2 is electrically connected to the network card C2 in the chiplet C using microbumps (i.e., electrical connections between the active interposer and the chiplet C or chiplet D). Router D1 is electrically connected to the network card D1 in the chiplet D using microbumps, and router D2 is electrically connected to the network card D2 in the chiplet D using microbumps. The active interposer is made using a standard CMOS process, and active devices are integrated on the interposer, which has a relay link. At the same time, the clock network on the active interposer provides efficient synchronous transmission. Figure 3 As shown, the general packaging structure also includes a packaging substrate, and the active interposer and the packaging substrate are connected by electrical connections to reduce the consumption of resources on the upper chiplets C and D.

[0045] For example: 3D network-on-chip structures based on active interposers such as Figure 4As shown, R in the active interposer represents different routers; different N in the chiplet C represents different network interface cards (i.e., network cards), different PEs represent processing units (Process Element, PE) connected to different network interface cards, and different network interface cards in the chiplet C are connected to different routers R in the active interposer; similarly, different N in the chiplet D represents different network interface cards (i.e., network cards), different PEs represent processing units connected to different network interface cards, and different network interface cards in the chiplet D are connected to different routers R in the active interposer.

[0046] Therefore, an embodiment of the present invention provides a packaging structure with an interposer, in which an active interposer is used to deploy router components, that is, a part of the router components of the on-chip network is moved out of the chiplet, thereby saving the area of ​​the chiplet; a passive interposer is used to connect the active interposer, thereby reducing production costs and improving production yield.

[0047] Specifically, such as Figure 5 As shown, an embodiment of the present invention provides a packaging structure with an interposer, and the packaging structure specifically includes:

[0048] Active interposer 53;

[0049] M small chips are located above the active interposer 53 and fixedly connected to the active interposer 53, and the M small chips are electrically connected to each other;

[0050] A passive interposer 54 is located below the active interposer 54 and is fixedly connected to the active interposer 53 ;

[0051] a packaging substrate, located below the passive interposer 54 and fixedly connected to the passive interposer 54;

[0052] Wherein, M is a positive integer greater than 1.

[0053] Furthermore, both the active interposer and the passive interposer may be silicon interposers.

[0054] In the above embodiment, M small chips are located above the active interposer 53, that is, the active interposer 53 is arranged below the M small chips; the passive interposer 54 is located below the active interposer 53, that is, the active interposer 53 is arranged above the passive interposer 54; the package substrate is arranged below the passive interposer 54; in other words, the specific structure of the package structure is from top to bottom: M small chips, active interposer 53, passive interposer 54, package substrate, and they are fixedly connected in sequence. Among them, the M small chips can be arranged as needed and are not specifically limited here. For example: Figure 5As shown, the value of M can be 2, that is, the packaging structure has two small chips, namely the first small chip 51 and the second small chip 52, and the first small chip 51 and the second small chip 52 are electrically connected, and the electrical connection can be through a conductive link, etc.

[0055] In the above embodiment of the present invention, M small chips are arranged above the active interposer 53 and fixedly connected to the active interposer 53, and the passive interposer 54 is arranged below the active interposer 53 and fixedly connected to the active interposer 53. This packaging structure combines the advantages of the passive interposer 54 and the active interposer 53, which can not only save the chip area but also reduce production costs and improve production yield.

[0056] Optionally, each of the M chiplets includes a first routing device, and the M chiplets are interconnected through the first routing device.

[0057] In the above embodiment, the first router device can perform data processing, data synchronization, and data transmission between different parts of the chiplet. Each intra-chiplet interface can connect two first router devices within a chiplet, and each inter-chiplet interface can connect first router devices in different chiplets via an active interposer. The first router device is a device capable of communication and can be a processor, router, network card, etc., without specific limitation.

[0058] Specifically, if M is 2 and each chiplet contains a first routing device, the two chiplets are respectively a first chiplet and a second chiplet; the first routing device contained in the first chiplet is electrically connected to the first routing device contained in the second chiplet. Figure 5 As shown, if M takes a value of 2 and each chiplet contains two first routing devices, the first routing devices included in the first chiplet 51 are respectively: the third routing device 511 and the fourth routing device 512; the first routing devices included in the second chiplet 52 are respectively: the fifth routing device 521 and the sixth routing device 522; the electrical connection between the first chiplet 51 and the second chiplet 52 can be achieved through the electrical connection between the fourth routing device 512 and the fifth routing device 521.

[0059] It should be noted that the value of M and the number of first routing components in each chiplet in the above embodiments are examples and are not limiting.

[0060] Preferably, each of the M chiplets is wrapped with packaging material.

[0061] The first routing devices in different chiplets are interconnected by first conductive lines passing through the packaging material.

[0062] In the above embodiment, each of the M chiplets is disposed in a packaging material, that is, each chiplet is wrapped with a packaging material, and two adjacent chiplets are not directly connected to each other but need to be connected through a first conductive line. Figure 5 As shown, the fourth routing device 512 in the first chiplet 51 is connected to one end of the first conductive line 55 , and the other end of the first conductive line 55 passes through the packaging material 56 and is connected to the fifth routing device 521 in the second chiplet 52 .

[0063] Optionally, when the number of first routing devices included in the target chiplet among the M chiplets is N, the N first routing devices are electrically connected;

[0064] Wherein, N is a positive integer greater than 1.

[0065] In the above embodiment, the target chiplet may be one of the M chiplets, or may be multiple chiplets among the M chiplets, or may be M chiplets. If the target chiplet includes N first routing components, the N first routing components are electrically connected; for example, the electrical connection may be through first conductive wires.

[0066] For example: Figure 5 As shown, if M takes a value of 2, and the target chiplets are the first chiplet 51 and the second chiplet 52, and each chiplet contains two first routing devices, then the third routing device 511 and the fourth routing device 512 in the first chiplet 51 are electrically connected, and the fifth routing device 521 and the sixth routing device 522 in the second chiplet 52 are electrically connected.

[0067] It should be noted that the number of first routing components included in the target chiplet is not limited to multiple, but can also be one. The above embodiment is only an example.

[0068] Optionally, the active interposer includes: a second routing device;

[0069] The second routing device is electrically connected to the first routing device.

[0070] In the above embodiment, the active interposer includes a second routing device. Electrical connection between the active interposer and the chiplet is achieved by electrically connecting the second routing device to the first routing device. The second routing device is a device capable of communication, and may be a processor, router, network card, or the like, without specific limitation.

[0071] For example: Figure 5As shown, the active interposer 53 includes four second routing devices, and different second routing devices are electrically connected to different first routing devices in the chiplet, thereby forming an electrical connection between the active interposer 53 and the chiplet.

[0072] Furthermore, the active interposer is provided with a through silicon via;

[0073] The second routing device is electrically connected to the first routing device through the through-silicon via.

[0074] In the above embodiment, a second routing device is provided in the active interposer, and the chiplet is provided above the active interposer. The first routing device in the chiplet is connected to the second routing device through conductive wires, microbumps, and through-silicon vias in the active interposer to form a path. Figure 5 As shown, the electrical connections between the chiplets (first chiplet 51 and second chiplet 52) ​​and the active interposer 53 are microbumps, which serve to provide a fixed connection and conduct electricity.

[0075] Optionally, there are multiple second routing devices, and the multiple second routing devices are electrically connected to each other.

[0076] like Figure 5 As shown, in the above embodiment, the number of second routing devices in the active interposer 53 is four, namely: a seventh routing device 531, an eighth routing device 532, a ninth routing device 533, and a tenth routing device 534; the seventh routing device 531 is electrically connected to the eighth routing device 532, the eighth routing device 532 is electrically connected to the ninth routing device 533, and the ninth routing device 533 is electrically connected to the tenth routing device 534, thereby realizing interconnection between the second routing devices in the active interposer 53.

[0077] Furthermore, the passive interposer layer includes metal links, and the plurality of second routing devices are electrically connected via the metal links.

[0078] like Figure 5 As shown, in the above embodiment, the passive interposer 54 includes a metal link 541, which is used to interconnect multiple second routing devices in the active interposer 53, that is, the active interposer 53 and the passive interposer 54 are connected through micro-bumps, and the micro-bumps play a role of fixed connection and conductivity. Therefore, the seventh routing device 531 in the active interposer 53 is electrically connected to the eighth routing device 532 through the micro-bumps and the metal link 541, the eighth routing device 532 is electrically connected to the ninth routing device 533 through the micro-bumps and the metal link 541, and the ninth routing device 533 is electrically connected to the tenth routing device 534 through the micro-bumps and the metal link 541.

[0079] Optionally, the number of the second routing components is greater than or equal to the number of the first routing components. Figure 5 As shown, the number of the second routing components is the same as the number of the first routing components, and the second routing components are connected to the first routing components in a one-to-one correspondence, thereby reducing the cost of the second routing components.

[0080] To sum up, in the embodiment of the present invention, the second routing device in the active interposer is connected to the first routing device in the upper chiplet through microbumps and TSVs, and the first routing devices in the chiplet are interconnected, and the second routing devices in the active interposer are interconnected through metal links in the passive interposer. Thus, data can be transmitted through the metal links in the passive interposer, the second routing device in the active interposer, and the microbumps on the chiplet. Moreover, the manufacturing cost of the active interposer is much higher than that of the passive interposer. Therefore, making full use of the active interposer to deploy the NOC router and integrating the passive interposer can reduce the area occupied by the upper chiplet while simplifying the manufacturing difficulty of the active interposer as much as possible and improve the yield.

[0081] In the description of the present invention, it should be understood that the terms "left", "bottom", "one end", "top", "front", "the other end", "up", "one side", "top", "back", "front", "right", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0082] In addition, it should be noted that, unless otherwise clearly stipulated and limited, the terms "setting", "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. Unless otherwise clearly defined, ordinary technicians in this field can understand the specific meanings of the above terms in the present invention according to specific circumstances.

[0083] It should be understood that references throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present invention. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout this specification do not necessarily refer to the same embodiment. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0084] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0085] It should also be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include," "comprises," or any other variations thereof are intended to cover non-exclusive inclusion.

[0086] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0087] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the scope of protection of the present invention.

Claims

1. A packaging structure with an interposer, characterized in that: include: Active interposer; M small chips are located above the active interposer and fixedly connected to the active interposer, and the M small chips are electrically connected to each other; Each of the M chiplets includes a first routing device, and the M chiplets are interconnected via the first routing device; a passive interposer, located below the active interposer and fixedly connected to the active interposer; A packaging substrate, located below the passive interposer and fixedly connected to the passive interposer; Wherein, M is a positive integer greater than 1; At least one micro-bump is provided between the active interposer and the passive interposer, for electrically connecting the active interposer and the passive interposer; The active interposer is provided with through silicon vias, and the active interposer includes: a second routing device; The second routing device is electrically connected to the first routing device through the through silicon via; The passive interposer layer includes metal links, and the plurality of second routing devices are electrically connected via the metal links.

2. The package structure with an interposer according to claim 1, wherein: Each of the M small chips is wrapped with a packaging material; The first routing devices in different chiplets are interconnected by first conductive lines passing through the packaging material.

3. The package structure with an interposer according to claim 1, wherein: When the number of first routing devices included in the target chiplet among the M chiplets is N, the N first routing devices are electrically connected; Wherein, N is a positive integer greater than 1.

4. The package structure with an interposer according to claim 1, wherein: The number of the second routing devices is greater than or equal to the number of the first routing devices.

5. The package structure with an interposer according to claim 1, wherein: The active interposer and the passive interposer are both silicon interposers.

Images