Semiconductor device, array layout thereof, and packaging structure including the same

Abstract

The present invention discloses a semiconductor device and its array layout and a packaging structure including the same, wherein the semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers that are alternately stacked. The memory strings pass through the stack along a first direction, and each memory string includes a channel layer, a memory structure, a first conductive column and a second conductive column. The channel layer extends along the first direction. The memory structure is arranged between the stack and the channel layer. The first conductive column and the second conductive column extend along the first direction and are electrically isolated from each other, and are respectively coupled to a first position and a second position of the channel layer, the first position is relative to the second position, and the memory structure surrounds the first position and exposes the second position.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and its array layout and a packaging structure including the same, and in particular to a three-dimensional semiconductor device and its array layout and a packaging structure including the same. Background Art

[0002] Recently, since non-volatile memories have an advantage that stored data does not disappear when the current is turned off, people have an increasing demand for them.

[0003] However, non-volatile memory (eg, flash memory) may have an over-erase problem due to a low threshold voltage, thereby generating leakage current. Therefore, there is an urgent need to develop an improved non-volatile memory to solve the above problem. Summary of the invention

[0004] The present invention relates to a semiconductor device, wherein a channel layer has a first position and a second position relative to each other. Since a memory structure surrounds the first position and exposes the second position, compared with a comparative example in which both the first position and the second position are surrounded by the memory structure, the current can be more fully shut down to avoid the problem of over erase.

[0005] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers that are alternately stacked. The memory strings pass through the stack along a first direction, and each memory string includes a channel layer, a memory structure, a first conductive column, and a second conductive column. The channel layer extends along the first direction. The memory structure is disposed between the stack and the channel layer. The first conductive column and the second conductive column extend along the first direction and are electrically isolated from each other, and are respectively coupled to a first position and a second position of the channel layer, the first position being relative to the second position, wherein the memory structure surrounds the first position and exposes the second position.

[0006] According to another aspect of the present invention, an array layout of a semiconductor device is proposed. The array layout of the semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers that are alternately stacked. The memory strings pass through the stack along a first direction, and are arranged on the substrate along a second direction and a third direction to form a memory array, wherein the first direction, the second direction and the third direction are perpendicular to each other. Each memory string includes a channel layer, a memory structure, a first conductive column and a second conductive column. The channel layer extends along the first direction. The memory structure is disposed between the stack and the channel layer. The first conductive column and the second conductive column extend along the first direction and are electrically isolated from each other, and are respectively coupled to a first position and a second position of the channel layer, wherein the first position is relative to the second position, wherein the memory structure surrounds the first position and exposes the second position. In the memory array, the memory strings are arranged along the third direction into multiple rows of memory strings, and adjacent rows of memory strings have an offset distance in the third direction, wherein the first positions of two adjacent rows of memory strings are adjacent to each other.

[0007] According to another aspect of the present invention, a packaging structure is provided. The packaging structure includes a memory chip and a memory control chip. The memory chip includes a semiconductor device as described herein. The memory control chip is used to control the memory chip. The memory chip is disposed on the memory control chip.

[0008] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1A to 8B A schematic diagram illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention is shown;

[0010] Fig. 9 A top view of a memory string according to an embodiment of the present invention is shown;

[0011] Fig.10 A top view of a memory string according to another embodiment of the present invention is shown;

[0012] Fig.11 A top view of an array layout of a semiconductor device according to an embodiment of the present invention is shown;

[0013] Fig. 12A A top view showing the positional relationship between the array layout and isolation trenches of a semiconductor device according to an embodiment of the present invention;

[0014] Fig. 12B A top view showing the positional relationship between the array layout and isolation trenches of a semiconductor device according to another embodiment of the present invention;

[0015] Fig. 12C A top view showing the positional relationship between the array layout and isolation trenches of a semiconductor device according to another embodiment of the present invention;

[0016] Fig.12D A top view showing the positional relationship between the array layout and isolation trenches of a semiconductor device according to another embodiment of the present invention;

[0017] Fig.13 A circuit diagram of a semiconductor device according to an embodiment of the present invention is shown;

[0018] FIG. 14A to FIG. 14G A schematic diagram illustrating a manufacturing process of a semiconductor device according to another embodiment of the present invention is shown;

[0019] Figures 15A to 20E A schematic diagram illustrating a manufacturing process of a semiconductor device according to another embodiment of the present invention is shown;

[0020] Fig.21 A circuit diagram of a semiconductor device according to another embodiment of the present invention is shown; and

[0021] Fig. 22 A schematic diagram of a packaging structure according to an embodiment of the present invention is shown.

[0022]

Explanation of symbols

[0023] 10: Corresponding area

[0024] 20: Packaging structure

[0025] 22: Memory chips

[0026] 24: Memory control chip

[0027] 100~700:Semiconductor devices

[0028] 102: Substrate

[0029] 102M, 202M, 302M, 402M, 502M: Memory serial

[0030] 104: Insulation layer

[0031] 104p1: First lateral opening

[0032] 104p2: Second side opening

[0033] 104p3: Third lateral opening

[0034] 104p4: Fourth lateral opening

[0035] 108,608: Open

[0036] 112, 612: oxide layer

[0037] 112a: First oxide layer

[0038] 112b: Second oxide layer

[0039] 114: Nitride layer

[0040] 116, 616: channel layer

[0041] 116c: protrusion

[0042] 116n: Annular inner surface

[0043] 116s: Ring outer surface

[0044] 118a, 218a, 318a, 418a, 518a, 618a, 718a: first conductive column

[0045] 118b, 218b, 318b, 418b, 518b, 618b, 718b: second conductive column

[0046] 120: Organic dielectric layer

[0047] 122, 622: Insulation material layer

[0048] 124, 624: Insulation column

[0049] 126: Conductive layer

[0050] 132, 232, 632, 732: Memory structure

[0051] 142: Conductive pattern

[0052] 144a: First through hole

[0053] 144b: Second through hole

[0054] 246, 346, 446, 546: Isolation channel

[0055] 606: Sacrificial Layer

[0056] 612, 712: Oxide layer

[0057] 622: Insulation material layer

[0058] 624: Insulation column

[0059] 626a, 726a: first conductive layer

[0060] 626b, 726b: second conductive layer

[0061] 632h: Slit

[0062] 634: Isolation Structure

[0063] 646a, 746a: first isolation channel

[0064] 646b, 746b: Second isolation channel

[0065] A, A′, A1, A1′, B1, B1′, C1, C1′: End points of the hatch line

[0066] BL1, BL2: bit lines

[0067] H1: First height

[0068] H2: Second height

[0069] H3: The third height

[0070] H4: The fourth height

[0071] IL1, IL2: Input lines

[0072] K1, K2: thickness

[0073] LC: Online

[0074] MB: Solder Ball

[0075] MG1~MG4: memory gate

[0076] OL1, OL2: output lines

[0077] R1~R4:row

[0078] S1, S1′: stacking

[0079] SG1~SG4:Selection gate

[0080] SL1, SL2: Source lines

[0081] T1, T2a, T2b: Transistors

[0082] W1, W2: Width

[0083] WA: First width

[0084] WB: Second Width

[0085] WL1~WL4:Word lines DETAILED DESCRIPTION

[0086] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0087] Figures 1A to 8B FIG. 1 is a schematic diagram illustrating a manufacturing process of a semiconductor device 100 according to an embodiment of the present invention. Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A and Fig. 8A Draw the plane formed by the X-axis and the Y-axis, Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B The plane formed by the X-axis and the Z-axis is shown.

[0088] Figure 1A A top view after the opening 108 is formed is shown. Figure 1B Draw along Figure 1A The cross-sectional view of the AA′ connection is a diagram showing a corresponding region 10 of one of the memory strings as a representative. The subsequent process steps are all represented by schematic diagrams of the corresponding region 10.

[0089] Please also refer to Figure 1A and Figure 1B , a substrate 102 is provided, and a stack S1′ is formed on the substrate 102. The stack S1′ includes a plurality of sacrificial layers 106 and a plurality of insulating layers 104 alternately stacked along a first direction (e.g., the Z direction, or the normal direction of the upper surface of the substrate 102). Thereafter, a plurality of openings 108 are formed through the stack S1′ along the first direction (e.g., the Z direction) by an etching process. The bottom of each opening 108 exposes a portion of the upper surface of the substrate 102. In this embodiment, the opening 108 is formed at Figure 1A The top view of the embodiment has a circular cross section, but the present invention is not limited thereto. The opening 108 is Figure 1A The cross-section in the top view may be an ellipse or other suitable geometric shape.

[0090] In some embodiments, the substrate 102 is, for example, a dielectric layer (e.g., a silicon oxide layer). The insulating layer 104 may be, for example, a silicon oxide layer, and the silicon oxide layer may include, for example, silicon dioxide. The sacrificial layer 106 may be, for example, a silicon nitride layer. In this embodiment, the topmost and bottommost layers of the stack S1′ are insulating layers 104, and four insulating layers 104 and three sacrificial layers 106 are shown, but the present invention is not limited thereto. The number and configuration of the insulating layer 104 and the sacrificial layer 106 may be adjusted as required.

[0091] After that, please also refer to Figure 2A and Figure 2B , the first oxide layer 112a and the nitride layer 114 are sequentially formed on the inner surface of each opening 108. For example, the first oxide layer 112a and the nitride layer 114 can be sequentially formed on the topmost insulating layer 104 and in the opening 108 by a deposition process, and then the excess first oxide layer 112a and the nitride layer 114 are removed by an etching process to form the first oxide layer 112a and the nitride layer 114 disposed on the inner surface of each opening 108. The first oxide layer 112a is, for example, a silicon oxide layer (such as a silicon dioxide layer). The nitride layer 114 is, for example, a silicon nitride layer.

[0092] Next, please also refer to Figure 3A and Figure 3B , an organic dielectric layer 120 is formed on the top insulating layer 104 and in the opening 108 , and then the organic dielectric layer 120 is patterned so that half of the opening 108 is covered by the organic dielectric layer 120 and the other half of the opening 108 is exposed by the organic dielectric layer 120 .

[0093] Please also refer to Figure 4A and Figure 4B , the nitride layer 114 not protected by the organic dielectric layer 120 is removed by an etching process. The etching process is, for example, chemical dry etching, which selectively removes half of the nitride layer 114 .

[0094] Please also refer to Figure 5A and Figure 5B , remove the organic dielectric layer 120. In the present embodiment, the nitride layer 114 is substantially semi-ring-shaped in a top view, such as U-shaped or C-shaped, but the present invention is not limited thereto.

[0095] Please also refer to Fig. 6A and Figure 6B, forming a second oxide layer 112b on the inner surface of the hole 108. Specifically, in the first side of the opening 108 having the nitride layer 114, the second oxide layer 112b covers the inner surface of the nitride layer 114; in the second side of the opening 108 not having the nitride layer 114, the second oxide layer 112b covers the inner surface of the first oxide layer 112a. In the opening 108, the first side is opposite to the second side. The second oxide layer 112b may have the same material as the first oxide layer 112a, for example, both are silicon oxide layers (for example, silicon dioxide layers). In the first side, part of the first oxide layer 112a, the nitride layer 114 and part of the second nitride layer 112b may form the memory structure 132; in the second side, the remaining part of the first oxide layer 112a and the second oxide layer 112b may be formed together as the oxide layer 112.

[0096] Please also refer to Fig. 7A and Figure 7B , a channel layer 116 is formed in the opening 108, that is, the channel layer 116 is formed on the inner surface of the second oxide layer 112b. The material of the channel layer 116 includes, for example, undoped polysilicon.

[0097] After that, please also refer to Fig. 8A and Figure 8B , an insulating material layer 122 and an insulating column 124 are filled in the opening 108 respectively by a deposition process. The deposition process is, for example, a chemical vapor deposition process. The insulating material layer 122 is, for example, a silicon oxide layer (for example, a silicon dioxide layer). The material of the insulating column 124 includes, for example, silicon nitride. Thereafter, a first vertical opening and a second vertical opening are formed on two opposite sides of the insulating column 124 (that is, the first side and the second side of the opening 108) by an etching process to expose the upper surface of the substrate 102. In other embodiments, the first vertical opening and the second vertical opening may pass through a portion of the stack S1, but do not expose the upper surface of the substrate 102. The first vertical opening and the second vertical opening correspond to the positions of the source and drain of the memory of the semiconductor device 100 of the present embodiment. After the first vertical opening and the second vertical opening are enlarged to expose the insulating column 124 and the channel layer 116, a first conductive column 118a and a second conductive column 118b are formed in the first vertical opening and the second vertical opening respectively. In other embodiments, the first vertical opening and the second vertical opening may be enlarged to a degree that the insulating pillar 124 is not exposed. The material of the first conductive pillar 118a and the second conductive pillar 118b may include doped polysilicon.

[0098] Afterwards, an isolation trench (not shown) is formed through the stack S1′, and the sacrificial layer 106 is removed from the isolation trench by an etching process (e.g., a wet etching process), and then a conductive material is filled in the position where the sacrificial layer 106 is removed to form a conductive layer 126 disposed between the insulating layers 104. The material of the conductive layer 126 is, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi X ) or cobalt silicide (CoSi X ). In some embodiments, a buffer layer and a barrier layer (not shown) may be formed between the conductive layer 126 and the insulating layer 104. The buffer layer may be made of, for example, a material having a dielectric constant greater than 7, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxides, lanthanide oxides, or any combination thereof. The barrier layer may be made of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or any combination thereof. In this way, the semiconductor device 100 (such as Fig.11 shown).

[0099] Semiconductor device 100 (eg Fig.11 1 and 2 (shown in FIG. 1 ). The stack S1 is formed on a substrate 102 and includes a plurality of conductive layers 126 and a plurality of insulating layers 104 that are alternately stacked. The memory strings 102M pass through the stack S1 along a first direction (e.g., the Z direction). Each memory string 102M includes a channel layer 116, a memory structure 132, an oxide layer 112, a first conductive pillar 118a, a second conductive pillar 118b, an insulating pillar 124, and an insulating material layer 122.

[0100] The channel layer 116, the memory structure 132, the first conductive pillar 118a and the second conductive pillar 118b all extend along a first direction (e.g., the Z direction). The memory structure 132 is disposed between the stack S1 and the channel layer 116, wherein the memory structure 132 includes a portion of the first oxide layer 112a, the nitride layer 114 and a portion of the second oxide layer 112b. The insulating pillar 124 is located in the central region of the memory string 102M. The first conductive pillar 118a and the second conductive pillar 118b are connected to the insulating pillar 124. The first conductive pillar 118a and the second conductive pillar 118b are electrically isolated from each other by the insulating pillar 124, and are respectively coupled to a first position and a second position of the channel layer 116, wherein the first position is opposite to the second position, wherein the memory structure 132 surrounds the first position and exposes the second position. In other words, the memory structure 132 does not surround the second position and the second conductive pillar 118b, and the portion of the channel layer 116 surrounding the second position is directly in contact with the oxide layer 112. The channel layer 116 surrounds the first conductive pillar 118 a , the second conductive pillar 118 b , the insulating pillar 124 , and the insulating material layer 122 .

[0101] In this embodiment, the first position and the second position are opposite to each other along the second direction (e.g., the X direction), but the present invention is not limited thereto. The extension direction of the connection between the first position and the second position (or the extension direction of the connection LC between the first conductive pillar 118a and the second conductive pillar 118b) can be parallel to the second direction (e.g., the X direction).

[0102] In the present embodiment, the memory structure 132 includes a charge storage material, such as a charge storage material formed by a first oxide layer 112 a , a nitride layer 114 , and a second oxide layer 112 b , but the invention is not limited thereto.

[0103] In some embodiments, the channel layer 116 has an annular cross section formed along a second direction (e.g., the X direction) and a third direction (e.g., the Y direction), and the second direction and the third direction are perpendicular to the first direction. The channel layer 116 has an annular inner surface 116n and an annular outer surface 116s, and the first conductive column 118a and the second conductive column 118b are coupled to the annular inner surface 116n. In the present embodiment, the annular inner surface 116n of the channel layer 116 is circular in the cross section formed along the second direction (e.g., the X direction) and the third direction (e.g., the Y direction), but the present invention is not limited thereto, and may be an elliptical or other suitable shapes.

[0104] In some embodiments, the memory structure 132 is substantially semi-circular in the cross-section formed along the second direction (for example, the X direction) and the third direction (for example, the Y direction), such as a U-shape or a C-shape. However, the present invention is not limited thereto. As long as the memory structure 132 is non-circular, it can surround the first position of the channel layer 116 (the position where the first conductive column 118a is coupled to the channel layer 116) and can expose the second position of the channel layer 116 (the position where the second conductive column 118b is coupled to the channel layer 116), which is within the scope of protection of the present invention.

[0105] In some embodiments, the semiconductor device 100 of the present invention may be applied to 3D AND flash memory, 3D NOR memory, or other suitable memories.

[0106] Compared to the comparative example in which the memory structure surrounds the first conductive pillar and the second conductive pillar together (i.e., the memory structure is ring-shaped), since the memory structure 132 of an embodiment of the present invention surrounds the first position and exposes the second position, the second position coupled to the second conductive pillar 118b can correspond to the oxide layer 112 rather than the memory structure 132, so the oxide layer 112 can more fully shut down the current of the second conductive pillar 118b, and even if the threshold voltage is low, the problem of over-erasure can be avoided to prevent the generation of leakage current.

[0107] Fig. 9 A top view of a memory string 102M according to an embodiment of the present invention is shown. Since the thickness K1 of the memory structure 132 corresponding to the first side (also known as the first conductive pillar 118a or the first position) in the second direction (e.g., the X direction) may be greater than the thickness K2 of the oxide layer 112 corresponding to the second side (also known as the second conductive pillar 118b or the second position) in the second direction (e.g., the X direction), the inner surface of the channel layer 116 may have a protruding portion 116c. It should be understood that even if the inner surface of the channel layer 116 has the protruding portion 116c, it can still be considered as a circle or ring.

[0108] Fig.10 A top view of a memory string according to an embodiment of the present invention is shown. Fig. 9 The memory serial is similar to Fig. 8A The memory string of FIG. 1 is different in that the memory structure 232 includes a ferroelectric material instead of being formed by a first oxide layer, a nitride layer and a second oxide layer.

[0109] In some embodiments, the ferroelectric material may include hafnium oxide, such as silicon-doped hafnium oxide, zirconium-doped hafnium oxide, or other suitable materials.

[0110] Fig.11 A top view of an array layout of a semiconductor device according to an embodiment of the present invention is shown. Fig.11 Draw on Figure 1A to Figure 8B Schematic diagram of the semiconductor device 100 after a plurality of input lines IL1 , IL2 . . . and a plurality of output lines OL1 , OL2 . . . are formed.

[0111] Please refer to Fig.11 , a plurality of memory strings 102M are arranged on the substrate 102 along a second direction (e.g., X direction) and a third direction (e.g., Y direction) to form a memory array. In the present embodiment, the first direction, the second direction, and the third direction are perpendicular to each other, but the present invention is not limited thereto. In the memory array, a plurality of memory strings 102M are arranged along the third direction to form a plurality of rows R1 to R4 of memory strings 102M, wherein two adjacent rows of memory strings 102M (e.g., adjacent memory strings 102M located in rows R1 and R2) have an offset distance D in the third direction, wherein the first positions of the two adjacent rows of memory strings 102M are adjacent to each other. In other words, the memory structure 132 of the memory string 102M in row R1 is adjacent to the memory structure 132 of the memory string 102M in row R2, and is away from the oxide layer 112 of the memory string 102M in row R2. The memory structure 132 of the memory string 102M of the row R3 is adjacent to the memory structure 132 of the memory string 102M of the row R4 and is away from the oxide layer 112 of the memory string 102M of the row R4.

[0112] A plurality of conductive patterns 142 are disposed on the memory string 102M and are electrically connected to one of the first conductive pillar 118a and the second conductive pillar 118b, respectively. A plurality of input lines IL1, IL2... and a plurality of output lines OL1, OL2... are parallel to each other and extend along the second direction. Each input line (for example, the input line IL1) can be coupled to the corresponding first conductive pillar 118a through a first through hole (for example, 144a) and a corresponding conductive pattern 142. Each output line (for example, the output line OL1) can be coupled to the corresponding second conductive pillar 118b through a second through hole (for example, 144b) and a corresponding conductive pattern 142. In the present embodiment, the first position and the second position are opposite to each other along the second direction, and the input lines IL1, IL2... and the output lines OL1, OL2... extend along the second direction, respectively. However, the present invention is not limited thereto. In other embodiments, the input lines and the output lines can extend along a third direction (not shown), and the first direction, the second direction, and the third direction can be perpendicular to each other.

[0113] FIG. 12A to FIG. 12D A top view of the array layout of semiconductor devices 200-500 and the positional relationship of isolation trenches 246-546 according to some embodiments of the present invention is shown. The structures of memory strings 202M-502M are the same or similar to memory string 102M, and the repeated parts will not be described in detail. FIG. 12A to FIG. 12D The memory strings 202M-502M in FIG. 1 only simply illustrate the positions of the first conductive pillars 218a-518a and the second conductive pillars 218b-518b. The other components of the memory strings 202M-502M can be referred to in Fig. 8A and Figure 8B For a clearer understanding.

[0114] Fig. 12A FIG. 2 is a top view showing the array layout of the semiconductor device 200 and the position relationship of the isolation trench 246 according to an embodiment of the present invention.

[0115] Please refer to Fig. 12A , the array layout of the memory strings 202M of the semiconductor device 200 is the same as or similar to Fig.11Array layout of memory string 102M of semiconductor device 100 shown. In the present embodiment, first conductive pillar 218a coupled to the first position and second conductive pillar 218b coupled to the second position are arranged along the second direction (e.g., X direction). That is, the direction of connection of first conductive pillar 218a and second conductive pillar 218b is parallel to the second direction. Multiple isolation channels 246 divide stack S1 into multiple sub-stacks, and the direction of connection of each isolation channel 246 (e.g., Y direction) may be perpendicular to the second direction (e.g., X direction), so that the direction of connection of first conductive pillar 218a and second conductive pillar 218b is perpendicular to the direction of connection of isolation channel 246. However, the present invention is not limited thereto, and in some embodiments, the direction of connection of first conductive pillar 218a and second conductive pillar 218b may form an acute angle with the direction of connection of isolation channel 246.

[0116] Fig. 12B FIG. 1 is a top view showing an array layout of a semiconductor device 300 and the positional relationship of an isolation trench 346 according to another embodiment of the present invention.

[0117] Please refer to Fig. 12B , the first conductive pillar 318a coupled to the first position and the second conductive pillar 318b coupled to the second position are arranged along a third direction (for example, the Y direction). That is, the extension direction of the connection between the first conductive pillar 318a and the second conductive pillar 318b is parallel to the third direction. The plurality of isolation channels 346 divide the stack S1 into a plurality of sub-stacks, and the extension direction (for example, the Y direction) of each isolation channel 346 may be parallel to the third direction, so that the extension direction of the connection between the first conductive pillar 318a and the second conductive pillar 318b is parallel to the extension direction of the isolation channel 346. However, the present invention is not limited thereto. In some embodiments, the extension direction of the connection between the first conductive pillar 318a and the second conductive pillar 318b may form an acute angle with the extension direction of the isolation channel 346.

[0118] Fig. 12C FIG. 4 is a top view showing an array layout of a semiconductor device 400 and the positional relationship of an isolation trench 446 according to yet another embodiment of the present invention.

[0119] Please refer to Fig. 12C, the array layout of the semiconductor device 400 is similar to the array layout of the semiconductor device 200, the difference being that the cross section of the memory string 402M in the second direction is an elliptical cross section rather than a circular cross section. In the present embodiment, the first conductive pillar 418a coupled to the first position and the second conductive pillar 418b coupled to the second position are arranged along the second direction (e.g., the X direction). That is, the extension direction of the connection between the first conductive pillar 418a and the second conductive pillar 418b is parallel to the second direction. The plurality of isolation channels 446 divide the stack S1 into a plurality of sub-stacks, and the extension direction of each isolation channel 446 may be perpendicular to the second direction, so that the extension direction of the connection between the first conductive pillar 418a and the second conductive pillar 418b5 is perpendicular to the extension direction of the isolation channel 246. However, the present invention is not limited thereto, and in some embodiments, the extension direction of the connection between the first conductive pillar 418a and the second conductive pillar 418b may form an acute angle with the extension direction of the isolation channel 446.

[0120] Fig.12D FIG. 5 is a top view showing an array layout of a semiconductor device 500 and the positional relationship of an isolation trench 546 according to yet another embodiment of the present invention.

[0121] Please refer to Fig.12D , the array layout of the semiconductor device 500 is similar to the array layout of the semiconductor device 300, the difference being that the cross-section formed by the memory string 502M along the second direction and the third direction is an elliptical cross-section rather than a circular cross-section. The first conductive pillar 518a coupled to the first position and the second conductive pillar 518b coupled to the second position are arranged along the third direction (for example, the Y direction). That is, the extension direction of the connection of the first conductive pillar 518a and the second conductive pillar 518b is parallel to the third direction. The plurality of isolation channels 546 divide the stack S1 into a plurality of sub-stacks, and the extension direction of each isolation channel 546 may be parallel to the third direction, so that the extension direction of the connection of the first conductive pillar 518a and the second conductive pillar 518b is parallel to the extension direction of the isolation channel 546. However, the present invention is not limited thereto, and in some embodiments, the extension direction of the connection of the first conductive pillar 518a and the second conductive pillar 518b may form an acute angle with the extension direction of the isolation channel 546.

[0122] Fig.13 A circuit diagram of a semiconductor device according to an embodiment of the present invention is shown, for example, in semiconductor devices 100-500, including Fig.10 A semiconductor device in the memory serial as shown, or other suitable semiconductor device.

[0123] Please refer to Fig.13, taking the semiconductor device 100 as an example, the conductive layer 126 can be used as word lines WL1-WL4. Each intersection of the conductive layer 126 and the memory string 102M can form 1.5 transistors (for example, transistor T1) (also called 1.5T). The word lines WL1-WL4 coupled to the transistors can be used as the gates of the corresponding transistors. For example, the word line WL1 coupled to the transistor T1 can be used as the gate of the transistor T1. The input lines IL1, IL2... coupled to the first conductive column 118a can be used as source lines SL1, SL2.... The output lines OL1, OL2... coupled to the second conductive column 118b can be used as bit lines BL1, BL2...

[0124] Compared to the comparative example in which the memory structure surrounds the first conductive pillar and the second conductive pillar (i.e., a 1T memory device), since the memory structure (e.g., 132, 232) of an embodiment of the present invention surrounds the first position of the channel layer (the position coupled to the first conductive pillar 118a) but does not surround the second position of the channel layer (the position coupled to the second conductive pillar 118b), the second position is surrounded by the oxide layer 112, so a 1.5T memory device can be formed, and the problem of over-erasure can be avoided, preventing the generation of leakage current of the drain or bit line of the transistor, and further, a low read voltage can be used for operation, such as a read voltage of 1V. Fig.13 As shown, when a read operation is performed, 1V may be applied to the selected word line WL1, 1V may be applied to the selected bit line BL1, and 0V may be applied to the unselected source lines SL1, SL2, the unselected bit line BL2, and the unselected word lines WL2-WL4.

[0125] Figures 14A to 14G FIG. 6 is a schematic diagram illustrating a manufacturing process of a semiconductor device 600 according to another embodiment of the present invention. Figures 14A to 14G The plane formed by the X direction and the Y direction is shown, and only the manufacturing process of one memory string is shown.

[0126] Please refer to Fig.14A , in the formation of Figure 1A After the multiple insulating layers and the multiple sacrificial layers 606 are alternately stacked on the substrate, a plurality of slits 632h are formed along a first direction (e.g., the Z direction) through the stack and exposing the upper surface of the substrate. In other embodiments, the slits 632h may pass through a portion of the stack along the first direction without exposing the upper surface of the substrate. In some embodiments, each slit 632h may extend along a third direction (e.g., the Y direction) and pass through the center point of a predetermined position of the memory string. Thereafter, an insulating material is filled into the slit 632h to form an isolation structure 634 extending along the third direction (e.g., the Y direction). The insulating material is, for example, an oxide, such as silicon oxide (e.g., silicon dioxide).

[0127] Please refer to Fig. 14B , forming a plurality of openings 608 passing through the stack along a first direction (eg, Z direction). The openings 608 may expose the upper surface of the substrate. In other embodiments, the openings 608 may pass through a portion of the stack along the first direction without exposing the upper surface of the substrate.

[0128] Please refer to Fig. 14C A channel layer 616 is formed in the opening 608 by a deposition process, that is, formed on the inner surface of the opening 608. The material of the channel layer 616 includes, for example, undoped polysilicon.

[0129] Please refer to Fig.14D , forming a first isolation channel 646a that passes through the stack along a first direction (eg, Z direction) and extends along a third direction (eg, Y direction). That is, the extension direction of the first isolation channel 646a is parallel to the extension direction of the isolation structure 634.

[0130] Please refer to Fig.14E , a portion of the sacrificial layer 606 is removed through the first isolation channel 646a by a selective etching process, that is, the sacrificial layer 606 located on the side of the isolation structure 634 adjacent to the first isolation channel 646a is removed. Thereafter, an oxide material and a conductive material are sequentially filled into the position where the sacrificial layer 606 is removed to form an oxide layer 612 and a first conductive layer 626a. Next, a second isolation channel 646b is formed on the side of the channel layer 616 relative to the first isolation channel 646a, and the extension direction of the second isolation channel 646b is parallel to the extension direction of the first isolation channel 646a. In detail, the oxide layer 612 surrounds the side of the channel layer 616 adjacent to the first isolation channel 646a. The material of the oxide layer 612 is, for example, the same as that of the isolation structure 634, for example, silicon oxide (such as silicon dioxide).

[0131] Please refer to Fig.14F , the remaining sacrificial layer 606 is removed through the second isolation trench 646b by a selective etching process, that is, the sacrificial layer 606 located on the side of the isolation structure 634 adjacent to the second isolation trench 646b is removed. Thereafter, the memory material and the conductive material are sequentially filled into the position where the sacrificial layer 606 is removed to form the memory structure 632 and the second conductive layer 626b. The materials of the first conductive layer 626a and the second conductive layer 626b are, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi X ) or cobalt silicide (CoSi X ).

[0132] Please refer to Figure 14G , through a process similar to Fig. 8A and Figure 8B In the manufacturing method described in the related paragraphs, an insulating material layer 622, an insulating column 624, a first conductive column 618a and a second conductive column 618b are formed in the opening 608 to form the semiconductor device 600. In other embodiments, the first isolation trench 646a (such as Fig.14D as shown) before and as Fig. 14C After the steps shown, the above-mentioned steps of forming an insulating material layer 622 , an insulating pillar 624 , a first conductive pillar 618 a and a second conductive pillar 618 b in the opening 608 are performed.

[0133] In the present embodiment, a conductive layer in the stack of the semiconductor device 600 includes a first conductive layer 626a and a second conductive layer 626b. Each intersection position of the first conductive layer 626a, the second conductive layer 626b and the memory string 602M can form two transistors (also referred to as 2T), and the two transistors are controlled by the first gate and the second gate, respectively. Further, the second conductive layer 626b can be the first gate, and the first conductive layer 626a can be the second gate. The first gate and the second gate are separated from each other by the isolation structure 634, the first gate is adjacent to the first position coupled to the first conductive column 618a, and the second gate is adjacent to the second position coupled to the second conductive column 618b. In addition, the first gate corresponds to the memory structure 632 and serves as a memory gate; the second gate corresponds to the oxide layer 612 and serves as a selection gate. The oxide layer 612 is disposed between the channel layer 616 and the second gate (for example, the first conductive layer 626a), and the memory structure 632 is disposed between the channel layer 616 and the first gate (for example, the second conductive layer 726b).

[0134] Figures 15A to 20E A schematic diagram of a manufacturing process of a semiconductor device 700 according to another embodiment of the present invention is shown. Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A and Fig. 20A A partial three-dimensional schematic diagram of a semiconductor device 700 is shown. Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B and Fig. 20B A top view of a semiconductor device 700 is shown, corresponding to Figure 15C to Figure 15D , Figure 16C to Figure 16D , Figure 17C to Figure 17D , Figure 18C to Figure 18D , Figure 19C to Figure 19D and Figure 20C to Figure 20D The plane formed by the X direction and the Y direction of the line C1-C1' in the figure. Fig. 15C , Fig. 16C , Fig. 17C , Fig. 18C , Fig.19C and Fig. 20C Draw separately Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B and Fig. 20B A cross-sectional view along the A1-A1′ line. Fig.15D , Fig.16D , Fig.17D , Fig.18D , Fig.19D , Fig.20D Draw separately Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B and Fig. 20B A cross-sectional view along the B1-B1′ line. Fig.20E Some embodiments of the present invention are shown in FIG. Fig. 20B A cross-sectional view along the B1-B1′ line.

[0135] The manufacturing method of the semiconductor device 700 is the same as or similar to the semiconductor device 600. Figures 14A to 14C Following the steps shown, Fig. 8A and Figure 8B According to the manufacturing method described in the related paragraphs, an insulating material layer 722, a first conductive column 718a and a second conductive column 718b are formed in the opening 608, such as Fig.15A 15. In some embodiments, an insulating column (not shown) may be formed between the first conductive column 718a and the second conductive column 718b. In some embodiments, the steps of forming the insulating material layer 722, the insulating column (not shown), the first conductive column 718a and the second conductive column 718b may be performed as shown in FIG. Figures 15A to 20E Then, please refer to Figures 15A to 15D , forming a first isolation channel 746a that passes through the stack along a first direction (e.g., the Z direction) and extends along a third direction (e.g., the Y direction). That is, the extension direction of the first isolation channel 746a is parallel to the extension direction of the isolation structure 634. Afterwards, a portion of the sacrificial layer 606 is removed through the first isolation channel 746a by a selective etching process, that is, the sacrificial layer 606 located on one side of the isolation structure 634 adjacent to the first isolation channel 746a is removed, and a plurality of first lateral openings 104p1 are formed at the position where the sacrificial layer 606 is removed (i.e., between the insulating layers 104 adjacent to the first isolation channel 746a).

[0136] Next, please refer to FIG. 16A to FIG. 16D, a portion of the insulating layer 104 is removed through the first lateral opening 104p1 by a first trimming process (e.g., wet etching) to form a second lateral opening 104p2 between the remaining insulating layer 104 adjacent to the first isolation trench 746a. The first lateral opening 104p1 has a first height H1 (e.g., 0.0433mm) in a first direction (e.g., Z direction) Fig. 15C The second lateral opening 104p2 has a second height H2 (eg, Fig. 16C In addition, after the first trimming process, the isolation structure 634 corresponding to the second lateral opening 104p2 also has a reduced width W1 in the second direction (eg, the X direction), as shown in FIG. Fig. 16B and Fig.16D shown.

[0137] Please refer to FIG. 17A to FIG. 17D , an oxide material and a conductive material are sequentially filled into the second lateral opening 104p2 to form an oxide layer 712 and a first conductive layer 726a. The material of the oxide layer 712 is, for example, the same as that of the isolation structure 634, for example, silicon oxide (such as silicon dioxide). In detail, the oxide layer 712 surrounds a side of the channel layer 616 adjacent to the first isolation channel 646a, and continuously extends to the same side of the isolation structure 634 and the channel layer 616 (for example, Fig. 17B on the right side of the image).

[0138] Next, please refer to FIG. 18A to FIG. 18D , a second isolation channel 746b is formed on a side of the channel layer 616 relative to the first isolation channel 746a, and the extension direction of the second isolation channel 746b is parallel to the extension direction of the first isolation channel 746a. Afterwards, the remaining sacrificial layer 606 is removed through the second isolation channel 746b by a selective etching process, that is, the sacrificial layer 606 located on a side of the isolation structure 634 adjacent to the second isolation channel 746b is removed, so as to form a plurality of third lateral openings 104p3 between the remaining insulating layer 104 adjacent to the second isolation channel 746b (that is, the position where the sacrificial layer 606 is removed).

[0139] Next, referring to FIGS. 19A to 19D , a portion of the insulating layer 104 is removed through the third lateral opening 104p3 by a second trimming process (e.g., wet etching) to form a fourth lateral opening 104p4 between the remaining insulating layer 104 adjacent to the second isolation trench 746b (i.e., the position where the sacrificial layer 606 is removed). The third lateral opening 104p3 has a third height H3 (e.g., 0.0433 m) in the first direction (e.g., the Z direction) Fig. 18C ), the fourth lateral opening 104p4 has a fourth height H4 (such as Fig.19C As shown in FIG. 1 , the fourth height H4 is greater than the third height H3. In addition, after the second trimming process, the isolation structure 634 corresponding to the fourth lateral opening 104p4 also has a reduced width W2 in the second direction (eg, the X direction), as shown in FIG. Fig.19B and Fig.19D shown.

[0140] Please refer to FIG. 20A to FIG. 20D , a memory material and a conductive material are sequentially filled into the fourth lateral opening 104p4 to form a memory structure 732 and a second conductive layer 726b. The materials of the first conductive layer 726a and the second conductive layer 726b are, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi X ) or cobalt silicide (CoSi X Specifically, the memory structure 732 surrounds a side of the channel layer 616 adjacent to the second isolation channel 746b and continuously extends to the same side of the isolation structure 634 and the channel layer 616 (eg, Fig. 20B on the left side of the image).

[0141] In the present embodiment, a conductive layer in the stack of the semiconductor device 700 includes a first conductive layer 726a and a second conductive layer 726b. Each intersection position of the first conductive layer 726a, the second conductive layer 726b and the memory string 702M can form two transistors (also referred to as 2T), and the two transistors are controlled by the first gate and the second gate, respectively. Further, the second conductive layer 726b can be the first gate, and the first conductive layer 726a can be the second gate. The first gate and the second gate are separated from each other by the isolation structure 634, the first gate is adjacent to the first position coupled to the first conductive column 718a, and the second gate is adjacent to the second position coupled to the second conductive column 718b. In addition, the first gate corresponds to the memory structure 732 and serves as a memory gate; the second gate corresponds to the oxide layer 712 and serves as a selection gate. The oxide layer 712 is disposed between the channel layer 616 and the second gate (for example, the first conductive layer 726a), and the memory structure 732 is disposed between the channel layer 616 and the first gate (for example, the second conductive layer 726b). The oxide layer 712 extends between the channel layer 616 and the second gate, and between the isolation structure 634 and the second gate; the memory structure 732 extends between the isolation structure 634 and the first gate, and between the channel layer 616 and the first gate.

[0142] In some embodiments, a portion of the isolation structure 634 corresponding to the insulating layer 104 located on the second conductive layer 726 b (i.e., the first gate) and the second conductive layer 726 a (i.e., the first gate) has a first width WA in the second direction (e.g., the X direction), and a portion of the isolation structure 634 corresponding to the second conductive layer 726 b (i.e., the first gate) and the second conductive layer 726 a (i.e., the first gate) has a second width WB in the second direction (e.g., the X direction). The first width WA is greater than the second width WB. Fig.20D In some embodiments, the height H2 of the second lateral etch opening 104p2 in the first direction (eg, the Z direction) may be the same as the height H4 of the fourth lateral etch opening 104p4 in the first direction (eg, the Z direction), as shown in FIG. Fig.20D However, the present invention is not limited thereto.

[0143] In some embodiments, the height H2 of the second lateral etching opening 104p2 in the first direction (e.g., the Z direction) may be less than the height H4 of the fourth lateral etching opening 104p4 in the first direction (e.g., the Z direction). For example, the thickness of the memory structure 732 may be greater than the thickness of the oxide layer 712. Fig.20E However, the present invention is not limited thereto.

[0144] Compared with the semiconductor device 600, the first gate and the second gate of the semiconductor device 700 have a smaller interval sp1 (eg Fig. 20B The spacing sp1 is, for example, equal to the sum of the widths of the isolation structure 634, the oxide layer 712, and the memory structure 732 in the second direction (for example, the X direction).

[0145] Fig.21 FIG. 5 is a circuit diagram of a semiconductor device 600 or 700 according to yet another embodiment of the present invention.

[0146] Please refer to Fig.21, the intersection of the first conductive layer (626a or 726a), the second conductive layer 626b (726b) and the memory string (602M or 702M) can form two connected transistors (for example, the first transistor T2a and the second transistor T2b), so the semiconductor device 600 or 700 of this embodiment can also be called a 2T memory device. The first transistor T2a, for example, corresponds to the memory structure 632 or 732; the second transistor T2b, for example, corresponds to the oxide layer 612 or 712. The first conductive layer (626a or 726a) can be used as the selection gates SG1 to SG4, and the second conductive layer (626b or 726b) can be used as the memory gates MG1 to MG4. The source lines SL1 and SL2 can be coupled to the first conductive pillars (618a or 718a), and the bit lines BL1 and BL2 can be coupled to the second conductive pillars (618b or 718b). In one embodiment, the first transistor T2 a and the second transistor T2 b may be controlled by a first gate (eg, the memory gate MG1 ) and a second gate (eg, the selection gate SG1 ), respectively.

[0147] Compared with the embodiment of 1.5T semiconductor device, since this embodiment is a 2T semiconductor device, the transistor can be controlled more accurately. For example, the first gate and the second gate can be given different voltages respectively, and the present invention is not limited to this and can be adjusted according to the needs.

[0148] In some embodiments, the present invention provides an AND flash memory device including the semiconductor device 100 ˜ 600 or 700 .

[0149] In some embodiments, the present invention provides a 1.5T memory device including the semiconductor device 100 ˜ 400 or 500 .

[0150] In some embodiments, the present invention provides a 2T memory device including the semiconductor device 600 or 700 .

[0151] Fig. 22 FIG. 1 is a schematic diagram of a package structure 20 according to an embodiment of the present invention.

[0152] Please refer to Fig. 22, the package structure 20 includes a memory chip 22 and a memory control chip 24. The memory chip 22 is disposed on the memory control chip 24 along a first direction (e.g., the Z direction). The memory chip 22 and the memory control chip 24 may be connected by through silicon vias (TSV) (not shown), bumps MB, or other suitable components. In the present embodiment, the material of the bumps 622 may include copper, but the present invention is not limited thereto. The memory chip 22 may include any semiconductor device 100 to 700 described in the present case or any combination thereof. In some embodiments, the memory chip 22 may include an AND flash memory device, a NOR memory device, or other suitable memory devices. The memory control chip 24 may be used to control the memory chip 22. The memory control chip 24 may include a logic circuit, a row decoder, a column decoder, or other suitable components.

[0153] Compared to the comparative example in which the row decoder and the column decoder need to be arranged horizontally with the memory chip (that is, the row decoder and the column decoder are not arranged below the memory chip), or the comparative example of embedded flash, the memory chip 22 of this embodiment can be vertically stacked on the memory control chip 24 including the row decoder, the column decoder and the logic circuit, and can use fewer pads, which can save costs and simplify manufacturing, and can have a smaller size, can form a high-density memory series, and can consume less energy during write operations.

[0154] According to one embodiment of the present invention, a semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers that are alternately stacked. The memory strings pass through the stack along a first direction, and each memory string includes a channel layer, a memory structure, a first conductive column, and a second conductive column. The channel layer extends along the first direction. The memory structure is disposed between the stack and the channel layer. The first conductive column and the second conductive column extend along the first direction and are electrically isolated from each other, and are respectively coupled to a first position and a second position of the channel layer, the first position being relative to the second position, wherein the memory structure surrounds the first position and exposes the second position.

[0155] Compared to the comparative example in which the memory structure surrounds the first conductive pillar and the second conductive pillar, since the memory structure of one embodiment of the present invention surrounds the first position and exposes the second position, the second position is surrounded by the oxide layer and is not surrounded by the memory structure, so the problem of over-erasure can be avoided, and the generation of leakage current of the drain of the transistor or the bit line can be prevented, and further, a low read voltage can be used for operation.

[0156] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, wherein: include: A stacked layer formed on a substrate, the stacked layer comprising a plurality of conductive layers and a plurality of insulating layers stacked alternately; as well as A plurality of memory strings are provided along a first direction through the stack, each of the memory strings comprising: a channel layer extending along the first direction; a memory structure disposed between the stack and the channel layer; and A first conductive pillar and a second conductive pillar extend along the first direction and are electrically isolated from each other, and are respectively coupled to a first position and a second position of the channel layer, the first position is relative to the second position, wherein the memory structure surrounds the first position and exposes the second position; the channel layer has an annular inner surface and an annular outer surface, and the first conductive pillar and the second conductive pillar are coupled to the annular inner surface.

2. The semiconductor device according to claim 1, wherein The channel layer has an annular cross section formed along a second direction and a third direction, and the second direction and the third direction are perpendicular to the first direction.

3. The semiconductor device according to claim 1, wherein Each of the memory strings includes an insulating column located in a central area.

4. The semiconductor device according to claim 3, wherein: The first conductive column and the second conductive column are connected to the insulating column.

5. The semiconductor device according to claim 1, wherein Also includes: A plurality of input lines, one of which is coupled to the first conductive column; as well as A plurality of output lines, one of which is coupled to the second conductive column.

6. The semiconductor device according to claim 5, wherein: The first position and the second position are opposite to each other along a second direction. The input lines and the output lines are parallel to each other and extend along the second direction. The second direction is perpendicular to the first direction.

7. The semiconductor device according to claim 1, wherein The first position and the second position are opposite to each other along a second direction, and the second direction is perpendicular to the first direction.

8. The semiconductor device according to claim 7, wherein: The invention also comprises a plurality of isolation channels, which divide the stack into a plurality of sub-stacks, and the extension direction of each isolation channel is perpendicular to the extension direction of the connection between the first conductive column and the second conductive column.

9. The semiconductor device according to claim 7, wherein: The invention also comprises a plurality of isolation channels, which divide the stack into a plurality of sub-stacks, and the extension direction of each isolation channel is parallel to the extension direction of the connection between the first conductive column and the second conductive column.

10. The semiconductor device according to claim 1, wherein The memory structure includes a charge storage material.

11. The semiconductor device according to claim 1, wherein The memory structure includes a ferroelectric material.

12. The semiconductor device according to claim 1, wherein Each of the memory strings has an elliptical cross section.

13. The semiconductor device according to claim 1, wherein At least one conductive layer of the conductive layers of the stack includes a first gate and a second gate, the first gate and the second gate are separated from each other by an isolation structure, the first gate corresponds to the first position, and the second gate corresponds to the second position.

14. The semiconductor device according to claim 13, wherein: The first gate is used as a memory gate, and the second gate is used as a selection gate.

15. The semiconductor device according to claim 13, wherein: The invention also comprises an oxide layer, wherein the oxide layer is arranged between the channel layer and the second gate, and the memory structure is arranged between the channel layer and the first gate.

16. The semiconductor device according to claim 15, wherein: The oxide layer extends between the channel layer and the second gate, and between the isolation structure and the second gate; the memory structure extends between the isolation structure and the first gate, and between the channel layer and the first gate.

17. The semiconductor device according to claim 13, wherein: The portion of the isolation structure corresponding to the insulating layers located above the first gate and the second gate has a first width in a second direction; the portion of the isolation structure corresponding to the first gate and the second gate has a second width in the second direction, the first width is greater than the second width, wherein the second direction is perpendicular to the first direction.

18. An array layout of a semiconductor device, wherein: include: A stacked layer formed on a substrate, the stacked layer comprising a plurality of conductive layers and a plurality of insulating layers stacked alternately; A plurality of memory strings are arranged on the substrate along a second direction and a third direction to form a memory array, the first direction, the second direction and the third direction being perpendicular to each other, wherein each of the memory strings comprises: a channel layer extending along the first direction; a memory structure disposed between the stack and the channel layer; A first conductive pillar and a second conductive pillar extend along the first direction and are electrically isolated from each other, and are respectively coupled to a first position and a second position of the channel layer, the first position is opposite to the second position, wherein the memory structure surrounds the first position and exposes the second position, the channel layer has an annular inner surface and an annular outer surface, and the first conductive pillar and the second conductive pillar are coupled to the annular inner surface; In the memory array, the memory strings are arranged into multiple rows of memory strings along the third direction, and adjacent rows of memory strings have an offset distance in the third direction. The first positions of two adjacent rows of the memory strings are adjacent to each other.

19. The array layout of the semiconductor device according to claim 18, wherein: Also includes: A plurality of conductive patterns are electrically connected to one of the first conductive pillar and the second conductive pillar respectively; A plurality of input lines extending along the second direction, each of the input lines being coupled to a corresponding first conductive column through a first through hole; as well as A plurality of output lines extend along the second direction, and each of the output lines is coupled to the corresponding second conductive column through a second through hole.

20. A packaging structure, wherein: include: A memory chip comprising the semiconductor device according to claim 1; as well as a memory control chip, used to control the memory chip, The memory chip is arranged on the memory control chip.

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