Oscillator circuit

Abstract

The present application relates to electronic technology and discloses an oscillator circuit, which includes: an integrator, a comparator, an edge trigger, a first capacitor and a second capacitor; wherein, the two input terminals of the comparator are respectively coupled to the output terminal and the first input terminal of the integrator; the output terminal of the comparator is coupled to the input terminal of the edge trigger; the edge trigger is configured to output a mutually exclusive first signal and a second signal, and flip the first signal and the second signal when a rising edge or a falling edge of the comparator output is detected; when the first signal is at a specified level, the first capacitor is charged, the second capacitor is discharged, and the first terminal of the first capacitor is coupled to the input terminal of the integrator; when the second signal is at a specified level, the second capacitor is charged, the first capacitor is discharged, and the first terminal of the second capacitor is coupled to the input terminal of the integrator.

Description

Technical Field

[0001] The present invention relates to electronic technology, and in particular to oscillator technology. Background Art

[0002] This section is intended to provide a background or context to the embodiments of the present application as recited in the claims. No admission is made that the description herein is prior art as disclosed by virtue of its inclusion in this section.

[0003] RC oscillator circuits (including relaxation oscillator circuits) are widely used in various chips due to their low power consumption and high integration. For example, they are used as low-power chip system clocks, low-power mode clocks for system-on-chip chips, and high-speed interface initialization clocks.

[0004] like Figure 1 As shown in Figure 1, a traditional relaxation oscillator circuit consists of a pair of current sources, an integrating capacitor, a pair of voltage comparators, and an SR latch circuit. The period of its output clock depends on the sum of the charging and discharging time of the integrating capacitor and the logic delays introduced by the comparators and latch. A disadvantage of traditional relaxation oscillator circuits is that the logic delays introduced by the comparators and latches vary with chip voltage and temperature, thus changing the frequency of the output clock.

[0005] In order to solve the above-mentioned problems of the traditional relaxation oscillator circuit, a voltage average feedback oscillator circuit is proposed, whose structure is as follows: Figure 2 For details, please refer to the paper "Y. Tokunaga, et al. "An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage," 2009 IEEE International Solid-State Circuits Conference-Digest of Technical Papers, San Francisco, CA, 2009, pp. 404-405, 405a, doi:10.1109 / ISSCC.2009.4977479." The voltage-averaging feedback oscillator circuit dynamically adjusts the reference voltage of the comparator circuit, absorbing the delays generated by the comparator and latch circuits into the charge and discharge time, thereby improving the frequency stability of the oscillator circuit's output clock. Furthermore, the low-bandwidth integrating loop introduced in the voltage-averaging feedback oscillator circuit suppresses the oscillator circuit's low-frequency noise and reduces the jitter of the output clock.

[0006] Although the existing voltage average feedback oscillator circuit has excellent performance, it still has three main shortcomings:

[0007] 1) The implementation is not optimized in terms of power consumption and hardware overhead. A typical implementation requires two RC charging circuits, two voltage comparators, and an SR latch.

[0008] 2) The oscillator circuit alternately uses one of the two RC charging circuits and one of the two voltage comparators in each half cycle. Mismatches in on-chip components cause deviations in the duration of adjacent half cycles, which in turn causes the oscillator output clock duty cycle to deviate from 50%.

[0009] 3) Reliance on a complex control process to ensure reliable startup. Two sets of voltage comparators share a dynamically adjusted internal reference voltage. Depending on the initial state at startup, the system may be in different states. The reference voltage is affected by the voltages at the charge and discharge nodes, which in turn affects the comparator outputs, creating a risk of system lockup in the initial state.

[0010] To reliably start the voltage-averaging feedback oscillator circuit, the latch must first be reset, followed by setting an initial reference voltage value, and then releasing the latch's two inputs with sufficient delay. Only after completing these three steps can the oscillator circuit enter normal operation. A reliable startup scheme can be found in the paper "Y. Tokunaga, S. Sakiyama, A. Matsumoto, and S. Dosho, "An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback," in IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1150-1158, June 2010, doi:10.1109 / JSSC.2010.2048732."

[0011] It's worth noting that the overhead of this complex startup process is non-negligible for many systems. The relaxation oscillator in a SoC often serves as the initialization clock in crystal-less systems. During its own startup, the system lacks a clock signal and cannot provide the aforementioned control flow. Summary of the Invention

[0012] The purpose of this application is to provide an oscillator circuit that can avoid a complicated startup process while maintaining a stable output frequency, achieve a better output clock duty cycle, and optimize the comparator area and power consumption by half.

[0013] The present application discloses an oscillator circuit, comprising: an integrator, a comparator, an edge trigger, a first capacitor and a second capacitor; wherein,

[0014] The two input terminals of the comparator are coupled to the output terminal and the first input terminal of the integrator respectively; the output terminal of the comparator is coupled to the input terminal of the edge trigger;

[0015] The edge trigger is configured to output mutually exclusive first and second signals, and flip the first and second signals when a rising edge or a falling edge of the comparator output is detected; when the first signal is at a specified level, the first capacitor is charged, the second capacitor is discharged, and the first end of the first capacitor is coupled to the input end of the integrator; when the second signal is at a specified level, the second capacitor is charged, the first capacitor is discharged, and the first end of the second capacitor is coupled to the input end of the integrator.

[0016] In a preferred embodiment, it further includes a plurality of controlled switching devices;

[0017] The plurality of controlled switching devices are controlled by the first signal and the second signal;

[0018] When the first signal is at a specified level, the plurality of controlled switching devices are configured to charge the first capacitor, discharge the second capacitor, and couple the first terminal of the first capacitor to the input terminal of the integrator;

[0019] When the second signal is at a specified level, the plurality of controlled switching devices are configured to charge the second capacitor, discharge the first capacitor, and couple the first terminal of the second capacitor to the input terminal of the integrator.

[0020] In a preferred example, the controlled switching device is a MOS transistor.

[0021] In a preferred embodiment, it further includes a first resistor;

[0022] The plurality of controlled switch devices include first to sixth MOS transistors;

[0023] The gates of the first MOS transistor, the second MOS transistor, and the third MOS transistor are coupled to the first signal; the gates of the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are coupled to the second signal;

[0024] A first end of the first resistor is coupled to a power source;

[0025] The source and drain of the first MOS transistor are respectively coupled to the second end of the first resistor and the first end of the first capacitor; the source and drain of the fourth MOS transistor are respectively coupled to the second end of the first resistor and the first end of the second capacitor;

[0026] The second end of the first capacitor is coupled to the ground; the second end of the second capacitor is coupled to the ground;

[0027] The source and drain of the second MOS transistor are connected in parallel with the second capacitor; the source and drain of the fifth MOS transistor are connected in parallel with the first capacitor;

[0028] The source and drain of the third MOS tube are coupled to the first end of the first capacitor and the first input end of the integrator respectively; the source and drain of the sixth MOS tube are coupled to the first end of the second capacitor and the first input end of the integrator respectively.

[0029] In a preferred example, the edge trigger is a rising edge trigger, which flips the first signal and the second signal only when a rising edge of the comparator output is detected.

[0030] In a preferred embodiment, it further includes a first resistor;

[0031] The plurality of controlled switch devices include first to sixth MOS transistors;

[0032] The gates of the first MOS transistor, the second MOS transistor, and the third MOS transistor are coupled to the first signal; the gates of the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are coupled to the second signal;

[0033] A first end of the first resistor is coupled to ground;

[0034] The source and drain of the first MOS transistor are respectively coupled to the second end of the first resistor and the first end of the first capacitor; the source and drain of the fourth MOS transistor are respectively coupled to the second end of the first resistor and the first end of the second capacitor;

[0035] The second end of the first capacitor is coupled to the power supply; the second end of the second capacitor is coupled to the power supply;

[0036] The source and drain of the second MOS transistor are connected in parallel with the second capacitor; the source and drain of the fifth MOS transistor are connected in parallel with the first capacitor;

[0037] The source and drain of the third MOS tube are respectively coupled to the first end of the first capacitor and the first input end of the integrator; the source and drain of the sixth MOS tube are respectively coupled to the first end of the second capacitor and the first input end of the integrator.

[0038] In a preferred example, the edge trigger is a falling edge trigger, which flips the first signal and the second signal only when a falling edge of the comparator output is detected.

[0039] In a preferred example, the second input terminal of the integrator is coupled to a reference voltage.

[0040] In a preferred example, the controlled switching device is a transmission gate.

[0041] In a preferred embodiment, the integrator includes an operational amplifier, a second resistor and a third capacitor;

[0042] The first end of the second resistor serves as the first input end of the integrator, and the second end of the second resistor is coupled to the first input end of the operational amplifier; the second input end of the operational amplifier is coupled to a reference voltage; one end of the third capacitor is coupled to the second end of the second resistor, and the other end is coupled to the output end of the operational amplifier.

[0043] In the embodiments of the present application, a single comparator multiplexing with an edge-triggered circuit replaces the dual comparator and SR latch circuit scheme. By increasing the delay of the logic delay portion that does not harm system performance and adding beneficial logic functions (edge-triggered circuits and non-overlapping clock generation), the comparator area and power consumption are optimized by half through comparator reuse in each half cycle without affecting overall performance. This structural optimization simplifies the possible states of the circuit at startup, making it possible to start the circuit concisely and reliably.

[0044] The various technical features disclosed in the above invention content, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (all of which should be deemed to have been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that play the same role. Technically, only one of them needs to be used, and it is impossible to use them at the same time. Feature E can be technically combined with feature C. In this case, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, while the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a schematic structural diagram of a conventional relaxation oscillator circuit in the prior art;

[0046] Figure 2 It is a schematic structural diagram of a voltage average feedback oscillator circuit in the prior art;

[0047] Figure 3 is a schematic structural diagram of an oscillator circuit according to an embodiment of the present application;

[0048] Figure 4 2 is a schematic diagram of an oscillator circuit structure according to another embodiment of the present application. DETAILED DESCRIPTION

[0049] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0050] Description of some concepts:

[0051] A comparator is a circuit that compares an analog voltage signal with a reference voltage. Its two inputs are analog signals, and its output is a binary signal of 0 or 1. When the difference between the input voltages increases or decreases without changing their sign, the output remains constant.

[0052] An integrator is an electronic component whose output signal is the time integral of the input signal.

[0053] Edge trigger: A trigger that flips its output signal when it detects a specific transition (rising or falling) of the input signal. For example, assuming the initial output signal is 0, when the first rising edge of the input signal is detected, the output signal flips from 0 to 1. When the second rising edge of the input signal is detected, the output signal flips from 1 to 0. When the third rising edge of the input signal is detected, the output signal flips from 0 to 1, and so on. The output signal can be one or two. For example, there can be two mutually exclusive output signals. Assume that in the initial state, the first output signal is 0 and the second output signal is 1. When the first falling edge of the input signal is detected, the first output signal flips to 1 and the second output signal flips to 0. When the second falling edge of the input signal is detected, the first output signal flips to 0 and the second output signal flips to 1. When the third falling edge of the input signal is detected, the first output signal flips to 1 and the second output signal flips to 0, and so on.

[0054] Controlled Switch: A switching device that can be turned on or off by a control signal. For example, a control signal of 1 turns the switch on, and a control signal of 0 turns the switch off.

[0055] MOS tube: Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

[0056] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0057] The first embodiment of the present application relates to an oscillator circuit, such as Figure 3 As shown, the oscillator circuit includes: an integrator 10, a comparator 12, an edge trigger 13, a first capacitor C1 and a second capacitor C2.

[0058] The two input terminals of the comparator are respectively coupled to the output terminal and the first input terminal of the integrator. The output terminal of the comparator is coupled to the input terminal of the edge trigger. The second input terminal of the integrator is coupled to the reference voltage Vref.

[0059] The edge trigger is configured to output the first signal of the mutually exclusive and the second signal And when the rising edge (or falling edge) of the comparator output is detected, the first signal and the second signal are flipped. When the first signal is at a specified level, the first capacitor is charged, the second capacitor is discharged, and the first end of the first capacitor is coupled to the input end of the integrator. When the second signal is at a specified level, the second capacitor is charged, the first capacitor is discharged, and the first end of the second capacitor is coupled to the input end of the integrator. Among them, the specified level can be a high level (or a signal representing 1) or a low level (or a signal representing 0). Because the first signal and the second signal are mutually exclusive, when the first signal is at a specified level, the second signal is at a non-specified level; and when the first signal is at a non-specified level, the second signal is at a specified level. The flipping of the first signal and the second signal refers to the flipping between the two states of the specified level and the non-specified level.

[0060] In this embodiment, the delay of the comparator and the edge trigger is absorbed into the RC charge and discharge time, thereby not causing the oscillation period of the oscillator circuit to change with voltage and temperature.

[0061] This implementation replaces the two comparators and SR latch in the voltage-averaged feedback oscillator circuit with a single comparator and edge-triggered flip-flop. This reduces the power consumption and area of ​​the comparator, simplifies the system state possibilities, and simplifies reliable startup conditions. The edge-triggered flip-flop adds additional logic delay, but because this delay is absorbed into the RC charging time along with the comparator delay, it is effectively indistinguishable from the comparator's own delay and does not cause clock period variations with voltage or temperature. and The non-overlapping clock signal generated by the edge trigger circuit is used to alternately charge and reset the two charging capacitors and correctly connect the charging capacitors to the integrator and comparator inputs. Thanks to the system simplification brought by the comparator multiplexing, the oscillator circuit can be used at any Start in status ( The opposite polarity can be ensured by the non-overlapping clock generation circuit.) The reliable startup of the oscillator circuit only requires that the potentials of the Vosc and Vcmp nodes are preset in the reset state and released at any time to enter the normal working mode.

[0062] In one embodiment, the oscillator circuit further comprises a plurality of controlled switch devices P1-P6. The plurality of controlled switch devices are controlled by the first signal and the second signal, wherein P1-P3 are controlled by Control, P4-P6 Control. When the first signal is at a specified level, the plurality of controlled switching devices are configured to charge the first capacitor, discharge the second capacitor, and couple the first end of the first capacitor to the input of the integrator. When the second signal is at a specified level, the plurality of controlled switching devices are configured to charge the second capacitor, discharge the first capacitor, and couple the first end of the second capacitor to the input of the integrator. When the first signal is at a specified level (e.g., a high level), the controlled switching devices are turned on, and when the first signal is at a non-specified level (e.g., a low level), the controlled switching devices are turned off.

[0063] In other embodiments, the number and configuration of the controlled switch devices are not limited to Figure 3 The method can be used as long as the following functions can be achieved: when the first signal is at a specified level, the first capacitor is charged, the second capacitor is discharged, and the first end of the first capacitor is coupled to the input end of the integrator; when the second signal is at a specified level, the second capacitor is charged, the first capacitor is discharged, and the first end of the second capacitor is coupled to the input end of the integrator.

[0064] The controlled switching device can be of various types, as long as it can be controlled by a control signal to achieve the function of connection and disconnection. Optionally, in one embodiment, the controlled switching device is a MOS transistor. Optionally, in one embodiment, the controlled switching device is a transmission gate. Optionally, in one embodiment, the controlled switching device is a switching transistor. Optionally, in one embodiment, a controlled switching device can also be a combination of multiple devices.

[0065] Optionally, in one embodiment, Figure 3 As shown, the oscillator circuit further includes a first resistor R1. The plurality of controlled switch devices include first to sixth MOS transistors (corresponding to positions P1-P6, respectively, Figure 3 The MOS tube is not drawn in the figure. The source and drain of the MOS tube correspond to Figure 3The two ends of the controlled switching device, for example, the source and drain of the first MOS transistor, can be respectively arranged at the two ends of the controlled switching device P1. The gates of the first, second, and third MOS transistors are coupled to the first signal. The gates of the fourth, fifth, and sixth MOS transistors are coupled to the second signal. The first end of the first resistor is coupled to the power supply VCC. The source and drain of the first MOS transistor are coupled to the second end of the first resistor and the first end of the first capacitor, respectively. The source and drain of the fourth MOS transistor are coupled to the second end of the first resistor and the first end of the second capacitor, respectively. The second end of the first capacitor is coupled to ground. The second end of the second capacitor is coupled to ground. The source and drain of the second MOS transistor are connected in parallel with the second capacitor. The source and drain of the fifth MOS transistor are connected in parallel with the first capacitor. The source and drain of the third MOS transistor are coupled to the first end of the first capacitor and the first input of the integrator, respectively. The source and drain of the sixth MOS transistor are coupled to the first end of the second capacitor and the first input of the integrator, respectively. In this embodiment, the edge trigger is a rising edge trigger that flips the first and second signals only when a rising edge of the comparator output is detected. In other words, a falling edge does not cause the edge trigger to flip the first signal and the second signal. In this application, the source and drain of a MOS transistor are coupled to A or B respectively, which means that the source is coupled to A and the drain is coupled to B, or the source is coupled to B and the drain is coupled to A. The specific coupling method may depend on the type of MOS transistor (P-type or N-type) and the specific design of the circuit.

[0066] Optionally, in one embodiment, the oscillator circuit has another variation, such as Figure 4 The plurality of controlled switch devices shown include first to sixth MOS transistors (corresponding to positions P1-P6, respectively, Figure 4 The MOS tube is not drawn in the figure. The source and drain of the MOS tube correspond to Figure 4The two ends of the controlled switching device, for example, the source and drain of the first MOS transistor, can be respectively provided at the two ends of the controlled switching device P1. The gates of the first, second, and third MOS transistors are coupled to the first signal. The gates of the fourth, fifth, and sixth MOS transistors are coupled to the second signal. The first end of the first resistor R1 is coupled to ground. The source and drain of the first MOS transistor are coupled to the second end of the first resistor and the first end of the first capacitor, respectively. The source and drain of the fourth MOS transistor are coupled to the second end of the first resistor and the first end of the second capacitor, respectively. The second end of the first capacitor is coupled to a power supply. The second end of the second capacitor is coupled to a power supply. The source and drain of the second MOS transistor are connected in parallel with the second capacitor. The source and drain of the fifth MOS transistor are connected in parallel with the first capacitor. The source and drain of the third MOS transistor are coupled to the first end of the first capacitor and the first input of the integrator, respectively. The source and drain of the sixth MOS transistor are coupled to the first end of the second capacitor and the first input of the integrator, respectively. In this embodiment, the edge trigger is a falling edge trigger that flips the first and second signals only upon detecting a falling edge of the comparator output.

[0067] Optionally, in other embodiments, Figure 3 and Figure 4 Other changes can be made to the circuit. For example, Figure 3 The resistor R1 in the figure is realized by two resistors, one of which is connected between VCC and one end of the controlled switch device P1 ( Figure 3 The other resistor is connected between VCC and one end of the controlled switch device P4 ( Figure 3 For example, Figure 4 Similar changes can be made to Figure 4 The resistor R1 in the figure is realized by two resistors, one of which is connected to the ground and one end of the controlled switch device P1 ( Figure 4 The other resistor is connected between the ground and one end of the controlled switch device P4 ( Figure 4 between the lower end of P4).

[0068] Integrator is a prior art and can be implemented in a variety of ways. Optionally, in one embodiment, the integrator includes an operational amplifier 11, a second resistor Rint and a third capacitor Cint (e.g. Figure 3 (as shown). A first end of the second resistor serves as a first input end of the integrator, and a second end of the second resistor is coupled to a first input end of the operational amplifier. The second input end of the operational amplifier is coupled to a reference voltage. One end of the third capacitor is coupled to the second end of the second resistor, and the other end is coupled to the output end of the operational amplifier.

[0069] Alternatively, in one embodiment, the oscillator circuit may be used in an integrated circuit as a part of the integrated circuit, which may be a SOC (system on a chip).

[0070] Optionally, in one embodiment, the above-mentioned oscillator circuit may be used in a digital clock circuit to provide an oscillation signal for the digital clock circuit.

[0071] This implementation replaces the dual comparator and SR latch circuit scheme by using a single comparator multiplexing circuit combined with an edge-triggered circuit. By increasing the delay of logic delays that don't harm system performance and adding beneficial logic functions (edge-triggered circuits and non-overlapping clock generation), the comparator area and power consumption are reduced by half by multiplexing the comparators in each half cycle without affecting overall performance. This structural optimization simplifies the possible states of the circuit during startup, enabling simple and reliable circuit startup.

[0072] It should be noted that, in the disclosure, relational terms such as first and second are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article, or device. Without further restriction, an element defined by the phrase "comprising a" does not exclude the presence of other identical elements in the process, method, article, or device comprising the element. In this application, if it is mentioned that an action is performed according to a certain element, it means that the action is performed at least according to that element, including two situations: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "multiple," and "multiple" include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0073] The term "coupled to" and its derivatives may be used herein. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

[0074] This specification includes combinations of the various embodiments described herein. Separate references to an embodiment (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated as such or clear to one skilled in the art. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0075] All documents mentioned in this application are considered to be included in their entirety in the disclosure of this application so that they can be used as a basis for modification when necessary. In addition, it should be understood that after reading the contents of this application, those skilled in the art may make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. An oscillator circuit, characterized in that: include: an integrator, a comparator, an edge trigger, a non-overlapping clock generating circuit, a first capacitor and a second capacitor; wherein, The two input terminals of the comparator are coupled to the output terminal and the first input terminal of the integrator respectively; the output terminal of the comparator is coupled to the input terminal of the edge trigger; The edge trigger is configured to output non-overlapping and mutually exclusive first and second signals, and flip the first and second signals when a rising edge or a falling edge of the comparator output is detected; the non-overlapping clock generation circuit is used to ensure that the first and second signals are non-overlapping clock signals with opposite polarities; when the first signal is at a specified level, the first capacitor is charged, the second capacitor is discharged, and the first end of the first capacitor is coupled to the input end of the integrator; when the second signal is at a specified level, the second capacitor is charged, the first capacitor is discharged, and the first end of the second capacitor is coupled to the input end of the integrator.

2. The oscillator circuit according to claim 1, wherein Also included are a plurality of controlled switching devices; The plurality of controlled switching devices are controlled by the first signal and the second signal; When the first signal is at a specified level, the plurality of controlled switching devices are configured to charge the first capacitor, discharge the second capacitor, and couple the first terminal of the first capacitor to the input terminal of the integrator; When the second signal is at a specified level, the plurality of controlled switching devices are configured to charge the second capacitor, discharge the first capacitor, and couple the first terminal of the second capacitor to the input terminal of the integrator.

3. The oscillator circuit according to claim 2, wherein: The controlled switch device is a MOS tube.

4. The oscillator circuit according to claim 3, wherein: Also comprising a first resistor; The plurality of controlled switch devices include first to sixth MOS transistors; The gates of the first MOS transistor, the second MOS transistor, and the third MOS transistor are coupled to the first signal; the gates of the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are coupled to the second signal; A first end of the first resistor is coupled to a power source; The source and drain of the first MOS transistor are respectively coupled to the second end of the first resistor and the first end of the first capacitor; the source and drain of the fourth MOS transistor are respectively coupled to the second end of the first resistor and the first end of the second capacitor; The second end of the first capacitor is coupled to the ground; the second end of the second capacitor is coupled to the ground; The source and drain of the second MOS transistor are connected in parallel with the second capacitor; the source and drain of the fifth MOS transistor are connected in parallel with the first capacitor; The source and drain of the third MOS tube are coupled to the first end of the first capacitor and the first input end of the integrator respectively; the source and drain of the sixth MOS tube are coupled to the first end of the second capacitor and the first input end of the integrator respectively.

5. The oscillator circuit according to claim 4, wherein: The edge trigger is a rising edge trigger that inverts the first signal and the second signal only when a rising edge of the comparator output is detected.

6. The oscillator circuit according to claim 3, wherein: Also comprising a first resistor; The plurality of controlled switch devices include first to sixth MOS transistors; The gates of the first MOS transistor, the second MOS transistor, and the third MOS transistor are coupled to the first signal; the gates of the fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are coupled to the second signal; A first end of the first resistor is coupled to ground; The source and drain of the first MOS transistor are respectively coupled to the second end of the first resistor and the first end of the first capacitor; the source and drain of the fourth MOS transistor are respectively coupled to the second end of the first resistor and the first end of the second capacitor; The second end of the first capacitor is coupled to the power supply; the second end of the second capacitor is coupled to the power supply; The source and drain of the second MOS transistor are connected in parallel with the second capacitor; the source and drain of the fifth MOS transistor are connected in parallel with the first capacitor; The source and drain of the third MOS tube are respectively coupled to the first end of the first capacitor and the first input end of the integrator; the source and drain of the sixth MOS tube are respectively coupled to the first end of the second capacitor and the first input end of the integrator.

7. The oscillator circuit according to claim 6, wherein: The edge trigger is a falling edge trigger that inverts the first signal and the second signal only when a falling edge of the comparator output is detected.

8. The oscillator circuit according to claim 1, wherein The second input terminal of the integrator is coupled to a reference voltage.

9. The oscillator circuit according to claim 2, wherein: The controlled switching device is a transmission gate.

10. The oscillator circuit according to claim 1, wherein: The integrator includes an operational amplifier, a second resistor and a third capacitor; The first end of the second resistor serves as the first input end of the integrator, and the second end of the second resistor is coupled to the first input end of the operational amplifier; the second input end of the operational amplifier is coupled to a reference voltage; one end of the third capacitor is coupled to the second end of the second resistor, and the other end is coupled to the output end of the operational amplifier.

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