System and method for calibrating frequency multiplier

Abstract

Embodiments of the present disclosure relate to systems and methods for calibrating frequency multipliers. According to one embodiment, a method includes receiving, by a tunable frequency multiplication circuit, a first clock signal having a first clock frequency; generating, using the tunable frequency multiplication circuit, a second clock signal having a second clock frequency, the second clock frequency being twice the first clock frequency; measuring a duty cycle parameter of the second clock signal, wherein the duty cycle parameter depends on a duty cycle of the first clock signal or a duty cycle of the second clock signal; and adjusting, using the tunable frequency multiplication circuit, the duty cycle of the first clock signal or the duty cycle of the second clock signal based on the measurement.

Description

Technical Field

[0001] This invention generally relates to a system and method for calibrating a frequency multiplier. Background Technology

[0002] In many radio frequency (RF) systems, such as portable wireless devices designed to operate in LTE or 5G-based cellular systems, a wide variety of circuits and systems are used to implement RF and baseband functions. For example, most systems include: an RF downconverter that downconverts the RF signal received from the antenna to baseband and / or intermediate frequency (IF) signals; an analog-to-digital converter (ADC) that digitizes the downconverted RF signal; a processor that performs calculations and processing on the digitized signal; a digital-to-analog converter (DAC) that generates the baseband or intermediate signal for transmission; and an RF upconverter that upconverts the baseband or intermediate signal to the RF frequency for transmission through the antenna. In addition to the necessary signal path circuitry (such as amplifiers, mixers, filters, and data conversion and processing circuitry for implementing these functions), each of these functions may require a clock signal or oscillator signal to operate. For example, RF downconverters and RF upconverters typically utilize an RF local oscillator (LO) signal, and the ADC, DAC, and processor utilize a digital clock signal. Therefore, such RF systems additionally include frequency generation circuitry to support RF, baseband, and processing functions.

[0003] Many RF systems use frequency generation systems where one or more voltage-controlled oscillators (VCOs) reference the frequency of a crystal oscillator using one or more phase-locked loop (PLL) circuits. One or more additional PLLs or delay-locked loops (DLLs) can also be used to generate high-frequency clocks for digital processors and / or data converters. In some cases, these clock and oscillator signals may have performance requirements for controlling phase noise and duty cycle. Designing a frequency generation system configured to cost-effectively generate multiple clock signals that meet performance requirements in portable devices presents numerous challenges and trade-offs in terms of board space, component cost, and power consumption. Summary of the Invention

[0004] According to one embodiment, a method includes: receiving a first clock signal having a first clock frequency via an adjustable frequency multiplier circuit; generating a second clock signal having a second clock frequency, the second clock frequency being twice the first clock frequency, using the adjustable frequency multiplier circuit; measuring a duty cycle parameter of the second clock signal, wherein the duty cycle parameter depends on the duty cycle of the first clock signal or the duty cycle of the second clock signal; and adjusting the duty cycle of the first clock signal or the duty cycle of the second clock signal based on the measurement using the adjustable frequency multiplier circuit.

[0005] According to another embodiment, a system includes: an adjustable frequency multiplier circuit including a clock input, a clock output, and a duty cycle adjustment input, the adjustable frequency multiplier circuit being configured to: receive a first clock signal having a first clock frequency at the clock input; generate a second clock signal having a second clock frequency at the clock output, the second clock frequency being twice the first clock frequency, and adjust the duty cycle of the first clock signal or the duty cycle of the second clock signal based on a duty cycle adjustment signal received at the duty cycle adjustment input; and a duty cycle measurement and adjustment circuit coupled to the clock output and the duty cycle adjustment input of the adjustable frequency multiplier circuit, the duty cycle measurement and adjustment circuit being configured to measure a duty cycle parameter of the second clock signal and generate a duty cycle adjustment signal based on the measured duty cycle parameter.

[0006] According to a further embodiment, an RF system includes: an RF front-end having an input port configured to be coupled to an antenna; a test tone generation circuit; a multiplexer having a first input coupled to an output of the RF front-end and a second input coupled to an output of the test tone generation circuit; an adjustable frequency multiplier circuit including a clock input, a clock input, and a duty cycle adjustment input, the adjustable frequency multiplier circuit being configured to: receive a first clock signal having a first clock frequency at the clock input; generate a second clock signal having a second clock frequency at the clock output, the second clock frequency being twice the first clock frequency; and adjust the duty cycle of the first clock signal or the duty cycle of the second clock signal based on the duty cycle adjustment signal received at the duty cycle adjustment input; and an analog-to-digital converter (ADC) having a clock input coupled to the clock output of the adjustable frequency multiplier circuit, an ADC signal input coupled to the output of the multiplexer, and an ADC signal output configured to provide a first time-domain digital signal. Attached Figure Description

[0007] Figure 1A and Figure 1B An example frequency multiplier system is shown;

[0008] Figures 2A-2D A graph describing the performance of the frequency multiplier system is shown;

[0009] Figures 3A-3I A schematic diagram of the frequency multiplier circuit of the embodiment is shown;

[0010] Figure 4A and Figure 4B A block diagram illustrating an embodiment of a method for calibrating a frequency multiplier circuit is shown;

[0011] Figures 5A-5D A schematic diagram of a system incorporating the frequency multiplier circuit of an embodiment is shown; and Figure 5E Calibration is shown Figure 5A A block diagram of an embodiment of the system method;

[0012] Figures 6A-6C A schematic diagram of a system incorporating the frequency multiplier circuit of an embodiment is shown; and Figure 6D Calibration is shown Figure 6A A block diagram of an embodiment method of the system.

[0013] Figure 7A and Figure 7B A schematic diagram of the RF system of the embodiment is shown; and

[0014] Figure 8 A block diagram of a processing system that can be used to implement a portion of the system in the embodiment is shown.

[0015] Unless otherwise specified, corresponding reference numerals and symbols in different figures generally refer to corresponding parts. The figures are drawn to clearly illustrate relevant aspects of preferred embodiments and are not necessarily drawn to scale. To further illustrate certain embodiments, letters indicating variations in the same structure, materials, or process steps may follow the figure numbers. Detailed Implementation

[0016] The manufacture and use of the presently preferred embodiments will now be discussed in detail. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific environments. The specific embodiments discussed are merely illustrative of particular ways of manufacturing and using the invention and do not limit the scope of the invention.

[0017] The invention will be described in a particular context with respect to preferred embodiments, systems and methods for calibrating frequency multipliers used in radio transceivers.

[0018] In various embodiments, an adjustable clock multiplier circuit configured to provide a clock signal with an adjustable duty cycle is used to double the frequency of the input clock signal. By adjusting the duty cycle of the double clock signal, the double clock signal is calibrated to a duty cycle substantially 50%, and can be used in clock duty cycle-sensitive circuitry (such as an ADC or a phase-locked loop circuit). In some embodiments, the duty cycle is calibrated by providing a test tone (such as an analog test tone) to the ADC, monitoring the spurious response of the ADC converter, and iteratively adjusting the duty cycle of the clock multiplier circuit to reduce or minimize the spurious response of the ADC converter. In other embodiments, the double clock signal can be monitored directly during calibration to determine and calibrate its duty cycle.

[0019] Alternatively, or in addition to adjusting the duty cycle of the double clock signal, the duty cycle of the input clock signal can be adjusted before doubling it. In various cases, duty cycle errors on the input clock signal can result in alternating duration periods on the double clock signal. These alternating duration periods can cause spurious behavior when used as input to circuitry sensitive to such errors on the double clock signal. For example, circuitry exhibiting this sensitivity includes ADCs that use an odd number of clock cycles per conversion. Therefore, in various embodiments, the duty cycle of the input clock signal can be adjusted or calibrated to substantially 50% before doubling it, thereby advantageously reducing spurious behavior in the data converter and other circuitry.

[0020] In some portable wireless systems, the clock frequencies required for timing data converters and phase-locked loop (PLL) circuits may be higher than those typically used for timing digital processing circuits. For example, in some systems, a 38.4 MHz crystal is typically used to generate the clock signal for the application processor, while higher clock frequencies around 80 MHz can be used to timing analog-to-digital converters and PLL circuits. In some systems, due to the large size of the oscillator crystal and the limited board space available in compact portable wireless devices, frequency multiplier circuitry (such as delay-locked loops (DLLs), additional PLLs, or delay-based frequency multipliers) are often used to obtain higher clock frequencies to provide clock signals to the data converters and PLL circuits. While delay-based frequency multipliers may be physically compact and consume relatively low power, some frequency multipliers may be sensitive to duty cycle errors in the clock signal generated by the crystal oscillator and may additionally tend to produce multiplied clock signals with a duty cycle deviation of 50%. In some cases, these duty cycle errors can degrade the performance of duty cycle-sensitive circuitry that references a multiple of the clock signal.

[0021] For example, in analog-to-digital converters (ADCs) that utilize both edges of the system clock for sampling and other operations, clock asymmetry can lead to spurious behavior and reduce spurious-free dynamic range (SFDR). Errors in the clock duty cycle can translate into frequency errors, resulting in jumps between two frequencies. Additionally, charge pump circuits that rely on both edges of the clock may experience operational difficulties due to a 50% deviation in the clock duty cycle. In ADCs that utilize an odd number of system clocks for conversion, periodic variations in the clock cycle length of the system clock caused by duty cycle asymmetry in the input clock of the frequency multiplier can also lead to spurious behavior and reduce spurious-free dynamic range (SFDR).

[0022] Therefore, in embodiments of the invention, a calibrated frequency multiplier is used to provide a clock with a duty cycle substantially equal to 50% and / or to provide a clock with substantially equal consecutive clock cycles, while advantageously benefiting from the smaller size and power savings offered by the delay-based frequency multiplier circuit.

[0023] Figure 1A An embodiment of a frequency multiplier system 10 is illustrated. As shown, system 10 includes a frequency multiplier 12, a duty cycle sensitive circuit arrangement 14, and a duty cycle measurement and adjustment circuit 16. For example, the duty cycle sensitive system circuit arrangement 14 may include an analog-to-digital converter, a duty cycle sensitive boost circuit (such as a charge pump), and / or other circuit arrangements (such as a PLL and timing-sensitive digital circuitry sensitive to the duty cycle of its input clock or to clock cycle variations caused by duty cycle errors in a pre-doubled clock). The frequency multiplier circuit 12 (also referred to as an "adjustable frequency multiplier circuit") is configured to double the frequency of a first clock signal Clk1x coupled to the clock input of the frequency multiplier circuit 12 and form a second clock signal Clk2x. For example, if the first clock signal Clk1x has a clock frequency of 40 MHz, then the second clock signal Clk2x will have a clock frequency of 80 MHz. However, it should be understood that, depending on the specific application and its specifications, the first clock signal Clk1x and the second clock signal Clk2x can be of any frequency.

[0024] As shown in the figure, the frequency multiplier circuit 12 includes a duty cycle adjustment input, such that the duty cycle adjustment signal DutyAdj is used to adjust the duty cycle of the first clock signal Clk1x and / or the duty cycle of the second clock signal Clk2x. The duty cycle adjustment signal DutyAdj can be implemented as an analog or digital signal comprising one or more bits. In various embodiments, the frequency multiplier circuit 12 is implemented using frequency multiplier circuits known in the art. For example, the frequency multiplier circuit 12 can be implemented using an XOR gate and an adjustable delay circuit as described below. However, in alternative embodiments, other frequency multiplier circuits can be used.

[0025] Duty cycle measurement and adjustment circuitry 16 can be used to directly or indirectly measure the duty cycle of a first clock signal Clk1x and / or the duty cycle of a second clock signal Clk2x, and to adjust the signal DutyAdj in response to these measurements. The measured duty cycle, or a measurement associated with the duty cycle, may also be referred to as a duty cycle parameter. In some embodiments, duty cycle measurement and adjustment circuitry 16 operates only during calibration time periods (e.g., during calibration mode). During normal operation periods, duty cycle measurement and adjustment circuitry 16 may be inactive or de-energized. In other embodiments, duty cycle measurement and adjustment circuitry 16 may operate only during the manufacturing and / or testing of a particular part. In this case, all or part of duty cycle measurement and adjustment circuitry 16 may reside on a test fixture separate from the remainder of the circuitry, including the frequency multiplier circuitry 12 and the duty cycle sensitive system circuitry 14. For example, the frequency multiplier 12 can be calibrated by the duty cycle measurement and adjustment circuitry 16 during wafer fabrication or production testing of the integrated circuit including the duty cycle sensitive system circuitry 14. In other embodiments, the duty cycle measurement and adjustment circuitry 16 can reside on the same integrated circuit or the same system as the frequency multiplier circuitry 12 and the duty cycle sensitive system circuitry 14. In still other embodiments, the duty cycle measurement and adjustment circuitry 16 can continuously monitor the second clock signal Clk2x and provide continuous adjustment of the duty cycle of the first clock signal Clk1x and / or the second clock signal Clk2x generated by the frequency multiplier circuitry 12.

[0026] For example, the duty cycle measurement and adjustment circuit 16 can be implemented using duty cycle measurement circuits known in the art, including but not limited to high-speed counters, mixers, and analog-to-digital converters. Additionally, the duty cycle measurement and adjustment circuit 16 may include digital circuitry (such as state machines and / or processing circuitry) that facilitates the measurement of the duty cycle and the formation of the duty cycle adjustment signal DutyAdj.

[0027] Figure 1BA frequency multiplier system 50 according to an alternative embodiment of the present invention is illustrated. As shown, the frequency multiplier system 50 includes a duty cycle-sensitive analog-to-digital converter 56, the input ADCIN (also referred to as the "ADC signal input") of which is selectively coupled to either a system circuit device 52 or a test tone generator 54 (also referred to as the "test tone generation circuit"). During normal operation of the system 50, the system circuit device 52 provides an analog signal at the input ADCIN of the duty cycle-sensitive analog-to-digital converter 56 via a selection switch 62. As shown, the duty cycle-sensitive analog-to-digital converter 56 is coupled to a second clock signal Clk2x, which provides a clock signal to the duty cycle-sensitive analog-to-digital converter 56 at a clock input, such that the second clock signal Clk2x times the duty cycle-sensitive analog-to-digital converter 56 during operation. The system circuit device 52 may include any system circuit device that generates the analog signal utilized by the system 50. For example, in an RF system, system circuitry 52 may include an RF front-end and / or a downconverter that generates analog signals associated with the received RF signals. In other systems, system circuitry 52 may generate other types of analog signals, including but not limited to audio signals, sensor signals, image signals, and video signals.

[0028] The duty cycle-sensitive analog-to-digital converter 56 converts the analog signal at the input ADCIN to the digital signal ADCOUT (also referred to as "ADC signal output") at its output. The duty cycle-sensitive analog-to-digital converter 56 can be implemented using various analog-to-digital converter architectures, including but not limited to successive approximation converters, Sigma Delta converters, flash memory converters, pipelined converters, and other data converter architectures known in the art. During calibration, a test tone generator 54 provides a test tone to the duty cycle-sensitive analog-to-digital converter 56, which is analyzed by the duty cycle analysis and adjustment circuitry 58. In some embodiments, the combination of the duty cycle-sensitive analog-to-digital converter 56 and the duty cycle analysis and adjustment circuitry 58 may also be referred to as a duty cycle measurement and adjustment circuit. For example, the test tone generator 54 can be implemented using a digital crossover and a low-pass filter. Other test tone generation circuits known in the art may also be used.

[0029] Duty cycle analysis and adjustment circuitry 58 is configured to analyze the spurious behavior of the digital signal ADCOUT and adjust the duty cycle of the frequency multiplier circuitry 12 using a duty cycle adjustment signal DutyAdj. In some embodiments, duty cycle analysis and adjustment circuitry 58 iteratively adjusts the duty cycle adjustment signal DutyAdj until the spurious response of the digital signal ADCOUT meets predetermined performance requirements and / or predetermined threshold requirements. In some embodiments, duty cycle analysis and adjustment circuitry 58 may reside on the same system integrated circuit, circuit board, and / or housing as system circuitry 52, test tone generator 54, duty cycle-sensitive analog-to-digital converter 56, and frequency multiplier circuitry 12. In other embodiments, duty cycle analysis and adjustment circuitry 58 may reside on a separate test fixture used during manufacturing testing and / or calibration of system 50. For example, duty cycle analysis and adjustment circuitry 58 may include a microprocessor, digital signal processing circuitry, dedicated logic, or other circuitry adapted to the spurious response of the digital signal ADCOUT determined according to the systems and methods further described below.

[0030] In some embodiments, the test controller 60 may be used to configure the frequency multiplier system 50 to perform calibration of the frequency multiplier circuit 12. For example, during calibration, the test controller 60 may control switch 62 to route the output of the test tone generator 54 to the input of the duty cycle-sensitive analog-to-digital converter 56. In some embodiments, calibration may occur during calibration test time or during calibration mode. The test controller 60 may also initiate a measurement of the digital signal ADCOUT via duty cycle analysis and adjustment circuitry 58, initiate adjustment of the duty cycle of the frequency multiplier circuit 12, and activate the test tone generator 54 during duty cycle calibration of the frequency multiplier circuit 12. In various embodiments, the test controller 60 or a portion thereof may reside on the same system integrated circuit, circuit board, and / or housing as the system circuitry 52, the test tone generator 54, the duty cycle-sensitive analog-to-digital converter 56, and the frequency multiplier circuit 12. In other embodiments, the test controller 60 or a portion thereof may reside on a separate test fixture used during manufacturing testing and / or calibration of the system 50.

[0031] Figures 2A to 2D Waveform diagrams relating to embodiments of the present invention are shown. Reference Figure 2A Three waveform diagrams are shown. The first waveform diagram shows the first clock signal Clk1x, which represents the clock signal provided to the input of the frequency multiplier circuit 12; the second diagram shows the second clock signal Clk2x output from the frequency multiplier circuit 12 with a non-50% duty cycle; and the third diagram shows the second clock signal Clk2x with a 50% duty cycle. As shown, the second clock signal Clk2x corresponds to a time period t.H It has a high value, and for a time period t L It has a low value. For non-50% duty cycle, the time period t H and t L They are not equal. In the example shown, the time period t H It is shown as shorter than the time period t L However, in other cases where the second clock signal Clk2x has a non-50% duty cycle, the time period t H It can be longer than the time period t L When the duty cycle of the second clock signal Clk2x is approximately 50%, the time period t H Basically equal to the time period t L In various embodiments, the duty cycle of the second clock signal Clk2x is adjusted until the duty cycle is substantially 50%. In some embodiments, the duty cycle of the second clock signal Clk2x is considered substantially 50% when the measured duty cycle parameter is within a predetermined range and / or the duty cycle is adjusted to have an acceptable quality metric.

[0032] Figure 2B The waveform diagram shows a first clock signal Clk1x with a non-50% duty cycle and a resulting second clock signal Clk2x with a varying time period. As shown, the first clock signal has a time period t... H It has high values ​​and for time period t L It has a low value, where the time period t H Not equal to the time period t L The resulting double second clock signal Clk2x has a time period with alternating durations. For example, at time t of the first clock signal Clk1x... H In the corresponding time period, the second clock signal Clk2x has t P1 The clock cycle. However, at time t of the first clock signal Clk1x. L In the corresponding time period, the second clock signal Clk2x has t P2 The clock cycle, where the time period t P1 Not equal to the time period t P2 These time periods t P1 and t P2 They alternate with each other. Therefore, as the duty cycle of the first clock signal Clk1x approaches 50%, the clock period t of the second clock signal... P1 With t P2 The changes between them decrease.

[0033] In various embodiments, the duty cycle of the second clock signal Clk2x is adjusted until the continuous clock period t.H and t L The lengths are substantially equal until they are all equal. In some embodiments, when the measured duty cycle parameter is within a predetermined range and / or the duty cycle of the first clock signal Clk1x is adjusted to have acceptable quality, the continuous clock period t H and t L The lengths are considered to be substantially equal.

[0034] Figure 2C The diagram shows the output spectrum of the duty cycle-sensitive analog-to-digital converter 56 when a 1MHz test tone from the test tone generator 54 is presented at the input ADCIN, and when timed by a second clock signal Clk2x with a non-50% duty cycle. Generated using Fast Fourier Transform (FFT). Figure 2B The peak in the spectrum at point 70 represents the 1MHz test tone, while the peak at point 72 represents the frequency spurious signal at 600kHz caused by the non-50% duty cycle of the second clock signal Clk2x.

[0035] Figure 2C The specific example shown illustrates a case where the duration of the sampling interval of a duty cycle-sensitive analog-to-digital converter 56 alternates due to an asymmetric nature of a non-50% duty cycle. For example, during operation, short and long sampling intervals alternate with each other. This alternation in the sampling intervals effectively results in high sampling frequency f. s The pitch at half the frequency of the input pitch. Mixing this pitch with the input pitch will cause the following spurious signals:

[0036] f spur =f s / 2–f in

[0037] Where f spur It is the spurious frequency and f in The frequency of the tone generated by the test tone generator 54 is shown. In the case shown, the sampling frequency is 3.2 MHz and the input tone is 1 MHz, with the expected spurious frequency at 600 kHz. It should be understood that the above equations assume the duration of the sampling interval alternates at each sampling interval. In an alternative embodiment of the invention, the duty cycle-sensitive analog-to-digital converter 56 is not timed at each cycle of the second clock signal Clk2x, and the frequency of the spurious frequency may differ from f depending on the specific ADC clocking scheme. s / 2-f in .

[0038] Figure 2DThe diagram shows the spurious-free dynamic range relative to duty cycle for various frequencies. Curve 74 represents an input frequency of 1 MHz, curve 76 represents an input frequency of 800 kHz, curve 78 represents an input frequency of 600 kHz, curve 80 represents an input frequency of 400 kHz, and curve 82 represents an input frequency of 200 kHz. Figure 2C The graph shows that the spurious-free dynamic range of the duty cycle-sensitive analog-to-digital converter 56 decreases as the duty cycle of the second clock signal Clk2x deviates from 50%. For example, for a 50% duty cycle, the spurious-free dynamic range of the duty cycle-sensitive analog-to-digital converter 56 exceeds 90 dB. However, for 47% or 53% duty cycles, the spurious-free dynamic range of the duty cycle-sensitive analog-to-digital converter 56 is only about 53 dB. Furthermore, the spurious-free dynamic range of the duty cycle-sensitive analog-to-digital converter 56 also decreases with increasing tone frequency. As shown, for a 47% or 53% duty cycle, the spurious-free dynamic range with an input tone of 200 kHz is approximately 66 dB, while the spurious-free dynamic range with an input tone of 1 MHz is approximately 53 dB. It should be understood that the actual spurious-free dynamic range can vary depending on the specific architecture used, its architecture, its clock speed, the amplitude of the input tone, and other factors. Although Figure 2C and 2D The waveform diagram illustrates an example of spurious performance in a system where the duty cycle of the second clock signal Clk2x varies. However, when the duty cycle of the first clock signal Clk1x changes, similar comparative performance can be observed for analog-to-digital converters, particularly those sensitive to the alternation period length of the second clock signal Clk2x, which is caused by the duty cycle error in the first clock signal Clk1x.

[0039] Figures 3A to 3D A schematic diagram of a frequency multiplier circuit 12 according to an embodiment of the present invention is shown. Figure 3AA top-level schematic diagram of the frequency multiplier circuit 12 is shown. As shown, the frequency multiplier circuit 12 includes a duty cycle correction circuit 102, an adjustable delay circuit 104, and an XOR gate 106. During operation, the duty cycle correction circuit 102 corrects the duty cycle of the first clock signal Clk1x and generates an adjusted duty cycle clock signal Clk1xC. As described above, by correcting errors in the duty cycle of the first clock signal Clk1x before doubling its frequency, a more accurate double clock signal frequency can be generated. However, in some embodiments, the duty cycle correction circuit 102 or the adjustable delay circuit can be omitted. For example, in embodiments where the first clock signal Clk1x already has a relatively accurate duty cycle, the duty cycle correction circuit 102 can be omitted, while in embodiments where the immediate circuitry is insensitive to non-50% cycles, a fixed delay can be used to implement the adjustable delay circuit 104.

[0040] The actual doubling of the clock frequency is performed via an adjustable delay circuit 104 and an XOR gate 106. During operation, the adjustable delay circuit 104 delays the adjustable duty cycle clock signal Clk1xC by a quarter of its clock cycle to form a delayed first clock signal Clk1xD. By performing an XOR operation on the adjusted duty cycle clock signal Clk1xC and the delayed first clock signal Clk1xD, a clock signal with a frequency twice that of the first clock signal Clk1x is generated. The resulting duty cycle of the second clock signal Clk2x can be adjusted by adjusting the delay of the adjustable delay circuit 104. In various embodiments, the delay of the adjustable delay circuit 104 is set by a signal DutyAdj, which is provided as a control input to the adjustable delay circuit 104.

[0041] Figure 3B A schematic diagram of an adjustable delay circuit 104 according to an embodiment of the present invention is shown. As shown, the adjustable delay circuit 104 includes a plurality of delay units 110 coupled in series with each other. The delay units 110 may also be referred to as selectable delay circuits. Based on a duty cycle adjustment signal DutyAdj, a multiplexer 111 selects the output of one of the plurality of delay units 110. Thus, for a longer programming delay, delay units 110 coupled near the end of a series of delay units can be selected; for a shorter programming delay, delay units 110 coupled near the beginning of a series of delay units 110 can be selected. In various embodiments, the adjustable delay circuit 104 may include any number of delay units 110. The number of delay units 110 and the amount of time delay that each delay unit 110 can produce can vary depending on the specific embodiment and its specifications. For example, a system with a higher clock frequency may require less delay and fewer delay units compared to a system with a lower clock frequency.

[0042] Figure 3C-3E It shows what can be used to implement Figure 3B A schematic diagram of the delay unit of the delay unit 110 shown. Figure 3C The delay unit includes a buffer 112 loaded by a capacitor 114. The amount of delay time achieved by the delay unit is a function of the strength of the buffer 112 and the size of the capacitor 114. For example, when the buffer 112 is weak and the capacitor 114 is large, the delay unit 110 can produce a longer delay. On the other hand, when the buffer 112 has a strong output and the capacitor 114 is small, the delay unit 110 can produce a shorter delay. In various embodiments, the buffer 112 can be implemented using digital buffer circuitry known in the art. For example, the buffer 112 can be implemented using two inverters coupled in series with each other. Figure 3D The delay unit includes an inverter 113 loaded by a capacitor 114 and buffered by a second inverter 113. Again, the delay time is a function of the capacitance of the capacitor 114 and the strength of the inverter 113 driving the capacitor 114. Alternatively, a series of inverters (such as...) can be used. Figure 3E The delay unit is constructed using the delay unit shown. Figure 3E The delay unit shown is a function of the number and strength of the inverters 113 used to construct the delay unit. Generally, longer delays are associated with weaker inverters and / or a larger number of inverters, while shorter delays are associated with weaker inverters and / or a smaller number of inverters.

[0043] However, it should be understood that Figure 3C-3E The delay units shown are merely a few examples of many possible delay unit architectures that can be used in embodiments of the invention. In alternative embodiments, other structures may be used. For example, delay unit 110 can be implemented using other delay structures that can be used, such as buffer chains, RC networks, etc. In some embodiments, combinations of different delay structures can be combined to implement the delay unit.

[0044] Figure 3F This shows that it can also be used to implement Figure 3AThe adjustable delay circuit 118 of the adjustable delay circuit 104 is shown. As illustrated, the adjustable delay circuit 118 includes an inverter 113 loaded by a variable capacitor 115 and buffered by a second inverter 113. The delay of the adjustable delay circuit 118 can be programmed by adjusting the capacitance of the variable capacitor 115 based on the value of the duty cycle adjustable signal DutyAdj. In some embodiments, the variable capacitor 115 can be implemented using multiple switched capacitors. Therefore, the delay of the adjustable delay circuit 118 can be increased by coupling more of the multiple capacitors to the inverter 113, and the delay can be reduced by coupling fewer of the multiple capacitors to the inverter 113. In alternative embodiments of the invention, the variable capacitor 115 can be implemented using other variable capacitor circuits known in the art, such as varactor diodes.

[0045] In some embodiments, the plurality of adjustable delay circuits 118 may be coupled in series. In other embodiments, the adjustable delay circuits 118 may be used to implement Figure 3B The various delay units 110 shown make the delay of the adjustable delay circuit 104 programmable by adjusting the capacitance of the variable capacitor 115 and by selecting one or more delay units 110 via the multiplexer 111.

[0046] Figure 3G A schematic diagram of an adjustable delay circuit 104 according to an alternative embodiment of the present invention is shown. As shown, the adjustable delay circuit 104 includes a plurality of delay units 110 coupled in series with each other and separated by a multiplexer 130, which is configured to selectively bypass its associated delay units 110 according to a selection signal provided by a duty cycle adjustment signal DutyAdj. Thus, for longer programming delays, more selectable delay units 110 are switched into the signal path using the multiplexer 130; for shorter programming delays, fewer delay units 110 are switched into the signal path using the multiplexer 130. In various embodiments, the adjustable delay circuit 104 may include any number of stages, each stage containing delay units 110 and multiplexers 130. The number of stages and the amount of time delay that each delay unit 110 can produce may vary depending on the specific embodiment and its specifications. For example, a system with a higher clock frequency may require less delay and fewer delay units compared to a system with a lower clock frequency. In some embodiments, Figure 3F The adjustable delay circuit 118 shown can be used to implement the delay unit 110.

[0047] Figure 3H It shows what can be used to implement Figure 3AThe duty cycle correction circuit 102 shown is a duty cycle correction circuit 102. As shown, the duty cycle correction circuit includes an inverter 113, a multiplexer 130, an adjustable delay circuit 104, and an OR gate 132. During operation, the multiplexer selects the clock input signal at node Clk1x based on the multiplexer selection signal POL, or selects the inverted version of the clock input signal generated by the inverter 130 at node Clk1xB. This polarity signal determines the polarity of the output node Clk1xC of the duty cycle correction circuit and which portion of the clock input signal at node Clk1xB is adjusted. For example, when the clock input signal at node Clk1x is selected, the high period of the clock input signal at node Clk1x can be extended by the time period t of the clock input signal at node Clk1x. H Adjustment. On the other hand, when the input signal Clk1xB is selected, the time during which the clock input signal at node Clk1x is low can be extended by extending the time period t of the clock input signal at node Clk1x. L adjust.

[0048] During operation, the output of the multiplexer MOUT is delayed by the adjustable delay circuit 104 to form a delayed signal DOUT. An OR gate 132 is used to perform an OR operation with the multiplexer output MOUT to form a duty cycle corrected signal at the output node OUT. As the delay of the adjustable delay circuit 104 increases, the high-period of the clock signal at the output node OUT increases. Conversely, as the delay of the adjustable delay circuit 104 decreases, the high-period of the clock signal at the output node OUT decreases. In various embodiments, the adjustable delay circuit 104 can be as described above regarding... Figure 3B-3G The described implementation.

[0049] In alternative embodiments, the duty cycle correction circuit 102 can be implemented differently. For example, Figure 3I A duty cycle correction circuit is shown, which can also be used to implement... Figure 3AThe duty cycle correction circuit 102 is shown. As shown, the duty cycle correction circuit 102 includes multiple inverters 120 coupled in parallel with each other. That is, the input of each inverter 120 is connected to the input node IN and the output of each inverter 120 is connected to the output node OUTB. As shown, each inverter 120 includes NMOS devices M1 and M2 and PMOS devices P2 and P1 coupled in series with each other. Both NMOS device M2 and PMOS device P2 have a gate connected to the input node IN and a load path coupled to the output node OUTB. The gate of NMOS device M1 of inverter 120 is coupled to the digital select signal DCPN[n:0], and the gate of PMOS device P1 is coupled to the digital select signal DCPb[n:0]. Therefore, during operation, one or more of the NMOS transistors M1 and PMOS transistor P1 are selectively activated to adjust the relative strength of the PMOS pull-up path and the NMOS pull-down path of inverter 120. For example, when it is necessary to delay the rising edge of the first clock signal Clk1x, fewer PMOS transistors P1 can be selected to slow down or delay the rising edge generated by the duty cycle correction circuit 102, while more NMOS devices M1 can be selected to keep the falling edge delay small. Similarly, when it is necessary to delay the falling edge of the first clock signal Clk1x, fewer NMOS transistors M1 can be selected to slow down or delay the falling edge generated by the duty cycle correction circuit 102, while more PMOS devices P1 can be selected to keep the rising edge delay small. Inverter 122 can be coupled to the output of inverter 120 to buffer the output of inverter 120. In various embodiments, the dimensions of transistors M1, M2, P1, and P2 may be the same or different in each inverter 120.

[0050] It should be understood that Figure 3A-3I The illustrated implementation example of the frequency multiplier circuit 12 is just a few examples among many possible implementations of the frequency multiplier circuit 12. In alternative embodiments, other circuits and methods may be used to achieve the same or similar functionality.

[0051] Figure 4A It shows that according to Figure 1AThe method 200 for calibrating the frequency multiplier circuit 12 in an embodiment. In step 202, the duty cycle parameter of the second clock signal Clk2x is measured using the duty cycle measurement and adjustment circuit 16. In various embodiments, the duty cycle parameter of the second clock signal Clk2x can be measured directly using a high-speed counter or other duty cycle measurement techniques known in the art. In step 204, the duty cycle of the first clock signal Clk1x and / or the duty cycle of the second clock signal Clk2x are adjusted until the determined duty cycle is 50% or within a predetermined tolerance of 50%, or the duty cycle of the first clock signal Clk1x is adjusted until the difference in adjacent clock cycles is within a predetermined tolerance. In some embodiments, the determined duty cycle parameter is compared with a threshold duty cycle parameter, and the process is performed iteratively. Figure 4A The method 200 shown continues until the measured duty cycle parameter meets a predetermined requirement.

[0052] Figure 4B It shows that according to Figure 1B The method 250 for calibrating the frequency multiplier circuit 12 in this embodiment. In step 252, a test tone is generated by a test tone generator 54 and routed to the input of a duty cycle-sensitive analog-to-digital converter 56. The frequency of the test tone generated by the test tone generator 54 can vary depending on the specific system and its specifications. In one embodiment, the frequency of the tone generated by the test tone generator 54 is 1 MHz; however, other frequencies may be used in other embodiments.

[0053] In step 254, the second clock signal Clk2x generated by the frequency multiplier 12 is provided as a clock signal to a duty cycle-sensitive analog-to-digital converter 56, which is sensitive to duty cycle changes in the first clock signal Clk1x or the second clock signal Clk2x. In step 256, the duty cycle-sensitive analog-to-digital converter 56 is operated in a manner that the test tone generated by the test tone generator 54 is digitized, and the digital output is sent to the duty cycle analysis and adjustment circuit 58. In step 258, a frequency transformation is performed on the digitized tone, transforming the digitized signal from the time domain to the frequency domain to form a frequency domain signal. In some embodiments, this frequency transformation is an FFT; however, in alternative embodiments of the invention, other frequency transformation algorithms may be used, such as, but not limited to, Discrete Fourier Transform, Discrete Cosine Transform (DCT), or other or other transformation types known in the art. In some embodiments, a windowing function may be applied to the digitized tone before performing the frequency transformation. In step 260, the SFDR of the frequency-transformed signal is determined. In some embodiments, the SFDR is determined by determining the amplitude difference between a frequency bin corresponding to the frequency of the test tone and a frequency bin corresponding to spurs caused by asymmetry in the duty cycle of the second clock signal Clk2x. As described above, in some embodiments, the spur frequency may be f spur =f s / 2-f in In other embodiments, the spurious frequency may vary depending on the specific implementation and its specifications. Alternatively, the SFDR can be calculated by determining the difference between the power of the signal in the frequency window corresponding to the test tone and the sum of the powers in the remaining frequency windows.

[0054] In step 262, the duty cycle of the first clock signal Clk1x and / or the duty cycle of the second clock signal Clk2x are adjusted until the determined SFDR is minimized or falls within a predetermined range. In some embodiments, the determined SFDR is compared with a threshold, and the process is performed iteratively. Figure 4A The method 250 shown continues until the SFDR meets predetermined requirements.

[0055] It should be understood that in methods 200 and 250 described above, the duty cycle of the first clock signal Clk1x, the duty cycle of the second clock signal Clk2x, or both the duty cycles of the first and second clock signals can be adjusted. In some embodiments, the adjustment of the duty cycle of the first clock signal Clk1x and the duty cycle of the second clock signal Clk2x is performed sequentially. For example, in one embodiment, methods 200 and / or 250 are performed to first correct the duty cycle of the first clock signal Clk1x, and then correct the duty cycle of the second clock signal Clk2x. In other embodiments, methods 200 and / or 250 can be performed to first correct the duty cycle of the second clock signal Clk2x, and then correct the duty cycle of the first clock signal Clk1x.

[0056] Figure 5A System 300 is shown, which includes an integrated circuit 302 coupled to a test fixture 308. System 300 is similar to Figure 1A The system 10 shown in the figure includes a frequency multiplier circuit 12 calibrated by directly measuring a double clock signal. As shown, integrated circuit 302 includes frequency multiplier circuit 12, duty cycle-sensitive analog-to-digital converter 56, system circuitry 52, test multiplexer 304, and control logic interface circuitry 313. In various embodiments, system circuitry 52 represents any type of system circuitry that generates a signal for measurement by the duty cycle-sensitive analog-to-digital converter 56. For example, system circuitry 52 may include RF circuitry, sensor circuitry, audio circuitry, or any other circuitry that can be integrated onto an integrated circuit. In alternative embodiments of the invention, the various components disposed on integrated circuit 302 can be divided in different ways. For example, one or more components of integrated circuit 302 may be disposed on multiple integrated circuits or may be implemented on a circuit board. System 300 also includes an oscillator 306 that generates a first clock signal Clk1x. In various embodiments, oscillator 306 may be a crystal oscillator or other type of oscillator capable of generating a clock signal. In some embodiments, system 300 may be configured such that oscillator 306 is a crystal and active circuitry (not shown) used to drive the crystal resides on integrated circuit 302.

[0057] The control logic and interface circuitry 313 includes logic that controls the state of some or all of the various components on the integrated circuit 302, and includes a digital interface circuitry configured to communicate with external components via a digital bus DBUS. In various embodiments, the digital interface of the control logic and interface circuitry 313 may be a serial bus interface circuit, a parallel bus interface circuit, and / or circuitry that conforms to any bus standard (including but not limited to SPI, CAN, I2C, LVDS, and USB). Therefore, the number n of signal pins on the digital bus DBUS can be any number suitable for the implemented bus protocol.

[0058] When the frequency multiplier circuit 12 is calibrated, the test fixture 308 can be coupled to the integrated circuit 302. For example, the test fixture 308 can be coupled to the integrated circuit 302 during wafer testing, package testing, manufacturing testing, or during routine maintenance or calibration operations. For example, the test fixture 308 can be implemented using a wafer test fixture, a package test fixture, or any other system configured to be coupled to the integrated system 302 for testing purposes. In some embodiments, the functionality of the test fixture 308 can reside in the same system as the integrated circuit 302. As shown, the test fixture 308 includes a clock measurement circuit 310, a processor 312, and a memory 314. The clock measurement circuit 310 is configured to be coupled to the integrated circuit 302 via the test interface signal line TEST. As shown, the test interface signal line TEST is coupled to the output of the multiplexer 304 on the integrated circuit 302. During operation, control logic and interface circuitry 313 select various signals to be output to the test interface signal line TEST. Among these selectable signals, the second clock signal Clk2x is a frequency-multiplied clock signal. It should be understood that multiplexer 304 can be selected from any number of selectable signals within integrated circuit 302. However, in some embodiments, multiplexer 304 can be omitted, and the second clock signal Clk2x can be directly routed to the test interface signal line TEST.

[0059] During test calibration, clock measurement circuit 310 monitors the second clock signal Clk2x and performs a duty cycle parameter measurement. In some embodiments, this duty cycle parameter measurement is transmitted to processor 312. Based on this duty cycle parameter measurement, processor 312 adjusts the duty cycle of frequency multiplier circuit 12 by issuing a command to control logic interface circuit 313 via digital bus DBUS. In some embodiments, the monitoring of the duty cycle measured by clock measurement circuit 310 and the adjustment of the duty cycle of frequency multiplier circuit 12 are functionally accomplished by executing a program residing in memory 314. In some embodiments, memory 314 may be used to store multiple duty cycles measured by clock measurement circuit 310, and multiple corresponding duty cycle adjustment settings. Therefore, during operation, processor 312 can select a duty cycle adjustment setting that satisfies predetermined duty cycle parameter requirements.

[0060] In some embodiments, processor 312 may be implemented using a microcontroller or other processing circuitry known in the art. In alternative embodiments of the invention, dedicated logic (such as a state machine) may be used to implement the duty cycle monitoring and duty cycle adjustment functions described above. In some embodiments, processor 312 may also include digital signal processing circuitry means for assisting in determining the duty cycle monitored by clock measurement circuitry 310. For example, in some embodiments, clock measurement circuitry 310 includes an analog-to-digital converter that provides a digital data stream to processor 312. In this embodiment, processor 312 receives the data stream generated by clock measurement circuitry 310 and uses one or more digital signal processing algorithms to determine the duty cycle parameter of the second clock signal Clk2x.

[0061] For example, an embodiment of the digital signal processing algorithm may include performing a frequency transformation (such as FFT) on a second clock signal Clk2x and measuring the spurious behavior of the second clock signal Clk2x. In one embodiment, the duty cycle parameter corresponding to the duty cycle of the second clock signal Clk2x is the second harmonic of the clock signal Clk2x. Therefore, depending on the duty cycle of the second clock signal Clk2x, the difference in amplitude between the frequency window at the frequency of the second clock signal Clk2x and the frequency window at the second harmonic of the second clock signal Clk2x changes. The closer the duty cycle of the second clock signal Clk2x is to 50%, the greater the amplitude difference between these frequency windows.

[0062] In some embodiments, the duty cycle parameter corresponding to the duty cycle of the first clock signal is the amplitude of spurious signals at half the clock frequency of the second clock signal Clk2x. It is assumed that the clock period of the second clock signal Clk2x changes once every clock cycle. Therefore, the difference in amplitude between the frequency window at the frequency of the second clock signal Clk2x and the frequency window at half the frequency of the second clock signal Clk2x changes depending on the duty cycle of the first clock signal Clk1x. The closer the duty cycle of the first clock signal Clk1x is to 50%, the greater the difference in amplitude between these frequency windows. In alternative embodiments, other digital signal processing algorithms known in the art can be used to determine the duty cycle parameter.

[0063] Figure 5B A circuit that can be used to implement clock measurement circuit 310 is shown. In one embodiment, clock measurement circuit 310 includes counter 322 that monitors the time when the second clock signal Clk2x is high and / or low. For example, this time measurement can be achieved by incrementing counter 322 when the second clock signal Clk2x is high and / or low. The result of this counting can be sent to processor 312, which can be configured to determine the duty cycle of the second clock signal Clk2x based on a comparison of the number of counts when the second clock signal Clk2x is high (high count) and the number of counts when the second clock signal Clk2x is low (low count). When these counts are equal, the measured duty cycle is considered to be 50%. The degree to which these counts are unequal relates to the deviation from the ideal 50% duty cycle. In some embodiments, the difference between high counts and low counts can be used as a duty cycle metric for the purpose of adjusting the duty cycle of frequency multiplier circuit 12.

[0064] In alternative embodiments, different metrics may be used. For example, in another embodiment, counter 322 may increment when the second clock signal Clk2x is in a first state (e.g., high or low), and counter 322 may not increment or decrement when the second clock signal Clk2x is in a second state (e.g., low or high). The resulting count after a predetermined time period can be used as a parameter representing the duty cycle of the second clock signal Clk2x.

[0065] The duty cycle parameter associated with the first clock signal Clk1x can be determined by measuring the length of consecutive clock cycles of the second clock signal Clk2x using counter 322. Therefore, as the lengths of two consecutive clock cycles approach each other, the duty cycle of the first clock signal Clk1x approaches 50%.

[0066] Figure 5CThis represents another way in which the clock measurement circuit 310 can be implemented. In one embodiment, the clock measurement circuit 310 can be implemented using an analog-to-digital converter 324. In this embodiment, the analog-to-digital converter 324 digitizes the second clock signal Clk2x and sends the converted digital value to the processor 312. The processor 312 can then perform frequency conversion of the converted digital value, determine the spurious-free dynamic range, and adjust the duty cycle of the frequency multiplier circuit 12 according to the determined spurious-free dynamic range.

[0067] Figure 5D Further circuitry that can be used to implement the clock measurement circuit 310 is shown. As illustrated, the clock measurement circuit 310 can be implemented using an analog-to-digital converter 324 and a mixer 326. For example, the mixer 326 can be used to down-convert the clock signal to a lower frequency, allowing a lower sampling rate to be used for the analog-to-digital converter 324. In some embodiments, the frequency of the local oscillator signal LO used to drive the mixer 326 can be set to down-convert spurious signals significantly affected by the duty cycle of the second clock signal Clk2x. Similar to... Figure 5C In some embodiments, processor 312 analyzes the digitized output of analog-to-digital converter 324 to perform frequency transformation (such as FFT) and compares the relative amplitudes of the down-converted clock signal and the down-converted spurious response. These differences in relative amplitude can be used as a basis for adjusting the duty cycle of frequency multiplier circuit 12. In various embodiments, analog-to-digital converter 324 can be implemented using any type of analog-to-digital converter architecture suitable for a particular application and a particular monitoring clock frequency. In some embodiments, analog-to-digital converter 324 can be implemented using a Sigma Delta analog-to-digital converter, a pipelined analog-to-digital converter, a flash analog-to-digital converter, or other types of analog-to-digital converters. Mixer 326 can be implemented using mixer circuitry known in the art. It should be understood that... Figures 5B-5D The examples provided are merely three examples of many types of circuits that can be used to measure the duty cycle of the second clock signal Clk2x. In alternative embodiments of the invention, other circuits known in the art may be used.

[0068] Figure 5E Calibration is shown Figure 5AMethod 350 for setting the duty cycle of the frequency multiplier circuit 12 in the system 300 shown. In step 352, the frequency multiplier circuit 12 is initialized. For example, this initialization may include configuring various delay settings (also referred to as duty cycle settings) within the frequency multiplier circuit 12 to predetermined values. In some embodiments, initializing the frequency multiplier circuit 12 may include writing these predetermined values ​​to local registers or memories residing on the system or integrated circuit 302 where the frequency multiplier circuit 12 resides. In one example, the processor 312 may send a configuration command to the control logic and interface circuitry device 313 via a digital bus DBUS. For example, the configuration command may be a single command within a control word or a register write command addressed to a specific register and / or a register dedicated to the delay settings of the frequency multiplier circuit 12.

[0069] In step 354, the second clock signal Clk2x is configured to be routed to the clock measurement circuit 310 on the test fixture 308. In an embodiment, the second clock signal Clk2x is routed to the clock measurement circuit 310 by configuring the multiplexer 304 to route the second clock signal Clk2x to the external test pin TEST. Next, the clock measurement circuit 310 is initialized in step 356. In some embodiments, such as Figure 5C and Figure 5D In one embodiment, the analog-to-digital converter 324 residing within the clock measurement circuit 310 is initialized. For example, this initialization may include activating the analog-to-digital converter 324 and / or routing the input coupled to the signal TEST to the input of the analog-to-digital converter 324.

[0070] In step 358, the frequency multiplier circuit 12 can be configured according to a first frequency multiplier configuration. For example, the first frequency multiplier configuration may include a first predetermined set of delay settings for the frequency multiplier circuit 12. In some embodiments, step 358 is performed in conjunction with step 352 as described above. In step 360, a second clock signal Clk2x is captured by clock measurement circuit 310. In some embodiments, this is achieved by using, as... Figure 5C and Figure 5DThe analog-to-digital converter 324 shown digitizes the second clock signal Clk2x to perform the capture of the second clock signal Clk2x. In embodiments utilizing frequency transformation (such as FFT), the capture of the second clock signal Clk2x can be achieved by digitizing a predetermined number of samples. In some embodiments, this predetermined number of samples can be a power of two. For example, 512, 1024, 2048, or 4096 samples can be digitized by the analog-to-digital converter 324. In alternative embodiments of the invention, other powers of two or even not powers of two samples can be captured depending on the specific system and its specifications. In some embodiments, a window function can be applied to the digitization sampling. Such a window function can include, but is not limited to, rectangular windows, triangular windows, cosine sum windows, Hann windows, Hamming windows, Blackman windows, and other windows known in the art. In some embodiments, the application of such a window can reduce spectral leakage and improve the accuracy of spectral measurements.

[0071] In step 364, the quality metric is calculated and stored. This can be done as follows: Figure 4A This quality metric is calculated as described in the embodiments. For example, the duty cycle and / or clock period variation of the second clock signal Clk2x can be measured directly from the digitized output. Alternatively, the spurious-free dynamic range of the digitized output of the frequency conversion can be determined by determining the difference between the pitch corresponding to the frequency of the second clock signal Clk2x and the spurious signals corresponding to the distortion caused by the duty cycle error within the second clock signal Clk2x. In some embodiments, the SFDR is determined by determining the difference between the power of the pitch in the frequency window corresponding to the second clock signal Clk2x and the sum of the powers of one or more other frequency windows. Alternatively, other performance metrics can be used. In some embodiments, the calculated quality metric is stored in memory or a register. In some embodiments, the calculated quality metric is stored in memory 314 within the test fixture 308. Alternatively, the calculated quality metric can be stored in memory or a register disposed on the integrated circuit 302.

[0072] In step 366, it is determined whether all configurations of the frequency multiplier circuit 12 have been evaluated. In some embodiments, all possible configurations of the frequency multiplier circuit 12 are evaluated. In alternative embodiments, a subset of all configurations of the frequency multiplier circuit 12 are evaluated. In other embodiments, a search algorithm (such as a binary search or a linear search) is performed until the calculated quality metric meets predetermined criteria (such as a predetermined duty cycle or a predetermined spurious-free dynamic range). If the criteria of step 366 are not met, further configurations of the frequency multiplier 12 are provided (step 362). Once all configurations have been provided, the method continues to step 368.

[0073] In step 368, a search for the optimal quality metric is performed. In some embodiments, each calculated quality metric is compared with each other, and a multiplier configuration corresponding to the optimal quality metric is selected to configure the multiplier circuit 12 during normal operation. In other embodiments, the search is performed until the calculated quality metric is within a predetermined range. In some embodiments, step 368 is performed iteratively along with capturing the clock output in step 360 and calculating and storing the quality metric in step 364. Then, in step 370, the multiplier configuration with the optimal quality metric is applied to the multiplier circuit 12. In some embodiments, this multiplier configuration is written into a register or memory coupled to the multiplier circuit 12.

[0074] Figure 6A A system 400 is shown, including an integrated circuit 402 coupled to a test fixture 408. System 400 is similar to... Figure 1B The system 10 shown calibrates the frequency multiplier circuit 12 by monitoring the duty cycle-sensitive analog-to-digital converter 56 and determining a quality metric (such as spurious-free dynamic range) depending on the duty cycle of a first clock signal Clk1x and / or a second clock signal Clk2x. As shown, the integrated circuit 402 includes the frequency multiplier circuit 12, the duty cycle-sensitive analog-to-digital converter 56, system circuitry 52, a test multiplexer 404, control logic and interface circuitry 413, a test tone generator 54, and a first-in-first-out (FIFO) memory 418. During calibration, the control logic and interface circuitry 413 activates the test tone generator 54, the output of which is routed to the input of the duty cycle-sensitive analog-to-digital converter 56 via the test multiplexer 404. (See above regarding...) Figure 4B As described, the output ADCOUT of the analog-to-digital converter 56 is buffered by FIFO 418, and the output of FIFO 418 is transmitted to controller 312 via digital bus DBUS. Controller 312 determines the quality metric, for example, by performing a frequency transformation (such as FFT), and determines the SFDR based on the output of the frequency transformation.

[0075] Based on a determined quality metric, processor 312 adjusts the duty cycle of frequency multiplier circuit 12 by issuing a command to control logic interface circuit 413 via digital bus DBUS. In some embodiments, the calculation of the quality metric and the adjustment of the duty cycle of frequency multiplier circuit 12 are functionally accomplished by executing a program residing in memory 314. In some embodiments, memory 314 may be used to store multiple quality metrics determined by processor 312 and multiple corresponding duty cycle adjustment settings. Therefore, during operation, processor 312 can select a duty cycle adjustment setting that satisfies the predetermined quality metric.

[0076] In alternative embodiments of the invention, the various components disposed on integrated circuit 402 can be divided in different ways. For example, one or more components of integrated circuit 402 may be disposed on multiple integrated circuits or may be implemented on a circuit board. System 400 also includes an oscillator 306 that generates a first clock signal Clk1x. In various embodiments, oscillator 306 may be a crystal oscillator or other type of oscillator capable of generating a clock signal. In some embodiments, system 400 may be configured such that oscillator 306 is a crystal and active circuitry (not shown) for driving the crystal resides on integrated circuit 402.

[0077] The control logic and interface circuitry 413 includes logic that controls the state of some or all of the various components on the integrated circuit 402, and includes a digital interface circuitry configured to communicate with external components via a digital bus DBUS. In various embodiments, the digital interface of the control logic and interface circuitry 413 may be a serial bus interface circuit, a parallel bus interface circuit, and / or circuitry that conforms to any bus standard (including but not limited to SPI, CAN, I2C, LVDS, and USB). Therefore, the number n of the signal pins of the digital bus DBUS can be any number suitable for the implemented bus protocol.

[0078] During the calibration of the frequency multiplier circuit 12, the test fixture 408 may be coupled to the integrated circuit 402. For example, the test fixture 408 may be coupled to the integrated circuit 402 during wafer testing, package testing, manufacturing testing, or during routine maintenance or calibration operations. The fixture 408 may be implemented using a wafer test fixture, a package test fixture, or any other system configured to couple to the integrated circuit 402 for testing purposes. In some embodiments, the functionality of the test fixture 408 may reside in the same system as the integrated circuit 402.

[0079] Figure 6BA circuit that can be used to implement a test tone generator 54 according to an embodiment is shown. As shown, the test tone generator 54 includes a frequency divider 422, which can be implemented using frequency divider circuits known in the art. During operation, the frequency divider 422 divides the second clock signal Clk2x to a lower frequency. In one embodiment, as described above... Figure 4B The frequency generated by frequency divider 422, as described in the embodiments, is approximately 1 MHz. Alternatively, other frequencies may be generated, depending on the specific system and its specifications. In some embodiments, the division ratio of frequency divider 422 can be programmed based on the division frequency DIV provided as input to frequency divider 422. In some embodiments, the operation of frequency divider 422 can be enabled via signal pin EN through control logic interface 413. In some embodiments, division frequency 422 is configured to divide the second clock signal Clk2x by at least two times using only the rising edge of the second clock signal Clk2x or only the falling edge of the second clock signal Clk2x. In this embodiment, a 50% duty cycle for the generated test tone can be ensured even when the duty cycle of the second clock signal Clk2x is not 50%.

[0080] In some embodiments, a ripple counter or synchronization counter with one or more registers is used to implement the frequency divider 422. In other embodiments, various prescaler circuits and systems known in the art can be used to implement the frequency divider 422.

[0081] In some embodiments, the output of the frequency divider 422 is low-pass filtered to attenuate or remove harmonics, such as Figure 6CAs shown, a low-pass filter 424 coupled to the output of frequency divider 422 is illustrated. The low-pass filter 424 can be implemented using analog low-pass filter circuitry known in the art. For example, in some embodiments, the low-pass filter 424 can be implemented using a simple single-pole RC filter employing a series resistor and a parallel capacitor. Higher-order passive filters, such as passive LC and / or RLC filters, can also be used. In other embodiments, more complex filter topologies can be used. For example, an active filter can be used, having one or more implementations of one or more poles. For example, such an active filter can be implemented using operational amplifier-based filter structures, transconductance amplifier-based filter structures (such as gmC filters), or other active filter structures known in the art. In some embodiments, the low-pass filter 424 is coupled between the output of test multiplexer 404 and the input of duty cycle-sensitive analog-to-digital converter 56. In this embodiment, the low-pass filter 424 also functions as an anti-aliasing filter for the duty cycle-sensitive analog-to-digital converter 56. The bandwidth of the low-pass filter 424 can be set to a frequency suitable for the specific system being implemented. For example, in some embodiments, the cutoff frequency of the low-pass filter 424 may be less than half the sampling frequency of the duty cycle-sensitive analog-to-digital converter 56.

[0082] Figure 6D Calibration is shown Figure 6A The method 450 for setting the duty cycle of the frequency multiplier circuit 12 in the system 400 shown. In step 452, the frequency multiplier circuit 12 is initialized. For example, this initialization may require configuring various delay settings (also referred to as duty cycle settings) within the frequency multiplier circuit 12 to predetermined values. In some embodiments, initializing the frequency multiplier circuit 12 may include writing these predetermined values ​​to local registers or memories residing on the system or integrated circuit 402 where the frequency multiplier circuit 12 resides. In one example, the processor 312 may send a configuration command to the control logic and interface circuitry device 413 via a digital bus DBUS. For example, the configuration command may be a single command within a control word or a register write command addressed to a specific register and / or a register dedicated to the delay settings of the frequency multiplier circuit 12.

[0083] In step 454, the test tone generator 54 is initialized and activated to generate a test tone. Next, in step 456, the duty cycle-sensitive analog-to-digital converter (ADC) is initialized to convert the output of the test tone generator 54 into a digital signal based on the second clock signal Clk2x. This initialization can be performed by configuring the test multiplexer 404 to route the output of the test tone generator 54 to the input of the duty cycle-sensitive ADC 56. In step 458, the frequency multiplier circuit 12 can be configured according to a first frequency multiplier configuration. For example, the first frequency multiplier configuration may include a first predetermined set of delay settings for the frequency multiplier circuit 12. In some embodiments, step 458 is performed in conjunction with step 452 as described above.

[0084] In step 460, a duty cycle-sensitive analog-to-digital converter 56 digitizes the test tone, and the output of the test tone is sent to FIFO 418. Next, in step 462, the digitized test tone data stored in FIFO 418 is read by processor 312 in test fixture 408. In some embodiments, one or more samples of the digitized test tone data may be stored in memory 314 on test fixture 408. In some embodiments, a predetermined number of samples may be transferred to processor 312 for each quality metric measurement. In embodiments where processor 312 performs an FFT on the digitized data, the predetermined number of samples may be a power of two. For example, 512, 1024, 2048, or 4096 samples may be digitized by duty cycle-sensitive analog-to-digital converter 56. In alternative embodiments of the invention, other powers of two or even not powers of two samples may be captured depending on the specific system and its specifications. In some embodiments, a window function may be applied to the digitized samples. Such window functions may include, but are not limited to, rectangular windows, triangular windows, cosine sum windows, Hann windows, Hamming windows, Blackman windows, and other windows known in the art. In some embodiments, the application of such windows can reduce spectral leakage and improve the accuracy of spectral measurements.

[0085] In step 464, the quality metric is calculated and stored. This can be done as follows: Figure 4B This quality metric is calculated as described in the embodiments. For example, an FFT can be applied to the digitized tone, and the SFDR can be determined by determining the difference between the power of the tone in a frequency window corresponding to the frequency of the digitized tone and the sum of the powers of one or more other frequency windows. Alternatively, other performance metrics can be used. In some embodiments, the calculated quality metric is stored in memory 314 within the test fixture 308. Alternatively, the calculated quality metric can be stored in memory or registers disposed on the integrated circuit 302.

[0086] In step 466, it is determined whether all configurations of the frequency multiplier circuit 12 have been evaluated. In some embodiments, all possible configurations of the frequency multiplier circuit 12 are evaluated. In alternative embodiments, a subset of all configurations of the frequency multiplier circuit 12 are evaluated. In other embodiments, a search algorithm (such as a binary search or a linear search) is performed until the calculated quality measurement meets predetermined criteria (such as a predetermined duty cycle or a predetermined spurious-free dynamic range). If the criteria of step 466 are not met, further configurations of the frequency multiplier circuit 12 are provided (step 462). Once all configurations have been provided, the method continues to step 468.

[0087] In step 468, a search for the optimal quality metric is performed. In some embodiments, each calculated quality metric is compared with each other, and a multiplier configuration corresponding to the optimal quality metric is selected to configure the multiplier circuit 12 during normal operation. In other embodiments, the search is performed until the calculated quality metric is within a predetermined range. In some embodiments, step 468 is performed iteratively along with the digitization of the test tone in step 460 and the calculation and storage of the quality metric in step 464. The multiplier configuration with the optimal quality metric is then applied to the multiplier circuit 12. In some embodiments, in step 470, the multiplier configuration is written into a register or memory coupled to the multiplier circuit 12.

[0088] Figure 7A An RF system 500 according to an embodiment of the present invention is illustrated. The RF system 500 includes components relative to... Figure 5A The integrated circuit 302 shown and described in the figure includes additional RF circuitry outside the frequency multiplier duty cycle adjustment circuitry. As shown, the RF system 500 includes an RF integrated circuit 502 coupled to an antenna 516 and an oscillator 306. The RF integrated circuit 502 may include components configured to be coupled to elements not in... Figure 7A The diagram shows one or more additional interface pins for other parts of the RF system 500. In various embodiments, the RF integrated circuit 502 can be used in a variety of RF applications, including but not limited to cellular communication systems such as cellular phone radar systems, automotive radar systems, and other RF systems. The RF integrated circuit 502 includes a frequency multiplier circuit 12, a test multiplexer 304, a duty cycle-sensitive analog-to-digital converter 56, and control logic and interface circuitry 313. These blocks are configured according to the description above. Figures 5A-5E Implementation examples and Figure 1A The operation is carried out according to the operating principle of the above embodiments. Figure 5AAs described in the embodiments, the outputs of the test multiplexer 304 and the digital bus DBUS can be coupled to an external test fixture. In some embodiments, the functionality of the test fixture 308 can be integrated within the RF integrated circuit 502.

[0089] In addition to the boxes described above, RF integrated circuit 502 includes RF components such as RF front-end 508, downconverter 510, VCO 512, and phase-locked loop circuit arrangement 514. RF front-end 508 has an input port configured to be coupled to antenna 516, and includes RF circuitry configured to amplify the RF signal received from antenna 516. Downconverter 510 is configured to downconvert the amplified RF signal to a lower frequency, such as intermediate frequency (IF) or baseband frequency. In some embodiments, downconverter 510 downconverts the amplified RF signal to zero IF (zero IF). The output of downconverter 510 is coupled to the input of an optional anti-aliasing filter 506 configured to attenuate frequency components higher than half the sampling frequency of the duty cycle-sensitive analog-to-digital converter 56. In some embodiments, RF integrated circuit 502 also includes a transmit path (not shown) configured to provide the transmitted RF signal to antenna 516 and / or another antenna (not shown). The RF front end 508 and the downconverter 510 can be implemented using RF circuitry known in the art.

[0090] The RF integrated circuit 502 also includes a frequency generation block, such as a voltage-controlled oscillator (VCO) 512 and a phase-locked loop (PLL) circuit arrangement 514. According to embodiments of the invention, the PLL circuit arrangement 514 receives a second clock signal Clk2x and tunes the VCO 512 to a frequency that is a multiple of the frequency of the second clock signal Clk2x using PLL circuits and systems known in the art. For example, the PLL circuit arrangement 514 may include a phase detector, a charge pump, and one or more frequency dividers and / or prescalers. The VCO 512 can be implemented using VCO circuits known in the art. In one example, the VCO 512 is implemented using a single-ended or differential Colpitts or negative resistance oscillator or other oscillator types. In some embodiments, all or part of the VCO 512 and the PLL circuit arrangement 514 can be implemented externally to the RF integrated circuit 502.

[0091] The RF integrated circuit 502 also includes an optional processor 504 configured to perform baseband signal processing on the output ADCOUT of the duty cycle-sensitive analog-to-digital converter 56. In alternative embodiments, baseband signal processing may be performed by an external processor instead of or in addition to processor 504. In some embodiments, alternative to or in addition to baseband filter 506, optional processor 504 may also perform baseband filtering. Processor 504 may also provide data to an external data bus (not shown) and / or control logic interface circuitry 313.

[0092] Figure 7B An RF system 550 according to a further embodiment of the present invention is shown. The RF system 500 includes, in addition to the frequency multiplier duty cycle adjustment circuitry shown and described with respect to the above embodiments, [further details regarding the RF system 550]. Figure 7A The additional RF circuitry is described above. During calibration, the output of the test tone generator 54 is routed via the test multiplexer 404 to the input of the duty cycle-sensitive analog-to-digital converter 56. In some embodiments, a baseband filter 506 is coupled between the test multiplexer 404 and the duty cycle-sensitive analog-to-digital converter 56 to perform baseband filtering and / or anti-aliasing filtering of the down-converted signal before it is converted by the analog-to-digital converter 56.

[0093] As shown in the figure, the RF integrated circuit 552 includes a frequency multiplier circuit 12, a test multiplexer 404, a duty cycle-sensitive analog-to-digital converter 56, control logic and interface circuitry 413, a test tone generator 54, and a FIFO 418. These blocks are configured according to the above description. Figures 6A-6D Implementation examples and Figure 1B The operation is carried out according to the operating principle of the embodiment. The outputs of FIFO418 and digital bus DBUS can be coupled to the above-mentioned... Figure 6A The external test fixture 408 is described in the embodiments. In some embodiments, the functionality of the test fixture 408 can be integrated within the RF integrated circuit 552. The RF front-end 508, downconverter 510, VCO 512, phase-locked loop circuit 514, and anti-aliasing filter 506 are as described above regarding... Figure 7A The operation is performed as described in the embodiments.

[0094] It should be understood that Figure 7A and Figure 7B The embodiments described are merely two of many possible system implementations of the embodiments of the present invention.

[0095] Now for reference Figure 8A block diagram of a processing system 800 is provided according to an embodiment of the present invention. The processing system 800 depicts a general platform as well as general components and functions that can be used to implement portions of the radar system of the embodiment and / or external computers or processing devices that interface with the radar system of the embodiment. For example, the processing system 800 can be used to implement... Figure 5A The processor 312 and / or control logic and interface circuitry 313 shown are... Figure 6A The control logic interface circuit 413 shown is... Figure 7A and 7B The processor 504 is shown. In some embodiments, the processing system 800 can be used to determine and evaluate the duty cycle metric of the embodiment, control the operation of the RF system of the embodiment, and control the calibration of the frequency multiplier 12.

[0096] For example, the processing system 800 may include a central processing unit (CPU) 802 and a memory 804 connected to a bus 808, and may be configured to perform the aforementioned processing. In some embodiments, the memory 804 may be used to implement... Figure 5A and 6A The memory 314 is shown in the diagram. Alternatively, the memory 314 may be separate from the memory 804. If desired or required, the processing system 800 may also include: a display adapter 810 to provide connectivity to a local display 812; and an input / output (I / O) adapter 814 to provide input / output interfaces for one or more input / output devices 816 (such as a mouse, keyboard, flash drive, etc.).

[0097] Processing system 800 may also include a network interface 818, which may be implemented using a network adapter configured to couple to a wired link (such as a network cable, USB interface, etc.) and / or a wireless / cellular link for communicating with network 820. Network interface 818 may also include suitable receivers and transmitters for wireless communication. It should be noted that processor system 800 may include other components. For example, if implemented externally, processing system 800 may include hardware components such as power supplies, cables, motherboards, removable storage media, housings, etc. Although not shown, these other components are considered part of processing system 800. In some embodiments, processing system 800 may be implemented on a single monolithic semiconductor integrated circuit and / or on the same monolithic semiconductor integrated circuit as other disclosed system components.

[0098] Exemplary embodiments of the invention are summarized herein. Other embodiments may also be understood from the entire specification and claims herein.

[0099] Embodiments of the invention are summarized herein. Other embodiments may also be understood from the entire specification and claims herein.

[0100] Example 1. A method comprising: receiving a first clock signal having a first clock frequency via an adjustable frequency multiplier circuit; generating a second clock signal having a second clock frequency, the second clock frequency being twice the first clock frequency, using the adjustable frequency multiplier circuit; measuring a duty cycle parameter of the second clock signal, wherein the duty cycle parameter depends on the duty cycle of the first clock signal or the duty cycle of the second clock signal; and adjusting the duty cycle of the first clock signal or the duty cycle of the second clock signal based on the measurement using an adjustable frequency multiplier circuit.

[0101] Example 2. According to the method of Example 1, wherein: adjusting the duty cycle includes adjusting the duty cycle of the first clock signal; and the method further repeats the steps of measurement and adjustment until the successive clock cycles of the second clock signal have substantially equal lengths.

[0102] Example 3. According to the method of Example 1 or 2, wherein: adjusting the duty cycle includes adjusting the duty cycle of the second clock signal; and the method further includes repeating the steps of measurement and adjustment until the duty cycle of the second clock signal is substantially 50%.

[0103] Example 4. According to the methods of Examples 1 to 3, adjusting the duty cycle of the first clock signal or the duty cycle of the second clock signal includes selecting one of a plurality of duty cycle settings of the adjustable frequency multiplier circuit.

[0104] Example 5. According to the method of Examples 1 to 4, wherein adjusting the duty cycle of the first clock signal includes selecting one of a plurality of duty cycle settings of the duty cycle correction circuit of the adjustable frequency multiplier circuit, the duty cycle correction circuit being coupled to the input of the frequency multiplier of the adjustable frequency multiplier circuit.

[0105] Example 6. According to the method of Examples 1 to 5, the adjustable frequency multiplier circuit includes an XOR gate and an adjustable delay circuit coupled to the input of the XOR gate; and adjusting the duty cycle of the second clock signal includes adjusting the delay of the adjustable delay circuit.

[0106] Example 7. The method according to Examples 1 to 6 further includes correcting the duty cycle of the first clock signal before generating the second clock signal.

[0107] Example 8. According to the method of Examples 1 to 7, wherein measuring the duty cycle parameter of the second clock signal includes: timing an analog-to-digital converter (ADC) using the second clock signal; receiving an analog test tone at the signal input of the ADC; digitizing the analog test tone by the ADC to form a first time-domain digital signal; transforming the first time-domain digital signal from the time domain to the frequency domain to form a first frequency-domain signal; and measuring the difference between a first frequency window of the first frequency-domain signal corresponding to the frequency of the analog test tone and at least one second frequency window of the first frequency-domain signal to form the measured duty cycle parameter; and adjusting the duty cycle of the second clock signal based on the measurement includes: generating a duty cycle adjustment signal based on the measured duty cycle parameter; and providing the duty cycle adjustment signal to an adjustable frequency multiplier circuit.

[0108] Example 9. Following the method of Example 8, transforming the first time-domain digital signal from the time domain to the frequency domain includes using FFT.

[0109] Example 10. According to the method of Example 8 or 9, at least one second frequency window corresponds to fs / 2-f1, where fs is the sampling rate of the ADC and f1 is the frequency of the analog test tone.

[0110] Example 11. The method according to one of Examples 1 to 10 further includes: receiving an RF signal; downconverting the received RF signal to form a downconverted signal; and digitizing the downconverted signal.

[0111] Example 12. A method according to one of Examples 1 to 11, wherein measuring the duty cycle parameter of the second clock signal includes digitizing the second clock signal using an analog-to-digital converter to form a digitized second clock signal, and estimating the duty cycle parameter based on the digitized second clock signal.

[0112] Example 13. The method of claim 12, wherein the duty cycle parameter estimation comprises: transforming a digitized second clock signal from the time domain to the frequency domain to form a frequency domain second clock signal; and measuring the difference between a first frequency window of the frequency domain second clock signal corresponding to the frequency of the second clock signal and at least one second frequency window of the frequency domain second clock signal to form a measured duty cycle parameter.

[0113] Example 14. A system comprising: an adjustable frequency multiplier circuit including a clock input, a clock output, and a duty cycle adjustment input, the adjustable frequency multiplier circuit being configured to: receive a first clock signal having a first clock frequency at the clock input; generate a second clock signal having a second clock frequency at the clock output, the second clock frequency being twice the first clock frequency; and adjust the duty cycle of the first clock signal or the duty cycle of the second clock signal based on a duty cycle adjustment signal received at the duty cycle adjustment input; and a duty cycle measurement and adjustment circuit coupled to the clock output and the duty cycle adjustment input of the adjustable frequency multiplier circuit, the duty cycle measurement and adjustment circuit being configured to measure a duty cycle parameter of the second clock signal and generate a duty cycle adjustment signal based on the measured duty cycle parameter.

[0114] Example 15. According to the system of Example 14, the duty cycle measurement and adjustment circuit is configured to iteratively measure the duty cycle parameter of the second clock signal and modify the duty cycle adjustment signal until the duty cycle of the second clock signal is substantially 50% or the consecutive clock cycles of the second clock signal have substantially equal lengths.

[0115] Example 16. A system based on one of the examples in Example 14 or 15, where the duty cycle adjustment signal is a digital signal.

[0116] Example 17. A system according to one of Examples 14 to 16, wherein the adjustable frequency multiplier circuit includes: a delay circuit having a signal input coupled to a clock input; and an XOR gate having a first input coupled to the clock input, a second input coupled to the output of the delay circuit, and an output coupled to the clock output.

[0117] Example 18. The system according to Example 17, wherein the delay circuit is an adjustable delay circuit having a control input coupled to a duty cycle adjustment input.

[0118] Example 19. The system according to Example 18, wherein the adjustable delay circuitry includes multiple optional delay circuits.

[0119] Example 20. The system according to one of the examples in Examples 17 to 19 further includes a duty cycle correction circuit having an input coupled to a clock input and an output coupled to a first input of an XOR gate and a signal input of a delay circuit.

[0120] Example 21. A system according to one of Examples 14 to 20, wherein the duty cycle measurement and correction circuitry includes: an analog-to-digital converter (ADC) having a clock input having a clock output coupled to an adjustable frequency multiplier circuit, an ADC signal input configured to receive an analog test tone, and an ADC signal output configured to provide a first time-domain digital signal; and a duty cycle analysis and adjustment circuitry coupled to the ADC signal output, the duty cycle analysis and adjustment circuitry being configured to: transform the first time-domain digital signal from the time domain to the frequency domain to form a first frequency-domain signal, measure the difference between a first frequency window of the first frequency-domain signal corresponding to the frequency of the analog test tone and at least one second frequency window of the first frequency-domain signal to form a measured duty cycle parameter, and generate a duty cycle adjustment signal based on the measured duty cycle parameter.

[0121] Example 22. The system according to Example 21, wherein an adjustable frequency multiplier circuit and an ADC are disposed on a first monolithic integrated circuit and a duty cycle analysis and adjustment circuit is disposed on a test fixture coupled to the first monolithic integrated circuit.

[0122] Example 23. The system according to Example 21 or 22 also includes a radio frequency (RF) front end having an output selectively coupled to the ADC signal input.

[0123] Example 24. A system according to one of Examples 14 to 23, wherein the duty cycle measurement and adjustment circuitry includes: an analog-to-digital converter (ADC) having an ADC signal input having a clock output coupled to an adjustable frequency multiplier circuit and an ADC signal output configured to provide a digitized second clock signal; and a processor having the ADC signal output coupled to the ADC, the processor being configured to: transform the digitized second clock signal from the time domain to the frequency domain to form a frequency-domain second clock signal, measure the difference between a first frequency window of the frequency-domain second clock signal corresponding to the frequency of the second clock signal and at least one second frequency window of the frequency-domain second clock signal to form a measured duty cycle parameter, and generate a duty cycle adjustment signal based on the measured duty cycle parameter.

[0124] Example 25. The system according to Example 24, wherein an adjustable frequency multiplier circuit is disposed on a first monolithic integrated circuit, and a duty cycle measurement and adjustment circuit is disposed on a test fixture coupled to the first monolithic integrated circuit.

[0125] Example 26. An RF system includes: an RF front end having an input port configured to be coupled to an antenna; a test tone generation circuit; a multiplexer having a first input coupled to an output of the RF front end and a second input coupled to an output of the test tone generation circuit; an adjustable frequency multiplier circuit including a clock input, a clock output, and a duty cycle adjustment input, the adjustable frequency multiplier circuit being configured to: receive a first clock signal having a first clock frequency at the clock input; generate a second clock signal having a second clock frequency at the clock output, the second clock frequency being twice the first clock frequency; and adjust the duty cycle of the first clock signal or the duty cycle of the second clock signal based on a duty cycle adjustment signal received at the duty cycle adjustment input; and an analog-to-digital converter (ADC) having a clock input coupled to the clock output of the adjustable frequency multiplier circuit, an ADC signal input coupled to an output of the multiplexer, and an ADC signal output configured to provide a first time-domain digital signal.

[0126] Example 27. The RF system according to Example 26 further includes: a test fixture coupled to a test tone generation circuit, a multiplexer, an adjustable frequency multiplier circuit, and an ADC, wherein the test fixture is configured to, during calibration mode: activate the test tone generation circuit, configure the multiplexer to select the output of the test tone generation circuit, determine the duty cycle parameter of a second clock signal based on digital data received from the ADC signal output, and generate a duty cycle adjustment signal based on the determined duty cycle.

[0127] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations thereof will be apparent to those skilled in the art from the specification, exemplary embodiments, and other embodiments of the invention. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. A method comprising: A first clock signal with a first clock frequency is received through an adjustable frequency multiplier circuit; Using the adjustable frequency multiplier circuit, a second clock signal with a second clock frequency is generated, the second clock frequency being twice the first clock frequency; Measure the duty cycle parameter of the second clock signal, wherein the duty cycle parameter depends on the duty cycle of the first clock signal or the duty cycle of the second clock signal; as well as Using the adjustable frequency multiplier circuit, the duty cycle of the first clock signal or the duty cycle of the second clock signal is adjusted based on the measurement. in: Measuring the duty cycle parameter of the second clock signal includes: The second clock signal is used to time the analog-to-digital converter (ADC). The analog test tone is received at the signal input of the ADC. The analog test tone is digitized by the ADC to form a first time-domain digital signal. The first time-domain digital signal is transformed from the time domain to the frequency domain to form a first frequency-domain signal, and The difference between a first frequency window of the first frequency domain signal corresponding to the frequency of the simulated test pitch and at least one second frequency window of the first frequency domain signal is measured to form the measured duty cycle parameter; and Adjusting the duty cycle of the second clock signal based on the measurement includes: A duty cycle adjustment signal is generated based on the measured duty cycle parameters, and The duty cycle adjustment signal is provided to the adjustable frequency multiplier circuit.

2. The method according to claim 1, wherein: Adjusting the duty cycle includes adjusting the duty cycle of the first clock signal; and The method further includes repeating the measurement and adjustment steps until the successive clock cycles of the second clock signal have substantially equal lengths.

3. The method according to claim 1, wherein: Adjusting the duty cycle includes adjusting the duty cycle of the second clock signal; and The method further includes repeating the measurement and adjustment steps until the duty cycle of the second clock signal is substantially 50%.

4. The method of claim 1, wherein adjusting the duty cycle of the first clock signal or the duty cycle of the second clock signal includes selecting one of a plurality of duty cycle settings of the adjustable frequency multiplier circuit.

5. The method of claim 1, wherein adjusting the duty cycle of the first clock signal includes selecting one of a plurality of duty cycle settings of the duty cycle correction circuit of the adjustable frequency multiplier circuit, the duty cycle correction circuit being coupled to the input of the frequency multiplier of the adjustable frequency multiplier circuit.

6. The method according to claim 1, wherein: The adjustable frequency multiplier circuit includes an XOR gate and an adjustable delay circuit coupled to the input of the XOR gate; and Adjusting the duty cycle of the second clock signal includes adjusting the delay of the adjustable delay circuit.

7. The method of claim 1, further comprising correcting the duty cycle of the first clock signal before generating the second clock signal.

8. The method of claim 1, wherein transforming the first time-domain digital signal from the time domain to the frequency domain includes using FFT.

9. The method of claim 1, wherein at least one second frequency window corresponds to fs / 2- f1 ,in fs It is the sampling rate of the ADC and f1 It is the frequency of the simulated test tone.

10. The method according to claim 1, further comprising: Receive RF signals; The RF signal received by the downconversion is used to form a downconverted signal; as well as The down-converted signal is digitized.

11. The method of claim 1, wherein measuring the duty cycle parameter of the second clock signal comprises digitizing the second clock signal using an analog-to-digital converter to form a digitized second clock signal, and estimating the duty cycle parameter based on the digitized second clock signal.

12. The method of claim 11, wherein estimating the duty cycle parameter includes: The digitized second clock signal is transformed from the time domain to the frequency domain to form a frequency domain second clock signal; as well as The difference between a first frequency window of the frequency-domain second clock signal corresponding to the frequency of the second clock signal and at least one second frequency window of the frequency-domain second clock signal is measured to form the measured duty cycle parameter.

13. A system comprising: An adjustable frequency multiplier circuit includes a clock input, a clock output, and a duty cycle adjustment input, wherein the adjustable frequency multiplier circuit is configured to receive a first clock signal having a first clock frequency at the clock input; A second clock signal with a second clock frequency is generated at the clock output, the second clock frequency being twice the first clock frequency; Furthermore, the duty cycle of the first clock signal or the duty cycle of the second clock signal is adjusted based on the duty cycle adjustment signal received at the duty cycle adjustment input; as well as A duty cycle measurement and adjustment circuit, coupled to the clock output and the duty cycle adjustment input of the adjustable frequency multiplier circuit, is configured to measure the duty cycle parameter of the second clock signal and generate the duty cycle adjustment signal based on the measured duty cycle parameter. The duty cycle measurement and adjustment circuit mentioned above includes: An analog-to-digital converter (ADC), an ADC signal input, and an ADC signal output, the ADC having a clock input coupled to the clock output of the adjustable frequency multiplier circuit, the ADC signal input being configured to receive an analog test tone, and the ADC signal output being configured to provide a first time-domain digital signal; as well as A duty cycle analysis and measurement circuit, coupled to the ADC signal output, is configured as follows: The first time-domain digital signal is transformed from the time domain to the frequency domain to form a first frequency-domain signal. The difference between a first frequency window of the first frequency domain signal corresponding to the frequency of the simulated test tone and at least one second frequency window of the first frequency domain signal is measured to form the measured duty cycle parameter, and The duty cycle adjustment signal is generated based on the measured duty cycle parameters.

14. The system of claim 13, wherein the duty cycle measurement and adjustment circuit is configured to iteratively measure the duty cycle parameter of the second clock signal and modify the duty cycle adjustment signal until the duty cycle of the second clock signal is substantially 50% or until consecutive clock cycles of the second clock signal have substantially equal lengths.

15. The system of claim 13, wherein the duty cycle adjustment signal is a digital signal.

16. The system of claim 13, wherein the adjustable frequency multiplier circuit comprises: Delay circuit, having a signal input coupled to the clock input; as well as An XOR gate has a first input coupled to the clock input, a second input coupled to the output of the delay circuit, and an output coupled to the clock output.

17. The system of claim 16, wherein the delay circuit is an adjustable delay circuit having a control input coupled to the duty cycle adjustment input.

18. The system of claim 17, wherein the adjustable delay circuit comprises a plurality of selectable delay circuits.

19. The system of claim 16, further comprising a duty cycle correction circuit having an input coupled to the clock input and an output coupled to the first input of the XOR gate and the signal input of the delay circuit.

20. The system of claim 13, wherein the adjustable frequency multiplier circuit and the ADC are disposed on the first monolithic integrated circuit, and the duty cycle analysis and adjustment circuit is disposed on a test fixture coupled to the first monolithic integrated circuit.

21. The system of claim 13 further includes a radio frequency (RF) front end having an output selectively coupled to the ADC signal input.

22. The system of claim 13, wherein the duty cycle measurement and adjustment circuit comprises: An analog-to-digital converter (ADC) has an ADC signal input coupled to the clock output of the adjustable frequency multiplier circuit and an ADC signal output configured to provide a digitized second clock signal. as well as A processor, coupled to the ADC signal output of the ADC, is configured to: The digitized second clock signal is transformed from the time domain to the frequency domain to form a frequency domain second clock signal. The difference between a first frequency window of the frequency-domain second clock signal corresponding to the frequency of the second clock signal and at least one second frequency window of the frequency-domain second clock signal is measured to form the measured duty cycle parameter, and The duty cycle adjustment signal is generated based on the measured duty cycle parameters.

23. The system of claim 22, wherein the adjustable frequency multiplier circuit is disposed on the first monolithic integrated circuit, and the duty cycle measurement and adjustment circuit is disposed on a test fixture coupled to the first monolithic integrated circuit.

24. An RF system, comprising: RF front end, having an input port configured to be coupled to an antenna; Test the tone generation circuit; A multiplexer having a first input coupled to the output of the RF front end and a second input coupled to the output of the test tone generation circuit; An adjustable frequency multiplier circuit includes a clock input, a clock output, and a duty cycle adjustment input, wherein the adjustable frequency multiplier circuit is configured to receive a first clock signal having a first clock frequency at the clock input; A second clock signal with a second clock frequency is generated at the clock output, the second clock frequency being twice the first clock frequency; Furthermore, the duty cycle of the first clock signal or the duty cycle of the second clock signal is adjusted based on the duty cycle adjustment signal received at the duty cycle adjustment input; as well as An analog-to-digital converter (ADC) has a clock input coupled to the clock output of the adjustable frequency multiplier circuit, an ADC signal input coupled to the output of the multiplexer, and an ADC signal output configured to provide a first time-domain digital signal.

25. The RF system of claim 24, further comprising: A test fixture, coupled to the test tone generation circuit, the multiplexer, the adjustable frequency multiplier circuit, and the ADC, is configured to operate in calibration mode as follows: Activate the test tone generation circuit. Configure the multiplexer to select the output of the test tone generation circuit. The duty cycle parameter of the second clock signal is determined based on the digital data received from the ADC signal output, and The duty cycle adjustment signal is generated based on the determined duty cycle parameters.

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