A signal generating circuit, a signal generating method, and a chip

Abstract

The application discloses a signal generation circuit, a signal generation method and a chip, relates to the technical field of integrated circuits, and is used for generating a first reset signal and a second reset signal while starting a reference power supply subcircuit, so that the volume of a chip including the signal generation circuit is reduced, and the miniaturization of the chip is facilitated. The signal generation circuit comprises a reference current source subcircuit, a starting subcircuit and a power-on reset output subcircuit. The power-on reset output subcircuit comprises a charging unit and a first delay unit. The first delay unit is used for outputting the first reset signal when the signal generation circuit is powered on, and controlling the starting subcircuit to start the reference current source subcircuit according to the first reset signal. The reference current source subcircuit is used for controlling the starting subcircuit to charge the charging unit. The first delay unit is used for outputting the second reset signal when the charging unit is in a charging state. The chip comprises the signal generation circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a signal generation circuit, a signal generation method, and a chip. Background Technology

[0002] The startup circuit and the power-on reset circuit are two important analog circuit modules in a chip. The startup circuit provides a startup signal to the reference current source circuit included in the chip when the chip is powered on. The power-on reset circuit provides a power-on reset signal to the modules to be initialized within the chip, so that the modules to be initialized are restored to a known state when the chip is powered on.

[0003] However, the existing startup circuit and power-on reset circuit result in a larger chip size, which is not conducive to chip miniaturization. Summary of the Invention

[0004] The purpose of this invention is to provide a signal generation circuit, a signal generation method, and a chip for generating a first reset signal and a second reset signal while activating a reference power supply sub-circuit, thereby reducing the size of the chip including the signal generation circuit and facilitating chip miniaturization.

[0005] To achieve the above objectives, the present invention provides a signal generation circuit, which includes: a reference current source sub-circuit, a start-up sub-circuit, and a power-on reset output sub-circuit; the power-on reset output sub-circuit includes a charging unit and a first delay unit; the input terminals of the reference current source sub-circuit and the start-up sub-circuit are both coupled to a power supply terminal; the first output terminals of the reference current source sub-circuit and the first output terminals of the start-up sub-circuit are both grounded; the first terminal of the charging unit is coupled to the input terminal of the first delay unit, and the second terminal of the charging unit is grounded;

[0006] The first output terminal of the first delay unit is coupled to the first control terminal of the starter circuit; the second output terminal of the starter circuit is coupled to the control terminal of the reference current source circuit; the second output terminal of the reference current source circuit is coupled to the second control terminal of the starter circuit; and the third output terminal of the starter circuit is coupled to the second terminal of the charging unit.

[0007] The first delay unit is used to output a first reset signal when the signal generation circuit is powered on, and to control the starter circuit to start the reference current source circuit according to the first reset signal; the reference current source circuit is used to control the starter circuit to charge the charging unit, and the first delay unit is used to output a second reset signal when the charging unit is in the charging state.

[0008] Compared with the prior art, in the signal generation circuit provided by the present invention, the first delay unit can output a first reset signal when the signal generation circuit is powered on. Furthermore, the first delay unit can control the starter circuit to start the reference current source sub-circuit according to the first reset signal. In addition, after starting, the reference current source sub-circuit can control the starter circuit to charge the charging unit. The first delay unit outputs a second reset signal when the charging unit is in the charging state. Therefore, the signal generation circuit provided by the present invention can simultaneously achieve the start-up of the reference current source sub-circuit and the output of the first and second reset signals after power-on, eliminating the need for separate start-up circuits for starting the reference current source sub-circuit and power-on reset circuits for outputting the power-on reset signal in the chip. Therefore, when the signal generation circuit provided by the present invention is applied to a chip, the chip size can be reduced, facilitating chip miniaturization.

[0009] The present invention also provides a signal generation method, which applies the signal generation circuit provided by the above technical solution;

[0010] The signal generation method includes:

[0011] The first delay unit outputs a first reset signal when the signal generation circuit is powered on;

[0012] The first delay unit controls the starter sub-circuit to start the reference current source sub-circuit according to the first reset signal;

[0013] The reference current source circuit controls the starter circuit to charge the charging unit;

[0014] The first delay unit outputs a second reset signal when the charging unit is in the charging state.

[0015] Compared with the prior art, the beneficial effects of the signal generation method provided by the present invention are the same as those of the signal generation circuit provided by the above-mentioned technical solutions, and will not be repeated here.

[0016] The present invention also provides a chip, which includes the signal generation circuit provided by the above-described technical solution.

[0017] Compared with the prior art, the beneficial effects of the chip provided by the present invention are the same as those of the signal generation circuit provided by the above-mentioned technical solutions, and will not be repeated here. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0019] Figure 1This is a structural block diagram of the signal generation circuit provided in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of the signal generation circuit provided in an embodiment of the present invention;

[0021] Figure 3 This is a waveform diagram of the reference current output by the reference current source circuit in an embodiment of the present invention;

[0022] Figure 4 This is a graph showing the voltage versus time relationship between the power supply signal and the signal at the first output terminal of the first delay unit in an embodiment of the present invention.

[0023] Figure 5 A flowchart of a signal generation method provided in an embodiment of the present invention.

[0024] Figure label:

[0025] 1 is the reference current source sub-circuit, 11 is the reference current generation unit, M7 is the seventh transistor, M8 is the eighth transistor, R is a resistor, 12 is the current mirror unit, M9 is the ninth transistor, and M10 is the tenth transistor; 2 is the startup sub-circuit, 21 is the startup unit, M11 is the eleventh transistor, 22 is the refresh unit, M1 is the first transistor, M2 is the second transistor, M3 is the third transistor, M4 is the fourth transistor, 23 is the shutdown unit, and M12 is the twelfth transistor; 3 is the power-on reset output sub-circuit, 31 is the charging unit, C1 is the first capacitor, 32 is the first delay unit, I1 is the first inverter, I2 is the second inverter, 33 is the voltage holding unit, M5 is the fifth transistor, M6 is the sixth transistor, 34 is the second delay unit, C2 is the second capacitor, 35 is the voltage regulation unit, and C3 is the third capacitor. Detailed Implementation

[0026] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0027] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0028] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0030] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0031] The startup circuit and the power-on reset circuit are two important analog circuit modules in a chip. The startup circuit provides a startup signal to the reference current source circuit included in the chip when the chip is powered on. The power-on reset circuit provides a power-on reset signal to the modules to be initialized within the chip, so that the modules to be initialized are restored to a known state when the chip is powered on.

[0032] In order to have both of the above functions at the same time, existing chips need to be equipped with two circuits: a startup circuit and a power-on reset circuit. This makes the chip larger and is not conducive to chip miniaturization.

[0033] To address the aforementioned technical problems, embodiments of the present invention provide a signal generation circuit, a signal generation method, and a chip. The signal generation circuit provided by these embodiments can simultaneously activate the reference current source sub-circuit and output a first reset signal and a second reset signal upon power-on, eliminating the need for separate activation circuits for the reference current source sub-circuit and power-on reset circuits for outputting the power-on reset signal within the chip. Therefore, when the signal generation circuit provided by these embodiments is applied to a chip, it can reduce the chip's size, facilitating chip miniaturization.

[0034] like Figure 1 As shown, this embodiment of the invention provides a signal generation circuit. The signal generation circuit includes: a reference current source sub-circuit 1, a startup sub-circuit 2, and a power-on reset output sub-circuit 3. The power-on reset output sub-circuit 3 includes a charging unit 31 and a first delay unit 32. The input terminals of both the reference current source sub-circuit 1 and the startup sub-circuit 2 are coupled to the power supply terminal VCC. The first output terminals of both the reference current source sub-circuit 1 and the startup sub-circuit 2 are grounded to GND. The first terminal of the charging unit 31 is coupled to the input terminal of the first delay unit 32. The second terminal of the charging unit 31 is grounded to GND.

[0035] like Figure 1 As shown, the first output terminal of the first delay unit 32 is coupled to the first control terminal of the starter circuit 2. The second output terminal of the starter circuit 2 is coupled to the control terminal of the reference current source circuit 1. The second output terminal of the reference current source circuit 1 is coupled to the second control terminal of the starter circuit 2. The third output terminal of the starter circuit 2 is coupled to the first terminal of the charging unit 31.

[0036] like Figure 1 As shown, the first delay unit 32 is used to output a first reset signal when the signal generation circuit is powered on, and to control the starter circuit 2 to start the reference current source circuit 1 according to the first reset signal. The reference current source circuit 1 is used to control the starter circuit 2 to charge the charging unit 31. The first delay unit 32 is used to output a second reset signal when the charging unit 31 is in the charging state.

[0037] Specifically, the charging unit included in the aforementioned power-on reset sub-circuit can be any unit with charging and discharging functions, such as the first capacitor. For example, such as... Figure 2 As shown, when the charging unit 31 is the first capacitor C1, the first end and the second end of the charging unit 31 can be either of the terminals of the first capacitor C1.

[0038] In addition, such as Figure 4As shown, the voltage of the first reset signal output by the first delay unit can be low, and the voltage of the second reset signal can be high. In this case, the reset signal output by the signal generation circuit provided in this embodiment of the invention is active low. Alternatively, the voltage of the first reset signal output by the first delay unit can also be high, and the voltage of the second reset signal can be low. In this case, the reset signal output by the signal generation circuit provided in this embodiment of the invention is active high. It should be understood that the first reset signal and the second reset signal constitute a power-on reset signal. The first output terminal of the first delay unit is the POR (Power-On Reset) output terminal.

[0039] The following is combined with Figure 5 The process of signal generation using the signal generation circuit provided in the embodiments of the present invention will be described as follows:

[0040] Step 101: The first delay unit outputs a first reset signal when the signal generation circuit is powered on. It should be understood that when the signal generation circuit is powered on, the voltage at the first terminal of the charging unit will not change abruptly, and the first delay unit outputs the first reset signal according to the voltage at the first terminal of the charging unit.

[0041] Step 102: The first delay unit controls the starter circuit to start the reference current source sub-circuit according to the first reset signal. It should be understood that the first reset signal output by the first delay unit can be fed back to the first control terminal of the starter circuit through the first output terminal of the first delay unit. Furthermore, the second output terminal of the starter circuit is coupled to the control terminal of the reference current source sub-circuit, thereby enabling the starter circuit to start the reference current source sub-circuit under the control of the first delay unit.

[0042] Step 103: The reference current source circuit controls the starter circuit to charge the charging unit. It should be understood that after startup, the reference current source circuit can output a reference current to the second control terminal of the starter circuit through its second output terminal. Simultaneously, the third output terminal of the starter circuit is coupled to the second terminal of the charging unit, thereby enabling charging of the charging unit under the control of the reference current source circuit.

[0043] Step 104: The first delay unit outputs a second reset signal when the charging unit is in the charging state. It should be understood that when in the charging state, the voltage at the first terminal of the charging unit will change, thereby refreshing the voltage of the second reset signal output by the first delay unit.

[0044] Based on the above signal generation process, it can be seen that in the signal generation circuit provided by the embodiments of the present invention, the first delay unit can output a first reset signal when the signal generation circuit is powered on. Furthermore, the first delay unit can control the starter circuit to start the reference current source sub-circuit according to the first reset signal. In addition, after starting, the reference current source sub-circuit can control the starter circuit to charge the charging unit. The first delay unit outputs a second reset signal when the charging unit is in a charging state. Therefore, the signal generation circuit provided by the embodiments of the present invention can simultaneously achieve the start-up of the reference current source sub-circuit and the output of the first and second reset signals after power-on, eliminating the need for separate start-up circuits for starting the reference current source sub-circuit and power-on reset circuits for outputting power-on reset signals in the chip. Therefore, when the signal generation circuit provided by the embodiments of the present invention is applied to a chip, it can reduce the chip's size and facilitate chip miniaturization.

[0045] As one possible implementation, such as Figure 2 As shown, the third control terminal of the aforementioned starter circuit 2 is coupled to the first output terminal of the first delay unit 32. The first delay unit 32 is also used to control the starter circuit 2 to turn off according to the second reset signal.

[0046] like Figure 2 As shown, the power-on reset output sub-circuit 3 further includes a voltage holding unit 33. The first input terminal of the voltage holding unit 33 is coupled to the power supply terminal VCC. The first control terminal of the voltage holding unit 33 is coupled to the second output terminal of the reference current source sub-circuit 1. Both the first output terminal and the second input terminal of the voltage holding unit 33 are coupled to the first output terminal of the first delay unit 32. The second control terminal of the voltage holding unit 33 is coupled to the second output terminal of the first delay unit 32. The second output terminal of the voltage holding unit 33 is coupled to the first terminal of the charging unit 31.

[0047] like Figure 2 As shown, the first delay unit 32 is also used to control the voltage holding unit 33 to turn off when the reference current source circuit 1 is in the start-up state. When the charging unit 31 is in the charging state, the voltage holding unit 33 is used to start under the control of the reference current source circuit 1 and the first delay unit 32, so that the second output terminal of the first delay unit 32 outputs a second reset signal.

[0048] It should be understood that, such as Figure 2As shown, the reset state corresponding to the second reset signal is an invalid state. After the first delay unit 32 outputs the second reset signal, it indicates that the signal generation circuit has completed the startup of the reference current source sub-circuit 1 and the power-on reset operation of the module to be initialized in the chip. Simultaneously, one function of the startup sub-circuit 2 is to start the reference current source sub-circuit 1. Based on this, the first delay unit 32 controls the startup sub-circuit 2 to shut down according to the second reset signal, thereby preventing the startup sub-circuit 2 from remaining in an operating state after the reference current source sub-circuit 1, reducing the power consumption of the signal generation circuit. Furthermore, another function of the startup sub-circuit 2 is to charge the charging unit 31 so that the first delay unit 32 outputs the second reset signal. When the startup sub-circuit 2 is off, the voltage holding unit 33 can be started under the control of the reference current source sub-circuit 1 and the first delay unit 32, causing the second output terminal of the first delay unit 32 to continuously output the second reset signal, thereby preventing the signal generation circuit from outputting a valid first reset signal when not powered on, improving the reliability of the signal generation circuit.

[0049] In an optional example, such as Figure 2 As shown, the aforementioned starter circuit 2 may include a start-up unit 21, a refresh unit 22, and a shutdown unit 23.

[0050] like Figure 2 As shown, the input terminal of the aforementioned startup unit 21 is coupled to the power supply terminal VCC. The control terminal of the startup unit 21 is the first control terminal of the startup sub-circuit 2. The output terminal of the startup unit 21 is the second output terminal of the startup sub-circuit 2. The startup unit 21 starts the reference current source sub-circuit 1 according to the first reset signal and shuts down when the first delay unit 32 outputs the second reset signal.

[0051] like Figure 2 As shown, the first input terminal of the refresh unit 22 is coupled to the power supply terminal VCC. The second input terminal of the refresh unit 22 is coupled to both the output terminal of the shutdown unit 23 and the first control terminal of the refresh unit 22. The second control terminal of the refresh unit 22 is the second control terminal of the startup sub-circuit 2. The first output terminal of the refresh unit 22 is the first output terminal of the startup sub-circuit 2. The second output terminal of the refresh unit 22 is coupled to the input terminal of the shutdown unit 23. The third output terminal of the refresh unit 22 is the third output terminal of the startup sub-circuit 2. The refresh unit 22 charges the charging unit 31 under the control of the reference current source sub-circuit 1.

[0052] like Figure 2 As shown, the control terminal of the shutdown unit 23 is the third control terminal of the starter circuit 2. The shutdown unit 23 is used to shut down the refresh unit 22 when the first delay unit 32 outputs a second reset signal.

[0053] Specifically, such as Figure 2As shown, the aforementioned startup unit 21 can be turned on under the control of the first reset signal output by the first delay unit 32, and after being turned on, it starts the reference current source circuit 1. Furthermore, it can be turned off under the control of the second reset signal output by the first delay unit 32 to reduce its own power consumption. For the refresh unit 22, the refresh unit 22 is turned on under the control of the reference current output by the reference current source circuit 1, and after being turned on, it charges the charging unit 31, causing a change in the voltage at the first terminal of the charging unit 31. This refreshes the voltage of the second reset signal output by the first delay unit 32, preventing the output of the first reset signal as valid when not powered on, thus improving the reliability of the signal generation circuit. For the shutdown unit 23, the shutdown unit 23 can be turned off under the control of the second reset signal output by the first delay unit 32, thereby turning off the startup sub-circuit 2 when the first delay unit 32 outputs the second reset signal, reducing the power consumption of the signal generation circuit.

[0054] In one example, such as Figure 2 As shown, the refresh unit 22 may include a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. The ratio of the channel width-to-length ratio of the second transistor M2 to that of the first transistor M1 is A. The ratio of the channel width-to-length ratio of the fourth transistor M4 to that of the third transistor M3 is B, and A > B.

[0055] like Figure 2 As shown, the input terminal of the first transistor M1 is coupled to the power supply terminal VCC. The control terminal of the first transistor M1 is coupled to the second output terminal of the reference current source circuit 1 and the control terminal of the second transistor M2, respectively. The output terminal of the first transistor M1 is coupled to the input terminal of the shutdown unit 23.

[0056] like Figure 2 As shown, the input terminal of the second transistor M2 is coupled to the power supply terminal VCC. The output terminal of the second transistor M2 is coupled to the first terminal of the charging unit 31 and the input terminal of the fourth transistor M4, respectively.

[0057] like Figure 2 As shown, the input and control terminals of the third transistor M3 are coupled to the output terminal of the shutdown unit 23 and the control terminal of the fourth transistor M4, respectively. The output terminal of the third transistor M3 is grounded to GND.

[0058] like Figure 2 As shown, the output terminal of the fourth transistor M4 is grounded to GND.

[0059] It should be understood that the channel width-to-length ratio of a transistor is the ratio of the width to the length of the conductive channel it comprises. A larger channel width-to-length ratio results in a larger saturation current for the transistor. Conversely, a smaller channel width-to-length ratio results in a larger saturation current. Therefore, when the ratio (A) of the channel width-to-length ratio of the second transistor to that of the first transistor is greater than the ratio (B) of the channel width-to-length ratio of the fourth transistor to that of the third transistor, the current flowing through the first and second transistors is greater than the current flowing through the third and fourth transistors after the refresh unit is activated. At this time, the current flows from the output terminal of the second transistor to the input terminal of the fourth transistor and the first terminal of the charging unit, respectively, thereby charging the charging unit. The specific values ​​of A and B, and the difference between A and B, can be set according to actual needs and are not specifically limited here.

[0060] Specifically, the first, second, third, and fourth transistors mentioned above can be PMOS transistors or NMOS transistors. For example, as shown... Figure 2 As shown, the first transistor M1 and the second transistor M2 are both PMOS transistors, while the third transistor M3 and the fourth transistor M4 are both NMOS transistors. In this configuration, the input terminals of the first transistor M1 and the second transistor M2 are the sources of the PMOS transistors. The output terminals of the first transistor M1 and the second transistor M2 are the drains of the PMOS transistors. The input terminals of the third transistor M3 and the fourth transistor M4 are the drains of the NMOS transistors. The output terminals of the third transistor M3 and the fourth transistor M4 are the sources of the NMOS transistors.

[0061] In one example, such as Figure 2 As shown, the above-mentioned start-up unit 21 and turn-off unit 23 can be NMOS transistors or PMOS transistors.

[0062] Specifically, the aforementioned startup unit can be the eleventh transistor. The shutdown unit can be the twelfth transistor. For example, as shown... Figure 2As shown, when the voltage of the first reset signal is low and the voltage of the second reset signal is high, both the eleventh transistor M11 and the twelfth transistor M12 can be PMOS transistors. At this time, the input terminals of the startup unit 21 and the shutdown unit 23 are the sources of the PMOS transistors. The output terminals of the startup unit 21 and the shutdown unit 23 are the drains of the PMOS transistors. Based on this, the source of the startup unit 21 is coupled to the power supply terminal VCC, and the control terminal of the startup unit 21 is connected to the first reset signal. At this time, the voltage difference between the source and gate of the startup unit 21 is VCC, and the startup unit 21 is turned on. Simultaneously, the drain of the startup unit 21 can output a large current to the control terminal of the reference current source circuit 1, thereby enabling the startup of the reference current source circuit 1. When the control terminal of the startup unit 21 is connected to the second reset signal, both the source and gate of the startup unit 21 are at a high level. At this time, the startup unit 21 is turned off. For the shutdown unit 23, since the refresh unit 22 is started under the control of the reference current output by the reference current source circuit 1, the second output terminal of the refresh unit 22 can output a large current to the source of the shutdown unit 23. Furthermore, after the second reset signal is applied to the gate of the shutdown unit 23, both the source and gate of the shutdown unit 23 are at a high level. At this time, the shutdown unit 23 is turned off. Simultaneously, because the input terminal of the shutdown unit 23 is coupled to the second output terminal of the refresh unit 22, and the output terminal of the shutdown unit 23 is coupled to both the second input terminal and the first control terminal of the refresh unit 22, the refresh unit 22 cannot be turned on after the shutdown unit 23 is turned off. This achieves the shutdown unit 23 turning off the refresh unit 22 when the first delay unit 32 outputs the second reset signal.

[0063] In an optional example, such as Figure 2 As shown, the voltage holding unit 33 may include a fifth transistor M5 and a sixth transistor M6.

[0064] like Figure 2 As shown, the input terminal of the fifth transistor M5 is the first input terminal of the voltage holding unit 33. The control terminal of the fifth transistor M5 is the first control terminal of the voltage holding unit 33. The output terminal of the fifth transistor M5 is the first output terminal of the voltage holding unit 33.

[0065] like Figure 2 As shown, the input terminal of the sixth transistor M6 is the second input terminal of the voltage holding unit 33. The control terminal of the sixth transistor M6 is the second control terminal of the voltage holding unit 33. The output terminal of the sixth transistor M6 is the second output terminal of the voltage holding unit 33.

[0066] Specifically, the fifth and sixth transistors mentioned above can be PMOS transistors or NMOS transistors. For example, as shown... Figure 2 As shown, when the voltage of the first reset signal is low and the voltage of the second reset signal is high, both the fifth transistor M5 and the sixth transistor M6 are PMOS transistors. At this time, the input terminals of the fifth transistor M5 and the sixth transistor M6 are the sources of the PMOS transistors. The output terminals of the fifth transistor M5 and the sixth transistor M6 are the drains of the PMOS transistors. Therefore, when the first reset signal is applied to the source of the sixth transistor M6, the source of the sixth transistor M6 is at a low level, and the sixth transistor M6 is turned off. Because the source of the sixth transistor M6 is coupled to the drain of the fifth transistor M5, the fifth transistor M5 cannot conduct when the sixth transistor M6 is turned off. However, when the second reset signal is applied to the source of the sixth transistor M6, the source of the sixth transistor M6 is at a high level. The voltage of the output signal at the second output terminal of the first delay unit 32 is opposite to the voltage of the output signal at the first output terminal of the first delay unit 32, therefore the gate of the sixth transistor M6 is at a low level, thus turning on the sixth transistor M6. Simultaneously, the fifth transistor M5 is also turned on under the control of the reference current output by the reference current source circuit 1. When the fifth transistor M5 is turned on, its drain can output a large current. Furthermore, the drain of the fifth transistor M5 is coupled to the first output terminal of the first delay unit 32, so the voltage holding unit 33 can continuously output the second reset signal at the first output terminal of the first delay unit 32 after the starter circuit 2 is turned off, thereby improving the reliability of the signal generation circuit.

[0067] In an optional example, such as Figure 2 As shown, the first delay unit 32 includes a first inverter I1 and a second inverter I2. The input terminal of the second inverter I2 is coupled to the output terminal of the first inverter I1. The input terminal of the first inverter I1 is the input terminal of the first delay unit 32. The output terminal of the first inverter I1 is the second output terminal of the first delay unit 32. The output terminal of the second inverter I2 is the first output terminal of the first delay unit 32.

[0068] Specifically, such as Figure 2 As shown, the first delay unit 32 includes a first inverter I1 and a second inverter I2 connected in series. Since the input terminal of the first inverter I1 is coupled to the first terminal of the charging unit 31, and the output terminal of the second inverter I2 is the first output terminal of the first delay unit 32, the first delay unit 32 can output a first reset signal and a second reset output with different voltages according to the potential change of the first terminal of the charging unit 31, and realize the start-up of the reference current source circuit 1.

[0069] As one possible implementation, such as Figure 2As shown, the power-on reset output sub-circuit 3 may further include a second delay unit 34. The first terminal of the second delay unit 34 is coupled to the first output terminal of the first delay unit 32. The second terminal of the second delay unit 34 is grounded to GND.

[0070] Specifically, such as Figure 2 As shown, the second delay unit 34 can be any unit with a delay function, such as the second capacitor C2. When the second delay unit 34 is the second capacitor C2, the delay function can be achieved by charging and discharging the second capacitor C2. It is understood that the capacitance of the second capacitor C2 affects the length of the delay time. Specifically, the larger the capacitance of the second capacitor C2, the longer the delay time. Conversely, the smaller the capacitance of the second capacitor C2, the shorter the delay time. Therefore, the capacitance of the second capacitor C2 can be set according to the requirements of the delay time required by the second delay unit 34 in the actual application scenario.

[0071] As one possible implementation, such as Figure 2 As shown, the power-on reset output sub-circuit 3 may further include a voltage regulator unit 35. The first terminal of the voltage regulator unit 35 is coupled to the input terminal of the first delay unit 32. The second terminal of the voltage regulator unit 35 is coupled to the first output terminal of the first delay unit 32. In this case, the presence of the voltage regulator unit 35 can prevent voltage fluctuations in the signal input terminal of the first delay unit 32, or maintain a substantially constant output voltage at the first output terminal of the first delay unit 32 when the load at the first output terminal of the first delay unit 32 changes, thereby improving the stability of the signal generation circuit.

[0072] Specifically, such as Figure 2 As shown, the voltage regulator unit 35 can be any unit with voltage regulation function, such as the third capacitor C3. Specifically, when the voltage regulator unit 35 is the third capacitor C3, the first and second terminals of the voltage regulator unit 35 can be either of the terminals of the third capacitor C3.

[0073] As one possible implementation, such as Figure 2 and Figure 3 As shown, the above-mentioned reference current source circuit 1 includes a reference current generation unit 11 and a current mirror unit 12.

[0074] like Figure 2As shown, the first input terminal of the aforementioned reference current generation unit 11 is coupled to the first output terminal and the control terminal of the current mirror unit 12, respectively. The second input terminal of the reference current generation unit 11 is coupled to the second output terminal of the starter circuit 2, the first control terminal and the second control terminal of the reference current generation unit 11, and the second output terminal of the current mirror unit 12, respectively. The first control terminal of the reference current generation unit 11 is the control terminal of the reference current source circuit 1. The output terminal of the reference current generation unit 11 is grounded to GND. The reference current generation unit 11 is used to generate a reference current under the control of the starter circuit 2.

[0075] like Figure 2 As shown, the input terminal of the current mirror unit 12 is coupled to the power supply terminal VCC. The first output terminal of the current mirror unit 12 is the second output terminal of the reference current source circuit 1. The current mirror unit 12 is used to output the reference current bias to the second control terminal of the starter circuit 2.

[0076] For example, such as Figure 2 As shown, the aforementioned reference current generating unit 11 may include a seventh transistor M7, an eighth transistor M8, and a resistor R. Specifically, the input terminal of the seventh transistor M7 is the first input terminal of the reference current generating unit 11. The control terminal of the seventh transistor M7 is the first control terminal of the reference current generating unit 11. The output terminal of the seventh transistor M7 is grounded to GND. The input terminal of the eighth transistor M8 is the second input terminal of the reference current generating unit 11. The control terminal of the eighth transistor M8 is the second control terminal of the reference current generating unit 11. The output terminal of the eighth transistor M8 is grounded to GND. One end of the resistor R is coupled to the input terminal of the eighth transistor M8, and the other end is coupled to the control terminal of the eighth transistor M8.

[0077] The seventh and eighth transistors mentioned above can be PMOS transistors or NMOS transistors. For example: Figure 2 As shown, both the seventh transistor M7 and the eighth transistor M8 are NMOS transistors. In this case, the input terminals of the seventh transistor M7 and the eighth transistor M8 are the drains of the NMOS transistors. The output terminals of the seventh transistor M7 and the eighth transistor M8 are the sources of the NMOS transistors.

[0078] like Figure 2As shown, the current mirror unit 12 described above may include a ninth transistor M9 and a tenth transistor M10. Specifically, the input terminal of the ninth transistor M9 is coupled to the power supply terminal VCC. The control terminal of the ninth transistor M9 is coupled to both the output terminal of the ninth transistor M9 and the control terminal of the tenth transistor M10. The output terminal of the ninth transistor M9 is the first output terminal of the current mirror unit 12. The input terminal of the tenth transistor M10 is coupled to the power supply terminal VCC. The output terminal of the tenth transistor M10 is the second output terminal of the current mirror unit 12.

[0079] The ninth and tenth transistors can be either PMOS or NMOS transistors. For example: Figure 2 As shown, both the ninth transistor M9 and the tenth transistor M10 are PMOS transistors. In this case, the input terminals of the ninth transistor M9 and the tenth transistor M10 are the sources of the PMOS transistors. The output terminals of the ninth transistor M9 and the tenth transistor M10 are the drains of the PMOS transistors.

[0080] In practical applications, such as Figure 2 As shown, taking NMOS transistors M7 and M8 as the seventh transistor and PMOS transistors M9 and M10 as the tenth transistor, respectively, when a large current is output from the second output terminal of the starter circuit 2 to the gate of the seventh transistor M7 and to the gate of the eighth transistor M8 through resistor R, the sources of both transistors M7 and M8 are grounded to GND. At this time, the voltage difference between the gates and sources of transistors M7 and M8 is greater than the turn-on voltage, causing transistors M7 and M8 to turn on, thus generating a reference current. Specifically, the relationship between the magnitude of the reference current and time can be found in [reference needed]. Figure 3 While the seventh transistor M7 and the eighth transistor M8 are turned on, the sources of the ninth transistor M9 and the tenth transistor M10 are both connected to a power supply signal, and the gates of the ninth transistor M9 and the tenth transistor M10 are respectively coupled to the drain of the ninth transistor M9 and the source of the seventh transistor M7. Therefore, the ninth transistor M9 and the tenth transistor M10 are also turned on at this time. After they are turned on, they can bias the reference current generated by the reference current generation unit 11 to the second control terminal of the starter circuit 2 through the drain of the ninth transistor M9. In addition, when the power-on reset output sub-circuit 3 also includes a voltage holding unit 33, the drain of the ninth transistor M9 biases the reference current generated by the reference current generation unit 11 to the first control terminal of the voltage holding unit 33, thereby realizing the control of the starter circuit and the voltage holding unit 33.

[0081] like Figure 5As shown, this embodiment of the invention also provides a signal generation method, which applies the signal generation circuit provided in the above embodiments. The signal generation method includes:

[0082] Step 101: The first delay unit outputs a first reset signal when the signal generation circuit is powered on.

[0083] Step 102: The first delay unit controls the starter circuit to start the reference current source circuit according to the first reset signal.

[0084] Step 103: The reference current source circuit controls the starter circuit to charge the charging unit.

[0085] Step 104: The first delay unit outputs a second reset signal when the charging unit is in the charging state.

[0086] The beneficial effects of the signal generation method provided in the embodiments of the present invention are the same as those of the signal generation circuit provided in the above embodiments, and will not be repeated here.

[0087] As one possible implementation, as described above, in the case where the third control terminal of the signal generation circuit is coupled to the first output terminal of the first delay unit, and the first delay unit is also used to control the start-up sub-circuit to shut down according to the second reset signal, and the power-on reset output sub-circuit also includes a voltage holding unit, after the first delay unit outputs the second reset signal when the charging unit is in the charging state, the signal generation method may further include:

[0088] Step 105: The first delay unit controls the starter circuit to shut down according to the second reset signal.

[0089] Step 106: When the charging unit is in the charging state, the voltage holding unit is started under the control of the reference current source circuit and the first delay unit, so that the second output terminal of the first delay unit outputs the second reset signal.

[0090] This invention also provides a chip that includes the signal generation circuit provided in the above embodiments.

[0091] The beneficial effects of the chip provided in this embodiment are the same as those of the signal generation circuit provided in the above embodiments, and will not be repeated here.

[0092] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A signal generating circuit, characterized by comprising: The application relates to a power-on reset output subcircuit, which comprises a reference current source subcircuit, a starting subcircuit and a power-on reset output subcircuit. The power-on reset output subcircuit comprises a charging unit and a first delay unit; the input end of the reference current source subcircuit and the input end of the starting subcircuit are coupled with a power supply end; the first output end of the reference current source subcircuit and the first output end of the starting subcircuit are grounded; the first end of the charging unit is coupled with the input end of the first delay unit, and the second end of the charging unit is grounded; The first output end of the first delay unit is coupled with the first control end of the starting subcircuit; the second output end of the starting subcircuit is coupled with the control end of the reference current source subcircuit; the second output end of the reference current source subcircuit is coupled with the second control end of the starting subcircuit; the third output end of the starting subcircuit is coupled with the second end of the charging unit; The first delay unit is used for outputting a first reset signal when the signal generation circuit is powered on, and controlling the starting subcircuit to start the reference current source subcircuit according to the first reset signal; the reference current source subcircuit is used for controlling the starting subcircuit to charge the charging unit, and the first delay unit is used for outputting a second reset signal when the charging unit is in a charging state; The starting subcircuit comprises a refreshing unit and a shutdown unit, and the refreshing unit comprises a first transistor, a second transistor, a third transistor and a fourth transistor; the ratio of the channel width-length ratio of the second transistor to the channel width-length ratio of the first transistor is A; the ratio of the channel width-length ratio of the fourth transistor to the channel width-length ratio of the third transistor is B, and A > B; The input end of the first transistor is coupled with the power supply end, the control end of the first transistor is coupled with the second output end of the reference current source subcircuit and the control end of the second transistor respectively, and the output end of the first transistor is coupled with the input end of the shutdown unit; The input end of the second transistor is coupled with the power supply end, and the output end of the second transistor is coupled with the first end of the charging unit and the input end of the fourth transistor respectively; The input end and the control end of the third transistor are coupled with the output end of the shutdown unit and the control end of the fourth transistor respectively, and the output end of the third transistor is grounded; The output end of the fourth transistor is grounded; The control end of the shutdown unit is the third control end of the starting subcircuit, and the shutdown unit is used for closing the refreshing unit when the first delay unit outputs the second reset signal. The third control end of the starting subcircuit is coupled with the first output end of the first delay unit; and the first delay unit is further used for controlling the starting subcircuit to be closed according to the second reset signal.

2. The signal generating circuit of claim 1, wherein ​ The power-on reset output sub-circuit further comprises a voltage holding unit, a first input terminal of the voltage holding unit is coupled with the power supply terminal, a first control terminal of the voltage holding unit is coupled with a second output terminal of the reference current source sub-circuit, a first output terminal of the voltage holding unit and a second input terminal of the voltage holding unit are both coupled with a first output terminal of the first delay unit, a second control terminal of the voltage holding unit is coupled with a second output terminal of the first delay unit, and a second output terminal of the voltage holding unit is coupled with a first terminal of the charging unit; The first delay unit is further configured to control the voltage holding unit to be closed when the reference current source sub-circuit is in a starting state; and when the charging unit is in a charging state, the voltage holding unit is configured to be started under the control of the reference current source sub-circuit and the first delay unit, so that the second output terminal of the first delay unit outputs a second reset signal.

3. The signal generating circuit of claim 2, wherein The starting sub-circuit further comprises a starting unit; An input terminal of the starting unit is coupled with the power supply terminal, a control terminal of the starting unit is a first control terminal of the starting sub-circuit, and an output terminal of the starting unit is a second output terminal of the starting sub-circuit; the starting unit starts the reference current source sub-circuit according to the first reset signal, and is closed when the first delay unit outputs a second reset signal; A first input terminal of the refreshing unit is coupled with the power supply terminal, a second input terminal of the refreshing unit is coupled with an output terminal of the turning-off unit and a first control terminal of the refreshing unit respectively, a second control terminal of the refreshing unit is a second control terminal of the starting sub-circuit, a first output terminal of the refreshing unit is a first output terminal of the starting sub-circuit, a second output terminal of the refreshing unit is coupled with an input terminal of the turning-off unit, a third output terminal of the refreshing unit is a third output terminal of the starting sub-circuit; the refreshing unit charges the charging unit under the control of the reference current source sub-circuit.

4. The signal generating circuit of claim 3, wherein The starting unit and the turning-off unit are NMOS transistors or PMOS transistors.

5. The signal generating circuit of claim 2, wherein, The voltage holding unit comprises a fifth transistor and a sixth transistor; An input terminal of the fifth transistor is a first input terminal of the voltage holding unit, a control terminal of the fifth transistor is a first control terminal of the voltage holding unit, and an output terminal of the fifth transistor is a first output terminal of the voltage holding unit; An input terminal of the sixth transistor is a second input terminal of the voltage holding unit, a control terminal of the sixth transistor is a second control terminal of the voltage holding unit, and an output terminal of the sixth transistor is a second output terminal of the voltage holding unit; and / or The first delay unit comprises a first inverter and a second inverter; an input terminal of the second inverter is coupled with an output terminal of the first inverter; an input terminal of the first inverter is an input terminal of the first delay unit, an output terminal of the first inverter is a second output terminal of the first delay unit, and an output terminal of the second inverter is a first output terminal of the first delay unit.

6. The signal generating circuit according to any one of claims 1 to 5, characterized by, The power-on reset output sub-circuit further comprises a second delay unit, a first end of the second delay unit is coupled with a first output end of the first delay unit, and a second end of the second delay unit is grounded; and / or, The power-on reset output sub-circuit further comprises a voltage stabilizing unit, a first end of the voltage stabilizing unit is coupled with an input end of the first delay unit, and a second end of the voltage stabilizing unit is coupled with a first output end of the first delay unit.

7. The signal generating circuit according to any one of claims 1 to 5, characterized by, The reference current source sub-circuit comprises a reference current generation unit and a current mirror unit; a first input end of the reference current generation unit is coupled with a first output end and a control end of the current mirror unit respectively, a second input end of the reference current generation unit is coupled with a second output end of the starter sub-circuit, a first control end and a second control end of the reference current generation unit, and a second output end of the current mirror unit respectively, a first control end of the reference current generation unit is a control end of the reference current source sub-circuit, and an output end of the reference current generation unit is grounded; the reference current generation unit is configured to generate a reference current under the control of the starter sub-circuit; an input end of the current mirror unit is coupled with the power supply end, and a first output end of the current mirror unit is a second output end of the reference current source sub-circuit; the current mirror unit is configured to bias the reference current to output to the second control end of the starter sub-circuit.

8. A signal producing method characterized by, The signal generation circuit according to any one of claims 1-7; The signal generation method comprises: the first delay unit outputs a first reset signal when the signal generation circuit is powered on; the first delay unit controls the starter sub-circuit to start the reference current source sub-circuit according to the first reset signal; the reference current source sub-circuit controls the starter sub-circuit to charge the charging unit; the first delay unit outputs a second reset signal when the charging unit is in a charging state.

9. The signal generating method according to claim 8, wherein The signal generation circuit according to any one of claims 2-6; After the first delay unit outputs the second reset signal when the charging unit is in a charging state, the signal generation method further comprises: the first delay unit controls the starter sub-circuit to be closed according to the second reset signal; under the condition that the charging unit is in a charging state, the voltage holding unit is started under the control of the reference current source sub-circuit and the first delay unit, so that the second output end of the first delay unit outputs the second reset signal.

10. A chip, characterized by The signal generation circuit according to any one of claims 1-7.

Images