Time-Programmable Fail-Safe Pull-Down Circuit for GaN Switches

Abstract

Circuits and devices are provided for reliably maintaining normally-off gate injection transistors (GITs), etc. in a non-conducting state when not driving the gate of the GIT with a turn-on control signal. This is achieved using a fail-safe pull-down coupled to the gate of the GIT. The fail-safe pull-down includes a resistance modulation circuit that changes the effective gate resistance of the GIT such that a low resistance is provided for a certain interval immediately after the turn-on transition of the GIT, thereby facilitating charging of the gate of the GIT with a high current pulse. Subsequently, a high resistance is provided such that a much lower current is driven to maintain the GIT in its conducting state. The fail-safe pull-down enables the use of a relatively simple driver to drive the GIT, etc., which relatively simple driver can be provided external to the power switch device or integrated with the power switch on the same die.

Description

Technical Field

[0001] The present application relates to a circuit topology and a power switching device, each including a time-programmable failsafe pulldown that provides a variable effective gate resistance for gallium nitride (GaN) or similar transistors. Background Art

[0002] Gallium nitride (GaN)-based switches and other similar high electron mobility transistors (HEMTs) based on heterojunctions provide high voltage support, low drain-to-source on-resistance, low gate drive charge requirements, and fast switching. Due to these characteristics, GaN-based switches are increasingly being used in applications that require high efficiency and high frequency support, especially including switched-mode power converters. However, compared to conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) and bipolar junction transistors (BJTs), GaN-based switches typically have unique gate drive requirements and often require complex gate drive circuitry.

[0003] A GaN-based switch in its natural state is a normally-on (depletion-mode) device. When no voltage is applied to its gate relative to its source, this device conducts current from its drain to its source, and a negative voltage needs to be applied to its gate to force the device into a non-conducting (blocking) state. This normally-on behavior is not suitable for most applications. Therefore, modifications to GaN-based switches have been developed to transform them into normally-off (enhancement-mode) devices. For example, a p-doped GaN layer introduced between the gate metal and the heterostructure of a GaN-based switch has the effect of raising the on / off voltage threshold of the switch to a positive value, thus providing a normally-off device. An enhancement-mode switch based on this gate structure is called a gate injection transistor (GIT).

[0004] GaN-based GITs have a relatively low threshold voltage for switching between their conducting (on) and blocking (off) states. This threshold voltage is typically in the range of 1.2 to 3.5 V, which is significantly lower than the corresponding threshold of other power transistors such as power MOSFETs, e.g., 5 V. In addition, HEMTs incorporating GaN-based GITs have a low gate-to-source capacitance, which is significantly smaller than the corresponding capacitance in power MOSFETs. While the low threshold voltage and low gate capacitance of GaN-based GITs advantageously provide fast switching speed and low gate charge requirements, these characteristics also make GaN-based GITs prone to unwanted conduction during intervals when the GIT is intended to remain in its non-conducting (blocking) state due to voltage perturbations at the gate of the GIT. For example, noise at the gate may cause its voltage to rise above the threshold voltage of the GIT, even though the gate is intended to remain at a low voltage. Such noise may occur during the operating intervals when the GIT is intended to remain in its non-conducting state and during startup intervals (during which the gate may not yet have been provided with a drive control signal). Additionally, the gate voltage may be prone to ringing after the control voltage transitions from a high (on) voltage level to a low (off) voltage level. The ringing voltage level may exceed the threshold voltage of the GIT, thereby inadvertently turning on the GIT.

[0005] Another complexity when driving a GIT is that a drive current is required to maintain the GIT in its conducting state after the turn-on transition. To quickly switch the GIT to its on state and maintain the on state without excessive driver power consumption, the GIT gate is preferably provided with a high-current pulse at the transition from the off to the on state, and a subsequent steady-state current having a lower level than the high-current pulse.

[0006] The above problems are typically solved using complex circuits customized for driving GaN-based GITs or similar enhancement-mode HEMTs. Such circuits typically drive a negative voltage onto the gate to turn off the GIT, thereby providing a significant margin between the drive gate voltage and the on-threshold voltage of the GIT. This margin allows the GaN-based GIT to reliably remain in its non-conducting (blocking) state. A resistor-capacitor (RC) circuit is typically included in the drive circuit to provide a high current when the GaN-based GIT initially transitions to the conducting state. A lower current is subsequently provided to maintain the conducting state of the GIT. When the GaN-based GIT transitions to off, the RC circuit also has the effect of applying a relatively high-magnitude negative voltage, and this negative voltage dissipates to zero as the off interval progresses.

[0007] The above-described exemplary GIT driver circuit has many problems. First, the negative voltage provided at the gate during the turn-off interval causes a large required voltage swing when the GIT transitions to its conducting state, thereby slowing the GIT transition and potential switching speed. Second, the RC-based time-varying voltage decay means that the level of the negative voltage will vary according to the switching duty cycle, resulting in inconsistent transition times, which complicates the use and control of the GIT. Third, although the above negative voltage reliably keeps the GIT off during steady-state operation, the pseudo non-zero voltage during the initial startup interval before the negative voltage is driven to the gate may undesirably turn on the GIT. Fourth, the negative voltage adds an offset to the effective reverse body diode voltage, thereby increasing the threshold voltage of the effective reverse body diode and increasing the associated losses. Finally, the driver circuit is rather complex and requires rather complex control of the switches within the driver circuit itself. Summary of the Invention

[0008] Circuits and power switching devices or similar devices incorporating GaN-based GITs are provided. These circuits and devices modulate the effective gate resistance of the GIT such that a high current level is provided to the GIT gate during the turn-on transition, while a low (holding) current level is provided during subsequent steady-state conduction intervals of the GIT. The resistance modulation circuit autonomously provides this variation in current level even when using a gate driver that only outputs two voltages to drive the GIT gate. In some embodiments, these circuits and devices are configured such that they can be driven by a conventional single-channel (two-level) driver, which is simpler than existing drivers for GaN-based GITs and does not require the use of a negative gate voltage to safely hold the GIT in its non-conducting state. In other embodiments, the device includes a driver function within the same device as the GIT and the resistance modulation circuit.

[0009] According to an embodiment of the power switching device, the power switching device includes a normally-off power transistor, a control terminal, a control reference terminal, a normally-on pull-down transistor, and a resistance modulation circuit. The normally-off power transistor has a gate, a source, and a drain, and the control terminal is connected to the gate. The pull-down transistor is configured to short the gate to the source (unless a voltage above the turn-on threshold is applied across the control terminal and the control reference terminal), and has a pull-down gate, a pull-down source, and a pull-down drain. The resistance modulation circuit is coupled between the source and the control reference terminal and includes a modulation transistor. The circuit is configured to modulate the resistance between the control terminal and the control reference terminal such that, in response to applying a device turn-on voltage between the control terminal and the control reference terminal, a charging current is provided to the gate during a predetermined charging interval, and a holding current is provided to the gate after the predetermined charging interval. The holding current has a level lower than the level of the charging current.

[0010] According to an embodiment of a power switch device with an integrated driver, the device and driver include a normally-off power transistor, first and second load terminals, a power supply and a power supply reference terminal, a control terminal, a normally-on pull-down transistor, an integrated driver, and a resistance modulation circuit. The normally-off power transistor includes a drain connected to the first load terminal, a source connected to the second load terminal, and a gate. The power supply and power supply reference terminal are configured to be connected to an external power supply. The control terminal is configured to input a digital control signal that controls conduction between the first load terminal and the second load terminal. The normally-on pull-down transistor has a pull-down gate, a pull-down source, and a pull-down drain, and is configured to short-circuit the gate and source of the power transistor when the digital control signal does not command conduction of the power switch device. The integrated driver circuit is configured to source current to and / or sink current from the pull-down gate based on the digital control signal. The resistance modulation circuit is coupled between the source and the power supply reference terminal and includes a modulation transistor. The circuit is configured to modulate the resistance between the power supply terminal and the power supply reference terminal such that a charging current is provided to the gate during a predetermined charging interval in response to the digital control signal transitioning to command conduction, and a holding current is provided to the gate after the predetermined charging interval. The holding current has a level lower than the level of the charging current.

[0011] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and viewing the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The elements in the drawings are not necessarily drawn to scale relative to each other. Like reference numerals denote corresponding like parts. Features of the various illustrated embodiments may be combined unless they are mutually exclusive. The embodiments are depicted in the drawings and detailed in the following description.

[0013] Figure 1 Schematic diagram showing a power switch device including a fail-safe pull-down circuit containing a circuit for modulating an effective gate resistance;

[0014] Figure 2 Waveform of the effective gate resistance near the turn-on transition of a GaN-based switch;

[0015] Figure 3 Showing Figure 1 voltage and current waveforms of the driver of the device during the turn-on interval;

[0016] Figures 4A - 4E Showing current within the Figure 1 power switch device at different times associated with the turn-on interval of the device;

[0017] Figure 5 Showing corresponding to Figure 1 voltage and current waveforms of the power switch device;

[0018] Figure 6 A power switching system including an alternative power switching device is shown, in which a resistor external to the power switching device is used to achieve programmability of an effective gate resistance, and the alternative power switching device is driven by an external single-channel driver;

[0019] Figure 7 A power switching device including a driver circuit and not requiring an external driver is shown;

[0020] Figure 8 Another power switching device including a driver circuit and also not requiring an external driver is shown. DETAILED DESCRIPTION

[0021] The embodiments described herein provide a circuit and a power switching device including a time-programmable fail-safe pull-down for a gate of a power switch. Although the examples described use a gallium nitride (GaN)-based gate injection transistor (GIT) as the power switch, the techniques and circuits can be advantageously used with other transistors or semiconductor types, particularly other enhancement-mode high electron mobility transistors (HEMTs) characterized by having a low on / off threshold voltage and a low gate capacitance. The fail-safe pull-down prevents the power switch from being inadvertently turned on due to parasitic noise or ringing and does not require a negative voltage at the gate of the power switch. Accordingly, many problems and complexities associated with applying a negative voltage to the power switch gate are avoided.

[0022] The fail-safe pull-down of the following examples modulates the effective gate resistance of the power switching device, where the modulation is time-programmable. The gate (control terminal) of the GIT or a similar power switch is preferably driven with a high-current pulse to rapidly transition the GIT from its off state to its on state and with a low current to maintain the on state until the GIT is turned off. This can be achieved by using a two-channel driver and / or other external components (including a current-limiting resistor between the two-channel driver and the GIT gate) in combination with a non-time-programmable fail-safe pull-down. The time-programmable fail-safe pull-down circuit described herein does not require such a two-channel driver and does not require a series resistor to limit the current level of the high-current pulse.

[0023] A time-programmable fail-safe pull-down circuit modulates the resistance of the gate path loop of a power switch device. The resulting gate path loop has a low resistance at the turn-on transition of the GIT to provide a desired high-current turn-on transition pulse. Subsequently, the resistance of the gate path loop is increased after the GIT transitions to the on state to provide a desired low-current level to maintain the on state of the GIT. Resistors determine (program) the duration of the high-current pulse and the resistance level of the gate path loop during the maintenance interval. These resistors can be monolithically integrated within the power switch device, such as in the same GaN die as the power switch and the fail-safe pull-down switch, to minimize size and cost. Alternatively, these resistors can be provided external to the GaN die to provide programming flexibility. Regardless of the level of integration, the time-programmable fail-safe pull-down enables the use of a relatively simple single-channel driver, such as those used with conventional power MOSFETs, while meeting the unique requirements of reliably holding the GIT in its off state and providing a high-current turn-on pulse and a low holding current to the GIT control terminal.

[0024] Embodiments are described primarily in the context of a power switch device where a fail-safe pull-down circuit and a power switch (such as a GIT) are integrated in the same GaN semiconductor die. The die can similarly be composed of some other III / V semiconductor or a silicon-based semiconductor. The integration of the described fail-safe pull-down circuit and power switch presents significant advantages in reliably maintaining the desired off (non-conducting) state of the power switch. In particular, this integration minimizes the parasitic inductance between the gate of the power switch and the fail-safe pull-down circuit, thereby constraining the voltage ringing that can occur when the control voltage driven to the gate transitions between a high voltage level and a low voltage level. The reduced ringing effectively clamps the gate-to-source voltage of the power switch to near zero during the off interval, which prevents the unintentional turn-on of the power switch. The integration of the fail-safe pull-down circuit very close to the power switch also reduces the interconnect paths (e.g., traces, terminals), thereby minimizing the likelihood of noise coupled to the gate. This also prevents the unintentional turn-on of the power switch, especially when no drive signal is applied to the gate as occurs during start-up intervals.

[0025] While embodiments are described primarily in the context of an integrated power switch device that includes both a fail-safe pull-down circuit and a power switch, the fail-safe pull-down circuit and the power switch can be provided on separate dies, i.e., they can be non-monolithically integrated. This solution provides an improvement over existing circuits for controlling the GIT, but may not achieve the significant noise reduction (improved reliability) advantages provided by the integrated power device.

[0026] A fail-safe pull-down circuit and a power switch can be provided on separate die integrated within the same package (i.e., within a system-in-package or multi-chip module). Such a system-in-package achieves reduced parasitic effects and improved reliability compared to a solution that is spread across separate packages, but may not achieve the same level of performance as a solution in which the fail-safe pull-down circuit and the power switch are integrated on the same die.

[0027] The power switch device can be controlled by a single-channel driver that is much simpler than existing drivers used to control GITs and significantly avoids complex switching sequences (state machines) within the driver and circuitry for generating negative voltages. The time-programmable fail-safe pull-down circuit operates autonomously and does not require separate control. Embodiments of power switch devices are described in which an external single-channel driver can be used to drive the power switch device. Other embodiments are described in which the driver functionality is integrated within the same GaN die as the GIT and the fail-safe pull-down circuit. The embodiments exhibit a common characteristic in that: the time-programmable fail-safe pull-down circuit provides a step change in the effective resistance of the gate path loop of the power switch.

[0028] Power switching device with a resistance modulation circuit

[0029] Figure 1 An embodiment of a power switch device 100 according to the present invention is shown. The power switch device 100 includes a power switch Q1, a first load terminal 106, a second load terminal 108, a control terminal 102, a control reference terminal 104, and a time-programmable fail-safe pull-down circuit 120. The shown power switch Q1 is a GaN-based GIT, which is of the enhancement-mode HEMT type. The power switch Q1 has a drain (D) connected to the first load terminal 106, a source (S) connected to the second load terminal 108, and a gate (G) connected to the control terminal 102. The control reference terminal 104 is connected to the source of the power switch Q1 via the time-programmable fail-safe pull-down circuit 120 and provides a reference connection (labeled GPD) for an external driver circuit that drives the gate of the power switch Q1. (Such an external driver circuit is not shown in Figure 1 but is shown, for example, in Figure 6 ). The shown power switch device 100 has only four terminals.

[0030] The power switch Q1 is a normally-off device, but for a GaN-based GIT, it has a relatively low threshold voltage for turning on or off, for example in the range of 1.2 to 3.5V. In addition to the low gate capacitance of the power switch Q1, this also makes it easy to inadvertently transition to a conducting state. The time-programmable fail-safe pull-down circuit 120 prevents such inadvertent transitions and does so autonomously, i.e., no separate external signal is required to control the time-programmable fail-safe pull-down circuit 120. In particular, the voltage V provided across the control and control reference terminals 102, 104 is GG When the voltage V GG During the period when it is not driven (eg, floating), the time-programmable fail-safe pull-down circuit 120 shorts the gate of the power switch Q1 to the source of the power switch Q1 so that there is no positive control voltage V Q1_GS To turn on the power switch Q1.

[0031] Figure 2 shows the gate and reference terminals (e.g. Figure 1 The power switching device (e.g., Figure 1 2 . Such a resistance Rg(t) is shown at and after the conduction transition of a power switch (e.g., power switch Q1). The power switch is turned on at or before time t0, at which point the effective gate resistance Rg(t) is quite low, such as on the order of single digit ohms or less. After the power switch transitions to its conducting state, the effective gate resistance Rg(t) increases to a much higher value, such as on the order of single digit kiloohms or more. As shown, between times t1 and t2, the effective gate resistance Rg(t) changes from the conduction transition resistance Rg(t) to the conduction transition resistance Rg(t). TRANS Change to the maintenance level R MAINT This modulation of the effective gate resistance Rg(t) facilitates a high drive current to turn the power switch on before time t1 and facilitates a low drive current to maintain the on state of the power switch after time t2, even when only a single-channel two-voltage level driver is coupled to the power switch device. The resistance level R MAINT can be adjusted to match the desired holding current level for a particular power switch, while the resistance level R TRANS The transition pulse duration τ and the maintaining resistance level R can be determined by the (relatively small) inherent resistance within the gate path loop, including the gate-to-source resistance of the power switch, the drain-to-source resistance of the modulation switch, and the effective diode resistance of the voltage clamp. As described in more detail below, the resistors in the time-programmable fail-safe pull-down circuit 120 can be used to adjust (program) the transition pulse duration τ and the maintaining resistance level R MAINT .exist Figure 3 and 5Additional waveforms showing the results of such modulation of the effective gate resistance Rg(t) are provided and will be further described below.

[0032] The time-programmable failsafe pull-down circuit 120 includes a normally-on pull-down switch Q PD and a resistance modulation circuit 130. The normally-on pull-down switch Q PD is preferably fabricated using the same or a similar technology as the power switch Q1 and on the same die as the power switch Q1. For the illustrated example in which the power switch Q1 is a GaN-based GIT (enhancement-mode HEMT), the pull-down switch Q PD is preferably a depletion-mode GaN-based HEMT, as shown. When the gate-to-source voltage V PD of such a pull-down switch Q PD_GS is sufficiently negative (e.g., below the turn-off threshold voltage V PD_THR which is typically in the range of -4V to -7V), such a pull-down switch Q PD turns off (is set to the blocking mode). Otherwise, including when a zero pull-down gate-to-source voltage is applied and when there is no voltage effectively driving across the pull-down gate and pull-down source, the pull-down switch Q PD conducts. Positioning the pull-down switch Q PD in the same die as the power switch Q1 and adjacent to the gate and source of the power switch Q1 can make the probability that the power switch Q1 inadvertently transitions to its conducting state extremely low.

[0033] The resistance modulation circuit 130 includes a voltage clamp 132 illustrated as a "10V clamp" diode and a steady-state pull-down resistor R SS which combine to autonomously provide the desired control of the pull-down switch Q PD . The voltage clamp 132 is configured to generate a pull-down gate-to-source voltage V PD below the negative threshold voltage V PD_THR required to turn off the pull-down switch Q during intervals when the power switch Q1 is conducting (conducting). The voltage clamp 132 can be a diode with a threshold voltage or can be modeled as a diode with a threshold voltage. The magnitude of the forward threshold voltage of a typical diode is lower than the magnitude of the turn-off threshold voltage V PD_GS of the pull-down switch Q PD . Although illustrated as a single diode, the voltage clamp 132 can actually include several individual diodes in series cascade (stacked) in order to achieve the clamping voltage V PD_THR required to turn off the pull-down switch Q PD , i.e., V CL >|V CL |. PD_THR

[0034] In some embodiments, the voltage clamp 132 may include multiple gate-controlled or PN diodes constructed from GaN-based GITs. A gate-controlled GIT diode can be constructed by coupling the gate and source of the GIT together to form a two-terminal device, where the gate / source acts as an anode and the drain acts as a cathode, and the device typically has a threshold (knee) voltage of 0.9 to 1.5V. A GIT-based PN diode is constructed by coupling the drain and source of the GIT together. The gate of the resulting two-terminal device acts as an anode, the drain / source acts as a cathode, and the device has a relatively stable threshold (knee) voltage of about 3.3V. For the pull-down switch Q PD The pull-down threshold voltage V of -7V PD_THR , a suitable voltage clamp having a threshold voltage of about 10V can be constructed by connecting three GIT-based PN diodes together, connecting ten gate-controlled GIT diodes together, or some other combination that results in a combined threshold voltage greater than about 10V. The advantage of using GIT-based diodes is that the voltage clamp 132 can be connected to the power switch Q1 and the pull-down switch Q PD Fabricated on the same GaN die.

[0035] Pull-down resistor R SS (also referred to herein as a steady-state resistor) ensures that the switch Q is pulled down in the absence of power / signal conditions PD For example, if no voltage is driven across the control and control reference terminals 102, 104, the pull-down resistor R SS Provides a path for the pull-down gate to discharge. This ensures that the pull-down gate and the pull-down source are pulled to the same voltage, V PD_GS = 0, so that the pull-down switch Q PD is turned on so that the power transistor gate (G) is shorted to the power transistor source (S). SS A typical resistor is 2KΩ, but as described below, this value can be adjusted to set the desired holding current level. PD In the preferred embodiment integrated in the same semiconductor die, the pull-down resistor R SS For the example of a GaN semiconductor die, one or more two-dimensional electron gas (2DEG) regions of the GaN semiconductor die may be used to construct a pull-down resistor R SS , where each region is essentially a GaN HEMT channel without a gate.

[0036] The resistance modulation circuit 130 further includes a modulation switch Q MOD , when the power switch Q1 is turned on, the modulation switch Q MOD The resistance of the gate path loop of the power switch device 100 is changed.PD ). The gate path circuit is a current path from the control terminal 102 to the control reference terminal 104, and when the power switch Q1 is turned on, it includes the gate of the power switch Q1, the source of the power switch Q1, and the path returning to the control reference terminal 104 through the fail-safe pull-down 120. When the modulation switch Q MOD is turned on, a low-impedance path is formed through the modulation switch Q MOD and the voltage clamp 132, and each of the modulation switch Q MOD and the voltage clamp 132 provides a negligible resistance. When the modulation switch Q MOD is turned off, the current is instead forced to flow through the resistors R BYP , R SS , presenting a high-impedance path at least compared to the current path through the modulation switch Q MOD . When the modulation switch Q BYP , R SS is turned on, the low-impedance path illustrated provides the aforementioned high-current transition pulse. When the modulation switch Q MOD is turned off, the high-impedance path illustrated provides a low-level current for maintaining the on state of the power switch Q1. MOD is turned off, the high-impedance path illustrated provides a low-level current for maintaining the on state of the power switch Q1.

[0037] The modulation switch Q MOD shown is a normally-on (depletion-mode) HEMT and is preferably integrated in the same GaN die as the power switch Q1. The modulation switch Q MOD has an associated gate-to-source capacitance C GS_MOD , which may not be a separate component but may be the intrinsic capacitance of the modulation switch Q MOD . This capacitance C GS_MOD is clearly shown in Figure 1 as it affects the duration of the high-current pulse. The modulation resistor R MOD couples the control reference terminal 104 and the gate of the pull-down switch Q PD to the gate of the modulation switch Q MOD , and the resistance of the modulation resistor R MOD is selected to achieve the desired duration of the high-current pulse.

[0038] Combining Figure 3 and Figures 4A - 4E provides a further explanation of the function of the power switch device 100, Figure 3 shows the current and voltage waveforms 310, 320 of the on-state interval of the power switch device 100, Figures 4A - 4E shows the corresponding current paths at different times. Figures 4A - 4E The circuit of Figure 1circuit, but further includes an external driver 160 that provides a drive voltage V DRV and a drive current I DRV . For purposes of illustration, Figures 4A - 4E the circuit of

[0039] does not explicitly show the demarcation of the time-programmable fail-safe pull-down 120, but the basic circuit of the power switch device 100 remains unchanged. DRV At time t0, the driver 160 begins to ramp the drive voltage V PD from 0V. In this initial state, the normally-on pull-down switch Q MOD conducts, shorting the gate and source of the power switch Q1 so that Q1 does not conduct. The normally-on modulation switch Q DRV is in its conducting state, but there is no initial current because V DRV = 0V. As the drive voltage V DRV increases, the drive current I PD begins to flow through the pull-down switch Q SS to charge the effective capacitance of the voltage clamp 132 (diode). The pull-down resistor R SS presents a higher impedance path than the charging of the voltage clamp 132, such that a minimal current flows through the pull-down resistor R Figure 4A The resulting current path 480 during this period while the pull-down switch Q PD is conducting is shown in MOD When the forward threshold voltage of the voltage clamp 132 has not yet been reached, the voltage drop established across the voltage clamp 132 produces a small current 480a that begins to absorb charge from the gate capacitance C MOD of the modulation switch Q GS_MOD via the modulation resistor R

[0040] The current 480 shown causes the voltage drop across the voltage clamp 132 to rise, which in turn generates a negative voltage V PD at the gate of the pull-down switch Q PD_GS . (In the case where the modulation switch Q MOD is in its fully-on conducting state, the voltage clamp 132 and the pull-down gate-to-source junction have substantially the same voltage across them.) Once the pull-down gate-to-source voltage becomes sufficiently negative, e.g., V PD_GS < -7V, then the pull-down switch Q PD turns off, blocking the low-impedance path between the gate and source of the power switch Q1. Then, the driver current I DRV flows to the gate (G) of the power switch Q1, as shown by the current path 481 in Figure 4B .

[0041] Once the drive voltage V DRVReach the conduction level (e.g., 13V) corresponding to the clamping voltage V of the power switch Q1 CL (e.g., 10V) and the turn-on threshold voltage (e.g., 3V), then the voltage clamp 132 is forward-biased. Current flows into the gate (G) of the power switch Q1, and the power switch Q1 starts to conduct. This is shown at time t1 in Figure 3 and in the current loop 481 shown in Figure 4B . The modulation switch Q MOD is still conducting. A low-impedance path is provided between the source (S) of the power switch Q1 and the reference control terminal 104 via the modulation switch Q MOD and the voltage clamp 132. The resistance of the resistance modulation circuit 130 is negligible at time t1, and the charging current I DRV supplied to the gate (G) of the power switch Q1 is mainly limited by the driving ability of the driver 160. Different from the existing solutions, there is no current-limiting resistor (component) that undesirably throttles the charging current or an RC network that consumes energy and space.

[0042] Before time t0, the gate-to-source voltage V MOD of the modulation switch Q GS_MOD is approximately 0V. After time t0, this voltage V GS_MOD starts to increase in magnitude, but has a negative polarity because current is drawn from the gate of the modulation switch Q MOD via path 480a. By time t1, the voltage across the voltage clamp 132 has reached its threshold and is clamped at its threshold, e.g., 10V. This increases the magnitude of the current (and the associated charge depletion rate) drawn from the gate of the modulation switch Q MOD via the current path 481a through the modulation resistor R MOD . The gate voltage V GS_MOD becomes more negative due to the charge drawn from the gate of the modulation switch. Once this voltage V GS_MOD decays to a level below the turn-off threshold (e.g., -7V) of the modulation switch Q MOD , the modulation switch Q MOD will turn off. The time interval between when the driver 160 initially starts to ramp the drive voltage V MOD * C GS_MOD and when the modulation switch Q MOD turns off is determined by the time constant R DRV and the turn-off threshold of the modulation switch Q MOD , e.g., t0 to t1 in Figure 2 . In a typical example, the gate capacitor C GS_MOD can have a capacitance of approximately 10 pF, while the modulation resistor R MOD can have a resistance of approximately 2 kiloohms. The modulation resistor RMOD The large resistance of MOD will keep the modulation switch Q MOD in its conducting state for a longer time, thus extending the duration of the high current level provided to the power switch Q1. The modulation resistor R GS_MOD with a smaller resistance will reduce the gate voltage V MOD faster and turn off the modulation switch Q

[0043] At Figure 3 time t2, the modulation switch Q MOD turns off (non-conducting), blocking the low impedance path through the modulation switch Q MOD . Instead, current flows through a higher impedance path including the bypass and the steady-state resistors R BYP and R SS , as shown by the current path 482 of Figure 4C . The resulting impedance seen across the control and control reference terminals 102, 104 is significantly higher than the impedance when the modulation switch Q MOD is conducting. This results in a relatively low level of drive current I Figure 3 between times t2 and t3 of DRV compared to the approximately 1 A peak current provided when transitioning the power switch Q1 to its on state, e.g., approximately 8 mA. The low current level is determined by the applied drive voltage V DRV , the threshold voltage V Q1_THR of the power switch Q1, the clamping voltage V CL , and the resistors R BYP , R SS . The resistor R BYP and / or R SS can be adjusted to program the current level for maintaining the on state of the power switch Q1, but it should be noted that the resistor R SS usually has the greatest impact on the level of the holding current.

[0044] Figure 4D shows the current corresponding to Figure 3 time t3 in DRV , which occurs shortly after the drive voltage V DRV begins to ramp down. More specifically, time t3 is within the interval when the drive voltage V CL is below the device conduction threshold required to forward bias the voltage clamp 132 and maintain the power switch Q1 in its on state (e.g., conduction threshold is V PD_Q1 +V DRV =10 V + 3 V), but before the drive voltage V PD drops to the level at which the pull-down switch Q Figure 4DAs shown, current 483a flows from the anode of the voltage clamp (diode) 132 via resistor R BYP 、R SS to its cathode. This discharges the effective capacitance of the voltage clamp 132 and drives the voltage across the voltage clamp 132 towards zero.

[0045] This clamped voltage is in parallel with the modulation resistor R MOD and the modulation switch gate capacitance C GS_MOD . When the clamped voltage decreases, current 483c flows through R MOD in order to equalize the (negative) voltage V MOD across the gate-source junction of the modulation switch Q GS_MOD . The magnitude of the negative gate charge of the modulation switch Q MOD decreases due to this current 483c.

[0046] Similarly, when the clamped voltage discharges towards zero, the charge across the gate-to-source junction of the pull-down switch Q PD is equalized via current 483b from the pull-down source via resistor R SS to the pull-down gate. For example, there may be a pull-down gate-to-source voltage V PD of -10V between times t1 and t3 in order to keep the pull-down switch Q PD_GS in its blocking state that rises towards 0V at least in part due to current 483b after time t3. Once the pull-down gate-to-source voltage V PD_GS rises to a value higher than the on / off threshold V PD_THR , e.g., V PD_GS >V PD_THR (-7V), then the pull-down switch Q PD conducts, thereby shorting the gate of the power switch Q1 to its source. Figure 4E Shows the resulting current corresponding to Figure 3 time t4 as shown.

[0047] As the pull-down switch Q PD conducts, current flows from the gate of the power switch Q1 via the shown current path 484a to the source, thereby discharging the gate charge of the power switch Q1 in order to turn off the power switch Q1. Additionally, any residual charge on the modulation switch capacitor C GS_MOD is equalized via current path 484b, which flows through the bypass resistor R BYP , the pull-down switch Q PD , the driver 160, and the modulation resistor R MOD . This is shown as a negative driver current I Figure 3 between times t3 and t4 in DRV . At time t4 or shortly thereafter, across the switch capacitor C GS_MODThe charges at both ends are substantially balanced, such that the modulation switch Q MOD has an approximately zero gate-to-source voltage V GS_MOD , thereby setting the modulation switch Q MOD to its conducting state to prepare for the next turn-on transition of the power switch Q1.

[0048] Figure 5 Shows voltage and current waveforms corresponding to the simulation of the turn-on interval of the power switch device 100 of Figure 1 . The voltage waveform 510 corresponds to the voltage V GG applied across the control and control reference terminals 102, 104, while the current waveform 520 corresponds to the current I G flowing into the control terminal 102 (the gate of the power switch Q1). The voltage waveform 530 corresponds to the gate-to-source voltage V Q1_GS of the power switch Q1. At time t = 0, the voltage V GG ramps from 0 V to its turn-on value of 15 V, thereby generating a high-current pulse for the gate current I G . The gate current I G rapidly rises to approximately 800 mA, as shown at time t1. At approximately time t1, the gate voltage V Q1_GS of the power switch Q1 rises above its threshold, for example 3 V, and the power switch Q1 turns on. As the power switch Q1 thus turns on, the high current can then be reduced during the steady-state (holding) interval of the turn-on period. This is shown in the gate current I G , where the gate current I G decays from its peak of 800 mA at time t1 to approximately 10 mA at time t2. The holding current level is maintained until time t3, at which point the control voltage V GG is driven to zero and the power switch Q1 turns off.

[0049] Power switching device system with an external driver

[0050] Figure 6 Shows a switching device system including a power switch device 600 and an external driver 610. The driver 610 does not need to include multiple channels to provide different current drive levels or to provide multiple voltage levels (e.g., negative voltages as provided by existing GIT drivers). Thus, the driver 610 can be a single-channel driver that provides two voltage levels (e.g., 0 and 15 V), which is similar or identical to drivers used with, for example, conventional MOSFETs.

[0051] As shown, the power switch device 600 is a 6-terminal device implemented in a GaN die. The circuit of the power switch device 600 is the same as that of Figure 1 circuit 100, but the modulation and steady-state resistors RMOD , R SS is disposed outside the power switching device 600. This allows for easy adjustment of the duration of the high-current conduction pulse by changing the modulation resistor R MOD without having to change the GaN die. Similarly, the steady-state (holding) current supplied to the power transistor Q1 can be easily adjusted by changing the resistor R SS also without changing the GaN die. As shown by the dashed box 630, the resistor modulation circuit has the same topology as the corresponding circuit 130 of Figure 1 , but with different component partitioning in Figure 6 . The power switch Q1, pull-down switch Q PD , modulation switch Q MOD , voltage clamp 132, and bypass resistor R BYP can be monolithically integrated in the same GaN die.

[0052] Different from the power switching device 100 of Figure 1 , the power switching device 600 is provided with a modulation terminal 605 (GMOD), which is configured to cause the modulation resistor R coupled between the modulation terminal 605 and the pull-down gate terminal 104 (GPD) MOD to determine the duration of the high-current conduction transition pulse, as described above. Additionally, the power switching device 600 is provided with a Kelvin source terminal 607 (KS), which is configured such that the steady-state current setting resistor R coupled between the KS terminal 607 and the pull-down gate terminal 104 (GPD) SS determines the level of the steady-state current used to hold the power switch Q1 in its conducting state. The KS terminal 607 is typically different from the source terminal 108 in that the KS terminal 607 is not configured to handle high load currents. In some applications, the KS terminal 607 can be removed, and the source load terminal 108 can be used to connect to the steady-state resistor R SS , such that the resulting power switching device is a 5-terminal device.

[0053] The driver 610 inputs a digital waveform, such as a pulse-width modulation (PWM) signal D_SIG. The signal D_SIG can alternate between TTL (transistor-transistor logic) or CMOS (complementary MOSFET) levels, such as between 0 and 3.3 V, between 0 and 5 V, etc. As shown, the driver 610 is powered by the supply Vcc or has a bootstrap configuration such that the power switching device 600 can be the high-side switch of a half-bridge or similar circuit. During the period when the source terminal 108 is grounded, the power supply capacitor C SUP is charged from Vcc. The blocking diode D SUP is required to block the 10 V clamped voltage; if the negative terminal of the power supply capacitor C SUP is directly coupled to the source load terminal 108, then from the power supply capacitor CSUP The current will flow through the pull - down switch Q PD and bypass the resistance modulation circuit 630.

[0054] Power switching device with an integrated driver

[0055] Figure 7 A power switch device 700 including an integrated driver is shown. Figure 7 The system of... is similar to Figure 6 the system of..., except that the external driver 610 is removed. The power switch device 700 also includes a control terminal 712 (GSIG) which is used to input a digital control signal D_SIG, such as a PWM signal having a digital level relative to the reference (SIG_REF) terminal 709. The power switch device 700 includes a signal switch Q SIG which has a gate (control terminal) coupled to the input control terminal 712. As shown, the signal switch Q SIG is a normally - off GIT, and so is the power switch Q1. Although the signal switch Q SIG is integrated in the same GaN die as the power switch Q1 etc., the signal switch Q SIG can be significantly smaller than the power switch Q1 because the signal switch Q SIG does not need to support the high load current levels flowing through the power switch Q1. For example, the signal switch Q SIG can have fewer channels (fingers) and / or a reduced channel thickness relative to the power switch Q1. (Similarly, the normally - on pull - down switch Q PD and the normally - on modulation switch Q MOD can be sized to support a smaller current than the power switch Q1.)

[0056] Blocking diode D SUP serves almost the same purpose as Figure 6 but is integrated within the GaN die of the power switch device 700. For example, as previously described, the blocking diode D SUP can be a GaN - based gate - controlled diode or a GaN - based PN diode.

[0057] The power supply Vcc is coupled to the gate terminal 102 and, together with the power supply capacitor C SUP provides a power supply voltage between the gate terminal 102 and the signal / power reference terminal 709 (SIG_REF). As previously and similarly explained, applying a conduction voltage between the control terminal 102 and the control reference terminal 104 can turn on the power switch Q1. (The conduction voltage is higher than the sum of the threshold voltage of the power switch Q1 and the forward - bias voltage of the voltage clamp 132. For a 3V threshold voltage and a 10V forward - bias threshold, as previously described, 15V of Vcc is sufficient.) For Figure 7The power switch device 700 uses the signal switch Q SIG The node corresponding to the control reference terminal 104 is switchably connected to the signal / power reference terminal 709. When the signal switch Q SIG is turned on, the voltage Vcc is effectively applied across the control terminal 102 and the control reference terminal 104 via the signal switch Q SIG and the signal / power reference terminal 709 (SIG_REF) to turn on the power switch Q1. When the signal switch Q SIG is turned off, no voltage is applied across the control terminal 102 and the control reference terminal 104, and the normally-off pull-down switch Q PD short-circuits the gate and source of the power switch Q1, and the power switch Q1 remains in its off state.

[0058] In summary, a positive voltage of D_SIG higher than the conduction threshold of the signal switch Q SIG causes the power switch Q1 to turn on. Otherwise, the power switch Q1 is turned off. The typical conduction / turn-off threshold for the GIT (such as the signal switch Q SIG ) is 1.2 to 3.5V. Therefore, applying a typical TTL or CMOS level (such as 0V and 3.3 to 5V) between the signal terminal 712 (G SIG ) and the signal / power reference terminal 709 (SIG_REF) can be used to control the power switch device 700.

[0059] Although TTL and CMOS levels can provide sufficient voltage to drive the power switch device 700, typical TTL and CMOS digital outputs may not provide sufficient current to transition the signal switch Q SIG to its conducting state within an acceptable time interval. Applications that require relatively fast turn-on and turn-off of the power switch device may require a more complex driver than the simple signal switch Q Figure 7 in SIG for the power switch device.

[0060] Figure 8 The power switch device 800 is shown, which provides additional drive current so that the signal switch Q SIG can transition to the on state faster. The power supply Vcc is used to provide this drive current for turning on the signal switch Q SIG , rather than relying on the digital input signal D_SIG.

[0061] The power switch device 800 is similar to the power switch device in Figure 7 , but includes a more complex driver 810. In addition to the signal switch Q SIG , the driver 810 includes an amplifier circuit that has a drive switch Q DRV and includes resistors R D1 , RD2 The resistive voltage divider. The power switch device 800 has differential input terminals 811, 812 for inputting differential signals D_SIG, D_SIG_REF. A positive control voltage above the conduction threshold of the driver switch Q DRV and applied between the signals D_SIG, D_SIG_REF causes the driver switch Q DRV to conduct. The resistors R D1 , R D2 are configured such that the resulting voltage across the gate-source junction of the signal switch Q SIG is sufficient to turn on the signal switch. For example, in the case of a supply voltage Vcc = 15V, the resistors R D1 , R D2 can be selected to provide a voltage division by 3 such that when the driver switch Q DRV conducts, 5V drives across the gate and source of the signal switch Q SIG . The current from the power supply Vcc charges the gate of the signal switch Q D1 via the resistor R DRV and the driver switch Q SIG so as to turn on the signal switch Q SIG . This in turn turns on the power switch Q1 in the same manner as described above. When the differential control voltage of the input signals D_SIG, D_SIG_REF is below the on / off threshold of the driver switch Q DRV (for example, the differential voltage is 0V), the driver switch Q DRV turns off, thereby isolating the gate of the signal switch Q SIG from the power supply Vcc. The accumulated charge on the gate of the signal switch Q SIG discharges via the resistor R D2 , and the signal switch Q SIG turns off. This in turn causes the power switch Q1 to transition to the off state in the same manner as described above.

[0062] Although two specific examples have been described for providing a driver integrated in a GaN die including the power switch Q1, it should be recognized that many other driver circuit topologies are possible. In one variant of the driver 810, a pull-down switch can be coupled in parallel to the resistor R D2 , and is used to provide a low-impedance path for discharging the gate of the signal switch Q SIG . As another example, the amplifier of the driver 810 can be replaced with a half-bridge (push-pull) driver, which is used to drive the signal switch Q SIG .

[0063] Although the present disclosure is not limited thereto, the following numbered examples illustrate one or more aspects of the present disclosure.

[0064] Example 1: A power switching device includes a normally-off power transistor, a control terminal, a control reference terminal, a normally-on pull-down transistor, and a resistance modulation circuit. The normally-off power transistor has a gate, a source, and a drain, and the control terminal is connected to the gate. The pull-down transistor is configured to short the gate to the source when no voltage is applied between the control terminal and the control reference terminal, and has a pull-down gate, a pull-down source, and a pull-down drain. The resistance modulation circuit is coupled between the source and the control reference terminal and includes a modulation transistor. The circuit is configured to modulate the resistance between the control terminal and the control reference terminal such that, in response to applying a device conduction voltage between the control terminal and the control reference terminal, a charging current is provided to the gate during a predetermined charging interval and a holding current is provided to the gate after the predetermined charging interval. The holding current has a level lower than the level of the charging current.

[0065] Example 2: The power switching device of Example 1, wherein the resistance modulation circuit is further configured to apply a negative voltage to the pull-down gate autonomously with respect to the pull-down source in response to the application of the device conduction voltage in order to turn off the normally-on pull-down transistor. The resistance modulation circuit can also be configured to discharge the negative voltage autonomously when no device conduction voltage is applied between the control terminal and the control reference terminal.

[0066] Example 3: The power switching device of Example 1, wherein the resistance modulation circuit includes a bypass resistor and a voltage clamping diode. The bypass resistor is connected in parallel with the modulation transistor. The modulation transistor and the voltage clamping diode are connected in series between the pull-down source and the pull-down gate and provide a low-impedance current path therebetween when the modulation transistor conducts.

[0067] Example 4: The power switching device of Example 3, wherein the modulation transistor has a modulation gate-to-source capacitance between the modulation gate and the modulation source. The predetermined charging interval is based on the modulation gate-to-source capacitance and a modulation resistor coupled to the modulation gate.

[0068] Example 5: The power switching device of Example 4, wherein the level of the holding current is based on the resistance of a steady-state resistor coupled between the pull-down gate and the pull-down source.

[0069] Example 6: The power switching device of Example 5, further including a first resistor terminal and a second resistor terminal. The first resistor terminal is electrically connected to the modulation gate and is configured for connection to the modulation resistor. The second resistor terminal is connected to the pull-down source and is configured for connection to the steady-state resistor. The modulation resistor and the steady-state resistor are external to the power switching device.

[0070] Example 7: The power switching device of Example 1, wherein the normally-off power transistor is a gate injection transistor (GIT), the normally-on pull-down transistor is a high electron mobility transistor (HEMT), and the modulation transistor is an HEMT. The normally-off power transistor, the normally-on pull-down transistor, and the modulation transistor are monolithically integrated on the same die.

[0071] Example 8: The power switching device of Example 7, wherein the die is a gallium nitride (GaN) die.

[0072] Example 9: The power switching device of Example 7, further comprising a bypass resistor and a voltage clamping diode. The bypass resistor is connected in parallel with the modulation transistor. The voltage clamping diode is connected in series to the modulation transistor such that the serially-connected voltage clamping diode and modulation transistor are coupled between the pull-down source and the pull-down gate. The bypass resistor and the voltage clamping diode are monolithically integrated with the normally-off power transistor, the normally-on pull-down transistor, and the modulation transistor on the same die.

[0073] Example 10: The power switching device of Example 9, further comprising a steady-state resistor and a modulation resistor. The steady-state resistor is coupled between the pull-down gate and the pull-down source. The modulation resistor is coupled between the pull-down gate and the gate of the modulation transistor. The steady-state resistor and the modulation resistor are monolithically integrated with the normally-off power transistor, the normally-on pull-down transistor, and the modulation transistor on the same die.

[0074] Example 11: The power switching device of Example 10, wherein the die is a gallium nitride (GaN) die, and each of the bypass resistor, the steady-state resistor, and the modulation resistor is formed by a two-dimensional electron gas (2DEG) region of the GaN die. The voltage clamping diode includes one or more GaN-based diodes, and the one or more GaN-based diodes include at least one of a gated diode and a PN diode. The gated diode can be constructed by coupling the source and the gate of the GIT to form an anode, and the drain of the GIT forms the cathode. The PN diode can be constructed by coupling the source and the drain of the GIT to form a cathode, and the gate of the GIT forms the anode.

[0075] Example 12: The power switching device of Example 1, wherein the device turn-on voltage is a positive voltage equal to or exceeding the sum of the turn-on threshold voltage of the normally-off power transistor and the turn-off threshold voltage of the normally-on pull-down transistor.

[0076] Example 13: A power switching device system including the power switching device of Example 1, wherein the system further includes a single-channel external driver powered by a driver power supply. The driver includes an input terminal for inputting a digital control signal and an output terminal for outputting an output voltage. The output terminal is connected to the control terminal of the power switching device, and the output voltage alternates between two levels based on the digital control signal.

[0077] Example 14: A power switch device with an integrated driver, comprising a normally-off power transistor, first and second load terminals, a power supply and a power supply reference terminal, a control terminal, a normally-on pull-down transistor, an integrated driver, and a resistance modulation circuit. The normally-on power transistor includes a drain connected to the first load terminal, a source connected to the second load terminal, and a gate. The power supply and the power supply reference terminal are configured to be connected to an external power supply. The control terminal is configured to input a digital control signal for controlling the conduction between the first load terminal and the second load terminal. The normally-on pull-down transistor has a pull-down gate, a pull-down source, and a pull-down drain, and is configured to short-circuit the gate and the source of the power transistor when the digital control signal does not command the conduction of the power switch device. The integrated driver circuit is configured to source current to and / or sink current from the pull-down gate based on the digital control signal to control the current conduction of the normally-on pull-down transistor. The resistance modulation circuit is coupled between the source and the power supply reference terminal and includes a modulation transistor. The circuit is configured to modulate the resistance between the power supply terminal and the power supply reference terminal such that a charging current is provided to the gate during a predetermined charging interval in response to the digital control signal transitioning to command conduction, and a holding current is provided to the gate after the predetermined charging interval. The holding current has a level lower than the level of the charging current.

[0078] Example 15: The power switch device with an integrated driver of Example 14, wherein the integrated driver circuit includes a driver switch that switchably couples the pull-down gate to the power supply reference terminal, and wherein the coupling between the source and the power supply reference terminal is via the driver switch.

[0079] Example 16: The power switch device with an integrated driver of Example 14, wherein the normally-off power transistor, the normally-on pull-down transistor, the integrated driver, and the modulation transistor are monolithically integrated on the same die.

[0080] Example 17: The power switch device with an integrated driver of Example 16, wherein the same die is a gallium nitride (GaN) die, wherein the normally-off power transistor is a gate injection transistor (GIT), wherein the normally-on pull-down transistor is a high electron mobility transistor (HEMT), wherein the modulation transistor is an HEMT, and wherein the integrated driver includes at least one GIT and / or HEMT.

[0081] Example 18: The power switch device with an integrated driver of Example 16, wherein the integrated driver circuit includes a GIT configured to short the pull-down gate to the power supply reference terminal.

[0082] Example 19: The power switch device with an integrated driver of Example 16 further includes a first resistor terminal and a second resistor terminal. The first resistor terminal is connected to the gate of the modulation transistor and is configured to be connected to an external modulation resistor having a modulation resistance, wherein a predetermined charging interval is based on the modulation resistance and the gate-to-source capacitance of the modulation transistor. The second resistor terminal is connected to the pull-down source and is configured to be connected to a steady-state resistor having a steady-state resistance, wherein the level of the holding current is based on the steady-state resistance.

[0083] As used herein, the terms "having", "containing", "including", "comprising", etc. are open-ended terms that indicate the presence of the stated element or feature, but do not exclude additional elements or features. The articles "a", "an", and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0084] It should be understood that, unless otherwise specifically stated, the features of the various embodiments described herein may be combined with each other.

[0085] Although specific embodiments have been shown and described herein, those of ordinary skill in the art should understand that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Accordingly, the present invention is intended to be defined only by the claims and their equivalents.

Claims

1. A power switch device, comprising: A normally-off power transistor, including a gate, a source, and a drain; A control terminal electrically connected to the gate; A control reference terminal; A normally-on pull-down transistor configured to short the gate to the source when no voltage is applied across the control terminal and the control reference terminal, and including a pull-down gate, a pull-down source, and a pull-down drain; And A resistance modulation circuit including a modulation transistor and coupled between the source and the control reference terminal, and configured to: Modulate the resistance between the control terminal and the control reference terminal such that in response to applying a device conduction voltage between the control terminal and the control reference terminal, a charging current is provided to the gate during a predetermined charging interval, and a holding current is provided to the gate after the predetermined charging interval, wherein the holding current has a positive level lower than the level of the charging current, Wherein the resistance modulation circuit includes: A bypass resistor connected in parallel with the modulation transistor; and A voltage clamping diode, Wherein the modulation transistor and the voltage clamping diode are connected in series between the pull-down source and the pull-down gate.

2. The power switch device according to claim 1, wherein, The resistance modulation circuit is further configured to: Apply a negative voltage to the pull-down gate autonomously with respect to the pull-down source in response to the application of the device conduction voltage to turn off the normally-on pull-down transistor; And Discharge the negative voltage autonomously when no device conduction voltage is applied between the control terminal and the control reference terminal.

3. The power switch device according to claim 1, wherein, The modulation transistor has a modulation gate-to-source capacitance between a modulation gate and a modulation source, and wherein the predetermined charging interval is based on the modulation gate-to-source capacitance and a modulation resistor coupled to the modulation gate.

4. The power switch device according to claim 3, wherein, The level of the holding current is based on the resistance of a steady-state resistor coupled between the pull-down gate and the pull-down source.

5. The power switch device according to claim 4, further comprising: A first resistor terminal electrically connected to the modulation gate and configured for connection to the modulation resistor, wherein the modulation resistor is external to the power switching device; and A second resistor terminal connected to the pull-down source and configured for connection to the steady-state resistor, wherein the steady-state resistor is external to the power switching device.

6. The power switch device according to claim 1, wherein, The normally-off power transistor is a gate injection transistor (GIT), Wherein the normally-on pull-down transistor is a high electron mobility transistor (HEMT), Wherein the modulation transistor is an HEMT, and Wherein the normally-off power transistor, the normally-on pull-down transistor, and the modulation transistor are monolithically integrated in the same die.

7. The power switch device according to claim 6, wherein, The same die is a gallium nitride (GaN) die.

8. The power switch device according to claim 6, further comprising: A bypass resistor connected in parallel with the modulation transistor; And A voltage clamping diode connected in series to the modulation transistor such that the series-connected voltage clamping diode and modulation transistor are coupled between the pull-down source and the pull-down gate, Wherein the bypass resistor and the voltage clamping diode are monolithically integrated with the normally-off power transistor, the normally-on pull-down transistor, and the modulation transistor in the same die.

9. The power switch device according to claim 8, further comprising: A steady-state resistor coupled between the pull-down gate and the pull-down source; and A modulation resistor coupled between the pull-down gate and the gate of the modulation transistor, wherein the steady-state resistor and the modulation resistor are monolithically integrated with the normally-off power transistor, the normally-on pull-down transistor, and the modulation transistor in the same die.

10. The power switch device according to claim 9, wherein, The same die is a gallium nitride (GaN) die, wherein each of the bypass resistor, the steady-state resistor, and the modulation resistor is included within the GaN die, wherein the voltage clamping diode includes one or more GaN-based resistors, one or more GaN-based capacitors, and one or more GaN-based diodes, and the one or more GaN-based diodes include at least one of the following: A gate-controlled diode, in which the source and gate of a normally-off GaN HEMT are coupled to one or more PN diodes to form an anode, and the drain of the GaN HEMT forms a cathode, and A PN diode, in which the source and drain of a normally-off GaN HEMT are coupled together to form a cathode, and the gate of the GaN HEMT forms an anode.

11. The power switch device according to claim 1, wherein, The device conduction voltage is a positive voltage equal to or exceeding the sum of the conduction threshold voltage of the normally-off power transistor and the turn-off threshold voltage of the normally-on pull-down transistor.

12. A power switch device system, comprising: The power switch device according to claim 1; and A single-channel external driver powered by a driver power supply and including: An input terminal for inputting a digital control signal; and An output terminal for outputting an output voltage, wherein the output terminal is connected to the control terminal of the power switch device, and wherein the output voltage alternates between two levels based on the digital control signal.

13. A power switch device with an integrated driver, comprising: A normally-off power transistor including a gate, a source, and a drain; A first load terminal electrically connected to the drain; A second load terminal electrically connected to the source; A power supply terminal and a power supply reference terminal for connecting to a power supply; A control terminal configured to input a digital control signal that controls conduction between the first load terminal and the second load terminal; A normally-on pull-down transistor including a pull-down gate, a pull-down source, and a pull-down drain, and configured to short the gate to the source when the digital control signal does not command conduction of the power switch device; An integrated driver circuit configured to control conduction of the normally-on pull-down transistor based on the digital control signal; and A resistance modulation circuit including a modulation transistor and coupled between the source and the power supply reference terminal, and configured to: Modulate the resistance between the power supply terminal and the power supply reference terminal such that in response to the digital control signal transitioning to command conduction, a charging current is provided to the gate during a predetermined charging interval, and a holding current is provided to the gate after the predetermined charging interval, wherein the holding current has a positive level lower than the level of the charging current. Among them, the integrated driver circuit includes a driver switch, the driver switch switchably couples the pull-down gate to the power reference terminal, and among them, the coupling between the source and the power reference terminal is via the driver switch.

14. The power switch device with an integrated driver according to claim 13, wherein, The normally-off power transistor, the normally-on pull-down transistor, the integrated driver, and the modulation transistor are monolithically integrated in the same die.

15. The power switch device with an integrated driver according to claim 14, wherein, The same die is a gallium nitride (GaN) die. Among them, the normally-off power transistor is a gate injection transistor (GIT). Among them, the normally-on pull-down transistor is a high electron mobility transistor (HEMT). Among them, the modulation transistor is an HEMT, and Among them, the integrated driver includes at least one GIT and / or HEMT.

16. The power switch device with an integrated driver according to claim 14, wherein, The integrated driver circuit includes a GIT, and the GIT is configured to short the pull-down gate to the power reference terminal.

17. The power switch device with an integrated driver according to claim 14, further comprising: A first resistor terminal, connected to the gate of the modulation transistor and configured to be connected to an external modulation resistor having a modulation resistance, wherein the predetermined charging interval is based on the modulation resistance; and A second resistor terminal, connected to the pull-down source and configured to be connected to a steady-state resistor having a steady-state resistance, wherein the level of the holding current is based on the steady-state resistance.

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