Millimeter wave radar SOC circuit board design method, circuit and circuit board structure

Abstract

This application proposes a millimeter-wave radar SOC circuit board design method, circuit, and circuit board structure. The method includes designing a circuit structure in which an LC filter circuit, an LDO, an output capacitor combination module, a load capacitor combination module, and the SOC's RF power supply terminal are connected in sequence; selecting a high PSRR LDO to power the SOC's RF power supply terminal; setting up a multi-layer circuit board, with LDOs and SOCs set on different layers; setting a Faraday cage around the RF section of the SOC; setting the load capacitor combination module and the SOC on the same layer; setting multiple ground terminals for the load capacitor combination module, ensuring that each ground terminal is independent on the surface layer and connected through the inner layer ground; classifying the circuit board's ground terminals into signal ground and RF ground, with the connection between signal ground and RF ground only through vias on the inner layer, and the vias being positioned as far away as possible from the return path of power interference signals.

Description

Technical Field

[0001] The present application relates to the technical field of millimeter wave radar SOC solutions, and in particular to a millimeter wave radar SOC circuit board design method, circuit and circuit board structure. Background Art

[0002] System noise refers to the total noise in the system except for the useful signal. Excessive system noise will reduce the signal-to-noise ratio and dynamic range of the radar target, and easily cause the millimeter-wave radar to miss reports, which will not help the driver detect potential collision risks well, so as to reduce the occurrence of traffic accidents, vehicle collisions and other problems.

[0003] Currently, the mainstream 77GHz millimeter-wave radar SOC solutions on the market are from TI and Calterah. This solution integrates MMIC (monolithic microwave integrated circuit), DSP (digital signal processing) and CPU (central processing unit) functional modules on one chip, greatly reducing the hardware development difficulty for millimeter-wave radar manufacturers.

[0004] This integrated SOC design inevitably brings a series of problems. For example, the integration of RF, analog, mixed signal and digital circuits on the SOC is prone to signal crosstalk, which increases the system noise; the chip generates a lot of heat, the RF performance is attenuated, and long-distance targets and small targets are easily masked by system noise, resulting in missed reports; different internal functional modules share an input power supply, which causes the power supply network ripple noise to deteriorate and increase the overall system noise; when designing the SOC periphery, the power supply noise crosstalk between different input power supplies is also likely to cause the system noise to increase, and even a certain noise frequency suddenly increases, causing false alarms; the unreasonable processing and segmentation of the peripheral signal ground and the RF ground is also likely to introduce other interference into the system, raising the system noise. Since the millimeter-wave radar system is sensitive to system noise, this parameter will directly affect the detection capability of the millimeter-wave radar. For example, when detecting small targets, due to their small RCS values, they are easily masked by system noise, resulting in missed reports. Therefore, how to effectively control the size of the system noise has become a practical problem that millimeter-wave radar developers urgently need to solve;

[0005] At present, the methods to reduce system noise are mainly improved from the hardware, and the methods are as follows:

[0006] 1. Use LDO to power the RF module circuit, and add capacitors at the input and output ends of the LDO to suppress the impact of input high-frequency noise on the RF part of the SOC.

[0007] Second, spatially isolate the power supply part and SOC, for example, place them on two different boards, and the two circuit boards are only connected through a socket. The advantage of this is that the power supply and SOC, which generate relatively large amounts of heat, are separated into two boards, which can reduce the concentration of heat-generating components, and is beneficial for the SOC to dissipate heat through the board itself, thereby reducing the attenuation of RF performance caused by temperature rise, and also reducing the impact of power supply noise on the RF part.

[0008] 3. The circuit board adopts a multi-layer design, with six layers or more, to provide a complete ground for the RF part, digital and analog parts. Through a single-point connection, the interference noise is controlled in a certain area without affecting each other.

[0009] The above methods can all play a role in reducing system noise to a certain extent. However, there are also problems in actual design and use. The method of adding LDO and capacitors at the input and output ends in method one, although it suppresses the impact of high-frequency noise of the input power supply on the SOC, the high-frequency noise and voltage fluctuations caused by the PA (power amplifier) ​​module in the SOC are in a fast switching state during operation, which can easily be reversely connected to other power supplies in the system, causing the quality of other power supplies to deteriorate. Although the spatial isolation in method two is effective, the design of two circuit boards increases the hardware cost to a certain extent, and also causes the product size to become taller, which is not conducive to assembly on the actual vehicle. The multi-layer board design idea and ground segmentation connection in method three often have little effect due to inadequate ground segmentation processing. Summary of the invention

[0010] The present application provides a millimeter wave radar SOC circuit board design method, circuit and circuit board structure to reduce radar SOC system noise.

[0011] In a first aspect, the present application provides a millimeter wave radar SOC circuit board design method, comprising:

[0012] Design a circuit structure, the circuit structure includes an LC filter circuit, an LDO, an output end capacitor combination module, a load end capacitor combination module and a radio frequency power supply end of the SOC which are electrically connected in sequence;

[0013] Selecting an LDO to power the SOC radio frequency power supply terminal, wherein the LDO is a high PSRR LDO, and the high PSRR LDO has a PSRR value of ≥25dB ​​under a condition of 1MHz;

[0014] A multi-layer circuit board is provided, and LDO and SOC are respectively provided on different board layers, and the power supply lines of the LDO and SOC are ensured to have a short spacing;

[0015] Provide a Faraday cage around the radio frequency portion of the SOC;

[0016] The load-end capacitor combination module and the SOC are respectively arranged on the same board layer so that the load-end capacitor combination and the SOC are close to each other;

[0017] Set multiple grounding terminals for the SOC and load capacitor combination modules respectively, ensure that each grounding terminal is independent of each other on the surface layer, and each grounding terminal is connected through the inner layer ground;

[0018] The grounding terminal of the circuit board is classified into signal ground and radio frequency ground, and the radio frequency ground and the signal ground are isolated from each other; the signal ground and the radio frequency ground are connected in the inner layer through vias, and the position of the vias is as far away as possible from the return path of the power interference signal.

[0019] In the second aspect, the present application also provides a circuit, comprising an LC filter circuit, an LDO, an output capacitor combination module, a load capacitor combination module and a SOC RF power supply end electrically connected in sequence; the LDO is a high PSRR LDO; wherein the high PSRR LDO is a LDO with a PSRR value ≥ 25dB under the condition of 1MHz.

[0020] On the third aspect, the present application also provides a circuit board structure, which adopts the above-mentioned millimeter wave radar SOC circuit board design method layout; it includes at least three layers, one of which is used to place the SOC, the layer below the SOC layer is a complete ground layer, and the LDO is placed on another layer; the circuit board structure is provided with an LC filter circuit, an LDO, an output end capacitor combination module, a load end capacitor combination module and a SOC RF power supply end which are electrically connected in sequence.

[0021] The present application discloses a millimeter-wave radar SOC circuit board design method, circuit and circuit board structure. The method adopts a high-PSRR LDO and filtering solution, which can effectively suppress the influence of external input high-frequency noise on the SOC radio frequency part, and suppress the voltage disturbance and high-frequency noise caused by the intermittent operation of the PA module in the SOC at the load end, thereby reducing the overall system noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 is a schematic flow chart of a millimeter wave radar SOC circuit board design method provided by an embodiment of the present application;

[0024] Figure 2is a schematic block diagram of a circuit provided by an embodiment of the present application;

[0025] Figure 3 It is a structural schematic diagram of the SOC signal ground and radio frequency ground positions of a circuit board structure provided in an embodiment of the present application;

[0026] Figure 4 It is a schematic diagram of a Faraday cage structure of a SOC layer of a circuit board structure provided by an embodiment of the present application;

[0027] Figure 5 It is a partial structural schematic diagram of a SOC layer of a circuit board structure provided by an embodiment of the present application;

[0028] Figure 6 A schematic diagram of a partial structure of a SOC lower layer of a circuit board structure provided in an embodiment of the present application;

[0029] Figure 7 An embodiment of the present application provides a schematic diagram of a partial structure of an inner layer of a circuit board structure. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0032] The embodiments of the present application provide a millimeter wave radar SOC circuit board design method, circuit and circuit board structure. The millimeter wave radar SOC circuit board design method can be applied to a circuit board to improve the system noise of the millimeter wave radar SOC solution.

[0033] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0034] See also Figure 1 , Figure 1 1 is a schematic flow chart of a millimeter wave radar SOC circuit board design method provided in an embodiment of the present application. The method includes steps S101 to S105.

[0035] S101. Design a circuit structure, wherein the circuit structure includes an LC filter circuit, an LDO, an output end capacitor combination module, a load end capacitor combination module, and a radio frequency power supply end of a SOC, which are electrically connected in sequence.

[0036] S102 . Select an LDO to power the radio frequency power supply end of the SOC, wherein the LDO is a high PSRR LDO, and the high PSRR LDO has a PSRR value of ≥25 dB under a condition of 1 MHz.

[0037] S103, setting a circuit board with at least three layers, setting LDO and SOC on different board layers respectively, and ensuring that the power supply lines of the LDO and SOC have a short spacing.

[0038] Specifically, LDO and SOC should be arranged on different layers on the circuit board, for example, if SOC is on the top layer, LDO should be on the bottom layer. LDO and SOC are placed on different layers to reduce the impact of LDO circuit noise on SOC radio frequency. Tests have found that when the PA module inside the SOC powered by LDO is transmitting, the PA is in a constant switching state, resulting in relatively large power supply noise for PA. If the two are placed on the same layer, it is easy to pass through the ground. If they are placed on different layers and refer to different grounds, this impact can be reduced. Second, cost reduction. Due to radiation issues, components placed on the SOC layer need to be shielded to reduce external radiation. If LDO is placed on the same layer, additional shielding covers are required for these components. The distance from the LDO power supply output to the SOC should be as short as possible. When the SOC is working, the voltage fluctuation is relatively large and the transient current is also large. If the wiring is short, the loop impedance is small, and the voltage drop caused by the transient current is also small, which can reduce power supply noise and also prevent the terminal voltage from exceeding the SOC working range.

[0039] S104: Set a Faraday cage around the radio frequency part of the SOC.

[0040] Specifically, a Faraday cage is set around the SOC to reduce the impact of onboard noise on the high-frequency part of the SOC. The RF part of the layer where the SOC is located, especially the antenna part, is surrounded by blind holes to form a Faraday cage, and is not directly connected to other grounds on the layer where the SOC is located.

[0041] S105 , respectively disposing a load-end capacitor combination module and the SOC on the same board layer, so that the load-end capacitor combination and the SOC are close to each other.

[0042] Specifically, the optimal layout of the load-end capacitor combination module and the SOC is to be located on the same layer, and the load-end capacitor combination module is set as close to the SOC as possible. If it cannot be placed on the same layer, it should be directly set to another layer through a via, and the load-end capacitor combination module should be set close to the via.

[0043] S106. Set a plurality of grounding terminals for the load capacitor combination module, ensure that the grounding terminals are independent of each other on the surface layer, and the grounding terminals are connected through the inner layer ground.

[0044] Specifically, the ground terminal of the load capacitor combination module is connected to the ground of the inner layer through a via hole alone, and is not connected to the ground of the layer where the LDO is located and the layer where the SOC is located. The via hole is not connected to the reference ground layer of the next layer of the SOC.

[0045] S107, classify the grounding terminal of the circuit board into signal ground and radio frequency ground, the radio frequency ground and the signal ground are isolated from each other, the radio frequency ground and the signal ground are connected in the inner layer through vias, and the position of the vias is as far away as possible from the return path of the power interference signal. By dividing the ground, the influence of the signal ground noise on the radio frequency module is effectively cut off, ensuring that the radio frequency ground is as clean as possible, and this processing method is low in cost and easy to implement in design.

[0046] The present application adopts a high PSRR LDO and adds an LC filter design at the input end to better prevent external input interference signals from being injected into the LDO. In addition to retaining capacitance near the output of the LDO, a combination of large and small capacitors is added at the load end to suppress voltage disturbances and high-frequency noise caused by the rapid switching of the PA, thereby effectively reducing the impact on other power supplies in the system; the layout of the SOC and power modules is completed on a single board, and the high-frequency interference introduced by the power supply wiring into the system is reduced by setting layout principles; the principle and processing method of ground segmentation are clearly proposed to reduce the interference signal from being injected into the system through the ground. The above measures are combined to achieve the purpose of improving system noise, thereby improving the radar signal-to-noise ratio, and ultimately improving the detection capability of the millimeter-wave radar.

[0047] The LC filter circuit and output capacitor combination module of the present application are arranged close to the LDO, and the RF ground does not add green oil when making the circuit board, and the copper skin is directly exposed. The design of exposing the copper skin is conducive to the heat dissipation of the board surface, conducts the heat of the SOC, reduces the RF performance attenuation caused by the rise of the SOC temperature, and improves the signal-to-noise ratio.

[0048] In this embodiment, the LC filter module includes a power inductor or magnetic bead, a capacitor C1, a capacitor C2 and a capacitor C3 connected in sequence; the capacitor C1 is a capacitor of the order of 47uF or more, the capacitor C2 is a capacitor of the order of 1uF to 47uF, and the capacitor C3 is a capacitor of the order of 1uF or less. The output end capacitor combination module includes a capacitor C4, a capacitor C5 and a capacitor C6 connected in sequence; wherein the capacitor C4 is a capacitor of the order of 10uF or more, the capacitor C5 is a capacitor of the order of 1uF to 10uF, and the capacitor C6 is a capacitor of the order of 470nF or less. The load end capacitor combination module includes a capacitor C7, a capacitor C8 and a capacitor C9 connected in sequence; the C7 is a capacitor of the order of 1uF or more, the C8 is a capacitor of the order of 0.1uF to 1uF, and the C3 is a capacitor of the order of 100nF or less.

[0049] See also Figure 2 , Figure 2 The schematic diagram of the structural framework of the circuit provided in the embodiment of the present application includes an LC filter circuit, an LDO, an output end capacitor combination module, a load end capacitor combination module and a SOC RF power supply end electrically connected in sequence; the LDO is a high PSRR LDO; wherein the high PSRR LDO is a LDO with a PSRR value of ≥25dB ​​under the condition of 1MHz.

[0050] In this embodiment, the LC filter module includes a power inductor or magnetic bead, a capacitor C1, a capacitor C2 and a capacitor C3 connected in sequence; the capacitor C1 is a capacitor of the order of 47uF or more, the capacitor C2 is a capacitor of the order of 1uF to 47uF, and the capacitor C3 is a capacitor of the order of 1uF or less. The output end capacitor combination module includes a capacitor C4, a capacitor C5 and a capacitor C6 connected in sequence; wherein the capacitor C4 is a capacitor of the order of 10uF or more, the capacitor C5 is a capacitor of the order of 1uF to 10uF, and the capacitor C6 is a capacitor of the order of 470nF or less. The load end capacitor combination module includes a capacitor C7, a capacitor C8 and a capacitor C9 connected in sequence; the C7 is a capacitor of the order of 1uF or more, the C8 is a capacitor of the order of 0.1uF to 1uF, and the C3 is a capacitor of the order of 100nF or less.

[0051] The embodiment of the present application provides a circuit board structure, which adopts the above-mentioned millimeter wave radar SOC circuit board design method layout. The circuit board structure includes at least three layers, one of which is placed on the SOC, the next layer of the SOC layer should be a complete stratum, and the LDO is placed on another layer; the circuit board structure is provided with an LC filter circuit, an LDO, an output end capacitor combination module, a load end capacitor combination module and a radio frequency power supply end of the SOC, which are electrically connected in sequence.

[0052] In this embodiment, the LC filter circuit and the output capacitor combination module are arranged close to the LDO layout on the circuit board layout, and the load-end capacitor combination module is arranged close to the SOC layout on the circuit board layout.

[0053] In this embodiment, the SOC and the LDO are placed on different board layers in the circuit board layout, for example, the SOC is on the top layer and the LDO is on the bottom layer, and the distance from the LDO power supply output terminal to the SOC is as short as possible.

[0054] In this embodiment, the load-end capacitor combination module is connected to the inner layer ground through a hole alone, and is not connected to the top and bottom layers. The via is not connected to the reference ground layer of the next layer of the SOC (such as Figure 5-Figure 7 ).

[0055] In this embodiment, the signal ground and the radio frequency ground of the circuit board are separated from each other and are only connected together through the inner layer. The outer layer is not connected. They are directly isolated by hollowing out. The position of the via connecting the signal ground and the radio frequency ground is as far away as possible from the return path of the power interference signal (such as Figure 3 The RF part of the SOC layer, especially the antenna part, is surrounded by blind holes to form a Faraday cage, and is not directly connected to other grounds on the SOC layer (such as Figure 4 ).

[0056] The RF reference ground cutting, that is, the layer below the SOC layer, should be a complete ground, and the reference ground of the RF part below should also be separated from the ground of the same layer and connected to other grounds in the inner layer through vias.

[0057] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A millimeter wave radar SOC circuit board design method, characterized in that: include: Design a circuit structure, the circuit structure includes an LC filter circuit, an LDO, an output end capacitor combination module, a load end capacitor combination module and a radio frequency power supply end of the SOC which are electrically connected in sequence; Selecting an LDO to power the radio frequency power supply end of the SOC, wherein the LDO is a high PSRR LDO, and the high PSRR LDO has a PSRR value of ≥25dB ​​under a condition of 1MHz; A circuit board having at least three layers is provided, wherein the LDO and the SOC are respectively provided on different board layers, and the power supply lines of the LDO and the SOC are ensured to have a short spacing; Provide a Faraday cage around the radio frequency portion of the SOC; Arranging a load-end capacitor combination module and the SOC on the same board layer so that the load-end capacitor combination module and the SOC are close to each other; Set multiple grounding terminals for the load-end capacitor combination module, ensure that each grounding terminal is independent of each other on the surface layer, and each grounding terminal is connected through the inner layer ground; The grounding terminal of the circuit board is classified into a signal ground and a radio frequency ground, and the radio frequency ground and the signal ground are isolated from each other; the radio frequency ground and the signal ground are connected in the inner layer through a via, and the position of the via is far away from the return path of the power interference signal.

2. The millimeter wave radar SOC circuit board design method according to claim 1, characterized in that: The layer where the SOC is placed is used to lay copper over a large area to dissipate the heat of the SOC. When making the circuit board, the copper sheet is directly exposed without covering it with oil.

3. The millimeter wave radar SOC circuit board design method according to claim 1, characterized in that: The LC filter circuit and the output terminal capacitor combination module are arranged close to the LDO.

4. The millimeter wave radar SOC circuit board design method according to claim 1, characterized in that: The LC filter circuit includes a power inductor, a capacitor C1, a capacitor C2 and a capacitor C3 connected in sequence, or a magnetic bead, a capacitor C1, a capacitor C2 and a capacitor C3 connected in sequence; the capacitor C1 is a capacitor of the order of 47uF or more, the capacitor C2 is a capacitor of the order of 1uF to 47uF, and the capacitor C3 is a capacitor of the order of 1uF or less.

5. The millimeter wave radar SOC circuit board design method according to claim 1, characterized in that: The output end capacitor combination module includes capacitor C4, capacitor C5 and capacitor C6 connected in sequence; wherein the capacitor C4 is a capacitor of the order of 10uF or more, the capacitor C5 is a capacitor of the order of 1uF to 10uF, and the capacitor C6 is a capacitor of the order of 470nF or less.

6. The millimeter wave radar SOC circuit board design method according to claim 1, characterized in that: The load-end capacitor combination module includes capacitors C7, C8 and C9 connected in sequence; C7 is a capacitor of 1uF or more, C8 is a capacitor of 0.1uF to 1uF, and C3 is a capacitor of 100nF or less.

7. A circuit, characterized in that: The invention comprises an LC filter circuit, an LDO, an output end capacitor combination module, a load end capacitor combination module and a radio frequency power supply end of a SOC which are electrically connected in sequence. The circuit also comprises a circuit board having at least three layers. The LDO and the SOC are respectively arranged on different board layers, and it is ensured that the power supply lines of the LDO and the SOC have a shorter spacing. The LDO is a high PSRR LDO. The high PSRR LDO has a PSRR value of ≥25dB ​​under the condition of 1MHz. A Faraday cage is arranged around the radio frequency part of the SOC. A plurality of grounding terminals are arranged for the load end capacitor combination module, and it is ensured that the grounding terminals are independent of each other on the surface layer, and the grounding terminals are connected through the inner layer.

8. A circuit board structure, characterized in that: The millimeter-wave radar SOC circuit board design method layout as described in any one of claims 1 to 6 is adopted; it includes at least three layers, one of which is for placing the SOC, the next layer of the SOC layer is a complete ground layer, and the LDO is placed in another layer; the circuit board structure is provided with an LC filter circuit, an LDO, an output capacitor combination module, a load capacitor combination module and a radio frequency power supply end of the SOC which are electrically connected in sequence, the signal ground and the radio frequency ground are connected in the inner layer through vias, and the position of the vias is far away from the return path of the power interference signal.

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