Stacked Low-Power FBAR Oscillator Circuit and Its Operating Method

Abstract

The present invention provides a stacked low-power FBAR oscillator circuit and its working method, which is characterized by comprising: a power supply port, a current generation circuit unit, and a stacked core oscillation circuit unit connected in sequence; the current generation circuit unit is used to generate a current independent of the input power supply voltage; the stacked core oscillation unit is used to provide negative resistance to compensate for the energy loss of the resonant circuit. This circuit is based on a stacked Pierce oscillator structure, which can achieve a large output swing and has characteristics such as low power consumption, low phase noise, and small area.

Description

Technical Field

[0001] The present invention belongs to the technical field of oscillator circuits, and specifically relates to a low-power, low-phase-noise, and small-area oscillator circuit, and particularly to a stacked low-power FBAR oscillator circuit and its working method. Background Art

[0002] With the rapid development of the Internet of Things, high requirements for low power consumption, low phase noise, and low cost are put forward for wireless sensor nodes. Since quartz crystal oscillators are large in size, difficult in processing, and poor in shock and vibration resistance, they can no longer meet the requirements of wireless communication systems. Therefore, a highly accurate, low-power, and low-phase-noise FBAR oscillator circuit is particularly important.

[0003] For traditional Pierce oscillators, the power consumption of the oscillator is mainly determined by the negative resistance composed of inverter circuits. Therefore, the optimization of Pierce oscillators is limited to improving the inverter to reduce power consumption, such as techniques that allow transistors in the inverter to operate in the weak inversion region. However, the disadvantage is poor stability and inapplicability to high-frequency bands, so it cannot meet the requirements in wireless communication. Summary of the Invention

[0004] In view of this, in order to make up for the gaps and deficiencies in the prior art, the purpose of the present invention is to provide a stacked low-power FBAR oscillator circuit and its working method, which overcomes the disadvantages of high power consumption and poor phase noise performance in Pierce oscillators, and has high integration. The provided stacked low-power FBAR oscillator circuit includes: a power supply port, a current generation circuit unit, and a stacked core oscillation circuit unit; the power supply port is used to provide a power supply voltage of 3.3V; the current generation circuit unit is used to generate a current independent of the input power supply voltage; the stacked core oscillation circuit unit includes a band-pass (low-pass) filter of a Π-type network composed of load capacitors C1, C2, and an FBAR resonator, and an N-stage stacked inverter for providing negative resistance to compensate for the energy loss of the resonant circuit. This circuit is based on a stacked Pierce oscillator structure, can achieve a large output swing, and has characteristics such as low power consumption, low phase noise, and small area.

[0005] The present invention specifically adopts the following technical solutions:

[0006] A stacked low-power FBAR oscillator circuit, characterized by including: connected in sequence: a power supply port, a current generation circuit unit, and a stacked core oscillation circuit unit; the current generation circuit unit is used to generate a current independent of the input power supply voltage; the stacked core oscillation unit is used to provide negative resistance to compensate for the energy loss of the resonant circuit.

[0007] Further, the power supply port is used to provide a power supply voltage of 3.3V; the power supply voltages of the MOS transistors in the circuit are all 3.3V.

[0008] Further, the current generation circuit unit adopts a Widlar current mirror structure.

[0009] Further, the current generation circuit unit includes MOS transistors PM1, PM2, NM1, NM2, NM3, NM4, PM3 and a control resistor R b , where the gates of MOS transistors PM1, PM2 and PM3 are connected, and the drains are also connected; the sources and gates of MOS transistors PM1, PM2, NM1 and NM2 are all connected to the power supply port; the drain of MOS transistor PM3 is the generated current output terminal; the drains of MOS transistors NM1 and NM2 are respectively connected to the sources of MOS transistors NM3 and NM4; the gates of MOS transistors NM3 and NM4 are connected, and the drain of MOS transistor NM3 is grounded through the control resistor R b and the drain of NM4 is directly grounded.

[0010] Further, the stacked core oscillation circuit unit includes a band-pass filter in the form of a Π-type network composed of a load capacitor and an FBAR resonator, and an N-stage inverter; the N-stage inverter is N parallel-connected inverters.

[0011] Further, the N-stage stacked inverter is used to provide a negative resistance to compensate for the energy loss of the resonant circuit, and the band-pass filter in the form of a Π-type network is used to provide a 180° phase shift and the voltage gain required for oscillation.

[0012] Further, each stage of the N-stage inverter includes a feedback resistor R B for making the input and output voltages of each stage of the inverter equal, and coupling capacitors C CG and C CD are respectively connected to the output terminal and the input terminal of each stage of the inverter for blocking DC.

[0013] Further, the band-pass filter in the form of a Π-type network includes: load capacitors C1, C2, and an FBAR resonator;

[0014] Both ends of each stage of the feedback resistor R B are respectively connected to the input terminal and the output terminal of this stage of the inverter, and the input terminal and the output terminal of each stage of the inverter are respectively connected to the coupling capacitor C D and the coupling capacitor C G ; both ends of the FBAR resonator are respectively connected to the coupling capacitors C CG and C CD and are respectively grounded through the load capacitors C1 and C2;

[0015] The generated current output terminal of the current generation circuit unit is connected to the source of the PMOS transistor in the Nth-stage inverter.

[0016] Further, the bias current I generated by the current generation circuit unit Bias has a magnitude of:

[0017]

[0018] where μ is the carrier mobility of the NMOS transistor, Cox is the unit capacitance of the gate oxide layer, and (W / L)3 and (W / L)4 are the aspect ratios of the MOS transistors NM3 and NM4, respectively;

[0019] If the channel modulation effect is considered, the bias current I Bias is written as:

[0020]

[0021] where λ is the channel length modulation coefficient, and V GS3 is the gate-source voltage of the MOS transistor NM3.

[0022] Further, the transconductance of the Nth-stage inverter is shown by the following formula:

[0023]

[0024] where g mi is the transconductance of each stage of the inverter;

[0025] The provided negative resistance is shown by the following formula:

[0026]

[0027] where ω osc is the resonant frequency, C1 and C2 are the values of the load capacitances, and C3 is the value of the parallel parasitic capacitance of the FBAR.

[0028] Compared with the prior art, the present invention and its preferred embodiments adopt a stacked Pierce structure FBAR oscillator, which has a low structural complexity and features such as a small area, low power consumption, and low phase noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The present invention will be further described in detail below with reference to the drawings and specific embodiments:

[0030] Figure 1 is a schematic diagram of the principle of the bias current generation circuit according to an embodiment of the present invention;

[0031] Figure 2 is a schematic diagram of the principle of the core oscillation circuit according to an embodiment of the present invention;

[0032] Figure 3 Schematic diagram of the principle of the stacked low-power FBAR oscillator circuit according to an embodiment of the present invention;

[0033] Figure 4 Schematic diagram of the basic structure according to an embodiment of the present invention. Detailed implementation manners

[0034] To make the features and advantages of this patent more obvious and understandable, specific embodiments are given below and described in detail as follows:

[0035] As Figures 1 - 4 shown, the stacked low-power FBAR oscillator circuit provided in this embodiment includes: connected in sequence: a power supply port, a current generation circuit unit, and a stacked core oscillation circuit unit; the current generation circuit unit is used to generate a current independent of the input power supply voltage; the stacked core oscillation unit is used to provide negative resistance to compensate for the energy loss of the resonance circuit.

[0036] It uses multi-stage parallel connection of inverters so that the transconductance g of each stage m is N times smaller than the transconductance g of the traditional first-order Pierce structure. A smaller transconductance means a smaller current, which can greatly reduce power consumption and phase noise in the stacked structure. And an improved body biasing technique is used so that the MOS transistors of each stage of the inverter operate in the saturation region, making the circuit have high stability. m In this embodiment, the frequency of the oscillator is 1.93 GHz, and the power supply port is used to provide a power supply voltage of 3.3 V; the power supply voltage of the MOS transistors in the circuit is all 3.3 V.

[0037]

[0038] Figure 1 As shown, the current generation circuit unit adopts a Widlar current mirror structure to provide a bias current I independent of the power supply voltage bias .

[0039] The current generation circuit unit includes MOS transistors PM1, PM2, NM1, NM2, NM3, NM4, PM3 and a control resistor R b . Among them, the gates of MOS transistors PM1, PM2, and PM3 are connected, and the drains are also connected; the sources and gates of MOS transistors PM1, PM2, NM1, and NM2 are all connected to the power supply port; the drain of MOS transistor PM3 is the current output terminal for generation; the drains of MOS transistors NM1 and NM2 are respectively connected to the sources of MOS transistors NM3 and NM4; the gates of MOS transistors NM3 and NM4 are connected, the drain of MOS transistor NM3 is grounded through the control resistor R b , and the drain of NM4 is directly grounded.

[0040] As Figure 2As shown, the stacked core oscillation circuit unit includes a band-pass filter in the form of a Π-type (or π-type) network composed of a load capacitor and an FBAR resonator, and an N-stage inverter; the N-stage inverter is N inverters connected in parallel.

[0041] The N-stage inverter is used to provide a negative resistance to compensate for the energy loss of the resonant circuit, and the band-pass filter in the form of a Π-type network is used to provide a 180° phase shift and the voltage gain required for oscillation.

[0042] Each stage of the N-stage inverter includes a feedback resistor R B for making the input and output voltages of each stage of the inverter equal, and a coupling capacitor C is connected to the output terminal and the input terminal of each stage of the inverter respectively CG and C CD for blocking direct current.

[0043] Preferably, N = 4, and the band-pass filter in the form of a Π-type network includes: feedback resistors R B1 , R B2 , R B3 and R B4 , coupling capacitors C G1 , C G2 , C G3 , C G4 , C D1 , C D2 , C D3 , C D4 ;

[0044] Both ends of each stage of feedback resistor R B are respectively connected to the input terminal and the output terminal of this stage of the inverter, and the input terminal and the output terminal of the fourth-stage inverter are respectively connected to the coupling capacitor C D4 and the coupling capacitor C G4 ; the input terminal and the output terminal of the third-stage inverter are respectively connected to the coupling capacitor C D3 and the coupling capacitor C G3 ; the input terminal and the output terminal of the second-stage inverter are respectively connected to the coupling capacitor C D2 and the coupling capacitor C G2 ; the input terminal and the output terminal of the first-stage inverter are respectively connected to the coupling capacitor C D1 and the coupling capacitor C G1 ;

[0045] Both ends of the FBAR resonator are respectively connected to the coupling capacitors C CG and C CD and are grounded through the load capacitors C1 and C2 respectively;

[0046] The generated current output terminal of the current generation circuit unit is connected to the source of the MOS transistor PM4 serving as the input terminal in the fourth-stage inverter.

[0047] In this embodiment, the bias current I generated by the current generation circuit unit Bias has a magnitude of:

[0048]

[0049] where μ is the carrier mobility of the NMOS transistor, Cox is the unit capacitance of the gate oxide layer, (W / L)3 and (W / L)4 are the aspect ratios of MOS transistors NM3 and NM4 respectively;

[0050] If the channel modulation effect is considered, then the bias current I Bias is written as:

[0051]

[0052] where λ is the channel length modulation coefficient, V GS3 is the gate-source voltage of MOS transistor NM3.

[0053] The core oscillation circuit is composed of N inverters cascaded through two filter capacitors CG and CD. Each stage of the inverter includes a feedback resistor R b and a resistor R for improving the body biasing technique. The transconductance of the N-stage inverter is shown as follows:

[0054]

[0055] where g mi is the transconductance of each stage of the inverter;

[0056] Whether it is an oscillator with a traditional Pierce structure or a stacked oscillator, a negative resistance is required to provide energy for the FBAR resonator. The negative resistance provided in this embodiment is shown as follows:

[0057]

[0058] where ω osc is the resonance frequency, C1 and C2 are the values of the load capacitors, and C3 is the value of the parallel parasitic capacitance of the FBAR.

[0059] Assume that the channel lengths of the NMOS and PMOS transistors are the same, i.e., L N = L P . When the sizes of each stage of the inverter are equal, it is not difficult to obtain g mN , g mP , G M , and the relationship between the current I D and the order N is:

[0060]

[0061] Substitute Equation (2) into Equation (4) and combine with Equation (3), we get:

[0062]

[0063] On the ideal premise of not considering adverse factors such as temperature, MOS transistor size process differences, etc. and the same power supply voltage, the power consumption of the stacked low-power FBAR oscillator circuit is reduced by 16 times compared with the traditional Pierce structure oscillator circuit.

[0064] It should be noted that the order N in the stacked low-power FBAR oscillator circuit is not necessarily the larger the better, and it needs to be determined according to specific indicators and the magnitude of the predetermined power supply voltage.

[0065] This patent is not limited to the above best implementation mode. Anyone inspired by this patent can obtain various other forms of stacked low-power FBAR oscillator circuits and their working methods. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope covered by this patent.

Claims

1. A stacked low-power FBAR oscillator circuit, characterized in that, Comprising: Connected in sequence: a power supply port, a current generation circuit unit, and a stacked-core oscillation circuit unit; The current generation circuit unit is used to generate a current independent of the input power supply voltage; the stacked-core oscillation unit is used to provide a negative resistance to compensate for the energy loss of the resonant circuit; The current generation circuit unit adopts a Widlar current mirror structure; The stacked-core oscillation circuit unit includes a band-pass filter in the form of a Π-type network composed of a load capacitor and an FBAR resonator, and an N-stage inverter; the N-stage inverter is N inverters connected in parallel; The N-stage inverter is used to provide a negative resistance to compensate for the energy loss of the resonant circuit, and the band-pass filter in the form of a Π-type network is used to provide a 180° phase shift and the voltage gain required for oscillation; Each inverter stage in the N-stage inverter includes a feedback resistor R B for making the input and output voltages of each inverter stage equal. Coupling capacitors C and C are respectively connected to the output terminal and the input terminal of each inverter stage CG and C CD for blocking direct current.

2. The stacked low-power FBAR oscillator circuit according to claim 1, wherein: The band-pass filter in the form of a Π-type network includes: load capacitors C1, C2, and an FBAR resonator; Each stage of feedback resistor R B is connected to the input and output terminals of the inverter of that stage respectively. The input and output terminals of each stage of inverter are connected to coupling capacitors C D and coupling capacitor C G respectively; both ends of the FBAR resonator are connected to the coupling capacitors C CG and C CD respectively, and are grounded through load capacitors C1 and C2 respectively; The current output terminal of the current generation circuit unit is connected to the source electrode of the PMOS transistor in the Nth-stage inverter.

3. The stacked-based low-power FBAR oscillator circuit according to claim 1, wherein: The transconductance of the N-stage inverter is shown by the following formula: where g mi is the transconductance of each stage of the inverter; The provided negative resistance is shown by the following formula: where ω osc is the resonant frequency, C1 and C2 are the values of the load capacitances, and C3 is the value of the shunt parasitic capacitance of the FBAR.

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