Semiconductor device and method for manufacturing semiconductor device

Abstract

A method of manufacturing a semiconductor device includes applying plasma to a portion of a metal dichalcogenide film. The metal dichalcogenide film includes a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. After applying the plasma, a metal layer including a second metal is formed over the portion of the metal dichalcogenide film. Embodiments of the present invention also relate to a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the semiconductor device. Background Art

[0002] A two-dimensional semiconductor (also called a 2D semiconductor) is a natural semiconductor with a thickness on the atomic scale. Transition metal dichalcogenides have been used in 2D devices. The performance of a single 2D transition metal dichalcogenide material for device applications has reached an upper limit. The resistance at the junction of the source / drain region and the source / drain electrode contact is the performance limiting factor in 2D devices. Summary of the invention

[0003] Some embodiments of the present invention provide a method for manufacturing a semiconductor device, comprising: applying plasma to a portion of a metal dichalcogenide film, wherein the metal dichalcogenide film comprises a first metal and a chalcogen element selected from the group consisting of S, Se, Te, and combinations thereof; after applying the plasma, forming a metal layer comprising a second metal over the portion of the metal dichalcogenide film.

[0004] Some other embodiments of the present invention provide a method for manufacturing a semiconductor device, comprising: forming a metal dichalcogenide film over a substrate, wherein the metal dichalcogenide film comprises a first metal and a chalcogenide element selected from the group consisting of S, Se, Te and combinations thereof; forming a buffer layer over the metal dichalcogenide film; patterning the buffer layer to expose a portion of the metal dichalcogenide film; plasma stripping the chalcogenide element from a surface layer of the exposed portion of the metal dichalcogenide film; and, after the plasma stripping, forming a metal layer comprising a second metal over the exposed portion of the metal dichalcogenide film.

[0005] Still other embodiments of the present invention provide a semiconductor device, comprising: a metal chalcogenide monolayer film disposed above a substrate, wherein the metal chalcogenide monolayer film includes a first metal and a chalcogenide element selected from the group consisting of S, Se, Te, and combinations thereof, and wherein the metal chalcogenide monolayer film has a first surface portion and a second surface portion; and a metal layer disposed above the metal chalcogenide film, wherein the metal layer includes a second metal, the metal layer is disposed above the first surface portion but not above the second surface portion, and wherein the metal layer is chemically bonded to the metal chalcogenide film. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A and Figure 1B are isometric and cross-sectional views of stages in a sequential method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

[0008] Figure 2A and Figure 2B are isometric and cross-sectional views of stages in a sequential method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

[0009] Figure 3A and Figure 3B are isometric and cross-sectional views of stages in a sequential method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

[0010] Figure 4A and Figure 4B are isometric and cross-sectional views of stages in a sequential method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

[0011] Figure 5A and Figure 5B are isometric and cross-sectional views of stages in a sequential method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

[0012] Fig. 6A and Figure 6B are isometric and cross-sectional views of stages in a sequential method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

[0013] Fig. 7A and Figure 7B are isometric and cross-sectional views of stages in a sequential method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

[0014] Figure 8 are schematic cross-sectional views of stages in a sequential method of fabricating a semiconductor device according to an embodiment of the present invention.

[0015] Fig. 9 are schematic cross-sectional views of stages in a sequential method of fabricating a semiconductor device according to an embodiment of the present invention.

[0016] Fig.10 are schematic cross-sectional views of stages in a sequential method of fabricating a semiconductor device according to an embodiment of the present invention.

[0017] Fig.11are schematic cross-sectional views of stages in a sequential method of fabricating a semiconductor device according to an embodiment of the present invention.

[0018] Fig.12 are schematic cross-sectional views of stages in a sequential method of fabricating a semiconductor device according to an embodiment of the present invention.

[0019] Fig.13A and Fig. 13B are plan and cross-sectional views of stages in a sequential method of fabricating a semiconductor device according to an embodiment of the present invention.

[0020] Fig.14A and Fig. 14B are plan and cross-sectional views of stages in a sequential method of fabricating a semiconductor device according to an embodiment of the present invention.

[0021] Fig.15A and Fig. 15B are plan and cross-sectional views of stages in a sequential method of fabricating a semiconductor device according to an embodiment of the present invention.

[0022] Fig.16 are cross-sectional views of stages in a sequential method of fabricating a semiconductor device according to an embodiment of the present invention.

[0023] Fig.17A and Fig. 17B are plan and cross-sectional views of stages in a sequential method of fabricating a semiconductor device according to an embodiment of the present invention.

[0024] Fig.18A and Fig.18B are plan and cross-sectional views of stages in a sequential method of fabricating a semiconductor device according to an embodiment of the present invention.

[0025] Fig.19 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0026] Fig. 20 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0027] Fig.21 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0028] Fig. 22 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0029] Fig.23 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0030] Fig.24is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

[0031] Fig.25 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] It should be understood that the following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, the size of the element is not limited to the disclosed range or value, but may depend on the process conditions and / or the desired characteristics of the device. In addition, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. For the purpose of simplicity and clarity, each component may be arbitrarily drawn in different proportions.

[0033] Moreover, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. Additionally, the term "made of" may mean "comprising" or "consisting of."

[0034] Figure 1A and Figure 1B 1 is an isometric view and cross-sectional view of stages of a sequential method of manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1A and Figure 1B As shown, in some embodiments, a 2D metal chalcogenide film 15 is formed over the substrate 10. In some embodiments, the 2D material is a metal chalcogenide, such as a metal dichalcogenide, having a layer thickness of about 0.5 nm to about 10 nm, in addition to a metal oxide. In some embodiments, the metal dichalcogenide is a transition metal dichalcogenide. In some embodiments, the metal is selected from the group consisting of Mo, W, Pd, and Hf. In some embodiments, the chalcogen element X is one or more selected from the group consisting of S, Se, and Te. In some embodiments, the transition metal dichalcogenide is selected from the group consisting of MoS2, WS2, MoSe2, WSe2, MoTe2, and WTe2.

[0035] In some embodiments, substrate 10 is a conductive material, such as doped silicon or intrinsic silicon. In some embodiments, the substrate is an insulator, such as silicon oxide or aluminum oxide. In some embodiments, the substrate includes a conductive material having an insulating layer formed thereon. In some embodiments, the substrate silicon dioxide is disposed above a silicon wafer. In other embodiments, a suitable aluminum oxide substrate includes sapphire.

[0036] In some embodiments, the metal dichalcogenide film 15 is a single layer film. In other embodiments, the metal dichalcogenide film 15 includes a plurality of single layer films arranged in a stack.

[0037] In some embodiments, the metal dichalcogenide film 15 represented by MX2 is formed by a transfer operation, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), or a phase change operation. To form the metal dichalcogenide film, in some embodiments of the present invention, a metal film is deposited on a substrate by using an RF sputtering system. The metal film is then converted into a metal dichalcogenide film. For example, in some embodiments, the metal dichalcogenide film is formed by sputtering at a power ranging from about 10 W to about 100 W at a temperature ranging from about 5×10 -2 Torr is about 5×10 -4 A metal (such as molybdenum) is deposited on a substrate (such as sapphire) by sputtering with an Ar gas flow of from about 10 sccm to about 100 sccm at a background pressure of 2.5 Torr. After the metal is deposited, the substrate is placed in the center of a hot furnace for chalcogenization, such as sulfurization. During the sulfurization process, Ar gas at a flow rate of from about 40 sccm to about 200 sccm is used as a carrier gas, and the furnace pressure is in the range of from about 0.1 Torr to about 10 Torr. The sulfurization temperature is from about 400°C to about 1200°C. In some embodiments, upstream of the furnace, about 0.5 g to about 2 g of S powder is heated in the gas flow to an evaporation temperature of about 120°C to about 200°C.

[0038] In one embodiment, by performing a 40W power test at about 5×10 -3 Molybdenum is deposited on a sapphire substrate by sputtering with an Ar gas flow of about 40 sccm at a background pressure of 1.5 Torr. The sulfurization operation takes place in a furnace at about 800°C at an Ar flow rate of about 130 sccm and a furnace pressure of about 0.7 Torr. S powder (about 1.5 g) is placed in the gas flow upstream of the furnace and heated to an evaporation temperature of about 120°C. By using this growth technique, large-area MoS2 films can be obtained on sapphire substrates.

[0039] In some embodiments, instead of a sulfidation operation to form an S-based material (MoS2, WS2, etc.), a selenization operation is performed to form a Se-based material, such as MoSe2 and WSe2, or a tellurization operation is performed to form a Te-based material, such as MoTe2 and WTe2. For selenium-based or tellurium-based materials, the parameters of the chalcogenization operation (e.g., temperature, pressure) can be adjusted as needed.

[0040] In some embodiments, a metal dichalcogenide film other than a metal oxide film is formed directly on a device substrate, while in other embodiments, the metal dichalcogenide film is formed on another substrate and then transferred to the device substrate. For example, in addition to a metal oxide film having a thickness of about 0.5 nm to about 10 nm, a first metal dichalcogenide film is formed on a first substrate. In some embodiments, the first metal dichalcogenide film is formed by chemical vapor deposition (CVD). In other embodiments, a first metal film is first formed by sputtering or atomic layer deposition, and then the metal film is converted into a metal dichalcogenide by reacting the metal film with a chalcogen element other than oxygen. A polymer film having a thickness from about 100 nm to about 5 μm is subsequently formed on the first metal dichalcogenide film. In some embodiments, the polymer film is poly(methyl methacrylate) (PMMA). After forming the polymer film, the sample is heated, such as by placing the sample on a hot plate. The sample can be heated at a temperature from about 70° C. to about 200° C. for about 30 seconds to about 20 minutes. After heating, the corners of the first metal dichalcogenide film are peeled off from the substrate, such as by using tweezers, and the sample is then immersed in a solution to facilitate separation of the first metal dichalcogenide film from the first substrate. In some embodiments, the solution is an alkaline aqueous solution. The first metal dichalcogenide film and the polymer film are transferred to a second substrate. In some embodiments, after the first metal dichalcogenide film is applied to the second substrate, the sample can be left to stand for 30 minutes to 24 hours. In some embodiments, the second substrate includes a silicon oxide or aluminum oxide substrate. In some embodiments, a suitable silicon oxide substrate includes a silicon dioxide layer formed on a silicon layer. In other embodiments, a suitable aluminum oxide substrate includes sapphire. The polymer film is removed from the first metal dichalcogenide film using a suitable solvent. In some embodiments, the second substrate / first metal dichalcogenide film / polymer film structure is immersed in a suitable solvent until the polymer film is dissolved. Any solvent suitable for dissolving the polymer film can be used. For example, in some embodiments, when the polymer film is a PMMA film, acetone is used as a solvent. In some embodiments, the first metal dichalcogenide film and the second substrate are then annealed by heating in an oven at a temperature of about 200° C. to about 500° C. for about 30 minutes to about 5 hours to provide a transferred metal dichalcogenide film on the second substrate.

[0041] In one embodiment, the film transfer operation of the two-dimensional metal sulfide crystal film is implemented as follows: (1) a 1.5 μm thick poly(methyl methacrylate) (PMMA) layer is spin-coated on the 2D metal sulfide crystal film; (2) the sample is heated on a hot plate at 120°C for 5 minutes; (3) a small portion of the PMMA / 2D crystal film at the corner is peeled off from the sapphire substrate with tweezers; (4) the sample is immersed in a KOH solution, and the PMMA / 2D crystal film is completely peeled off; (5) the PMMA / 2D crystal film is placed on a 300 nm SiO2 / Si substrate; (6) the sample is placed under atmospheric conditions for 8 hours; (7) the sample is then immersed in acetone to remove PMMA; and (8) the sample is annealed in a furnace at 350°C for 2 hours to retain the 2D metal sulfide crystal film on the surface of the SiO2 / Si substrate.

[0042] Figure 2A and Figure 2B 1 is an isometric view and cross-sectional view of stages of a sequential method of manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2A and Figure 2B As shown, a buffer layer 55 is formed over the 2D metal dichalcogenide layer 15. In some embodiments, the buffer layer is a photoresist or an insulating layer, such as an oxide layer. In some embodiments, the oxide layer is silicon oxide (such as SiO2) or aluminum oxide (such as Al2O3). In some embodiments, the thickness of the buffer layer 55 is in a range from about 5 nm to about 100 nm. In some embodiments, the thickness of the buffer layer 55 is in a range from about 10 nm to about 50 nm. In some embodiments, the buffer layer is formed by a photoresist deposition operation, a CVD or a PVD operation.

[0043] Figure 3A and Figure 3B 1 is an isometric view and cross-sectional view of stages of a sequential method of manufacturing a semiconductor device according to an embodiment of the present invention. Figure 3A and Figure 3B As shown, the buffer layer 55 is patterned to form an opening 60 in the buffer layer. The opening exposes a portion of the metal dichalcogenide layer 15. In some embodiments, the exposed portion of the metal dichalcogenide layer 15 is a source / drain region of a semiconductor device. When the buffer layer 55 is a photoresist layer, the photoresist is patterned by a photolithography technique, including selectively exposing the photoresist layer to actinic radiation and developing the selectively exposed photoresist layer. In some embodiments, when the buffer layer 55 is an oxide layer, a photoresist layer is formed over the buffer layer, and a photolithography and etching operation is performed to form an opening 60 in the buffer layer 55, followed by removing the photoresist layer by an appropriate photoresist stripping or ashing operation.

[0044] Figure 4A and Figure 4B1 is an isometric view and cross-sectional view of stages of a sequential method of manufacturing a semiconductor device according to an embodiment of the present invention. Figure 4A and Figure 4B As shown, plasma 90 is applied to the device. Plasma 90 interacts with the exposed portion of the metal dichalcogenide layer 15. In some embodiments, plasma 90 is a hydrogen plasma. In some embodiments, the chalcogenide X of MX2 at a surface portion 65 of the metal dichalcogenide layer 15 is removed and replaced by hydrogen to form a metal hydrogenated chalcogenide MXH. In some embodiments, the hydrogen replacement is performed using a plasma stripping operation. In an embodiment of a plasma stripping operation, a hydrogen plasma is applied to the surface of the metal dichalcogenide film. The hydrogen plasma strips the chalcogen at the portion 65 of the metal dichalcogenide film surface exposed to the hydrogen plasma, and the hydrogen in the plasma replaces the chalcogen removed from the metal dichalcogenide film surface. The portion 65 of the surface of the metal dichalcogenide layer where the hydrogen replaces the chalcogen is the uppermost layer of the chalcogen of the metal chalcogenide (see Fig. 9 ).

[0045] In some embodiments, the plasma is applied at a pressure ranging from about 10 mTorr to about 500 mTorr. In some embodiments, the plasma is applied at a pressure ranging from about 20 mTorr to about 300 mTorr, and in other embodiments, the plasma is applied at a pressure ranging from about 50 mTorr to about 200 mTorr. In some embodiments, the plasma is applied at a power ranging from about 10 W to about 150 W. In some embodiments, the plasma is applied at a power ranging from about 20 W to about 100 W, and in other embodiments, the plasma is applied at a power ranging from about 30 W to about 50 W.

[0046] Figure 5A and Figure 5B 1 is an isometric view and cross-sectional view of stages of a sequential method of manufacturing a semiconductor device according to an embodiment of the present invention. Figure 5A and Figure 5BAs shown, a first metal layer 70 is formed over the device. The first metal layer 70 is made of a second metal, wherein the metal of the metal dichalcogenide is the first metal. In some embodiments, the second metal is a metal different from the first metal. In some embodiments, the second metal is more active than the metal (first metal) of the metal dichalcogenide layer 15. An active metal (second metal) is applied to the surface 65 of the metal chalcogenide film treated with plasma. An active metal is applied to the metal hydrogenated chalcogenide film MXH, hydrogen is removed from the MXH film, and hydrogen is replaced with an active metal, thereby forming a film MXM2, wherein M is the metal of the metal chalcogenide film, X is a chalcogen, and M2 is an active metal (second metal) 70. In some embodiments, the active metal is chemically combined with the first metal of the metal chalcogenide film. In some embodiments, the active metal forms an alloy with the metal of the metal chalcogenide film to form an alloy layer 105. In some embodiments, the active metal is one or more selected from the group consisting of Ni, Mo, In, Ti, W, Sc, Pd, Pt, Co, and Ru. In some embodiments, the metal dichalcogenide film MX2, and the metal hydrogenated chalcogenide film MXH are single layer films. The film MXM2 is part of a combination of an alloy-bonded metal chalcogenide film and a first metal layer.

[0047] The formation of the metal active metal alloy 105 at the interface between the active metal and the metal of the metal chalcogenide film forms an interface with reduced resistance. In other words, the formation of the metal active metal alloy 105 at the interface provides a highly conductive contact between the semiconductor material and the electrical contact due to the full metal contact. The metal active metal alloy 105 eliminates the van der Waals gap between the metal contact layer and the metal chalcogenide semiconductor layer. The active metal acts as a glue to form a metal alloy between the top metal pad and the active metal and between the active metal and the metal chalcogenide layer MX. The metal active metal interface also provides a seamless edge contact of MX-MXM2 between the source / drain region and the channel region of the semiconductor device.

[0048] In some embodiments, the thickness of the first metal layer 70 is in a range from about 1 nm to about 25 nm. In other embodiments, the thickness of the first metal layer 70 is in a range from about 2 to about 15 nm.

[0049] In an embodiment, the first metal layer 70 is formed at a temperature ranging from 100°C to 300°C, or after forming the first metal layer, the device is heated to a temperature ranging from 100°C to 300°C (or annealed at a temperature ranging from 100°C to 300°C).

[0050] In some embodiments, a second metal layer 75 is formed over the first metal layer 70. The second metal layer 75 is made of a third metal that is less active than the second metal. Because the second metal of the first metal layer 70 is more active, it is more susceptible to oxidation. The second metal layer 15 is less susceptible to oxidation and protects the contact from oxidation and increased resistivity due to oxidation.

[0051] In some embodiments, the second metal layer 75 is made of Au, Pt, Cu or TiN. In some embodiments, the thickness of the second metal layer 75 is in the range from about 10 nm to about 100 nm. In other embodiments, the thickness of the second metal layer 75 is in the range from about 20 nm to about 50 nm.

[0052] In some embodiments, because the active metal layer 70 (first metal layer) may be oxidized in the air, a protective metal layer 75 (second metal layer) having lower activity than the active metal layer is formed over the active metal layer.

[0053] Fig. 6A and Figure 6B 1 is an isometric view and cross-sectional view of stages of a sequential method of manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 6A and Figure 6B As shown, in other regions of the device except the source / drain regions, the buffer layer 55, the first metal layer 70 and the second metal layer 75 above the buffer layer 55 are removed. These layers are removed by appropriate photolithography or etching operations, such as a lift-off operation by wet etching.

[0054] Fig. 7A and Figure 7B 1 is an isometric view and cross-sectional view of stages of a sequential method of manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 7A and Figure 7B As shown, a gate dielectric layer 80 is subsequently formed over the 2D layer 15 , and a gate electrode layer 85 is formed over the gate dielectric layer in the channel region 110 of the semiconductor device. Fig. 7A and Figure 7B The semiconductor device shown is a top gate device. As shown, a channel region 110 is located between a pair of opposing source / drain regions 120 .

[0055] In some embodiments, the gate dielectric layer 80 is an oxide layer, such as silicon dioxide. In other embodiments, the gate dielectric layer 80 is one or more layers of silicon nitride or a high-k dielectric layer. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials and / or combinations thereof. The gate dielectric layer 80 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD) or any suitable method. In some embodiments, the thickness of the gate dielectric layer 80 is in the range of from about 1 nm to about 10 nm.

[0056] The gate electrode 85 may be formed of any suitable conductive material, including polysilicon, graphene, and metal (including one or more layers of aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, nickel, manganese, silver, palladium, rhenium, iridium, ruthenium, platinum, and zirconium), tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode 85 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) (sputtering), electroplating, or other suitable methods.

[0057] Reference Figures 8 to 12 The embodiments of the present invention are described in more detail. Figure 8 As shown, a metal dichalcogenide layer 15 is formed over the substrate 10 . The metal dichalcogenide includes a metal M and a chalcogen element X. A patterned buffer layer 55 is formed over the metal dichalcogenide layer 15 , exposing a portion of the metal dichalcogenide layer 15 .

[0058] Then, hydrogen plasma 90 is applied to the exposed portion of the metal dichalcogenide layer 15, such as Fig. 9 As shown. A hydrogen plasma is applied within the power and pressure ranges discussed previously herein. As shown, the hydrogen replaces the chalcogen in the surface portion 65 of the metal dichalcogenide film to form a metal hydrogenated chalcogenide MXH.

[0059] Fig.10 The formation of a metal layer 70 over the exposed portion of the metal chalcogenide film is shown, as well as the presence of a van der Waals gap 100 between the metal layer and the metal chalcogenide film 15. In an embodiment of the present invention, because the metal layer 70 is chemically bonded directly to the metal chalcogenide film 15, the van der Waals gap is eliminated and a lower resistance interface between the source / drain regions and the metal contacts of the semiconductor device is provided. Fig.11As shown, the active metal of the metal layer 70 replaces the hydrogen 90 of the MXH film, forming a film MXM2 having an alloy bonding region 105 where the metal layer 70 is directly bonded to the metal chalcogenide film MX.

[0060] In some embodiments, the second metal layer 75 is deposited over the first metal layer 70, such as Fig.12 The second metal layer 75 is less active than the first metal layer 70 and protects the first metal layer 70 from oxidation. In some embodiments, the second metal layer 75 forms an alloy bond with the first metal layer 70 at the interface between the first metal layer and the second metal layer.

[0061] In some embodiments, the semiconductor device is a 2D crystalline heterostructure. FIG. 13A to FIG. 18B A method of forming a 2D crystalline heterostructure according to an embodiment of the present invention is described. In some embodiments, the 2D crystalline heterostructure provides a semiconductor device with a greater drain current and field effect mobility than a single layer device.

[0062] Fig.13A and Fig. 13B 1 is a plan view and a cross-sectional view of stages of a sequential method of manufacturing a semiconductor device according to an embodiment of the present invention. Fig.13A and Fig. 13BAs shown, the metal dichalcogenide heterostructure includes a first metal dichalcogenide film 15 formed on a substrate 10 and a second metal dichalcogenide film 25 formed on the first metal dichalcogenide film 15. In some embodiments, the first metal dichalcogenide film 15 and the second metal dichalcogenide film 25 are formed by chemical vapor deposition (CVD). In other embodiments, the first metal film is formed by physical vapor deposition (sputtering) or atomic layer deposition (ALD), and then the first metal film is converted into a metal chalcogenide by reacting the metal film with a chalcogen. In some embodiments, the second metal film is formed by physical vapor deposition (sputtering) or atomic layer deposition (ALD), and then the second metal film is converted into a metal dichalcogenide by reacting the second metal film with a chalcogen to subsequently form the second metal chalcogenide film 25 over the first metal dichalcogenide film 15. In some embodiments, the first metal dichalcogenide film 15 and the second metal dichalcogenide film 25 each have a thickness of about 0.5 nm to about 10 nm. In some embodiments, one or both of the first metal dichalcogenide film 15 and the second metal dichalcogenide film 25 are monolayer films. In some embodiments, the first and second metal dichalcogenides are different transition metal dichalcogenides. In some embodiments, the transition metal dichalcogenide is selected from the group consisting of MoS2, WS2, PdS2, HfS2, MoSe2, WSe2, PdSe2, HfSe2, MoTe2, WTe2, PdTe2 and HfTe2. In some embodiments, a WS2 / MoS2 heterostructure including a MoS2 film (as film 15) formed on a sapphire substrate and a WS2 film (as film 25) formed on the MoS2 film is provided.

[0063] Fig.14A and Fig. 14B 1 is a plan view and a cross-sectional view of stages of a sequential method of manufacturing a semiconductor device according to an embodiment of the present invention. Using photolithography and etching operations, the first metal dichalcogenide film 15 and the second metal dichalcogenide film 25 are patterned to form a channel region 110 and a source / drain region 120, as shown in FIG. Fig.14A and Fig. 14B The photolithography and etching operations expose the substrate 10 surrounding the patterned first metal dichalcogenide film 15 and the second metal dichalcogenide film 25 .

[0064] Fig.15A and Fig. 15B 1 is a plan view and a cross-sectional view of stages of a sequential method of manufacturing a semiconductor device according to an embodiment of the present invention. A buffer layer 55 is formed over the second metal dichalcogenide layer 25, such as Fig.15A and Fig. 15BAs described above, the buffer layer 55 may be a photoresist layer or an oxide layer. Using appropriate photolithography and etching operations, a contact window opening 20 is formed in the buffer layer 55 and the second metal dichalcogenide film 25 exposing the first metal dichalcogenide film 15. Fig.15A and Fig. 15B shown.

[0065] Then, plasma 90 is applied to the exposed portion of the first dichalcogenide layer 15, such as Fig.16 As previously discussed, the plasma 90 interacts with the exposed portion of the metal dichalcogenide layer 15. In some embodiments, the plasma is a hydrogen plasma. The chalcogen at the surface portion 65 of the metal dichalcogenide is removed, and the chalcogen is replaced by hydrogen to form a metal hydrogenated chalcogenide MXH. In some embodiments, the plasma is applied at a pressure ranging from about 10mTorr to about 500mTorr. In some embodiments, the plasma is applied at a pressure ranging from about 20mTorr to about 300mTorr, and in other embodiments, the plasma is applied at a pressure ranging from about 50mTorr to about 200mTorr. In some embodiments, the plasma is applied at a power ranging from about 10W to about 150W. In some embodiments, the plasma is applied at a power ranging from about 20W to about 100W, and in other embodiments, the plasma is applied at a power ranging from about 30W to about 50W.

[0066] Fig.17A and Fig. 17B 1 is a plan view and a cross-sectional view of stages of a sequential method for manufacturing a semiconductor device according to an embodiment of the present invention. In some embodiments, after removing the buffer layer 55, a metal layer 70 is formed over the exposed first metal dichalcogenide layer 15 in the contact window opening 20, such as Fig.17A and Fig. 17B As shown, to form source / drain contacts. As previously described, the metal layer removes hydrogen from the MXH film and replaces the hydrogen with a metal to form a film MXM2, where M is the metal of the metal chalcogenide film, X is a chalcogen, and M2 is an active metal. In some embodiments, the active metal forms an alloy with the metal of the metal chalcogenide film to form an alloy layer 105. In some embodiments, the active metal is selected from one or more of the group consisting of Ni, Mo, In, Ti, W, Sc, Pd, Pt, Co, and Ru.

[0067] In an embodiment, metal layer 70 is formed at a temperature ranging from 100°C to 300°C, or after forming metal layer 70, the device is heated to a temperature ranging from 100°C to 300°C (or annealed at a temperature ranging from 100°C to 300°C).

[0068] In some embodiments, the second metal layer is formed over the first metal layer 70 ( Fig.17A and Fig. 17B The second metal layer is made of a third metal having a lower activity than the second metal. In some embodiments, the second metal layer is made of Au, Pt, Cu or TiN.

[0069] like Fig.18A and Fig.18B As shown, a gate dielectric layer 80 is subsequently formed over the metal layer 70, the second metal chalcogenide film 25, the first metal chalcogenide film 15, and the substrate 10. A gate electrode layer 85 is then formed over the dielectric layer 80, and source / drain electrodes connected to the first metal layer 70 are formed to form a top gate heterostructure transistor.

[0070] In some embodiments, the gate dielectric layer 80 is a silicon oxide, such as silicon dioxide. In other embodiments, the gate dielectric layer 80 is one or more layers of silicon nitride or a high-k dielectric layer. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-k dielectric materials and / or combinations thereof. The gate dielectric layer 80 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or any suitable method.

[0071] The gate electrode 85 may be formed of any suitable conductive material, including polysilicon, graphene, and metal (including one or more layers of aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, nickel, manganese, silver, palladium, rhenium, iridium, ruthenium, platinum, and zirconium), tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode 85 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) (sputtering), electroplating, or other suitable methods.

[0072] Fig.19 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. In some embodiments, the channel region 110 includes a single metal dichalcogenide monolayer film 15. The source / drain region 120 includes a metal chalcogenide monolayer film MX 125, including a metal M other than oxygen and a chalcogen element X; an alloy layer 105, including an alloy of a first metal layer 70 and a metal chalcogen element monolayer film 125; a first metal layer 70; an alloy layer 135, including an alloy of the first metal layer 70 and a second metal layer 75; and a second metal layer 75.

[0073] Fig. 20is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. In some embodiments, the channel region 110 includes a plurality of metal dichalcogenide monolayer films 15a, 15b, 15c. The source / drain region 120 includes a plurality of metal dichalcogenide monolayer films 15a, 15b; a metal chalcogenide monolayer film MX 125 including a metal M other than oxygen and a chalcogen element X; an alloy layer 105 including an alloy of a first metal layer 70 and a metal chalcogen element monolayer film 125; a first metal layer 70; an alloy layer 135 including an alloy of a first metal layer 70 and a second metal layer 75; and a second metal layer 75. The number of metal dichalcogenide films in the channel region 110 is not limited to three, as shown in the figure, but may be four or more metal dichalcogenide films.

[0074] Fig.21 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. In some embodiments, the channel region 110 includes a single metal dichalcogenide monolayer film 15a. The source / drain region 120 includes a plurality of metal dichalcogenide monolayer films 15a, 15b; a metal chalcogenide monolayer film MX 125 including a metal M other than oxygen and a chalcogen element X; an alloy layer 105 including an alloy of a first metal layer 70 and a metal chalcogen element monolayer film 125; a first metal layer 70; an alloy layer 135 including an alloy of a first metal layer 70 and a second metal layer 75; and a second metal layer 75. The number of metal dichalcogenide films in the source / drain region 120 is not limited to two, as shown in the figure, but may be three or more metal dichalcogenide films.

[0075] Fig. 22 2 is a flow chart showing a method 200 of manufacturing a semiconductor device according to an embodiment of the present invention. The method 200 includes an operation S210 of applying plasma 90 to a portion of a metal dichalcogenide film 15. In some embodiments, the metal dichalcogenide film 15 includes a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. In operation S220, after applying the plasma 90, a metal layer 70 including a second metal is formed over the portion of the metal dichalcogenide film 15. In some embodiments, the plasma 90 is a hydrogen plasma. In some embodiments, the method includes an operation S230 of forming a second metal layer 75 including a third metal over the metal layer 70.

[0076] Fig.233 is a flow chart showing a method 300 for manufacturing a semiconductor device according to an embodiment of the present invention. The method 300 includes an operation S310 of forming a metal dichalcogenide film 15 over a substrate 10. In some embodiments, the metal dichalcogenide film 15 includes a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. In operation S320, a buffer layer 55 is then formed over the metal dichalcogenide film 15, and in operation S330, the buffer layer 55 is patterned to expose a portion of the metal dichalcogenide film 15. Then, in operation S340, the chalcogen is plasma stripped from a surface layer 65 of the exposed portion of the metal dichalcogenide film 15. In operation S350, after the plasma stripping, a metal layer 70 including a second metal is formed over the exposed portion of the metal dichalcogenide film 15. In some embodiments, the plasma stripping is performed at a plasma pressure ranging from 10 mTorr to 500 mTorr and a power ranging from 10 W to 150 W. In some embodiments, in operation S360, a second metal layer 75 including a third metal is formed over the metal layer 70. The third metal is less active than the second metal.

[0077] Fig.24 4 is a flow chart showing a method 400 for manufacturing a semiconductor device according to an embodiment of the present invention. The method includes an operation S410 of forming a first metal ditin disulfide monolayer film 15 over a substrate 10, and an operation S420 of forming a second metal dichalcogenide monolayer film 25 over the first metal dichalcogenide monolayer film 15. The first metal dichalcogenide film 15 and the second metal dichalcogenide film 25 include a first metal and a chalcogen element selected from the group consisting of S, Se, Te, and a combination thereof. In operation S430, the second metal dichalcogenide monolayer film 25 is patterned to expose a portion of the first metal dichalcogenide monolayer film 15. Subsequently, plasma 90 is applied to the exposed portion of the first metal dichalcogenide monolayer film 15 in operation S440. Then, in operation S450, after applying the plasma 90, a metal layer 70 including a second metal is formed over the exposed portion of the first metal dichalcogenide monolayer film 15. In some embodiments, method 500 includes operation S460 of forming a buffer layer 55 over the second metal dichalcogenide monolayer film 25 before patterning the second dichalcogenide monolayer. In some embodiments, method 400 includes forming a second metal layer 75 including a third metal over metal layer 70 .

[0078] Fig.25is a flow chart showing a method 500 of manufacturing a semiconductor device according to an embodiment of the present invention. The method 500 includes an operation S510 of replacing a chalcogenide element of a metal chalcogenide film 15 with hydrogen to form a metal chalcogenide having a surface layer including hydrogen. The metal chalcogenide film 15 includes a first metal and a chalcogenide element selected from the group consisting of S, Se, Te, and combinations thereof. Then, in operation S520, hydrogen of a surface layer 65 of the metal chalcogenide is replaced by a second metal to form a metal chalcogenide film having a surface layer 105 including the second metal. In some embodiments, the method 50 includes forming the metal chalcogenide film 15 over the semiconductor substrate 10 before replacing the chalcogen element in operation S530. In some embodiments, the method 500 includes forming a buffer layer 55 over the metal chalcogenide film 15 before replacing the chalcogen element in operation S540. In some embodiments, replacing the chalcogenide element of the metal chalcogenide film with hydrogen includes applying a hydrogen plasma 90 to the metal chalcogenide film 15. In some embodiments, the hydrogen plasma is applied at a plasma pressure ranging from 10 mTorr to 500 mTorr and a power ranging from 10 W to 150 W. In some embodiments, the first metal is one or more selected from the group consisting of Mo, W, Pd, and Hf. In some embodiments, the second metal is one or more selected from the group consisting of Ni, Mo, In, Ti, W, Sc, Pd, Pt, Co, and Ru. In some embodiments, the method 500 includes an operation S550 of forming a second metal layer 75 including a third metal over the metal layer 70, wherein the third metal is less active than the second metal.

[0079] It should be understood that the semiconductor device undergoes further manufacturing processes to form various features, such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc. Other operations performed on the semiconductor device may include photolithography, etching, chemical mechanical polishing, thermal processing (including rapid thermal annealing), deposition, doping (including ion implantation), photoresist ashing, and liquid solvent cleaning.

[0080] According to the metal alloy interface structure of the present invention, in some embodiments, defect formation at the interface is reduced and the Fermi level pinning effect is prevented. The metal alloy interface structure of the present invention enables a higher current density through the metal to the channel. In an embodiment of the present invention, the transmission of electrons from the metal contact to the metal chalcogenide MX2 layer will not encounter any van der Waals gap. Therefore, the seamless alloy edge contact structure reduces the contact resistance.

[0081] It should be understood that not all advantages are necessarily discussed herein, no particular advantage is required in all embodiments, and other embodiments or examples may provide different advantages.

[0082] An embodiment of the present invention is a method for manufacturing a semiconductor device, comprising applying plasma to a portion of a metal dichalcogenide film. The metal dichalcogenide film comprises a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. After applying the plasma, a metal layer comprising a second metal is formed over the portion of the metal dichalcogenide film. In an embodiment, the plasma is a hydrogen plasma. In an embodiment, the pressure of the plasma is in a range from 10mTorr to 500mTorr, and the plasma is applied at a power in a range from 10W to 150W. In an embodiment, the first metal is one or more selected from the group consisting of Mo, W, Pd, and Hf. In an embodiment, the second metal is one or more selected from the group consisting of Ni, Mo, In, Ti, W, Sc, Pd, Pt, Co, and Ru. In an embodiment, the metal layer is formed at a temperature in a range from 100°C to 300°C, or the device is heated to a temperature in a range from 100°C to 300°C after forming the metal layer. In an embodiment, the method comprises forming a second metal layer comprising a third metal over the metal layer. In an embodiment, the third metal is less active than the second metal. In an embodiment, the third metal is one or more selected from the group consisting of Au, Pt, Cu and TiN. In an embodiment, the second metal layer has a thickness in the range from 10nm to 100nm. In an embodiment, the first metal layer has a thickness in the range from 1nm to 25nm.

[0083] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising forming a metal dichalcogenide film over a substrate, wherein the metal dichalcogenide film comprises a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. A buffer layer is formed over the metal dichalcogenide film. The buffer layer is patterned to expose a portion of the metal dichalcogenide film. The chalcogen is plasma stripped from a surface layer of the exposed portion of the metal dichalcogenide film. After the plasma stripping, a metal layer comprising a second metal is formed over the exposed portion of the metal dichalcogenide film. In an embodiment, the buffer layer is a photoresist layer or an oxide layer. In an embodiment, the plasma stripping comprises replacing the chalcogen in the surface layer of the exposed portion of the metal dichalcogenide film with hydrogen. In an embodiment, forming the metal layer comprises replacing hydrogen with a second metal. In an embodiment, the plasma stripping is performed at a plasma pressure ranging from 10 mTorr to 500 mTorr and a power ranging from 10 W to 150 W. In an embodiment, the first metal is one or more selected from the group consisting of Mo, W, Pd, and Hf. In an embodiment, the second metal is one or more selected from the group consisting of Ni, Mo, In, Ti, W, Sc, Pd, Pt, Co and Ru. In an embodiment, the method includes forming a second metal layer including a third metal above the metal layer, wherein the activity of the third metal is less than the second metal. In an embodiment, the third metal is one or more selected from the group consisting of Au, Pt, Cu and TiN. In an embodiment, the second metal layer has a thickness ranging from 10nm to 100nm. In an embodiment, the first metal layer has a thickness ranging from 1nm to 25nm. In an embodiment, the metal dichalcogenide film includes a metal dichalcogenide selected from the group consisting of WS2, MoS2, WSe2, MoSe2, WTe2 and MoTe2. In an embodiment, the substrate includes silicon, silicon oxide or aluminum oxide.

[0084] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising forming a first metal dichalcogenide monolayer film over a substrate, and forming a second metal dichalcogenide monolayer film over the first metal dichalcogenide monolayer film. The first and second metal dichalcogenide films include a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. The second metal dichalcogenide monolayer film is patterned to expose a portion of the first metal dichalcogenide monolayer film. Plasma is applied to the exposed portion of the first metal dichalcogenide monolayer film. After applying the plasma, a metal layer including the second metal is formed over the exposed portion of the first metal dichalcogenide monolayer film. In an embodiment, the method includes forming a buffer layer over the second metal dichalcogenide monolayer film before patterning the second dichalcogenide monolayer. In an embodiment, the plasma is a hydrogen plasma. In an embodiment, the pressure of the plasma is in a range from 10 mTorr to 500 mTorr, and the plasma is applied at a power in a range from 10 W to 150 W. In an embodiment, the first metal is one or more selected from the group consisting of Mo, W, Pd and Hf. In an embodiment, the second metal is one or more selected from the group consisting of Ni, Mo, In, Ti, W, Sc, Pd, Pt, Co and Ru. In an embodiment, the metal layer is formed at a temperature ranging from 100°C to 300°C, or the device is heated to a temperature ranging from 100°C to 300°C after forming the metal layer. In an embodiment, the method includes forming a second metal layer including a third metal above the metal layer. In an embodiment, the activity of the third metal is less than that of the second metal. In an embodiment, the third metal is one or more selected from the group consisting of Au, Pt, Cu and TiN.

[0085] Another embodiment is a method of manufacturing a semiconductor device, comprising forming a first metal dichalcogenide monolayer film over a substrate, and forming a second metal dichalcogenide monolayer film over the first metal dichalcogenide monolayer film. The first and second metal dichalcogenide films include a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. A first portion of the second metal dichalcogenide monolayer film is removed to expose a first portion of the first metal dichalcogenide monolayer film. Plasma is applied to a second portion of the second metal dichalcogenide monolayer film. After applying the plasma, a metal layer including the second metal is formed over the second portion of the second metal dichalcogenide monolayer film. In an embodiment, the first portion of the first metal dichalcogenide monolayer film is a channel region of a semiconductor device. In an embodiment, the second portion of the second metal dichalcogenide monolayer film is a source / drain region of a semiconductor device. In an embodiment, the plasma is a hydrogen plasma. In an embodiment, the pressure of the plasma is in a range from 10 mTorr to 500 mTorr, and the plasma is applied at a power in a range from 10 W to 150 W. In an embodiment, the first metal and the second metal are different metals. In an embodiment, the first metal is one or more selected from the group consisting of Mo, W, Pd and Hf. In an embodiment, the second metal is one or more selected from the group consisting of Ni, Mo, In, Ti, W, Sc, Pd, Pt, Co and Ru. In an embodiment, the metal layer is formed at a temperature ranging from 100°C to 300°C, or the device is heated to a temperature ranging from 100°C to 300°C after the metal layer is formed. In an embodiment, the method includes forming a second metal layer including a third metal above the metal layer. In an embodiment, the activity of the third metal is less than that of the second metal. In an embodiment, the third metal is one or more selected from the group consisting of Au, Pt, Cu and TiN.

[0086] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising: replacing a chalcogen of a metal chalcogenide film with hydrogen to form a metal chalcogenide having a surface layer containing hydrogen. The metal chalcogenide film comprises a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. Replacing hydrogen of the surface layer of the metal chalcogenide with a second metal to form a metal chalcogenide film having a surface layer comprising the second metal. In an embodiment, the method comprises forming a metal chalcogenide film over a semiconductor substrate before replacing the chalcogen. In an embodiment, the method comprises forming a buffer layer over the metal chalcogenide film before replacing the chalcogen. In an embodiment, the buffer layer is a photoresist layer or an oxide layer. In an embodiment, the oxide layer comprises silicon oxide or aluminum oxide. In an embodiment, replacing the chalcogen of the metal chalcogenide film with hydrogen comprises applying a hydrogen plasma to the metal chalcogenide film. In an embodiment, the hydrogen plasma is applied at a plasma pressure ranging from 10 mTorr to 500 mTorr and a power ranging from 10 W to 150 W. In an embodiment, the first metal is one or more selected from the group consisting of Mo, W, Pd and Hf. In an embodiment, the second metal is one or more selected from the group consisting of Ni, Mo, In, Ti, W, Sc, Pd, Pt, Co and Ru. In an embodiment, the method includes forming a second metal layer including a third metal over the metal layer, wherein the third metal is less active than the second metal.

[0087] Another embodiment of the present invention is a method for manufacturing a semiconductor device, the method comprising forming a metal dichalcogenide film over a substrate, wherein the metal dichalcogenide film comprises a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. A buffer layer is formed over the metal dichalcogenide film. The buffer layer is patterned to expose a portion of the metal dichalcogenide film. The chalcogen in the surface layer of the exposed portion of the metal dichalcogenide film is replaced with hydrogen, and the hydrogen in the surface layer of the exposed portion of the metal dichalcogenide film is replaced with a second metal different from the first metal. In an embodiment, the buffer layer is a photoresist layer or an oxide layer. In an embodiment, the oxide layer comprises silicon oxide or aluminum oxide. In an embodiment, replacing the chalcogen in the surface layer of the exposed portion of the metal dichalcogenide film with hydrogen comprises applying hydrogen plasma to the metal dichalcogenide film. In an embodiment, the hydrogen plasma is applied at a plasma pressure ranging from 10 mTorr to 500 mTorr and a power ranging from 10 W to 150 W. In an embodiment, the first metal is one or more selected from the group consisting of Mo, W, Pd, and Hf. In an embodiment, the second metal is one or more selected from the group consisting of Ni, Mo, In, Ti, W, Sc, Pd, Pt, Co and Ru. In an embodiment, the method includes forming a second metal layer including a third metal over the metal layer, wherein the third metal is less active than the second metal. In an embodiment, the third metal is selected from the group consisting of Au, Pt, Cu and TiN.

[0088] Another embodiment of the present invention is a semiconductor device, comprising a metal chalcogenide monolayer film disposed over a substrate, wherein the metal chalcogenide monolayer film comprises a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. The metal chalcogenide monolayer film has a first surface portion and a second surface portion. A metal layer is disposed over the metal chalcogenide film, wherein the metal layer comprises a second metal. The metal layer is disposed over the first surface portion and not over the second surface portion, and the metal layer is chemically bonded to the metal chalcogenide film. In an embodiment, the first metal is one or more selected from the group consisting of Mo, W, Pd, and Hf. In an embodiment, the second metal is one or more selected from the group consisting of Ni, Mo, In, Ti, W, Sc, Pd, Pt, Co, and Ru. In an embodiment, a second metal layer comprising a third metal is disposed over the metal layer. In an embodiment, the activity of the third metal is less than that of the second metal. In an embodiment, the third metal is one or more selected from the group consisting of Au, Pt, Cu, and TiN. In an embodiment, the second metal layer has a thickness ranging from 10 nm to 100 nm. In an embodiment, the first metal layer has a thickness ranging from 1 nm to 25 nm. In an embodiment, the metal dichalcogenide film comprises W or Mo. In an embodiment, the substrate comprises silicon, silicon oxide, or aluminum oxide.

[0089] Another embodiment of the present invention is a semiconductor device, comprising a first metal chalcogenide monolayer film disposed over a substrate. A second metal chalcogenide monolayer film is disposed over the first metal chalcogenide monolayer film. The first and second metal chalcogenide monolayer films each include a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. The second metal chalcogenide monolayer film is patterned so that a portion of the first metal chalcogenide monolayer film is exposed through a patterned portion of the second metal chalcogenide monolayer film. A metal layer is disposed over a portion of the first metal chalcogenide monolayer film exposed through the second metal chalcogenide monolayer film, wherein the metal layer includes a second metal, and the metal layer is chemically bonded to the first metal chalcogenide monolayer film. In an embodiment, the first metal is one or more selected from the group consisting of Mo, W, Pd, and Hf. In an embodiment, the second metal is one or more selected from the group consisting of Ni, Mo, In, Ti, W, Sc, Pd, Pt, Co, and Ru. In an embodiment, the semiconductor device includes a second metal layer, the second metal layer including a third metal disposed over the metal layer. In an embodiment, the third metal is less active than the second metal. In an embodiment, the third metal is one or more selected from the group consisting of Au, Pt, Cu and TiN. In an embodiment, the second metal layer has a thickness ranging from 10nm to 100nm. In an embodiment, the first metal layer has a thickness ranging from 1nm to 25nm.

[0090] Another embodiment of the present invention is a semiconductor device, comprising a channel region disposed above a first region of a semiconductor substrate, wherein the channel region comprises one or more metal dichalcogenide monolayers. A source / drain region is disposed above a second region of the semiconductor substrate, wherein the second region of the semiconductor substrate is located on an opposite side of the first region of the semiconductor substrate. The source / drain region comprises one or more metal chalcogenide monolayers. Each of the metal chalcogenide monolayers comprises a first metal and a chalcogen selected from the group consisting of S, Se, Te, and combinations thereof. A metal layer comprising a second metal is disposed above the source / drain region, and the metal layer is chemically bonded to the metal chalcogenide film in the second region. In an embodiment, the first metal is one or more selected from the group consisting of Mo, W, Pd, and Hf. In an embodiment, the second metal is one or more selected from the group consisting of Ni, Mo, In, Ti, W, Sc, Pd, Pt, Co, and Ru. In an embodiment, the semiconductor device comprises a second metal layer, the second metal layer comprising a third metal disposed above the metal layer. In an embodiment, the activity of the third metal is less than that of the second metal. In an embodiment, the third metal is one or more selected from the group consisting of Au, Pt, Cu and TiN. In an embodiment, the second metal layer has a thickness in the range of from 10nm to 100nm. In an embodiment, the first metal layer has a thickness in the range of from 1nm to 25nm. In an embodiment, the channel region is formed by a single metal dichalcogenide monolayer, and the source / drain region includes two or more metal dichalcogenide monolayers. In an embodiment, the channel region is formed by two or more metal dichalcogenide monolayers, and the source / drain region is formed by a single metal dichalcogenide monolayer. In an embodiment, the metal dichalcogenide film includes a metal dichalcogenide selected from the group consisting of WS2, MoS2, WSe2, MoSe2, WTe2 and MoTe2. In an embodiment, the semiconductor substrate includes silicon, silicon oxide or aluminum oxide. In an embodiment, the metal dichalcogenide film has a thickness of 0.5nm to 10nm.

[0091] The features of several embodiments or examples are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also appreciate that this equivalent construction does not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and changes herein without deviating from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: applying a plasma to a portion of the metal dichalcogenide film, wherein the metal dichalcogenide film comprises a first metal and a chalcogen element selected from the group consisting of S, Se, Te and a combination thereof; After applying the plasma, forming a first metal layer over a portion of the metal dichalcogenide film, wherein the first metal layer is a layer of one or more second metals selected from the group consisting of Ni, Mo, In, Ti, W, Sc, Pd, Pt, Co and Ru; and forming a second metal layer including a third metal over the first metal layer, wherein the third metal is less active than the one or more second metals.

2. The method according to claim 1, wherein: The plasma is hydrogen plasma.

3. The method according to claim 1, wherein: The pressure of the plasma ranges from 10 mTorr to 500 mTorr, and the plasma is applied at a power ranging from 10 W to 150 W.

4. The method according to claim 1, wherein: The first metal is one or more selected from the group consisting of Mo, W, Pd and Hf.

5. The method according to claim 1, further comprising: A gate dielectric layer is formed over the second metal layer.

6. The method according to claim 1, wherein: The first metal layer is formed at a temperature ranging from 100° C. to 300° C., or the semiconductor device is heated to a temperature ranging from 100° C. to 300° C. after forming the first metal layer.

7. The method according to claim 5, wherein: The gate dielectric layer is an oxide layer. 8 . The method according to claim 5 , further comprising forming a gate electrode layer over the gate dielectric layer.

9. The method according to claim 8, wherein: The third metal is one or more selected from the group consisting of Au, Pt, Cu and TiN.

10. The method according to claim 7, wherein: The second metal layer has a thickness ranging from 10 nm to 100 nm.

11. The method according to claim 1, wherein: The first metal layer has a thickness ranging from 1 nm to 25 nm.

12. A method for manufacturing a semiconductor device, comprising: forming a metal dichalcogenide film over the substrate, wherein the metal dichalcogenide film comprises a first metal and a chalcogen element selected from the group consisting of S, Se, Te and a combination thereof; forming a buffer layer over the metal dichalcogenide film; patterning the buffer layer to expose portions of the metal dichalcogenide film; plasma stripping the chalcogen from a surface layer of an exposed portion of the metal dichalcogenide film; and forming a first metal layer over the exposed portion of the metal dichalcogenide film after the plasma stripping, wherein the first metal layer is a layer of one or more second metals selected from the group consisting of Ni, Mo, In, Ti, W, Sc, Pd, Pt, Co and Ru; and forming a second metal layer including a third metal over the first metal layer, wherein the third metal is less active than the one or more second metals.

13. The method according to claim 12, wherein: The buffer layer is a photoresist layer or an oxide layer.

14. The method according to claim 12, wherein: The plasma stripping includes replacing chalcogen in a surface layer of an exposed portion of the metal dichalcogenide film with hydrogen.

15. The method according to claim 14, wherein: Forming the first metal layer includes replacing hydrogen with the second metal.

16. The method according to claim 12, wherein: The plasma stripping is performed at a plasma pressure ranging from 10 mTorr to 500 mTorr and at a power ranging from 10 W to 150 W.

17. The method according to claim 12, wherein: The first metal is one or more selected from the group consisting of Mo, W, Pd and Hf.

18. The method according to claim 12, further comprising: A gate dielectric layer is formed over the second metal layer. 19 . The method of claim 18 , further comprising forming a gate electrode layer over the gate dielectric layer.

20. A semiconductor device comprising: A metal chalcogenide monolayer film disposed above a substrate, wherein the metal chalcogenide monolayer film comprises a first metal and a chalcogen element selected from the group consisting of S, Se, Te and a combination thereof, and wherein the metal chalcogenide monolayer film has a first surface portion and a second surface portion; A first metal layer is disposed above the metal chalcogenide monolayer film, wherein the first metal layer is a layer of one or more second metals selected from the group consisting of Ni, Mo, In, Ti, W, Sc, Pd, Pt, Co and Ru; and a second metal layer disposed above the first metal layer and including a third metal, wherein the activity of the third metal is less than that of the one or more second metals, The first metal layer is disposed over the first surface portion and not over the second surface portion, and The first metal layer is chemically bonded to the metal chalcogenide monolayer film.

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