Semiconductor package and method of manufacturing the same

Abstract

The semiconductor package includes: a semiconductor chip disposed above a first main surface of a first substrate; a package cover disposed above the semiconductor chip; and a spacer extending from the package cover through a corresponding hole in the first substrate. The spacer enters the hole at the first main surface of the first substrate and extends beyond the opposite second main surface of the first substrate. Embodiments of the present application also relate to a method for manufacturing a semiconductor package.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor package and a method for manufacturing the same. Background Art

[0002] As the demand for computing speed and heterogeneous integration increases, more and more silicon chips are assembled into a single package. As a result, multi-chip package size (>4000mm 2 ) and weight continue to increase. During the surface mount technology (SMT) process, heavier packages may cause the ball grid array (BGA) to distort because the melted solder bumps of the BGA may not be able to support the weight of the package. If the BGA is severely deformed so that adjacent solder bumps touch, bridging may occur and may cause an electrical short. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor package, comprising: a semiconductor chip, disposed above a first main surface of a first substrate; a packaging cover, disposed above the semiconductor chip; and a spacer, extending from the packaging cover through a corresponding hole in the first substrate, wherein the spacer enters the hole at the first main surface of the first substrate and extends beyond the opposite second main surface of the first substrate.

[0004] Other embodiments of the present application provide a semiconductor package, comprising: a semiconductor chip, disposed above a first main surface of a first substrate; a ring-shaped or frame-shaped packaging cover, having an opening and disposed above the semiconductor chip; a second substrate, disposed below the first substrate; and a spacer, extending from the packaging cover through a corresponding hole in the first substrate, wherein the spacer enters the hole at the first main surface of the first substrate, and extends beyond the opposite second main surface of the first substrate and contacts the main surface of the second substrate.

[0005] Still other embodiments of the present application provide a method for manufacturing a semiconductor package, the method comprising: positioning a package cover over a chip disposed above a first main surface of a first substrate, wherein the package cover has a plurality of spacers extending from a periphery of the package cover, and the first substrate has a plurality of holes corresponding to the plurality of spacers; and positioning the spacers in the holes so that the spacers pass through the first main surface of the first substrate and extend beyond a second relative main surface of the first substrate to form a packaged semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 One of various stages in sequential fabrication operations for a semiconductor device package in accordance with an embodiment of the present invention is shown.

[0008] Figure 2A and Figure 2B One of various stages in sequential fabrication operations for a semiconductor device package in accordance with an embodiment of the present invention is shown.

[0009] Figure 3 One of various stages in sequential fabrication operations for a semiconductor device package in accordance with an embodiment of the present invention is shown.

[0010] Figure 4 One of various stages in sequential fabrication operations for a semiconductor device package in accordance with an embodiment of the present invention is shown.

[0011] Figure 5A and Figure 5B One of various stages in sequential fabrication operations for a semiconductor device package in accordance with an embodiment of the present invention is shown.

[0012] Figure 6 One of various stages in sequential fabrication operations for a semiconductor device package in accordance with an embodiment of the present invention is shown.

[0013] Fig. 7A and Figure 7B A semiconductor device package according to an embodiment of the present invention is shown.

[0014] Fig. 8A and Figure 8B A semiconductor device package according to an embodiment of the present invention is shown.

[0015] Fig. 9A , Fig. 9B , Fig. 9C and Fig.9D Components of a semiconductor device package according to an embodiment of the present invention are shown.

[0016] Fig. 10A and Fig. 10B One of various stages in sequential fabrication operations for a semiconductor device package in accordance with an embodiment of the present invention is shown.

[0017] Fig. 10C and Fig. 10DComponents of a semiconductor device package according to an embodiment of the present invention are shown.

[0018] Fig.11A and Fig. 11B One of various stages in sequential manufacturing operations of a semiconductor device package in accordance with an embodiment of the present invention is shown.

[0019] Fig.12 One of various stages in sequential fabrication operations for a semiconductor device package in accordance with an embodiment of the present invention is shown.

[0020] Fig.13 A semiconductor device package according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various embodiments. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Moreover, for ease of description, spatially relative terms such as "under," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component as shown in the figure to another (or other) originals or components. In addition to the orientation shown in the figure, spatially relative terms are intended to include different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, the term "made of" can mean "including" or "consisting of." In the present invention, the phrase "one of A, B and C" means "A, B and / or C" (A, B, C, A and B, A and C, B and C or A, B and C), and does not mean one element from A, one element from B and one element from C unless otherwise specified.

[0023] The package for the semiconductor device includes a plurality of materials having different coefficients of thermal expansion (CTE). Therefore, due to the mismatch of the thermal expansion coefficients, the package may bend during the surface mount technology process. In particular, when the mismatch of the thermal expansion coefficients between the package cover and the substrate of the package is large, the package is prone to bend. In some embodiments, the package cover of the package is made of a material having a thermal expansion coefficient of about 17×10 -6 C -1 The package substrate is made of Cu with a thermal expansion coefficient of about 10×10 -6 C -1 The thermal expansion coefficient of the polymer material is high at high temperatures. In this case, the substrate bends toward the package cover (crying face warping), and the bent substrate squeezes the melted solder bumps set on the back side of the package substrate close to each other, especially the solder bumps at the corners of the BGA. When the BGA is deformed, adjacent solder bumps may contact and cause bridging, resulting in unnecessary short circuits.

[0024] On the other hand, if the thermal expansion coefficient of the package substrate is higher than that of the package lid, the opposite state (smiley face warping) of the package concave toward the package lid will occur during the surface mounting process. In this case, the center solder bump may form a bridge.

[0025] Embodiments of the present invention provide a spacer structure that prevents BGA deformation and prevents solder ball bridging. Some embodiments of the present invention are directed to three-dimensional (3D) IC package technology, including integrated fan-out (InFO) packages, chip-on-wafer-on-substrate (CoWoS) packages, and multi-chip modules (MCMs). Other suitable packages are used in some embodiments. In some embodiments, it is desirable to maintain a uniform gap between the package substrate and the printed circuit board (PCB) during the entire surface mounting process.

[0026] Figures 1 to 6 1 shows sequential manufacturing operations of a semiconductor device package according to an embodiment of the present invention. It should be understood that Figures 1 to 6 Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the methods. The order of the operations / processes may be interchanged.

[0027] like Figure 1As shown, the semiconductor chip 15 is molded over the package substrate 50. In some embodiments, the semiconductor chip 15 is an integrated fan-out chip, a system on chip, a wafer-level chip scale package, or a chip on a wafer on a substrate. In some embodiments, the semiconductor chip 15 is placed on a lead frame or connected to a redistribution layer (wire) 20. In some embodiments, the package is a flip chip package, and the semiconductor chip 15 is embedded in a molding 25 such as a thermosetting resin. In addition, the lead frame or the redistribution layer 20 is connected to the conductive pillars or solder bumps 30.

[0028] The redistribution layer 20 is formed by one or more metal layers and one or more intermetallic dielectric layers. The intermetallic dielectric layer is disposed between the metal layers. Conductive components such as vias are disposed in the dielectric material of the intermetallic dielectric layer, and conductive components such as traces or wiring in the metal layer must be connected. In some embodiments, the dielectric material is, for example, silicon oxide, nitride, carbide, polymer or other insulating or dielectric material, and can be formed using chemical vapor deposition (CVD), spin coating or other deposition processes. Conductive components can be formed using a damascene or dual damascene process, in which an opening is etched in the dielectric layer of the redistribution layer 20, and a conductive material such as copper, aluminum, etc. is deposited in the opening and then flattened. The redistribution layer is established by forming multiple metal layers and intermetallic dielectric layers, in which traces and vias are electrically connected from the conductive structure wiring on the package substrate 50, and then the semiconductor chip 15 is set to the top surface of the redistribution layer 20 on the package substrate 50.

[0029] The package substrate 50 has a first main surface 50A on which the semiconductor chip is attached via posts or solder bumps 30 on the redistribution layer 20, and a second main surface 50B including a solder ball array (ball grid array) 55. In some embodiments, conductive vias or wiring layers are formed in the package substrate 50 to electrically connect the posts or solder bumps 30 on the redistribution layer to the solder balls 55 on the second main surface 50B of the substrate 50. In some embodiments, the package substrate 50 is made of an insulating material, such as a resin or ceramic.

[0030] The semiconductor chip 15 with the lead frame or redistribution layer 20 is attached to the package substrate by the bottom fill material 60. The bottom fill material 60 is applied to the side of the molding 25 and the space below the bottom of the semiconductor chip 15 and the bottom of the package substrate 50 and the upper surface of the package substrate 50. The bottom fill material 60 fills the area between the pillars or solder bumps 30. In some embodiments, the bottom fill material 60 is also disposed on the side of the semiconductor substrate 15. In some embodiments, the bottom fill material 60 is an epoxy resin, such as a silicon dioxide-filled epoxy resin, polyimide or other suitable insulating material. The bottom fill material 60 improves mechanical reliability by distributing stress on the top of the package substrate 50 instead of concentrating stress in the pillars or solder bumps 30. In addition, the bottom fill material 60 provides a sealing effect against moisture and contaminants in the external environment.

[0031] In some embodiments, a thermal interface material (TIM) 85 is disposed over the semiconductor chip 15. The thermal interface material 85 includes a solder material, such as a tin-containing alloy (e.g., PbSn, AgSn, SnAgCu, CuSnNi, AgCuSbSn, AuSn, and / or CuSn). In some embodiments, the PbSn solder has a thermal conductivity of about 50 W / mK, the AgSn solder has a thermal conductivity of about 78 W / mK, the SnAgCu solder has a thermal conductivity of about 60 W / mK, the CuSnNi has a thermal conductivity of about 64 W / mK, the AgCuSbSn solder has a thermal conductivity of about 57 W / mK, the AuSn solder has a thermal conductivity of about 57 W / mK, and the CuSn solder has a thermal conductivity of about 65 W / mK. In some embodiments, a pad layer (not shown) is formed between the semiconductor chip 15 and the thermal interface material 85. In some embodiments, the pad layer is formed of a suitable conductive metal including aluminum, copper, silver, gold, nickel, tungsten, titanium, alloys thereof, and / or multilayers thereof.

[0032] In some embodiments, the thermal interface material 85 is a thermally conductive gel, paste, pad, grease, or phase change material having a thermal conductivity between about 0.5 W / mK and 10 W / mK. In some embodiments, the thermal grease can be a ceramic or metal such as beryllium oxide, aluminum nitride, aluminum oxide, zinc oxide, silver, aluminum, etc. suspended in a silicone-based gel. In some embodiments, the thermal interface material 85 is a liquid metal paste of a gallium alloy, or a metal alloy pad that is reflowed to attach the thermal interface material to a surface. In some embodiments, the thermal interface material is a non-conductive ceramic-based paste filled with ceramic powders such as beryllium oxide, aluminum nitride, aluminum oxide, or zinc oxide.

[0033] like Figure 2A and Figure 2BAs shown, the package cover 65 is then placed over the package substrate with the semiconductor chip 15. The package cover 65 serves as a heat sink to dissipate the heat generated by the semiconductor chip 15. The package cover 65 is made of a thermally conductive material. In some embodiments, the package cover is made of aluminum, copper, nickel, cobalt, and alloys thereof or other thermally conductive materials. In some embodiments, the package cover 65 is made of a Cu alloy such as CuMo, CuW, or CuBe. In some embodiments, the package cover is made of a composite material, including ceramics, silicon carbide, aluminum nitride, graphite, etc.

[0034] like Figure 2A As shown in 2A (cross-sectional view) and 2B (stereoscopic view), the package cover 65 includes a top 65A and a wall portion 65B, and a plurality of spacers 70 further extending from the bottom of the wall portion 65B. The spacers 70 are formed integrally with the package cover 65 as one element. In some embodiments, the package cover 65 has a square shape in a plan view. Figure 2A and Figure 2B As shown, a plurality of through holes 75 are formed in the package substrate 50 from the front side 50A to the back side 50B to respectively accommodate a plurality of spacers 70. In some embodiments, the through holes 75 are made by a standard drilling process or a laser drilling process. The height of the wall portion 65B is in the range of about 0.5 mm to 5 mm, and the thickness of the wall portion 65B is in the range of about 1 mm to 10 mm.

[0035] In some embodiments, spacers 70 are disposed at the four corners of the wall portion, and one or more spacers are disposed between the corner spacers along the side of the wall portion 65B. In some embodiments, one spacer is disposed between the corner spacers at the center of each side (the total number of spacers is 8). In other embodiments, two spacers are disposed between the corner spacers at equal intervals between the spaces including the corner spacers at each side (the total number of spacers is 12). The number of spacers 70 is not limited, and in some embodiments, 3-20 spacers are disposed between the corner spacers at each side of the wall portion 65B. In some embodiments, the number of spacers 70 and the spacing (pitch) of each side are the same. In some embodiments, there are no spacers at the corners of the wall portion 65B.

[0036] In some embodiments, the pitch of the spacers 70 is greater than the pitch of the ball grid array 55. In some embodiments, the pitch of the ball grid array is in the range of about 200 μm to about 800 μm. In some embodiments, the pitch of the spacers 70 is in the range of about 1 mm to about 10 mm, and in other embodiments in the range of about 2 mm to about 5 mm.

[0037] When the shape of the package cover (in plan view) is rectangular (not square), the number of spacers 70 on each side is different between the short side and the long side. In some embodiments, the number of spacers 70 on each side is the same for the short side and the long side. In some embodiments, the spacers 70 are arranged at the same interval (pitch) for both the short side and the long side, and in other embodiments, the interval of the spacers 70 at the short side is different from the interval at the long side.

[0038] In some embodiments, the spacer 70 has a cylindrical shape with a circular cross section. In other embodiments, the cross-sectional shape is a rectangle including a square, an ellipse, or a polygon (e.g., a hexagon). The cross-sectional shape of the spacer matches the cross-sectional shape of the through hole 75 in the package substrate. The tolerance of the spacer 70 and the through hole 75 is maintained so that the spacer 70 and the through hole 75 fit tightly. In some embodiments, the diameter of the spacer 70 is in the range of about 100 μm to about 2 mm. In other embodiments, in the range of about 500 μm to about 1 mm. In some embodiments, the diameter of the spacer 70 is 0.5%-5% larger than the diameter of the through hole. In some embodiments, the diameter of the spacer is about 1 μm to about 10 μm larger than the diameter of the through hole 75. When the diameter of the spacer is larger than the diameter of the through hole 75, the package substrate 50 is made of a softer or softer material than the spacer 70 so that the spacer 70 is press-fitted into the through hole 75.

[0039] In other embodiments, the diameter of the spacer 70 is equal to or smaller than the diameter of the through hole. In some embodiments, the diameter of the spacer 70 is 0.5%-5% smaller than the diameter of the through hole. In some embodiments, the diameter of the spacer is about 10 μm to about 50 μm smaller than the diameter of the through hole 75.

[0040] In some embodiments, the diameter of spacer 70 is equal to or less than the thickness of wall 65B. In some embodiments, the diameter of spacer 70 is about 30% to about 100% of the thickness of wall 65B, and in other embodiments, in the range of about 50% to about 80% of the thickness of wall 65B.

[0041] The height of the spacer 70 is greater than the thickness of the package substrate 50, so that when the package cover 65 is assembled to the package substrate 50, the spacer 70 extends beyond the back surface 50B of the package substrate 50. In some embodiments, the protrusion amount D1 of the spacer 70 from the back surface 50B (see Figure 5A ) is equal to or less than the thickness D2 of the solder ball 55.

[0042] Then, if Figure 3 As shown, the package cover 65 is attached to the package substrate 50 by inserting the spacer 70 into the through hole 75. In some embodiments, the package cover 65 is press-fitted to the package substrate 50.

[0043] Then, the package lid 65 is heated and pressed into close contact with the semiconductor chip 15 via the solder layer (thermal interface material) 85, such as by using a thermocompression bonding head 72, as shown in FIG. Figure 4 As shown, a semiconductor device having a package cover 65 bonded to the chip 15 and the package substrate 50 is obtained, as shown in FIG. Figure 5A (Cross-section) and Figure 5B (stereoscopic image) shown.

[0044] During the application of heat and pressure to the package cover 65, the solder layer (thermal interface material) 85 flows to form a continuous and substantially flat solder layer between the package cover 65 and the chip 15. The thermocompression bonding head 72 heats the solder layer 85 to a temperature of about 150°C to about 400°C. In some embodiments, the solder layer 85 is heated to a temperature of about 200°C to about 300°C. In an embodiment, the solder layer 85 is heated to a temperature of about 250°C. In some embodiments, a pressure in the range of about 50 kPa to about 20 MPa is applied while pressing the package cover 65 to contact the semiconductor chip 15. In some embodiments, the applied pressure is in the range of about 300 kPa to about 3 MPa. In some embodiments, the applied pressure is in the range of about 500 KPa to about 2 MPa. The continuous solder layer 85 serves as an improved thermal interface material (TIM) layer having sufficient thermal conductivity to radiate heat from the semiconductor chip 15. The heat from the semiconductor chip 15 is transferred to the package cover 65 through the continuous thermal interface material 85. Package cover 65 dissipates heat from chip 15, thereby allowing semiconductor chip 15 to operate at a higher speed and with less thermal stress.

[0045] In some embodiments, when the diameter of the spacer 70 of the package cap 65 is smaller than the diameter of the through hole 75 of the package substrate 50 , the spacer 70 is fixed to the package substrate 50 using an adhesive material (eg, epoxy adhesive).

[0046] Then, Figure 5A and Figure 5B The packaged semiconductor device is shown mounted on a board 90, such as a printed circuit board (PCB), as shown in FIG. Figure 6 In some embodiments, a surface mounting process is used to mount the packaged semiconductor device to the printed circuit board 90 .

[0047] During the surface mounting process, heat is applied to at least partially melt the solder balls 55 of the ball grid array to bond the solder balls 55 to the electrode pads formed on the printed circuit board 90, respectively. Figure 6As shown, the pad 70 of the cover 65 made of a rigid material maintains a uniform and sufficient gap between the back side 50B of the package substrate 50 and the printed circuit board 90. Therefore, the pressure applied to the solder balls 55 of the ball grid array is uniform, which can prevent the solder balls 55 from being deformed undesirably. In some embodiments, the variation in the distance of the gap between the back side 50B of the package substrate 50 is about 1% to about 5% of the average distance of the gap (e.g., measured at 20-50 points).

[0048] Fig. 7A and Figure 7B Also shown is the role of the spacer 70. As described above, due to the difference in thermal expansion coefficients between the package substrate 50 and the package lid 65, the packaged semiconductor device may bend. Fig. 7A shows that the frown face is warped (convex upward), while Figure 7B A smiley face warp (a downward bulge) is shown. In both cases, the spacer 70 between the back surface 50B of the package substrate 50 and the printed circuit board 90 prevents the solder balls 55 from bridging or deforming.

[0049] In some embodiments, the distance D3 (gap or space) between the back surface 50B of the package substrate 50 and the printed circuit board 90 is as follows: Fig. 8A and Figure 8B In some embodiments, the distance is in the range of about 20 μm to about 800 μm. In other embodiments, the distance is in the range of about 50 μm to about 500 μm. In some embodiments, the distance is in the range of about 100 μm to about 400 μm. In other words, the protrusion amount D1 of the spacer 70 (see Figure 5A ) is set equal to distance D3.

[0050] In some embodiments, the spacer 70 of the package cover 65 is fixed to the printed circuit board 90 by an adhesive material (eg, epoxy adhesive). In this case, the protrusion amount D1 of the spacer 70 is slightly smaller than the distance D3 due to the thickness of the adhesive material.

[0051] In other embodiments, a portion of the spacer 70 is embedded in the printed circuit board 90. In some embodiments, a shallow hole 95 is formed in the upper surface of the circuit board 90 so that the end of the spacer 70 fits into the shallow hole, such as Fig. 8A In some embodiments, the depth of the shallow hole 95 is in the range of about 5 μm to about 200 μm. In this case, the protrusion amount D1 of the spacer 70 is greater than the depth of the shallow hole 95 by a distance D3.

[0052] Furthermore, in some embodiments, Figure 8BAs shown, the end of the spacer 70 has a narrow portion 73 with a smaller diameter. In some embodiments, the narrow portion 73 is fitted into the shallow hole 95. In some embodiments, the narrow portion 73 has a conical shape. Fig. 8A and Figure 8B The illustrated configuration can more securely or firmly secure the gap or space between the back surface 50B of the package substrate 50 and the printed circuit board 90 .

[0053] 9A to 9D Various configurations of package cover 65 according to embodiments of the present invention are shown.

[0054] In some embodiments, the center of the spacer 70 is aligned with the center of the wall portion 65B, such as Fig. 9A In other embodiments, the center of the spacer 70 is offset inwardly or outwardly from the center of the wall portion 65B, such as Fig. 9B In some embodiments, the outer surface of the wall portion 65B is flush with the outermost portion of the spacer 70, such as Fig. 9C As shown, and in other embodiments, the inner surface of the wall portion 65B is flush with the innermost portion of the spacer 70, such as Fig.9D Depending on the device configuration (eg, the arrangement of the ball grid array 55), an appropriate configuration of the spacer 70 is selected. Embodiments of the spacer 70 accommodate various designs of different ball sizes and pitches of the solder balls 55 of the ball grid array.

[0055] Embodiments of the present invention may also allow process temperatures up to 260° C. without substantial deformation of the package substrate, thereby preventing bridging and short circuits.

[0056] Fig. 10A and Fig. 10B The opening cover with a ring or frame shape according to an embodiment of the present invention is shown. Figures 1 to 9D The same or similar materials, configurations, dimensions, structures, conditions, and operations as those described are described, and some descriptions may be omitted.

[0057] In some embodiments, semiconductor chip 15 includes an image sensor, such as a charge coupled device (CCD) or a CMOS image sensor, which receives light from the outside and generates an image signal corresponding to the light. In some embodiments, semiconductor chip 15 is a light (e.g., infrared light) sensor. In this case, the package should have an opening for receiving incident light.

[0058] like Fig. 10A and Fig. 10B As shown, instead of having the above-mentioned closed packaging cover 65, an open cover 80 having a ring or frame shape is used. Similar to the closed cover 65, the open cover 80 includes a wall portion 80B surrounding an opening 80A and a plurality of spacers 70 protruding from the bottom of the wall portion 80B.

[0059] The open cover 80 is made of a thermally conductive material. In some embodiments, the open cover 80 is used as a heat sink to dissipate the heat generated by the semiconductor chip 15. However, unlike the closed cover 65, no thermal conductive path is provided between the top of the semiconductor chip 15 and the closed cover 65 (no top and no thermal interface material), and therefore the semiconductor chip 15 used with the open cover 80 generates less heat than the heat generated when used with the closed cover 65. In other embodiments, an external heat sink is attached to the semiconductor chip 15 through the opening 80A, or a cooling fan is provided above the opening 80A to cool the semiconductor chip 15.

[0060] In some embodiments, the open cover 80 is made of aluminum, copper, nickel, cobalt, and alloys thereof or other thermally conductive materials. In some embodiments, the open cover 80 is made of a Cu alloy, such as CuMo, CuW, or CuBe. In some embodiments, the open cover 80 is made of a composite material, including silicon carbide, aluminum nitride, graphite, etc. In some embodiments, the open cover 80 is made of a composite material, including ceramic, silicon carbide, aluminum nitride, graphite, etc.

[0061] In some embodiments, a transparent sheet 88 is placed in the opening 80A, such as Fig. 10C As shown, or covering opening 80A, as Fig. 10D As shown, to protect the semiconductor chip 15. In some embodiments, the transparent sheet is made of glass or plastic. In some embodiments, the transparent sheet allows visible light and / or infrared light to pass through.

[0062] In some embodiments, the height of the wall portion 80B is equal to or less than the height of the semiconductor chip 15 measured from the front side 50A of the package substrate 50. In other embodiments, the height of the wall portion 80B is greater than the height of the semiconductor chip 15.

[0063] In some embodiments, the interior of the wall is coated with a light absorbing material, or has a rough surface. In some embodiments, the rough surface has a roughness Ra in a range of about 1 μm to about 100 μm.

[0064] Furthermore, in some embodiments, a transparent resin is filled to cover the semiconductor chip 15 in the open cover 80 to protect the semiconductor chip 15 .

[0065] Similar to Figure 5A and Figure 5B , the open cover 80 is attached to the package substrate 50 by inserting the spacer 70 into the through hole 75 by press fitting, as shown Fig.11A and Fig. 11B shown.

[0066] In some embodiments, when the diameter of the decapped spacer 70 is smaller than the diameter of the through hole 75 of the package substrate 50 , an adhesive material (eg, epoxy adhesive) is used to secure the spacer 70 to the package substrate 50 .

[0067] Then, Fig.11A and Fig. 11B The packaged semiconductor device is shown mounted on a board 90, such as a printed circuit board (PCB), as shown in FIG. Fig.12 In some embodiments, the packaged semiconductor device is mounted to the printed circuit board 90 using a surface mounting process.

[0068] During the surface mounting process, heat is applied to at least partially melted solder balls 55 of the ball grid array to bond the solder balls 55 to electrode pads formed on the printed circuit board 90, respectively. Fig.12 As shown, the spacer 70 made of a rigid material of the decap 80 maintains a uniform and sufficient gap between the back surface 50B of the package substrate 50 and the printed circuit board 90. Therefore, the pressure applied to the solder balls 55 of the ball grid array is uniform, which can prevent undesired deformation of the solder balls 55. In some embodiments, the variation in the distance of the gap between the back surface 50B of the package substrate 50 is about 1% to about 5% of the average distance of the gap (e.g., measured at 20-50 points).

[0069] Fig.13 FIG. 1 shows a package cover with a spacer according to an embodiment of the present invention. Figures 1 to 12 The same or similar materials, configurations, dimensions, structures, conditions, and operations as those described are described, and some descriptions may be omitted.

[0070] In the aforementioned embodiment, the spacer 70 is disposed to surround the BGA 55. When the size of the semiconductor chip 15 is large, the central portion of the package substrate may not be sufficiently supported by the spacer 70 to maintain a uniform air distance between the package substrate 50 and the printed circuit board 90.

[0071] In some embodiments, Fig.13As shown, one or more additional spacers 79 are provided between the package substrate 50 and the printed circuit board 90. In some embodiments, the additional spacers 79 are made of aluminum, copper, nickel, cobalt, alloys thereof, or other thermally conductive materials. In some embodiments, the additional spacers 79 are made of a Cu alloy such as CuMo, CuW, or CuBe. In some embodiments, the additional spacers 79 are made of a composite material including silicon carbide, aluminum nitride, graphite, and the like. In some embodiments, the additional spacers 79 are made of a composite material including ceramic, silicon carbide, aluminum nitride, graphite, and the like. In some embodiments, the additional spacers 79 are made of the same material as the package cover 65 or the open cover 80. In other embodiments, the additional spacers 79 are made of a different material from the package cover 65 or the open cover 80. In this case, the stiffness of the additional spacers 79 is less than or greater than the stiffness of the package cover 65 or the open cover 80.

[0072] In some embodiments, when the additional spacer 79 is made of a conductive material, the additional spacer 79 is disposed so as not to contact the solder balls 55 of the ball grid array. In some embodiments, when the additional spacer 79 is made of an insulating material, the additional spacer 79 contacts or does not contact the solder balls 55 of the ball grid array. In some embodiments, when a plurality of additional spacers 79 are provided, the additional spacers 79 are arranged point-symmetrically with respect to the center of the package substrate 50 (or the center of the semiconductor chip 15).

[0073] According to the embodiments of the present invention, since the spacer formed integrally with the package cover or the decap passes through the package substrate to contact the printed circuit board below, deformation of the package during a thermal process can be effectively prevented or suppressed.

[0074] According to one aspect of the present invention, a semiconductor package includes: a semiconductor chip disposed above a first main surface of a first substrate; a package cover disposed above the semiconductor chip; and a spacer extending from the package cover through a corresponding hole in the first substrate. The spacer enters the hole at the first main surface of the first substrate and extends beyond the opposite second main surface of the first substrate. In one or more embodiments above and below, the spacer is made of the same material as the package cover. In one or more embodiments above and below, the spacer and the package cover form an integral component. In one or more embodiments above and below, the package cover is made of aluminum, aluminum alloy, copper, copper alloy, stainless steel or ceramic. In one or more embodiments above and below, the copper alloy is selected from the group consisting of CuMo, CuW and CuBe. In one or more embodiments above and below, the package cover contacts the semiconductor chip through a thermal interface material. In one or more embodiments above and below, the semiconductor package also includes a ball grid array disposed above the second main surface of the first substrate. In one or more embodiments above and below, the pitch of the ball grid array is in the range of 200μm to 800μm. In one or more embodiments above and below, the first substrate is disposed above the second substrate. In one or more embodiments above and below, the spacer contacts the main surface of the second substrate. In one or more embodiments above and below, the second substrate is a printed circuit board. In one or more embodiments above and below, the first substrate and the second substrate are separated by a distance of 20 μm to 800 μm. In one or more embodiments above and below, the spacer is provided at least at a corner of the package cover.

[0075] According to another aspect of the present invention, a semiconductor package includes: a semiconductor chip, which is arranged above the first main surface of a first substrate; a packaging cover in a ring or frame shape, having an opening and arranged above the semiconductor chip; a second substrate arranged below the first substrate; and a spacer extending from the packaging cover through a corresponding hole in the first substrate. The spacer enters the hole at the first main surface of the first substrate and extends beyond the opposite second main surface of the first substrate and contacts the main surface of the second substrate. In one or more of the above and below embodiments, the semiconductor chip is an image sensor or a light sensor. In one or more of the above and below embodiments, the packaging cover is made of aluminum, aluminum alloy copper, copper alloy, stainless steel or ceramic. In one or more of the above and below embodiments, the second substrate includes a hole in which the spacer is assembled. In one or more of the above and below embodiments, the semiconductor package also includes a transparent cover arranged in or above the opening.

[0076] According to another aspect of the present invention, in a method for manufacturing a semiconductor package, a package cover is located above a chip disposed above a first main surface of a first substrate. The package cover has a plurality of spacers extending from the periphery of the package cover, and the first substrate has a plurality of holes corresponding to the plurality of spacers. The spacers are positioned in the holes so that the spacers pass through the first main surface of the substrate and extend beyond the second opposite main surface of the substrate to form a packaged semiconductor device. In one or more of the above and following embodiments, the packaged semiconductor device is attached to the second substrate by a surface mounting process.

[0077] An embodiment of the present invention is a semiconductor package, comprising a chip disposed above a first main surface of a substrate. A package cap or ring is disposed above the semiconductor chip, and a spacer extends from the package cap or ring through a corresponding hole in the substrate. The spacer enters the hole at the first main surface of the substrate and extends beyond the opposite second main surface of the substrate. In an embodiment, the spacer is made of the same material as the package cap or ring. In an embodiment, the spacer and the package cap or ring form an integral part. In an embodiment, the package cap or ring is made of copper, a copper alloy or stainless steel. In an embodiment, the copper alloy is selected from a group consisting of CuMo, CuW and CuBe. In an embodiment, the package cap contacts the semiconductor chip through a thermal interface material. In an embodiment, the semiconductor package comprises a ball grid array disposed above the second main surface of the substrate. In an embodiment, the pitch of the ball grid array is in the range of 200 μm to 800 μm. In an embodiment, the substrate is disposed above the second substrate. In an embodiment, the spacer contacts the main surface of the second substrate. In an embodiment, the second substrate is a printed circuit board. In an embodiment, the substrate and the second substrate are separated by a distance in the range of 20 μm to 800 μm. In an embodiment, the substrate and the second substrate are separated by a distance in the range of 50 μm to 500 μm. In an embodiment, the substrate and the second substrate are separated by a distance in the range of 100 μm to 400 μm. In an embodiment, the spacer is arranged around the periphery of the package cover or ring. In an embodiment, the package cover or ring is roughly rectangular in plan view. In an embodiment, there are three spacers on each side of the package cover or ring. In an embodiment, each spacer is spaced substantially the same distance from adjacent spacers around the periphery of the package cover or ring. In an embodiment, the spacer is located at the corner of the package cover or ring. In an embodiment, the diameter of the hole is in the range of 100 μm to 1,000 μm. In an embodiment, the diameter of the spacer is 10 μm to 50 μm smaller than the diameter of the hole. In an embodiment, the semiconductor chip is an integrated fan-out chip, a system on chip, a wafer-level chip scale package, or a wafer-on-wafer chip on a substrate. In an embodiment, the semiconductor package includes a bottom fill layer between the semiconductor chip and the substrate.

[0078] Another embodiment of the present invention is a method, including positioning a package cap or ring over a chip disposed over a first main surface of a substrate. The package cap or ring has a plurality of spacers extending from the periphery of the package cap or ring, and the substrate has a plurality of holes corresponding to the plurality of spacers. The spacers are positioned in the holes so that the spacers pass through the first main surface of the substrate and extend beyond the second opposite main surface of the substrate. In an embodiment, the method includes drilling a plurality of holes in the substrate before positioning the package cap or ring over the semiconductor chip. In an embodiment, the method includes forming a thermal interface material layer over the semiconductor chip before positioning the package cap or ring over the semiconductor chip. In an embodiment, the package cap contacts the semiconductor chip through the thermal interface material. In an embodiment, the method includes providing an underfill material between the semiconductor chip and the substrate before positioning the package cap or ring over the semiconductor chip. In an embodiment, the method includes soldering the semiconductor chip to the first main surface of the substrate before positioning the package cap or ring over the substrate. In an embodiment, the substrate includes a ball grid array disposed over the second main surface of the substrate. In an embodiment, the pitch of the ball grid array is in the range of 200 μm to 800 μm. In an embodiment, the method includes attaching a substrate to a first major surface of a second substrate. In an embodiment, the substrate is soldered to the first major surface of the second substrate. In an embodiment, the second substrate is a printed circuit board. In an embodiment, a plurality of spacers contact the first major surface of the second substrate. In an embodiment, the substrate and the second substrate are separated by a distance in the range of 20 μm to 800 μm. In an embodiment, the substrate and the second substrate are separated by a distance in the range of 50 μm to 500 μm. In an embodiment, the substrate and the second substrate are separated by a distance in the range of 100 μm to 400 μm. In an embodiment, the spacer is made of the same material as the encapsulation cap or ring. In an embodiment, the spacer and the encapsulation cap or ring form an integral part. In an embodiment, the encapsulation cap or ring is made of copper, a copper alloy or stainless steel. In an embodiment, the copper alloy is selected from the group consisting of CuMo, CuW and CuBe. In an embodiment, the encapsulation cap or ring is roughly rectangular in plan view. In an embodiment, there are three spacers on each side of the encapsulation cap or ring. In an embodiment, each of the plurality of spacers is spaced substantially the same distance from an adjacent spacer around the periphery of the encapsulation cap or ring. In an embodiment, the spacer is located at a corner of the package lid or ring. In an embodiment, the diameter of the hole is in the range of 100 μm to 1,000 μm. In an embodiment, the diameter of the spacer is 10 μm to 50 μm smaller than the diameter of the hole. In an embodiment, the semiconductor chip is an integrated fan-out chip, a system on chip, a wafer-level chip scale package, or a chip on wafer on a substrate.

[0079] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent configuration does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor package, comprising: a semiconductor chip disposed above the first main surface of the first substrate; a heat-conductive packaging cover, disposed above the semiconductor chip and having a wall portion; as well as a spacer having a cylindrical shape extending from the package cover through a corresponding hole in the first substrate, wherein the spacer enters a hole at a first major surface of the first substrate and extends beyond an opposite second major surface of the first substrate, The diameter of the spacer is smaller than the width of the wall, and The outer surface of the wall is flush with the outermost portion of the spacer, or the inner surface of the wall is flush with the innermost portion of the spacer, A ball grid array is provided on the second main surface of the first substrate, and the spacer is a rigid spacer, which is fixed to a second substrate located below the first substrate, wherein the fixing is: a shallow hole is formed on the upper surface of the second substrate facing the second main surface so that the end of the rigid spacer can be assembled into the shallow hole.

2. The semiconductor package according to claim 1, wherein: The spacer is made of the same material as the package cover.

3. The semiconductor package according to claim 1, wherein: The spacer and the packaging cover form an integral component.

4. The semiconductor package according to claim 1, wherein: The packaging cover is made of aluminum, aluminum alloy, copper, copper alloy, stainless steel or ceramic.

5. The semiconductor package according to claim 4, wherein: The copper alloy is selected from the group consisting of CuMo, CuW and CuBe.

6. The semiconductor package according to claim 1, wherein: The package cover contacts the semiconductor chip via a thermal interface material.

7. The semiconductor package according to claim 1, wherein: The diameter of the spacer is equal to the diameter of the hole at the first major surface.

8. The semiconductor package according to claim 1, wherein: The pitch of the ball grid array is in the range of 200 μm to 800 μm.

9. The semiconductor package according to claim 1, wherein: The semiconductor chip is embedded in a molding, and sidewalls of the molding and sidewalls of a redistribution layer located below the semiconductor chip are covered by an underfill material.

10. The semiconductor package according to claim 1, wherein The spacer contacts a major surface of the second substrate.

11. The semiconductor package according to claim 10, wherein: The second substrate is a printed circuit board.

12. The semiconductor package according to claim 10, wherein: The first substrate and the second substrate are separated by a distance of 20 μm to 800 μm.

13. The semiconductor package according to claim 1, wherein: The spacer is disposed at least at a corner of the package cover.

14. A semiconductor package, comprising: a semiconductor chip disposed above the first main surface of the first substrate, wherein the semiconductor chip is an image sensor or a light sensor; a heat-conductive packaging cover in a ring or frame shape, having an opening and disposed above the semiconductor chip; A second substrate, disposed below the first substrate; a spacer extending from the package cover through a corresponding hole in the first substrate; as well as a transparent cover, arranged in or above the opening, wherein the spacer enters a hole at a first major surface of the first substrate and extends beyond an opposite second major surface of the first substrate and contacts a major surface of the second substrate, A ball grid array is provided on the second main surface of the first substrate, and the spacer is a rigid spacer. One end of the rigid spacer that contacts the main surface of the second substrate is fixed to the second substrate, wherein the fixing is: a shallow hole is formed on the main surface of the second substrate so that the end of the rigid spacer that contacts the main surface of the second substrate can be assembled into the shallow hole.

15. The semiconductor package according to claim 14, wherein: The transparent cover allows visible light to pass through.

16. The semiconductor package according to claim 14, wherein: The packaging cover is made of aluminum, aluminum alloy copper, copper alloy, stainless steel or ceramic.

17. The semiconductor package according to claim 14, wherein: The second substrate includes a hole in which the spacer is fitted.

18. The semiconductor package according to claim 14, wherein: The transparent cover allows infrared light to pass through.

19. A method for manufacturing a semiconductor package, the method comprising: positioning a heat-conductive packaging cover having an opening in a ring or frame shape over a chip disposed over a first main surface of a first substrate, the chip being an image sensor or a light sensor; as well as placing a transparent cover in or over the opening, wherein the package cover has a plurality of spacers extending from a periphery of the package cover, and the first substrate has a plurality of holes corresponding to the plurality of spacers; and positioning the spacer in the hole so that the spacer passes through the first major surface of the first substrate and extends beyond the second opposing major surface of the first substrate to form a packaged semiconductor device, A ball grid array is provided on the second relative main surface of the first substrate, and the spacer is a rigid spacer. One end of the rigid spacer extending beyond the second relative main surface is fixed to a second substrate located below the first substrate, wherein the fixing is: a shallow hole is formed on the upper surface of the second substrate facing the second relative main surface so that the end of the rigid spacer extending beyond the second relative main surface is assembled into the shallow hole.

20. The method of claim 19, further comprising attaching the packaged semiconductor device to the second substrate by a surface mounting process.

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