Semiconductor Structure and Method of Manufacturing the Same

Abstract

A semiconductor structure includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, and a bonding structure disposed on the interconnect structure. The bonding structure includes a dielectric layer covering the interconnect structure, signal transmission features penetrating the dielectric layer, and thermal conduction features penetrating the dielectric layer. The thermal conduction features include thermal conduction wirings and thermal conduction pads, and the thermal conduction pads are disposed on the thermal conduction wirings and share the thermal conduction wirings.

Description

Technical Field

[0001] Some embodiments of the present invention relate to a semiconductor structure and a method of fabricating the same. Background Art

[0002] Due to the continuous increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. To a large extent, the increase in integration density is derived from the repeated reduction of the minimum feature size (e.g., shrinking semiconductor process nodes towards the sub-20nm node), which enables more components to be integrated into a given area. With the recent growth in the demand for miniaturization, higher speed, larger bandwidth, lower power consumption, and latency, the need for smaller and more innovative semiconductor die packaging technologies has also increased.

[0003] As semiconductor technology further develops, stacked and bonded semiconductor devices have become an effective alternative for further reducing the physical size of semiconductor devices. In a stacked semiconductor device, active circuits such as logic, memory, processor circuits, etc. are fabricated at least partially on separate substrates and then physically and electrically bonded together to form a functional device. Such bonding processes utilize complex technologies and there is a desire to improve them. Summary of the Invention

[0004] According to some embodiments of the present invention, there is provided a semiconductor structure including a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, and a bonding structure disposed on the interconnect structure. The bonding structure includes a dielectric layer covering the interconnect structure, signal transmission features penetrating the dielectric layer, and thermal conduction features penetrating the dielectric layer. The thermal conduction features include thermal conduction wirings and thermal conduction pads, and the thermal conduction pads are disposed on the thermal conduction wirings and share the thermal conduction wirings.

[0005] According to some embodiments of the present invention, a semiconductor structure is provided, which includes a first semiconductor die, a second semiconductor die, and an insulating encapsulant. The first semiconductor die includes a first bonding structure, and the first bonding structure includes a first dielectric layer, a first signal transmission feature penetrating the first dielectric layer, and a first heat conduction feature penetrating the first dielectric layer. The first heat conduction feature includes a first heat conduction wiring and a first heat conduction pad, and the first heat conduction pad is disposed on the first heat conduction wiring and shares the first heat conduction wiring. The second semiconductor die includes a second bonding structure, and the second bonding structure includes a second dielectric layer, a second signal transmission feature penetrating the second dielectric layer, and a second heat conduction feature penetrating the second dielectric layer. The second heat conduction feature includes a second heat conduction wiring and a second heat conduction pad, and the second heat conduction pad is disposed on the second heat conduction wiring and shares the second heat conduction wiring. The insulating encapsulant is disposed on the second semiconductor die and encapsulates the first semiconductor die. The first dielectric layer is bonded to the second dielectric layer, the first signal transmission feature is bonded and electrically connected to the second signal transmission feature, and the first heat conduction pad is bonded and thermally coupled to the second heat conduction pad.

[0006] According to some embodiments of the present invention, a method including the following steps is provided. Provide a semiconductor substrate having an interconnect structure disposed thereon. Form an interlayer dielectric layer over the interconnect structure. Form a plurality of vias and heat conduction wirings in the interlayer dielectric layer. Form a bonding dielectric layer over the interlayer dielectric layer. Form a plurality of bonding pads and heat conduction pads in the bonding dielectric layer, wherein the bonding pads are formed on the vias, and the heat conduction pads are formed on the heat conduction wirings and share the heat conduction wirings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention are best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a cross-sectional view showing a system on integrated circuit (SoIC) chip according to some embodiments of the present invention.

[0009] Figures 2A to 2E is a cross-sectional view showing a process flow for fabricating a semiconductor die according to some embodiments of the present invention.

[0010] Figure 3 is a view showing Figure 2E a perspective view of the bonding structure shown.

[0011] Figure 4A is a cross-sectional view showing a semiconductor die according to other embodiments of the present invention.

[0012] Figure 4B is a view showing Figure 4A a perspective view of the bonding structure shown.

[0013] Figure 5A is a cross-sectional view showing a semiconductor die according to some alternative embodiments of the present invention.

[0014] Figure 5B is a view showing Figure 5A a perspective view of the bonding structure shown.

[0015] Figures 6A to 6D is a cross-sectional view showing a process flow for fabricating Figure 1 the SoIC chip shown according to some embodiments of the present invention. Detailed Description

[0016] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are set forth below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature "on" or "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present invention may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0018] The present invention may also include other features and processes. For example, it may include test structures to assist in performing verification tests on three-dimensional (3D) packages or three dimensional integrated circuit (3DIC) devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows testing of the 3D package or 3DIC, allows the use of probes and / or probe cards, etc. Verification tests may be performed on intermediate structures as well as final structures. Additionally, the structures and methods disclosed herein may be used in conjunction with test methods that include intermediate verification of known good dies to improve yield and reduce costs.

[0019] Figure 1 is a cross-sectional view showing a system-on-integrated-circuit (SoIC) chip 100 according to some embodiments of the present invention. Referring to Figure 1 , the SoIC chip 100 includes a first semiconductor die 100A and a second semiconductor die 100B stacked on and bonded to the first semiconductor die 100A. The first semiconductor die 100A may include a first semiconductor substrate 110A, a first interconnect structure 120A disposed on the first semiconductor substrate 110A, and a first bonding structure 130A disposed on the first interconnect structure 120A. In other words, the first interconnect structure 120A is disposed between the first semiconductor substrate 110A and the first bonding structure 130A. In addition, the first bonding structure 130A may include at least one first heat-conducting feature 132A and a plurality of first signal-transmission features 134A. The second semiconductor die 100B may include a second semiconductor substrate 110B, a second interconnect structure 120B disposed on the second semiconductor substrate 110B, and a second bonding structure 130B disposed on the second interconnect structure 120B. In other words, the second interconnect structure 120B is disposed between the second semiconductor substrate 110B and the second bonding structure 130B. In addition, the second bonding structure 130B may include at least one second heat-conducting feature 132B and a plurality of second signal-transmission features 134B.

[0020] As Figure 1As shown, the second semiconductor die 100B is flipped and bonded to the first semiconductor die 100A such that the first bonding structure 130A of the first semiconductor die 100A and the second bonding structure 130B of the second semiconductor die 100B are in contact with and bonded to each other. The first bonding structure 130A and the second bonding structure 130B are located between the first interconnect structure 120A and the second interconnect structure 120B. In some embodiments, a hybrid bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first bonding structure 130A and the second bonding structure 130B. In addition, as Figure 1 shown, the die size of the second semiconductor die 100B can be smaller than the die size of the first semiconductor die 100A such that a portion of the first bonding structure 130A is not covered by the second semiconductor die 100B.

[0021] At least one first heat conduction feature 132A in the first bonding structure 130A can be in contact with and thermally coupled to at least one second heat conduction feature 132B in the second bonding structure 130B so as to enhance the heat transfer performance of the pseudo-region 132 in the SoIC chip 100. Since the first heat conduction feature 132A and the second heat conduction feature 132B in the second bonding structure 130B are made of a material with a high thermal conductivity (k) (such as a metal material with a high thermal conductivity), the heat transfer performance of the pseudo-region 132 in the SoIC chip 100 can be significantly improved. In some embodiments, the materials of the first heat conduction feature 132A and the second heat conduction feature 132B include copper, etc., while the dielectric materials in the first bonding structure 130A and the second bonding structure 130B include silicon oxide (e.g., an oxide formed from tetraethyl orthosilicate (TEOS)), silicon nitride, silicon oxynitride, etc. In some embodiments, the first heat conduction feature 132A and the second heat conduction feature 132B include a barrier layer, such as a Ta / TaN composite layer. In some embodiments, the thermal conductivity (k) of the first heat conduction feature 132A and the second heat conduction feature 132B is between about 0.575 Wm -1 K -1 and about 4.01 Wm -1 K -1 in the range, while the thermal conductivity (k) of the dielectric materials in the first bonding structure 130A and the second bonding structure 130B is between about 0.01 Wm -1 K -1 and about 0.1 Wm -1 K -1 in the range.

[0022] In some embodiments, the layout area of the first heat conduction feature 132A is larger than the layout area of the first signal transmission feature 134A, while the layout area of the second heat conduction feature 132B is larger than the layout area of the second signal transmission feature 134B. For example, the layout area of the first heat conduction feature 132A or the second heat conduction feature 132B is about 0.4% to about 0.6% of the entire area of the SoIC chip 100, while the layout area of the first signal transmission feature 134A or the second signal transmission feature 134B is about 1% to about 30% of the entire area of the SoIC chip 100.

[0023] The first signal transmission feature 134A can be in contact with and electrically connected to the second signal transmission feature 134B, such that signal transmission between the first semiconductor die 100A and the second semiconductor die 100B can be achieved through the signal transmission region 134 in the SoIC chip 100. The first heat conduction feature 132A and the second heat conduction feature 132B distributed in the pseudo region 132 are electrically insulated from the first signal transmission feature 134A and the second signal transmission feature 134B distributed in the signal transmission region 134. For example, the first heat conduction feature 132A and the second heat conduction feature 132B are electrically floating.

[0024] In some embodiments, the SoIC chip 100 may further include an insulating encapsulant 140 that laterally encapsulates the second semiconductor die 100B, a through insulator via (TIV) 150 that penetrates the insulating encapsulant 140 and is electrically connected to the first semiconductor die 100A, a redistribution layer 160 disposed over the second semiconductor die 100B and the insulating encapsulant 140, and an electrical terminal 170 disposed over the redistribution layer 160 and electrically connected to the redistribution layer 160. The insulating encapsulant 140 and the TIV 150 may be arranged to cover the portion of the first bonding structure 130A that is not covered by the second semiconductor die 100B, and the TIV 150 may be electrically connected to the first bonding structure 130A of the first semiconductor die 100A. In some embodiments, the insulating encapsulant 140 may be disposed beside the second semiconductor die 100B and encapsulate at least one sidewall of the second semiconductor die 100B. In some alternative embodiments, the insulating encapsulant 140 may surround and laterally encapsulate the sidewalls of the second semiconductor die 100B.

[0025] As Figure 1As shown, the redistribution layer 160 may include one or more redistribution wiring layers. In some embodiments, the redistribution layer 160 is electrically connected to the first semiconductor die 100A through the TIV 150. In some other embodiments, the redistribution layer 160 is electrically connected to the second semiconductor die 100B through the TIV 150 and the first semiconductor die 100A. In some alternative embodiments, the redistribution layer 160 is electrically connected to the second semiconductor die 100B through the through-silicon vias (TSVs) in the second semiconductor die 100B. Additionally, the electrical terminals 170 may include solder bumps, solder balls, solder columns, or other suitable conductors.

[0026] Figure 1 The illustrated SoIC chip 100 can be used as a flip-chip and can be mounted on a substrate (e.g., an interposer, a printed circuit board, etc.), or can be packaged through a series of packaging processes (e.g., an integrated fan-out process or other suitable processes). In embodiments where the SoIC chip 100 is used as a flip-chip, the SoIC chip 100 can be electrically connected to the substrate through the electrical terminals 170.

[0027] will be elaborated in conjunction with Figures 2A to 2E the process flow for fabricating the first semiconductor die 100A or the second semiconductor die 100B in the SoIC chip 100 in detail.

[0028] Referring to Figure 2A , a semiconductor wafer 200 is provided, which includes a semiconductor substrate 210 and an interconnect structure 220 on the semiconductor substrate 210. The semiconductor substrate 210 can be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor substrate 210 can comprise other suitable semiconductor materials. In some embodiments, the semiconductor substrate 210 may include other conductive layers or other semiconductor elements, such as transistors, diodes, resistors, capacitors, etc.

[0029] The interconnect structure 220 is electrically connected to a conductive layer or other semiconductor components formed in the semiconductor substrate 210. The interconnect structure 220 formed on the semiconductor substrate 210 may include a dielectric layer 221, interconnect wirings 222, 224, and 226 embedded in the dielectric layer 221, and a passivation layer 228 covering the dielectric layer 221 and the interconnect wirings 222, 224, and 226. In some embodiments, the interconnect wirings may include signal transmission wirings 222, dummy wirings 224, and thermal conductors 226. The signal transmission wirings 222 are electrically connected to a conductive layer or other semiconductor components formed in the semiconductor substrate 210 and are configured to transmit signals in the interconnect structure 220. The signal transmission wirings 222 may include multilayer patterned wirings embedded in the dielectric layer 221.

[0030] In some embodiments, the dummy wirings 224 and the thermal conductors 226 are electrically insulated from the signal transmission wirings 222. For example, the dummy wirings 224 and the thermal conductors 226 are electrically floating. The dummy wirings 224 and the thermal conductors 226 are formed in the topmost patterned wirings of the interconnect structure 220 and are covered by the passivation layer 228. The dummy wirings 224 are formed to ensure that the semiconductor wafer 200 may have a more uniform metal density. The thermal conductors 226 are configured to provide a thermal path for dissipating heat generated from semiconductor components (such as transistors, diodes, resistors, capacitors, etc.) in the semiconductor substrate 210.

[0031] In some embodiments, the material of the dielectric layer 221 may include silicon oxide, silicon nitride, etc. In some embodiments, the interconnect wirings 222, 224, and 226 may be made of the same metal material or different metal materials, and the materials of the interconnect wirings 222, 224, and 226 may include copper, etc. In some embodiments, the material of the passivation layer 228 may include silicon oxide (such as an oxide formed by TEOS), silicon nitride, silicon oxynitride, etc. In some embodiments, the interconnect wirings 222, 224, and 226 include a barrier layer, such as a Ta / TaN composite layer.

[0032] Refer to Figure 2B, an inter-dielectric layer 230 is formed over the interconnect structure 220 of the semiconductor wafer 200. The inter-dielectric layer 230 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable processes. In some embodiments, the material of the inter-dielectric layer 230 may include silicon oxide (e.g., oxide formed from TEOS), silicon nitride, silicon oxynitride, etc. A patterned photoresist layer PR1 is formed over the inter-dielectric layer 230 such that portions of the inter-dielectric layer 230 are exposed by the openings of the patterned photoresist layer PR1. In some embodiments, the patterned photoresist layer PR1 is formed by a photolithography process including soft baking, mask alignment, exposure, baking, developing the photoresist layer, and hard baking. In some alternative embodiments, the patterned photoresist layer PR1 is formed by electron-beam writing, ion-beam writing, maskless lithography, molecular imprint, or other suitable patterning processes.

[0033] Referring to Figure 2B and Figure 2C , by using the patterned photoresist layer PR1 as a mask, the portions of the inter-dielectric layer 230 exposed by the openings of the patterned photoresist layer PR1 and the portions of the passivation layer 228 below the openings of the patterned photoresist layer PR1 are sequentially removed. In some embodiments, the inter-dielectric layer 230 and the underlying passivation layer 228 are sequentially etched by dry etching or wet etching until the top surfaces of the signal transmission wiring 222, the intended wiring 224, and the thermal conductor 226 are exposed. After patterning the inter-dielectric layer 230 and the passivation layer 228, via holes for exposing the top surface of the signal transmission wiring 222 and via openings for exposing the top surface of the thermal conductor 226 are formed in the inter-dielectric layer 230. After patterning the inter-dielectric layer 230 and the passivation layer 228, the patterned photoresist layer PR1 is removed from the inter-dielectric layer 230, and a metal material is deposited over the semiconductor wafer 200 such that the metal material can fill the via holes and via openings in the inter-dielectric layer 230 and cover the top surface of the inter-dielectric layer 230. In some embodiments, the metal material is formed by PVD (e.g., sputtering, electroplating, etc.), CVD, or a combination thereof.

[0034] The metal material may be partially removed to form a heat conduction wiring 232 in a via opening defined in the interlayer dielectric layer 230 and form a signal transmission via 234 in a via defined in the interlayer dielectric layer 230. In some embodiments, a portion of the metal material distributed outside the via opening and the via of the interlayer dielectric layer 230 is removed until the top surface of the interlayer dielectric layer 230 is exposed. For example, the portion of the metal material distributed outside the via opening and the via of the interlayer dielectric layer 230 is removed by an etching process, a mechanical polishing process, a chemical mechanical polishing (CMP) process, or other suitable removal processes or a combination thereof.

[0035] As Figure 2C shown, the heat conduction wiring 232 is formed on the heat conductor 226, and the signal transmission via 234 is formed on the signal transmission wiring 222. The heat conduction wiring 232 and the signal transmission via 234 may be embedded in the interlayer dielectric layer 230 and penetrate the interlayer dielectric layer 230. In addition, the dummy wiring 224 does not contact the heat conduction wiring 232 and the signal transmission via 234. In some embodiments, the heat conduction wiring 232 and the dummy wiring 224 are electrically floating.

[0036] Referring Figure 2D to, after the heat conduction wiring 232 and the signal transmission via 234 are formed, a bonding dielectric layer 236 is deposited on the semiconductor wafer 200 to cover the top surfaces of the interlayer dielectric layer 230, the heat conduction wiring 232, and the signal transmission via 234. The bonding dielectric layer 236 may be formed by PVD, CVD, or other suitable deposition processes. In some embodiments, the material of the bonding dielectric layer 236 may include silicon oxide (e.g., oxide formed by TEOS), silicon nitride, silicon oxynitride, etc. A patterned photoresist layer PR2 is formed on the bonding dielectric layer 236 such that a portion of the bonding dielectric layer 236 is exposed by an opening of the patterned photoresist layer PR2. In some embodiments, the patterned photoresist layer PR2 is formed by a photolithography process including soft baking, mask alignment, exposure, baking, developing the photoresist layer, and hard baking. In some alternative embodiments, the patterned photoresist layer PR2 is formed by electron beam writing, ion beam writing, maskless lithography, nanoimprinting, or other suitable patterning processes.

[0037] Referring Figure 2D and Figure 2E, the exposed portion of the bonding dielectric layer 236 that is exposed by the openings of the patterned photoresist layer PR2 is removed by using the patterned photoresist layer PR2 as a mask. In some embodiments, the bonding dielectric layer 236 is etched by dry etching or wet etching until the top surfaces of the interlayer dielectric layer 230, the thermal conduction wiring 232, and the signal transmission vias 234 are exposed. After patterning the bonding dielectric layer 236, pad openings are formed in the bonding dielectric layer 236 to expose the top surfaces of the interlayer dielectric layer 230, the thermal conduction wiring 232, and the signal transmission vias 234. After patterning the bonding dielectric layer 236, the patterned photoresist layer PR2 is removed from the bonding dielectric layer 236, and then a metal material is deposited over the semiconductor wafer 200 such that the metal material can fill the pad openings in the bonding dielectric layer 236 and cover the top surface of the bonding dielectric layer 236. In some embodiments, the metal material is formed by PVD (e.g., sputtering, electroplating, etc.), CVD, or a combination thereof.

[0038] The metal material can be partially removed to form a thermal conduction pad 238a, a bonding pad 238b, and a dummy pad 238c in the pad openings defined in the bonding dielectric layer 236. In some embodiments, a portion of the metal material that is distributed outside the pad openings of the bonding dielectric layer 236 is removed until the top surface of the bonding dielectric layer 236 is exposed. For example, the portion of the metal material that is distributed outside the pad openings of the bonding dielectric layer 236 is removed by an etching process, a mechanical grinding process, a chemical mechanical polishing (CMP) process, or other suitable removal processes or a combination thereof.

[0039] In some embodiments, a wafer singulation process can be performed to singulate Figure 2E the illustrated semiconductor wafer 200 to obtain singulated semiconductor die.

[0040] The thermal conduction pad 238a is formed on the thermal conduction wiring 232 and is in contact with the thermal conduction wiring 232, the bonding pad 238b is formed on the signal transmission via 234 and is in contact with the signal transmission via 234, and the dummy pad 238c is formed on the interlayer dielectric layer 230. The thermal conduction pad 238a, the bonding pad 238b, and the dummy pad 238c can be embedded in the bonding dielectric layer 236 and penetrate the bonding dielectric layer 236. In some embodiments, the dummy pad 238c is not in contact with the thermal conduction pad 238a and the bonding pad 238b. The dummy pad 238c can be electrically insulated from the thermal conduction pad 238a, the bonding pad 238b, the thermal conduction wiring 232, and the signal transmission vias 234. In addition, the dummy pad 238c can be spaced apart from the dummy wiring 224 through the interlayer dielectric layer 230. For example, the thermal conduction pad 238a and the dummy pad 238c are electrically floating.

[0041] As Figure 2EAs shown, semiconductor wafer 200 includes a bonding structure, which includes a dielectric layer covering the interconnect structure 220, signal transmission features penetrating the dielectric layer, and thermal conduction features penetrating the dielectric layer. In some embodiments, the dielectric layer of the bonding structure includes an interlayer dielectric layer 230 and a bonding dielectric layer 236, the signal transmission features include signal transmission vias 234 and bonding pads 238b, and the thermal conduction features include thermal conduction wirings 232 and thermal conduction pads 238a. In addition, the thermal conduction pad 238a is disposed on the thermal conduction wiring 232 and shares the thermal conduction wiring 232.

[0042] Figure 3 is a perspective view showing Figure 2E the bonding structure of the semiconductor wafer 200 shown.

[0043] Referring to Figure 2E and Figure 3 , signal transmission wiring 222, dummy wiring 224, and thermal conductor 226 are arranged at a horizontal height in the semiconductor wafer 200, while thermal conduction pad 238a, bonding pad 238b, and dummy pad 238c are arranged at another horizontal height in the semiconductor wafer 200. In some embodiments, the dummy wiring 224 includes a dummy dot pattern arranged regularly or irregularly. The thermal conduction pad 238a, bonding pad 238b, and dummy pad 238c embedded in the bonding dielectric layer 236 can be arranged in an array. The thermal conduction pad 238a is thermally coupled to the thermal conductor 226 through the thermal conduction wiring 232, and the bonding pad 238b is electrically connected to the signal transmission wiring 222 through the signal transmission via 234. In some embodiments, the thermal conduction wiring 232 is located on the top surface of the thermal conductor 226, the thermal conductor 226 can be wider than the thermal conduction wiring 232, and the pattern of the thermal conductor 226 can be similar to the pattern of the thermal conduction wiring 232. In some embodiments, the thermal conduction wiring 232 can include a via portion and a wall portion that laterally connects the via portion, where the via portion is located below the thermal conduction pad 238a and contacts the thermal conduction pad 238a. The via portion of the thermal conduction wiring 232 can be a cylindrical column, and the wall portion of the thermal conduction wiring 232 and the thermal conductor 226 can extend along a meandering path below at least two or all of the thermal conduction pads 238a. In some other embodiments, the thermal conduction wiring 232 can be a mesh thermal conduction wiring, and the thermal conductor 226 can be a mesh thermal conductor.

[0044] Figure 4A is a cross-sectional view showing a semiconductor die according to other embodiments of the present invention. Figure 4B is a perspective view showing Figure 4A the bonding structure shown.

[0045] Referring to Figure 2E , Figure 3 , Figure 4A and Figure 4B , Figure 4A andFigure 4B The semiconductor wafer 200a shown and Figure 2E and Figure 3 the semiconductor wafer 200 shown are similar, except that the interconnect structure 220a further includes a heat conductor 225a and an interconnect wiring 225b. The heat conductor 225a is disposed on the passivation layer 228 and thermally coupled to the heat conductor 226, and the interconnect wiring 225b is disposed on the passivation layer 228 and electrically connected to the signal transmission wiring 222. In addition, a portion of the signal transmission wiring 222 may be covered by the heat conductor 225a, and the heat conductor 225a is spaced apart from the underlying signal transmission wiring 222 by the passivation layer 228.

[0046] In some embodiments, the heat conductor 225a and the interconnect wiring 225b are embedded in the interlayer dielectric layer 230, the heat conduction wiring 232 is located on the heat conductor 225a, and the signal transmission via 234 is located on the interconnect wiring 225b. In some embodiments, the heat conduction wiring 232 is located on the top surface of the heat conductor 225a, the heat conductor 225a may be wider than the heat conduction wiring 232, and the pattern of the heat conductor 225a may be similar to the pattern of the heat conduction wiring 232.

[0047] In some embodiments, the heat conduction wiring 232 may include a via portion and a wall portion that laterally connects the via portion, wherein the via portion is located below the heat conduction pad 238a and contacts the heat conduction pad 238a. The via portion of the heat conduction wiring 232 may be a cylindrical column, and the wall portion of the heat conduction wiring 232 and the heat conductor 225a may extend along a zigzag path under at least two or all of the heat conduction pads 238a. In some other embodiments, the heat conduction wiring 232 may be a mesh heat conduction wiring, and the heat conductor 225a may be a mesh heat conductor. In some embodiments, the heat conductor 225a and the interconnect wiring 225b include aluminum pads formed on the passivation layer 228. In some other embodiments, the materials of the heat conductor 225a and the interconnect wiring 225b include copper, aluminum, Al-Cu alloy, etc.

[0048] Figure 5A is a cross-sectional view showing a semiconductor die according to some alternative embodiments of the present invention. Figure 5B is a perspective view showing Figure 5A the bonding structure shown.

[0049] Referring to Figure 4A , Figure 4B , Figure 5A and Figure 5B , Figure 5A and Figure 5B the semiconductor wafer 200b shown and Figure 4A and Figure 4BSimilar to the semiconductor wafer 200a shown, the difference is that a part of the heat conduction wiring 232 is located on the heat conductor 225a, another part of the heat conduction wiring 232 is located on the heat conductor 226, some signal transmission vias 234 are located on the internal connection wiring 225b, and the remaining signal transmission vias 234 are located on the internal connection wiring 222.

[0050] Combined Figures 6A to 6D Elaborate in detail the process flow for fabricating Figure 1 the SoIC chip 100 shown.

[0051] Refer to Figure 6A , a semiconductor wafer W is provided, and the semiconductor wafer W includes a plurality of first semiconductor dies 100A disposed therein. Each first semiconductor die 100A in the semiconductor wafer W may include a first semiconductor substrate 110A, a first internal connection structure 120A disposed on the first semiconductor substrate 110A, and a first bonding structure 130A disposed on the first internal connection structure 120A. In addition, the first bonding structure 130A includes at least one first heat conduction feature 132A embedded therein. In some embodiments, Figure 6A the semiconductor wafer W shown may be the same as Figure 2E the semiconductor wafer 200 shown, and may be fabricated by Figures 2A to 2E the process shown. In some alternative embodiments, Figure 6A the semiconductor wafer W shown may be the same as Figure 4A the semiconductor wafer 200a shown or Figure 5A the semiconductor wafer 200b shown.

[0052] Refer to Figure 6B and Figure 6C , at least one second semiconductor die 100B is provided and mounted on the semiconductor wafer W. The second semiconductor die 100B may include a second semiconductor substrate 110B, a second internal connection structure 120B disposed on the second semiconductor substrate 110B, and a second bonding structure 130B disposed on the second internal connection structure 120B. In addition, the second bonding structure 130B includes at least one second heat conduction feature 132B embedded therein. In some embodiments, the second semiconductor die 100B is bonded to the semiconductor wafer W through a chip-to-wafer bonding process. For example, the second bonding structure 130B of the second semiconductor die 100B is bonded to the first bonding structure 130A of the semiconductor wafer W through a hybrid bonding process or other suitable bonding processes.

[0053] In some embodiments, the second semiconductor die 100B may be made of Figure 2EThe singulated semiconductor die fabricated from the semiconductor wafer 200 shown. In some other embodiments, the second semiconductor die 100B may be a singulated semiconductor die fabricated from the semiconductor wafer 200a shown by Figure 4A or a singulated semiconductor die fabricated from the semiconductor wafer 200b shown by Figure 5A .

[0054] As Figure 6C shown, after the second semiconductor die 100B is bonded to the semiconductor wafer W, an insulating encapsulant 140 is formed over the semiconductor wafer W to laterally encapsulate the second semiconductor die 100B. In some embodiments, the insulating encapsulant 140 may be formed first by an over molding process and then by a grinding process. For example, a molding compound is formed over the semiconductor wafer W to cover the second semiconductor die 100B, and then the molding compound is ground by a CMP process such that the insulating encapsulant 140 can be formed over the semiconductor wafer W. After performing the CMP process, the second semiconductor substrate 110B of the second semiconductor die 100B is also polished such that the semiconductor vias TSVs are exposed at the back surface of the second semiconductor substrate 110B. In some embodiments, the semiconductor vias TSVs protrude from the back surface of the second semiconductor substrate 110B. In Figure 6C some other embodiments not shown, the semiconductor vias TSVs may not protrude from the back surface of the second semiconductor substrate 110B, and the exposed surface of the semiconductor vias TSVs may be substantially flush with the back surface of the second semiconductor substrate 110B.

[0055] In some other embodiments, the insulating encapsulant 140 may be formed by other materials and other fabrication processes. For example, the insulating encapsulant 140 is a single-layer or multi-layer oxide layer, a single-layer or multi-layer nitride layer, or other suitable insulating materials, and the insulating encapsulant 140 is formed by CVD or other suitable processes.

[0056] Referring to Figure 6D , at least one TIV 150 is formed to penetrate the insulating encapsulant 140 and electrically connect to the semiconductor wafer W. Then, a redistribution layer 160 and electrical terminals 170 are formed over the second semiconductor die 100B and the insulating encapsulant 140. After forming the redistribution layer 160 and the electrical terminals 170, the wafer-level package including the semiconductor wafer W, the second semiconductor die 100B, the insulating encapsulant 140, the TIV 150, the redistribution layer 160, and the electrical terminals 170 is subjected to a wafer singulation process to obtain a plurality of singulated SoIC chips 100. The detailed structure of the singulated SoIC chips 100 has been described in conjunction with Figure 1 .

[0057] In the above embodiments of the present invention, a plurality of thermal conductive features are formed in the bonding structure of the SoIC chip to increase the metal ratio of the bonding structure and enhance the heat transfer performance of the SoIC chip. Therefore, the SoIC chip can have improved heat dissipation performance.

[0058] According to some embodiments of the present invention, a semiconductor structure is provided, which includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate, and a bonding structure disposed on the interconnect structure. The bonding structure includes a dielectric layer covering the interconnect structure, signal transmission features penetrating the dielectric layer, and thermal conductive features penetrating the dielectric layer. The thermal conductive features include thermal conductive wirings and thermal conductive pads, and the thermal conductive pads are disposed on the thermal conductive wirings and share the thermal conductive wirings. In some embodiments, the dielectric layer includes a bonding dielectric layer and an interlayer dielectric layer disposed between the bonding dielectric layer and the interconnect structure. In some embodiments, each of the signal transmission features in the signal transmission features includes a via penetrating the interlayer dielectric layer and a bonding pad penetrating the bonding dielectric layer, and the bonding pad is electrically connected to the interconnect structure through the via. In some embodiments, the thermal conductive wiring penetrates the interlayer dielectric layer, and the thermal conductive pad penetrates the bonding dielectric layer. In some embodiments, the bonding structure further includes dummy pads embedded in the bonding dielectric layer, and the dummy pads are electrically insulated from the interconnect structure through the interlayer dielectric layer. In some embodiments, the bonding structure further includes dummy pads embedded in the dielectric layer, and the dummy pads are electrically insulated from the interconnect structure. In some embodiments, the thermal conductive wiring includes a via portion and a wall portion laterally connecting the via portion, and the via portion is in contact with the thermal conductive pad. In some embodiments, the interconnect structure includes interconnect wirings, a passivation layer covering the interconnect wirings, and a heat conductor partially covered by the passivation layer, and the thermal conductive wiring is located on the heat conductor. In some embodiments, the interconnect structure includes interconnect wirings, a passivation layer covering the interconnect wirings, and a heat conductor disposed on the passivation layer, and the thermal conductive wiring is located on the heat conductor. In some embodiments, the interconnect structure includes interconnect wirings, a passivation layer covering the interconnect wirings, a first heat conductor partially covered by the passivation layer, and a second heat conductor disposed on the passivation layer, a first portion of the thermal conductive wiring is located on the first heat conductor, and a second portion of the thermal conductive wiring is located on the second heat conductor.

[0059] According to some embodiments of the present invention, a semiconductor structure is provided, which includes a first semiconductor die, a second semiconductor die, and an insulating encapsulant. The first semiconductor die includes a first bonding structure, and the first bonding structure includes a first dielectric layer, a first signal transmission feature penetrating the first dielectric layer, and a first heat conduction feature penetrating the first dielectric layer. The first heat conduction feature includes a first heat conduction wiring and a first heat conduction pad, and the first heat conduction pad is disposed on the first heat conduction wiring and shares the first heat conduction wiring. The second semiconductor die includes a second bonding structure, and the second bonding structure includes a second dielectric layer, a second signal transmission feature penetrating the second dielectric layer, and a second heat conduction feature penetrating the second dielectric layer. The second heat conduction feature includes a second heat conduction wiring and a second heat conduction pad, and the second heat conduction pad is disposed on the second heat conduction wiring and shares the second heat conduction wiring. The insulating encapsulant is disposed on the second semiconductor die and encapsulates the first semiconductor die. The first dielectric layer is bonded to the second dielectric layer, the first signal transmission feature is bonded and electrically connected to the second signal transmission feature, and the first heat conduction pad is bonded and thermally coupled to the second heat conduction pad. In some embodiments, the first heat conduction feature and the second heat conduction feature are electrically floating. In some embodiments, the first heat conduction feature and the second heat conduction feature are electrically insulated from the first signal transmission feature and the second signal transmission feature. In some embodiments, the first bonding structure further includes a first dummy pad embedded in the first dielectric layer, the second bonding structure further includes a second dummy pad embedded in the second dielectric layer, and the first dummy pad and the second dummy pad are bonded. In some embodiments, the first heat conduction wiring includes a first via portion and a first wall portion laterally connecting the first via portion, and the first via portion is in contact with the first heat conduction pad. In some embodiments, the second heat conduction wiring includes a second via portion and a second wall portion laterally connecting the second via portion, and the second via portion is in contact with the second heat conduction pad.

[0060] According to some embodiments of the present invention, a method including the following steps is provided. Provide a semiconductor substrate having an interconnect structure disposed thereon. Form an interlayer dielectric layer over the interconnect structure. Form a plurality of vias and thermal wirings in the interlayer dielectric layer. Form a bonding dielectric layer over the interlayer dielectric layer. Form a plurality of bonding pads and thermal pads in the bonding dielectric layer, wherein the bonding pads are formed over the vias, and the thermal pads are formed over the thermal wirings and share the thermal wirings. In some embodiments, when forming the bonding pads and the thermal pads in the bonding dielectric layer, there are dummy pads in the bonding dielectric layer, and the dummy pads are electrically insulated from the interconnect structure through the interlayer dielectric layer. In some embodiments, the thermal wirings are formed on a thermal conductor partially covered by a passivation layer of the interconnect structure. In some embodiments, the thermal wirings are formed on a thermal conductor disposed over a passivation layer of the interconnect structure, and the thermal conductor is embedded in the interlayer dielectric layer.

[0061] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present invention as a basis to design or modify other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present invention.

[0062] [Description of Symbols]

[0063] 100: System-on-Integrated-Circuit (SoIC) chip

[0064] 100A: First semiconductor die

[0065] 100B: Second semiconductor die

[0066] 110A: First semiconductor substrate

[0067] 110B: Second semiconductor substrate

[0068] 120A: First interconnect structure

[0069] 120B: Second interconnect structure

[0070] 130A: First bonding structure

[0071] 130B: Second bonding structure

[0072] 132: Dummy region

[0073] 132A: First heat conduction feature

[0074] 132B: Second heat conduction feature

[0075] 134: Signal transmission region

[0076] 134A: First signal transmission feature

[0077] 134B: Second signal transmission feature

[0078] 140: Insulating encapsulation

[0079] 150: Through Insulator Via (TIV)

[0080] 160: Redistribution layer

[0081] 170: Electrical terminal

[0082] 200, 200a, 200b, W: Semiconductor wafer

[0083] 210: Semiconductor substrate

[0084] 220, 220a, 220b: Interconnection structure

[0085] 221: Dielectric layer

[0086] 222: Interconnection wiring / Signal transmission wiring

[0087] 224: Interconnection wiring / Pseudo wiring

[0088] 225a: Heat conductor

[0089] 225b: Interconnection wiring

[0090] 226: Interconnection wiring / Heat conductor

[0091] 228: Passivation layer

[0092] 230: Interlayer dielectric layer

[0093] 232: Heat conduction wiring

[0094] 234: Signal transmission via hole

[0095] 236: Bonding dielectric layer

[0096] 238a: Heat conduction pad

[0097] 238b: Bonding pad

[0098] 238c: Pseudo pad

[0099] PR1, PR2: Patterned photoresist layer

[0100] TSV: Through-Silicon Via

Claims

1. A semiconductor structure, comprising: A semiconductor substrate; An interconnect structure disposed on the semiconductor substrate; And A bonding structure disposed on the interconnect structure, the bonding structure including a dielectric layer covering the interconnect structure, a plurality of signal transmission features penetrating the dielectric layer, and a heat conduction feature penetrating the dielectric layer, wherein the heat conduction feature includes a heat conduction wiring and a heat conduction pad, and the heat conduction pad is disposed on the heat conduction wiring and shares the heat conduction wiring, and the heat conduction wiring laterally extends between at least two adjacent signal transmission features among the plurality of signal transmission features; Wherein the interconnect structure includes interconnect wiring, a passivation layer covering the interconnect wiring, and a first heat conductor partially covered by the passivation layer, and a first portion of the heat conduction wiring is located on the first heat conductor.

2. The semiconductor structure according to claim 1, wherein The dielectric layer includes a bonding dielectric layer and an interlayer dielectric layer disposed between the bonding dielectric layer and the interconnect structure.

3. The semiconductor structure according to claim 2, wherein Each of the signal transmission features includes a via penetrating the interlayer dielectric layer and a bonding pad penetrating the bonding dielectric layer, and the bonding pad is electrically connected to the interconnect structure through the via.

4. The semiconductor structure according to claim 2, wherein The heat conduction wiring penetrates the interlayer dielectric layer, and the heat conduction pad penetrates the bonding dielectric layer.

5. The semiconductor structure according to claim 2, wherein The bonding structure further includes dummy pads embedded in the bonding dielectric layer, and the dummy pads are electrically insulated from the interconnect structure through the interlayer dielectric layer.

6. The semiconductor structure according to claim 1, wherein The heat conduction wiring laterally extends along a meandering path.

7. The semiconductor structure according to claim 1, wherein The heat conduction wiring includes a via portion and a plurality of wall portions laterally connecting the via portion, and the via portion is in contact with the heat conduction pad, and at least one of the plurality of wall portions laterally extends between at least two adjacent signal transmission features among the plurality of signal transmission features.

8. The semiconductor structure according to claim 1, characterized in that, The heat conduction feature is electrically insulated from the plurality of signal transmission features.

9. The semiconductor structure according to claim 1, wherein The heat conduction feature is electrically floating.

10. The semiconductor structure according to claim 1, wherein, The interconnect structure further includes a second heat conductor disposed on the passivation layer, and a second portion of the heat conduction wiring is located on the second heat conductor.

11. A semiconductor structure, comprising: A first semiconductor die, including an interconnect structure and a first bonding structure, the interconnect structure including interconnect wiring, a passivation layer covering the interconnect wiring, and a heat conductor partially covered by the passivation layer, the first bonding structure including a first dielectric layer, a first signal transmission feature penetrating the first dielectric layer, and a first heat conduction feature penetrating the first dielectric layer, wherein the first heat conduction feature includes a first heat conduction wiring and a first heat conduction pad located on the heat conductor, the first heat conduction pad is disposed on the first heat conduction wiring and shares the first heat conduction wiring, and the first heat conduction wiring laterally extends between at least two adjacent first signal transmission features among a plurality of first signal transmission features; A second semiconductor die, including a second bonding structure, the second bonding structure including a second dielectric layer, a second signal transmission feature penetrating the second dielectric layer, and a second heat conduction feature penetrating the second dielectric layer, wherein the second heat conduction feature includes a second heat conduction wiring and a second heat conduction pad, and the second heat conduction pad is disposed on the second heat conduction wiring and shares the second heat conduction wiring; And An insulating encapsulant, disposed on the second semiconductor die and encapsulating the first semiconductor die, wherein the first dielectric layer is bonded to the second dielectric layer, the first signal transmission feature is bonded and electrically connected to the second signal transmission feature, and the first heat conduction pad is bonded and thermally coupled to the second heat conduction pad.

12. The semiconductor structure according to claim 11, wherein, The first heat conduction wiring includes a mesh heat conduction wiring.

13. The semiconductor structure according to claim 11, wherein The first heat conduction feature and the second heat conduction feature are electrically floating, and the first heat conduction feature and the second heat conduction feature are electrically insulated from the first signal transmission feature and the second signal transmission feature.

14. The semiconductor structure according to claim 11, wherein, The first bonding structure further includes a first dummy pad embedded in the first dielectric layer, the second bonding structure further includes a second dummy pad embedded in the second dielectric layer, and the first dummy pad is bonded to the second dummy pad.

15. The semiconductor structure according to claim 11, wherein, The first heat conduction wiring includes a first via portion and a plurality of first wall portions laterally connecting the first via portion, and the first via portion is in contact with the first heat conduction pad, and at least one first wall portion of the plurality of first wall portions laterally extends between at least two adjacent first signal transmission features of the plurality of first signal transmission features.

16. The semiconductor structure according to claim 11, wherein The second heat conduction wiring includes a second via portion and a plurality of second wall portions laterally connecting the second via portion, and the second via portion is in contact with the second heat conduction pad, and at least one second wall portion of the plurality of second wall portions laterally extends between at least two adjacent second signal transmission features of the plurality of second signal transmission features.

17. A method of manufacturing a semiconductor structure, including: Providing a semiconductor substrate having an interconnect structure disposed thereon, wherein the interconnect structure includes interconnect wiring, a passivation layer covering the interconnect wiring, and a heat conductor partially covered by the passivation layer; Forming an interlayer dielectric layer on the interconnect structure; Forming a plurality of vias and a heat conduction wiring on the heat conductor in the interlayer dielectric layer; Forming a bonding dielectric layer on the interlayer dielectric layer; And Forming a plurality of bonding pads and heat conduction pads in the bonding dielectric layer, wherein the bonding pads are formed on the vias, the heat conduction pads are formed on the heat conduction wiring and share the heat conduction wiring, and the heat conduction wiring laterally extends between at least two adjacent signal transmission features of a plurality of signal transmission features.

18. The method for fabricating a semiconductor structure according to claim 17, wherein When forming the bonding pads and the heat conduction pads in the bonding dielectric layer, there are dummy pads in the bonding dielectric layer, and the dummy pads are electrically insulated from the interconnect structure through the interlayer dielectric layer.

19. The method for fabricating a semiconductor structure according to claim 17, wherein, The heat conduction wiring is formed on a heat conductor partially covered by the passivation layer of the interconnect structure.

20. The method for manufacturing a semiconductor structure according to claim 17, wherein, The heat-conducting wiring is formed on a heat conductor disposed on a passivation layer of the interconnect structure, and the heat conductor is embedded in the interlayer dielectric layer.

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