Semiconductor device structure having multiple gate terminals and method of forming the same

Abstract

The present invention provides a semiconductor device structure having multiple gate terminals and a method of forming the same. The present invention provides an integrated circuit including a field effect transistor having a metal-semiconductor contact and more than one gate terminal. In the present invention, an integrated circuit of a field effect transistor having multiple gate contacts (105) is proposed, and the multiple gate contacts (105) are preferably independent. Using the same channel (101) and a common source-drain contact formed by a metal-semiconductor contact at the channel ends, the gate contacts (105) are adjacent to each other. The present invention includes a method of forming an accurate metal-semiconductor alloy contact (124) at the ends of a channel (101) below an appropriate gate (105) of a transistor having multiple gate terminals, which is compatible with the dense integration of multiple gate contacts adjacent to each other using the same channel.

Description

Field of the Invention

[0001] The present invention relates to the field of microelectronics and, more particularly, to field effect transistors. Background of the Invention

[0002] Traditional microelectronic products are dominated by metal oxide field effect transistors (MOSFETs). A MOSFET is a three-terminal switching device that includes a source terminal, a drain terminal, and a gate terminal, which are isolated from other terminals by dielectric spacers. Conductivity in the MOSFET channel is fixed by doping to provide electron (n-type) or hole (p-type) conduction. Various types of metal oxide field effect transistors have been developed, which differ in their conduction mechanisms and structural configurations. The channel conductivity of a MOSFET is adjusted by the voltage applied to the gate terminal, which does not change the conduction mechanism. Normally-off MOSFET transistors with n-type or p-type conductivity are fabricated such that if 0V is applied to the gate terminal, the channel will not conduct electricity.

[0003] A second type of field effect transistor is the reconfigurable field effect transistor that often uses multiple gate terminals through a single channel region, where the conduction mechanism can be changed by varying the external voltage applied to the gate terminals. A typical example is a transistor that can be configured for electron or hole conduction. Another example is to reconfigure or the conduction mechanism itself, such as from inversion-mode conduction to interband tunneling conduction. To facilitate this functionality, a reconfigurable transistor requires at least two gate terminals. Devices with three or more gate terminals in series have also been described.

[0004] Typical reconfigurable transistors exhibit a metal-to-semiconductor contact at the source and drain terminals. This contact can be an ohmic contact, such as in the case of an interband tunneling field effect transistor, or characterized by a Schottky barrier. In typical silicon-based reconfigurable transistors, both contacts use nickel silicide with a near mid-gap Schottky junction as the contact material to enable reconfiguration between electron and hole conduction. In those reconfigurable transistors, the junction is directly controlled by two gates aligned above the metal-semiconductor contact to ensure carrier flow. However, other material combinations with different Schottky barrier heights are also possible, such as germanium and germanium manganite.

[0005] The third type of field-effect transistor is a normally-on transistor. One of the most well-known of these is called the junctionless field-effect transistor. This transistor type has a narrow but highly conductive channel that can be electrostatically depleted to turn off the transistor. If no external signal is applied such that the voltage applied to the gate terminal is 0V, the device is always in the on state. Despite being called "junctionless", they typically consist of ohmic metal-semiconductor contacts for ease of connection to the surrounding circuitry. Junctionless transistors are usually similar to MOSFETs, having only one gate terminal.

[0006] Field-effect transistors are the basic building blocks of integrated circuits such as microprocessors. A single integrated circuit contains thousands of individual devices that are connected in a specific way to produce the desired electrical functionality. To increase the number of transistors per unit area, the area required for an individual transistor is frequently reduced by shrinking the device size. This process is called scaling. Transistors with multiple gate terminals open up new ways of scaling integrated circuits because they combine multiple functions in a single element. Thus, even if the number of devices remains constant, the total number of functions on a chip can be increased.

[0007] To form an integrated circuit, multiple transistors must be connected to each other. Two basic variants are series connection, where two transistors are in a row, and parallel connection, where two transistors are adjacent to each other. Any number of parallel and series paths that form the connection from the power supply to the output is called a network. Several networks are combined to form a specific circuit. This is achieved by subsequent metal layers that are deposited on top of the transistors themselves. The connection between this metal layer and the transistors is typically achieved by doped raised source or drain epitaxial regions near the two edges of the MOSFET gate terminal. On top of this raised source-drain region, a self-aligned silicide is formed by a thermally activated diffusion process and then brought into contact with a metal plug. As the transistors are further miniaturized, the resistance of this contact becomes a major contribution to the total resistance of the transistor. In devices based on Schottky barriers, this effect is even stronger.

[0008] The precise, uniform, and reliable fabrication of such metal contacts is one of the greatest challenges in fabricating large-scale electronic devices. If a single transistor with a metal-semiconductor contact having a relatively large lateral dimension (i.e., a gate length of 100 nm or greater) is fabricated, metal containers with a relatively large lateral distance can be used to provide metal-semiconductor contacts at the source and drain. The large distance from the metal containers impedes the fabrication of small scaling and may be accompanied by variations in the contact position with the channel. In the case of a reconfigurable transistor, a metal-semiconductor alloy needs to contact the semiconductor under the gate terminal, and the alloy contacts formed through the entire raised source-drain region impose a large amount of stress, resulting in structural failure. In addition, the diffusion process is prone to large variations. Therefore, for a large number of transistors, precise alignment of the contacts under or near the gate terminal cannot be ensured. Although normally-on transistors (e.g., junctionless transistors) do not require the same amount of precision in electrical contact formation, having the metal-semiconductor contact close to the gate region is beneficial because such a structure reduces the overall resistance and minimizes the parasitic capacitance.

[0009] A solution is needed for forming precise metal contacts under the external gate terminals of transistors having multiple gate terminals, which is also compatible with the dense integration of many devices connected to each other. In addition, the total contact resistance and parasitic capacitance of each network should be minimized. Embodiments of the present disclosure provide devices for solving this problem and methods for forming such devices. SUMMARY OF THE INVENTION

[0010] The present invention provides an integrated circuit including a field-effect transistor having a metal-semiconductor contact and more than one gate terminal. In the present invention, an integrated circuit of a field-effect transistor having multiple gate contacts (105) is proposed, which is preferably self-contained ( Figure 1 , cross-section). Using the same (or one) channel (101) and a common source-drain contact formed by a metal-semiconductor contact (124) at the channel ends, the gate contacts (105) are adjacent to each other. The gate terminals generally include gate contacts (105) (metal or semiconductor contacts) having two adjacent dielectric spacers (106), which are isolated from the channel region by at least one dielectric layer (104) (usually a high-k dielectric) and electrically connected to another network or circuit.

[0011] According to the present invention, the gate terminals are divided into two groups ( Figure 2 , top view): firstly, the outermost gate terminals (221) located near the channel ends, and the second gate terminals (220) located between two or more other gate terminals. Additionally, according to the present invention, the channel is two or more parts (hereinafter named channel parts or sub-channels) without a gate, with one gate, or with more than one gate.

[0012] Thus, according to the present invention, the channel includes a plurality of channel portions. Additionally, according to the present invention, the channel includes nodes or intersections that electrically connect three or more channel portions. Another example of a field effect transistor according to the present invention includes two or more nodes that electrically connect four or more channel portions. In a specific embodiment of the present invention, the nodes divide the channel into different portions or unify the channel portions into one channel, and in some embodiments, one or more gate terminals (220) are used to control the conductivity of the channel portions.

[0013] The channel portions are electrically independent or autonomously controlled by their gate contacts. Except for forming nodes or intersections, all channel portions are electrically isolated from other channel portions of the transistor by a dielectric material. Thus, according to the present invention, the channels of different transistors are also spaced apart by a dielectric material.

[0014] Additionally, it may be advantageous to extend the channel or sub-channel into a third dimension perpendicular to the substrate surface direction. Thus, the common source-drain contact formed by a metal-semiconductor contact at the channel end can extend or be positioned in a third dimension perpendicular to the two dimensions described by the channel portions or the surface of the substrate.

[0015] Compared to the substrate surface, all sub-channels can be horizontally or vertically oriented. A single channel can include a mixture of horizontal and vertical sub-channels. Multiple sub-channels can be used in parallel. This can also be implemented in a stacked form. A single gate can be shared between horizontal and vertical sub-channels of the same or different devices.

[0016] Preferably for the present invention, one or more gate contacts are placed to control the conduction of the channel or sub-channel. Additionally, according to the present invention, the sub-channel ends ( Figure 2 ) are preferably implemented as raised source or drain terminals (222) that are connected by a metal-semiconductor alloy (223) to form a metal alloy-semiconductor contact below or near the outermost gate terminal (221) at the channel (201) end.

[0017] In one embodiment, the metal-semiconductor contact is a Schottky contact that forms a Schottky barrier. In this case, it is preferred that the channel has a low conductivity and has a small number of free charge carriers without the application of an external electric field. In another embodiment, the metal-semiconductor contact has an ohmic behavior. In this case, it is preferred that the channel has a high conductivity and has a large number of free charge carriers without the application of an external electric field.

[0018] Furthermore, according to the present invention, the metal-semiconductor contact (124) for a reconfigurable field-effect transistor is implemented at the channel ends as a source or drain contact of the Schottky barrier type located under or at the appropriate gate contact (105). Figure 1 ) In another embodiment, the metal-semiconductor contact for a junctionless field-effect transistor is implemented at the channel ends as a source or drain contact that is not located under or at the appropriate gate.

[0019] According to the present invention, the metal-semiconductor contact (124) is connected by a metal alloy wire or trace (123). In an advantageous embodiment of the present invention, the metal alloy conductor (108) reaches the top of the source and drain regions (107) that protrude beside the channel. Figure 1 ) Furthermore, according to the present invention, a spacing is achieved between the raised source-drain contact region and the gate contact, which is located above the metal-semiconductor contact at the channel ends.

[0020] The present invention provides a structure capable of reducing the amount of contact resistance and parasitic capacitance per network. Due to the scalability of this concept, the present invention relates to reducing variability as well as higher reliability and performance. As a specific result, the function of any logic network can be achieved within the scope of as few as a single transistor described in the present invention. In this way, the total amount of contact resistance and parasitic capacitance is reduced because each network only needs to be used once, rather than each device only once. However, it is still possible to build a network of more than one device or use a single device as multiple sub-networks.

[0021] The present invention realizes the scaling of the reconfigurable field-effect transistor concept or the normally-on transistor concept and the co-integration in a CMOS platform. It includes a method of forming an accurate metal-semiconductor contact (124) under or near the appropriate gate contact (105) of a transistor having multiple gate terminals at the channel ends, which can be compatible with many gate contacts densely integrated adjacent to each other using the same channel (101). Figure 1 ) The present invention includes an arbitrary-shaped semiconductor channel (101) as part of the semiconductor material on top of a dielectric layer (102) on top of a semiconductor body (103). Figure 1 ) In another embodiment of the present invention, the arbitrary-shaped semiconductor channel region is part of a semiconductor substrate.

[0022] On top of a semiconductor channel (101) of arbitrary shape, a dielectric layer (104) (gate dielectric) is formed and then two or more gate terminals are placed on top of the dielectric layer (104). Each sub-channel can be gated by one or more individual gate terminals. Thus, the total number of gate terminals is at least two. The regions between the gate terminals are isolated by a dielectric (109) and no electrical contact to the channel is formed, while at the outer edges of the outer gate structure, raised source and drain regions (107) are formed in a manner that has a substantial lateral distance from adjacent gate structures.

[0023] A metal alloy wire or trace (123) is formed in the channel portion near the outer gate structure such that a metal-semiconductor contact (124) (metal-semiconductor alloy-semiconductor junction) is formed near but not between two adjacent individual gate structures. In this way, the metal-semiconductor alloy contact can be formed very finely near the channel and there is no high variability. In addition, an electrical contact can be formed to the top of the raised source-drain structure, thus ensuring the possibility of the transistor contacting the metal layer above to form a circuit. Generally, at least two metal-semiconductor junctions are formed in the device, but depending on the number of sub-channels and intersections, devices with more than two metal-semiconductor junctions are also possible.

[0024] The proposed invention is fully compatible with the standard CMOS process. It can be co-integrated with classical CMOS devices. Description of the Drawings

[0025] Figure 1 : A cross-section of the device structure of a reconfigurable transistor is depicted, which has three gate contacts (105) formed on a semiconductor body (103) including at least one first semiconductor channel (101) as part of the present invention.

[0026] Figure 2 : A top view of an embodiment of the transistor of the present invention, which is composed of a single channel (201) and multiple independent gate terminals (220), wherein a part of the channel is two sub-channels and the two channels form a parallel network.

[0027] Figure 3 : A top view of another embodiment of the transistor of the present invention is depicted, which is composed of a channel (301) (formed by five sub-channels with two nodes) and eight gate terminals (320), wherein four gates are called the outermost gate contacts (321).

[0028] Figure 4a : A top view of a transistor having the function of routing the signals of two independent input terminals (431) to one output terminal (430).

[0029] Figure 4b : Figure 4a Logic table of the device in

[0030] Figure 4c : As a three-dimensional embodiment of the present invention, Figure 4a Cross-sectional view of a metal-semiconductor device of , having two horizontal channel portions stacked on top of each other and a vertical channel portion electrically connecting the two horizontal channel portions.

[0031] Figure 5a : Top view of a transistor having the function of distributing the potential of an input terminal (531) IN1 to two independent output terminals (530) OUT1 and (530) OUT2.

[0032] Figure 5b : Figure 5a Logic table of the device in , where OUT1 depends on gate terminal A and OUT2 depends on gate terminal B, and both OUT1 and OUT2 depend on the same terminal IN.

[0033] Figure 5c : As a three-dimensional embodiment of the present invention, Figure 5a Cross-sectional view of a metal-semiconductor device of , having two horizontal sub-channels stacked on top of each other and a vertical sub-channel portion electrically connecting the two horizontal sub-channels.

[0034] Figure 6a : Top view of a transistor forming a logic gate with internal branches. The branches connect two parallel sub-channels independently gated by gate terminals A and B (input signals) to two other parallel sub-channels independently gated by C and D.

[0035] Figure 6b : Figure 6a Logic table of the device in .

[0036] Figure 6c : As a three-dimensional embodiment of the present invention, Figure 6a Cross-sectional view of a metal-semiconductor device of , having two horizontal sub-channels stacked on top of each other and three vertical sub-channel portions electrically connecting the two horizontal sub-channels.

[0037] Figure 6d : Figure 6c Another embodiment of the device in , a vertical cross-section perpendicular to the substrate surface.

[0038] Figure 7a : Top view of a transistor forming a logic gate with multiple parallel sub-channels. A gate with multiple branches and inner gate vertical contacts is realized through one input terminal (731) IN, one output terminal (730) OUT, and six independent control gate terminals (732) A, B, C, D, E, and F.

[0039] Figure 7b : Figure 7a Logic table of the device in

[0040] Figure 8a : Top view of a transistor forming a logic gate with three parallel sub-channels. The device has an input terminal (831) IN, an output terminal (830) OUT, and four independent control gate terminals (832) A, B, C, and D.

[0041] Figure 8b : Figure 8a Logic table of the device in

[0042] Figure 9a : Top view of a transistor forming a logic gate with multiple sub-channels, including parallel and series sub-channel structures. Complex reconfigurable functions integrated in a single active region (901) are achieved through an input terminal (931) IN, an output terminal (930) OUT, and four independent control gate terminals (932) A, B, C, and D.

[0043] Figure 9b : Figure 9a Logic table of the device in

[0044] Figure 10a : Top view of an embodiment of a transistor structure. In this embodiment, a channel region (1001) is formed by eight sub-channel regions having four nodes and four ends. Two input terminals (1031) IN1 and IN2 and two output terminals (1030) OUT1 and OUT2 each share one of the outermost gate terminals (1034) P1 or the gate terminal (1033) P2 and are connected through two non-gated channels.

[0045] Figure 10b : Figure 10a Logic table of the device in

[0046] Figure 11 : Top view of an embodiment of the final transistor structure. In this embodiment, the gate has multiple sub-channels, four forming an inner ring and eight branching to the IN / OUT terminals. The structure includes 20 gates, 8 of which are program gates that closely cover the contact area.

[0047] Figure 12a : Top view of an integrated circuit constructed from two transistors with a shared OUT terminal. The external contacts of the device are respectively labeled P and NOT(P). The program gates of each circuit have inverted signals NOT(P) and P. Four input signals are applied to the circuit through the gate terminals A, B, C, and D.

[0048] Figure 12b : Figure 12a Logic table of the device in

[0049] Figure 13a : Cross-sectional view of an integrated circuit having hybrid vertical and horizontal channels.

[0050] Figure 13b : Figure 13a Top view of the circuit in along the vertical cutting axis A-A'.

[0051] Figure 14a : Top view of an integrated circuit implementation of a binary logic gate having gate terminals A, B, and C (inputs), which can be switched to function as a NAND gate for P at binary 0 and a NOR gate for P at binary 1.

[0052] Figure 14b : Figure 14a Cross-sectional view of the circuit in along the vertical cutting axis S-S'.

[0053] Figure 14c : Figure 14a Logic table of the device in

[0054] Figure 15a : Cross-sectional view depicting the formation of three gate terminals on a substrate including a first semiconductor channel region (1501) on top of a dielectric layer (1502) on top of at least a semiconductor body (1503).

[0055] Figure 15b : Cross-sectional view depicting the selective formation of raised semiconductor material on opposite sides of the outermost gate structure, whereby the raised source and drain regions (1507) do not directly contact the gate structure (1505) (gate contact) or its adjacent dielectric spacer (1506).

[0056] Figure 15c : Cross-sectional view depicting the selective formation of raised semiconductor material on opposite sides of the outermost gate structure, whereby, after partial removal of an additional spacer, the raised source and drain regions (1507) do not directly contact the gate structure (1505) (gate contact) or its adjacent dielectric spacer (1506).

[0057] Figure 15d : Cross-sectional view depicting the deposition of a metal layer (1511) on an entire structure including raised source and drain regions and gate terminals, whereby direct metal-channel contact is achieved in regions between each external gate structure (1505) and the raised source and drain regions (1507), but no metal-semiconductor contact is formed in the semiconductor channel region under the protective remnants of the spacers (1509) between the gate structures.

[0058] Figure 15e : A cross-sectional view depicting the final semiconductor device structure contemplated by the present invention.

[0059] Figure 16 : Figure 15e Another embodiment of the structure shown, wherein the semiconductor device structure according to the present invention includes two gate terminals. A raised source or drain contact of the semiconductor device is shared with an adjacent conventional MOSFET channel (1612).

[0060] Figure 17 : A cross-sectional view depicting another embodiment of the semiconductor device structure according to the present invention having four gate terminals for forming a junctionless or normally-off transistor with a highly doped channel. Detailed Description

[0061] In an effort to reduce power consumption and information transfer time, a new approach to devices and architectures that can scale current technology and potentially provide a new information processing platform is needed. The present invention applies this by providing an integrated circuit including a field effect transistor having a metal-semiconductor contact and multiple gate terminals. In the present invention, a field effect transistor integrated circuit ( Figure 1 ) having independent multiple gate contacts (105) is described. The gate contacts (105) are patterned adjacent to each other using the same channel (101), and a common source-drain contact is formed at the channel ends through a metal-semiconductor contact.

[0062] According to the present invention, the channel (201)( Figure 2 ) is two or more sub-channels or channel portions that do not have, have one or more gate terminals (220), and two outermost gate terminals (221). The sub-channels or channel portions are connected by nodes or intersections. Additionally, according to the present invention, it is advantageous to extend the channel portion or sub-channel into a third dimension perpendicular to the direction of the region spanned by the two sub-channels, which in most cases is the planar region of the substrate. Thus, the common source-drain contact formed at the channel ends through a metal-semiconductor contact can extend or be located in the third dimension, which is the direction perpendicular to the region spanned by the sub-channels or the substrate.

[0063] According to the present invention, the integrated circuit includes a transistor that includes a semiconductor channel and the channel includes three channel portions or sub-channels. Additionally, according to the present invention, the integrated circuit includes a transistor that includes a semiconductor channel that includes a node electrically connecting the three channel portions. Further, according to the present invention, the semiconductor channel includes more than one node that electrically connects three or more channel portions.

[0064] In one embodiment, Schottky contacts are formed at each end of the channel. A gate contact is provided to control the Schottky barrier type of each Schottky contact of the channel. According to the present invention, the Schottky contacts are electrically independent and electrically independently addressable. In a particular embodiment, two or more Schottky contacts are electrically connected to apply the same electric potential to the electrically connected Schottky contacts.

[0065] The gate contact is provided to control the conductivity of a channel portion. In another embodiment, the semiconductor channel includes more than one gate contact provided to control the conductivity of a channel portion. Additionally, in one embodiment of the present invention, the channel includes more than one gate contact to control the conductivity of the channel portion. According to the present invention, the gate contacts are electrically independent and electrically independently addressable. In a particular embodiment, two or more gate contacts are electrically connected to apply the same electric potential to the electrically connected gate contacts.

[0066] In other embodiments including a transistor channel that electrically connects three or more channel portions to one or more nodes, ohmic contacts are formed at each end of the channel. One or more gate contacts are provided to control the conductivity of a channel portion or are provided to control the conductivity of the channel portions. Each sub-channel or channel portion is controlled by a separate gate contact.

[0067] One embodiment of the present invention is an integrated circuit including a planar or vertical semiconductor channel having two ends. The channel is divided into a plurality of sub-channels or channel portions between the two ends of the semiconductor channel or includes a plurality of sub-channels or channel portions.

[0068] In a more complex embodiment of the present invention, the transistors of the integrated circuit elements are designed such that the semiconductor channel has a plurality of source or drain Schottky contacts that are preferably parallel to each other. The polarity of each Schottky contact is controlled by a gate contact. In a particular embodiment, the conductivity of one or more sub-channels is controlled by one or more gate contacts in series that control different segments along the sub-channel.

[0069] In a particular embodiment, a plurality of parallel planar sub-channels or channel portions are connected together to a common source or drain Schottky contact. Additionally, the Schottky contact is connected to one or more planar sub-channels. In another embodiment, a plurality of parallel planar sub-channels are connected together to a common source or drain Schottky contact, and the common source or drain Schottky contact is oriented perpendicular to the planar sub-channels of the channel portion. In another embodiment, the Schottky contact is oriented perpendicular to the substrate and is connected through one or more sub-channels oriented parallel to the substrate.

[0070] In another, more complex, embodiment of the present invention, the transistors of the integrated circuit element are designed such that the semiconductor channel has more than one ohmic contact, preferably in parallel with each other. For each sub-channel, the conductivity is controlled by a separate gate contact. In a particular embodiment, the conductivity of one or more sub-channels is controlled by one or more gates that are serially controlled along different segments of the sub-channel.

[0071] Furthermore, according to the present invention, in an integrated circuit including more than one transistor as described herein, the transistors are mainly isolated by an isolation material. The channel portions of two or more transistors connected by a node (sometimes referred to as a point contact or node contact) are electrically isolated by gate contacts that apply the required respective electrical potentials, thereby achieving electrical isolation of the two or more transistors.

[0072] Figure 2 A top view of an embodiment of a reconfigurable or junctionless transistor according to the present invention is described, which consists of a channel (201), where a portion of the channel divides into two sub-channels or is two sub-channels at a node. The two sub-channels form a parallel network that is in series with the other portions of the channel. A plurality of independent gate terminals (220) are shown adjacent to the sub-channels. In this embodiment, two of them can be distinguished as the outermost gate terminals (221). A metal-semiconductor alloy (223) is formed directly on the semiconductor channel near the two outermost gate terminals (221). Formation of a contact between the two separate gates is prevented. The top source and drain terminals (222) having a metal-semiconductor alloy are electrically connected to the channel (201) by forming an alloy that makes electrical contact directly at the end of the channel (201).

[0073] According to the present invention, Figure 1 A cross-sectional view showing the device structure of a reconfigurable transistor having three gate terminals is shown. A plurality of gate terminals are formed on a substrate of at least a first semiconductor channel (101) on top of a dielectric layer (102) on top of a semiconductor body (103), and Figure 1 in this case there are three gate terminals. Thus, the gate terminals include a gate contact (105) (metal or semiconductor contact) having two adjacent dielectric spacers (106), which are isolated by at least one dielectric layer (104), typically a high-k dielectric, through the channel region.

[0074] In the described embodiment, in addition, a metal-semiconductor alloy (110) is formed on top of the gate contact (105) (gate metal stack or polysilicon). The channel portion between the two gate terminals is passivated by the same dielectric layer. The individual gate contacts are isolated from each other. Raised source and drain regions (107) are formed to ensure connection of the device to the subsequent metal layer. A metal-semiconductor alloy is formed directly on the ends of the semiconductor channel (101) and on the adjacent raised source and drain regions (107) near the two outer gate terminals. The region between the two gate terminals is isolated by a dielectric (109). No electrical contact with the channel is formed between the two gate terminals. With this structure, the position of the metal-semiconductor contact (124) (metal-semiconductor alloy-semiconductor junction) between the semiconductor channel (101) and the metal alloy conductor (108) and the metal alloy wire or trace (123) is adjusted. The metal alloy conductor (108) and the metal alloy wire or trace (123) are preferably also connected to the raised source and drain regions (107) to reduce variability.

[0075] In Figure 1 or Figure 2 In an exemplary embodiment of the planar implementation of the described transistor, the channel is made of single-crystalline silicon. The channel dimensions are 5 nm high, 20 nm wide, and 600 nm long. The silicon layer is on top of a dielectric layer (102) (SiO2 layer) on top of the semiconductor body (103) (silicon substrate). The silicon of the channel is intrinsic or lightly p-doped, less than 10E16 dopants / cm 3 . The crystal orientation of the silicon sub-channel is described by the Miller indices as

[110] . The channel has a dielectric layer (104) (thermally grown SiO2 dielectric shell) with a thickness of 5 nm. The gate contact (105) is made of ALD-deposited TiN with a thickness of 10 nm, which has a work function of 4.8 eV and 30 nm of Pt covering the TiN. The width of the gate contact (105) is 300 nm. Adjacent gates are set at a distance of 150 nm from each other. The spacer (106) is made of SiN. The raised source and drain regions (107) are made of epitaxially grown silicon and are 40 nm long, 40 nm wide, and 40 nm high at the maximum extension point. The remaining dielectric mask material between the gate contacts (105) consists of sputtered SiO2. The metal alloy wire or trace (123) at the metal-semiconductor contact (124) is made of nickel silicide, which has an atomically clear interface with the silicon atoms of the channel. The nickel silicide in this embodiment has an effective work function of 4.84 eV, and a wire or trace (123) of nickel silicide is formed that reaches the top of the raised source and drain regions.

[0076] Figure 3A top view depicting another embodiment of a reconfigurable or junctionless crystal formed by a channel (301) in accordance with the present invention is shown. The channel (301) is composed of five sub-channels connected by two nodes. A plurality of gate terminals (320) are patterned above the channel. In this embodiment, the channel is formed such that four gate contacts are the outermost gate contacts, so that the metal-semiconductor contact is positioned below the appropriate gate contact (321) at the end of each sub-channel. Source and drain terminals with a raised portion having a metal-semiconductor alloy are formed at the top (322) and are far from all four outermost gate contacts. A metal-semiconductor alloy (323) is formed directly on the semiconductor channel (301) near the two outer gate terminals. Contact formation between two independent gates is prevented.

[0077] The figures of FIGS. 4 to 14 depict specific circuit elements for solving circuit tasks for different electronic applications that use a semiconductor transistor structure in accordance with the present invention. The following detailed description is given by way of example of specific circuit elements and is not intended to limit the present invention thereto. The corresponding logic tables assume a binary 1 on the input (IN), a binary 0 on the gate covering the contact to the output through the gate terminal (P2), and the use of a reconfigurable field effect transistor (RFET). P2 is necessary to ensure that the Schottky junction adjacent to each gate is open to transmit the required charge carriers. For the use of normally-on transistors, no gate covering or surrounding the contact area is required to set the polarity. The given truth table remains valid. The value of P is determined by the doping type and is fixed for each individual embodiment. The corresponding logic table for a normally-on transistor requires an input signal level opposite to that of the RFET to generate the same output.

[0078] If all the outermost gates are controlled simultaneously by the same programming, all devices with more than two gates can also be used as transfer gates.

[0079] Figure 4aShows a top view of the final metal-semiconductor device structure of an embodiment of a transistor according to the present invention, the transistor having the function of routing two independent input terminals (431) to one output terminal (430). This embodiment can be used in a multiplexer. The transistor consists of two sub-channels, one having an input terminal (431) IN1 and a control gate terminal (432) A, and the other having an input terminal (431) IN2 and a control gate terminal (432) B. The two sub-channels are connected to each other and to a third sub-channel leading to the output terminal (430) OUT. Additional gate terminals (434) such as P1a and P1b near the input terminals (431) IN1 and IN2 can be used to integrate the wired-AND functionality of P1a and A and P1b and B respectively. A fourth gate terminal (433) P2 is used to set the polarity of the device.

[0080] Figure 4b shows Figure 4a the logic table of the device in. If at least both of P1a and A or P1b and B are binary 0, the output is binary 1. In other cases, the output is at the logic level high impedance (Z). In another embodiment of the present invention, Figure 4a the semiconductor device of is arranged by a stacked layer ([[]] Figure 4c ). In [[[]] Figure 4c a three-dimensional embodiment according to the present invention is shown, which is formed by stacking layers having two horizontal channel portions stacked on top of each other and a vertical channel portion electrically connecting the two horizontal channel portions. The channel portions are vertically electrically isolated by a dielectric layer (414), preferably a low-k dielectric. The gate terminals (432, 433, 434) for a single signal are electrically isolated from the channel (401) by a gate dielectric layer (404). Source and drain contacts are formed at the input terminals (431) and the output terminal (430) by a metal alloy-semiconductor contact (424).

[0081] In a particular embodiment, Figure 4a the transistor in can be part of a network of two such devices connected at the output. If in this embodiment, IN1 and IN2 in one device are binary 1, while P1a, P1b and P2 are binary 0, and if in another device these binary values are opposite, and if the input through gate terminal A is defined as the inverted signal of the input through gate terminal B, then this network can be used as a multiplexer.

[0082] Figure 5aA top view of another embodiment of a transistor according to the present invention is shown, having the function of distributing the potential on the input terminal (531) IN1 to two independent output terminals (530) OUT1 and OUT2. Each output terminal is controlled by a separate gate terminal (532) A and B. In the case of using an RFET, the gate terminal (534) P1 is used as an additional control unit to turn off the device. The fourth gate terminal (533) P2 is used to set the polarity of the device. If P1 is used as an independent control signal, a higher amount of functionality can be achieved.

[0083] Figure 5a The binary function of the device in Figure 5b is described by two tables in Figure 5a One table refers to the signal level of OUT1 and the other table refers to the signal level of OUT2. In another embodiment of the present invention, Figure 5c ) Figure 5c A three-dimensional embodiment according to the present invention is shown, which is formed by stacking layers ([[]] Figure 5c ) having two horizontal channel portions stacked on top of each other and a vertical channel portion electrically connecting the two horizontal channel portions. The channel portions are vertically electrically isolated by a dielectric layer (514) preferably having a low k dielectric. The gate terminals (532, 533, 534) of individual signals are electrically isolated from the channel (501) through a gate dielectric layer (504) and from the input terminal (531) IN1 (source terminal) and output terminals (530) OUT1 and OUT2 (drain terminals) formed through a metal alloy-semiconductor contact (524).

[0084] Figure 6a Another embodiment of the present invention describing a logic transistor employing internal branches is described. The branches connect two parallel sub-channels gated by gate terminals (632) A and B respectively to two parallel sub-channels gated by gate terminals (632) C and D respectively. In the case of an RFET, the gate terminals P1 and P2 are used to set the polarity of the device. If P1 is used as an independent control signal, a higher amount of functionality can be achieved. Figure 6a The table in Figure 6a describes the binary function of the device in

[0085] Figure 6c shows Figure 6a an alternative embodiment of the transistor in Figure 6cShows a three - dimensional embodiment according to the present invention, which is formed by stacking layers having two horizontal channel portions stacked on top of each other and a vertical channel portion electrically connecting the two horizontal channel portions. These two layers are connected by vertical columns of semiconductor material, which can be grown, for example, by epitaxial growth or from polycrystalline or crystalline amorphous materials. The channel portions are vertically electrically isolated by a dielectric layer (614). As an example, a low - k dielectric is used to isolate the channel portions from each other and from the carrier substrate. The gate terminals (632, 633, 634) are electrically isolated from the channel (601) and the source and drain terminals (630, 631) formed by a metal - alloy - semiconductor contact (624) through a gate dielectric layer (604).

[0086] Figure 6d Shows in cross - section Figure 6c Another embodiment of a semiconductor device structure. Three horizontal channel layers are stacked on top of each other. Vertical pillars of semiconductor material connect the channel portions. All gates surround the vertical channel portion in four layers and are electrically insulated from the channels by a gate dielectric layer (604) (high - k dielectric) and a dielectric layer (614) (low - k dielectric).

[0087] Figure 7a Shows a top view of another embodiment of a transistor according to the present invention, which has three parallel sub - channels. The internal gate terminal can be realized by a vertical contact. A transistor with multiple sub - channels (701) having connections to the same node and a vertical contact for the internal gate terminal is realized through an input terminal (731) IN, an output terminal (730) OUT, and six independent control gate terminals (732) A, B, C, D, E, and F. In the case of an RFET, the gate terminals (734) P1 and the gate terminal (733) P2 are used to set the polarity of the device. If P1 is used as an independent control terminal, a higher amount of functionality can be achieved.

[0088] By Figure 7b The table in Figure 7a describes the binary functions of the devices in

[0089] Figure 8aA top view of another embodiment of a transistor according to the present invention is shown. The transistor has three parallel sub-channels (801). The transistor has an input terminal (831) IN, an output terminal (830) OUT, and four independent control gate terminals (832) A, B, C, and D. In the case of an RFET, gate terminals (834) P1 and gate terminal (833) P2 are used to set the polarity of the device. If P1 is used as an independent control terminal, a higher amount of functionality can be achieved. The internal channel is gated by gate terminals A and D. If gates B and D have the same signal, such a device can be used as a pull-up or pull-down network in a 3-MIN or 3-MAJ gate, respectively.

[0090] Through Figure 8b The table in Figure 8a describes the binary functions of the device in

[0091] Figure 9a A top view of another embodiment of a transistor according to the present invention is shown. The transistor has multiple sub-channels, including sub-channels in series and parallel layouts. By an input terminal (931) IN, an output terminal (930) OUT, and four independent control gate terminals (932) A, B, C, and D, complex reconfigurable functions are integrated within a single active region (including parallel and series regions). In the case of an RFET, gate terminals (934) P1 and gate terminal (933) P2 are used to set the polarity of the device. If P1 is used as an independent control terminal, a higher amount of functionality can be achieved. Gate terminals A and B control the sub-channel between P1 and the node. Gate terminal B additionally covers the node connecting three sub-channels to save area and prevent the formation of potential barriers in long ungated sub-channel segments. Gate terminals C and D are each independently aligned with one in parallel.

[0092] Through Figure 9b The table in Figure 9a describes the binary functions of the device in

[0093] Figure 10a A top view of another embodiment of a transistor according to the present invention is shown. In this embodiment, a channel region (1001) is formed by eight sub-channel regions having four nodes and four ends. Two input terminals (1031) IN1 and IN2 and two output terminals (1030) OUT1 and OUT2 each share one of the outermost gate terminals (1034) P1 or gate terminal (1033) P2 and are connected via two ungated sub-channels. Thus, effectively, the device has only one input and one output, but with Figure 2Compared with the variants in [reference], both have a larger channel cross-section. Two of the sub-channels have gate terminals (1032) thereon and form a parallel network. One of these sub-channels is covered by the gate terminal, and the other is connected in series through gate terminals B and C.

[0094] Figure 10b shows Figure 10a the logic table of the device in [reference]. As long as P1 is binary 0, and at least the inputs through gate terminals A or B and C are both binary 0, the output of the device is 1. In all other cases, the output is at the logic level high impedance (Z). Therefore, these devices combine the AND operation of the inputs through gate terminals B and C with the OR operation of the AND connection of the input through gate terminal A and the inputs through gate terminals B and C. In the case of RFETs, gate terminals P1 and P2 are used to set the polarity of the device. If P1 is used as an independent control terminal, a higher amount of functionality can be achieved.

[0095] Figure 11 shows a top view of another embodiment of a transistor according to the present invention, having a channel (1101) with multiple sub-channels connected by four nodes, thereby forming an inner ring and eight connections to the IN / OUT terminal (1136). This structure contains 20 gate terminals, of which 8 are program gate terminals (1133) near the contact area. Each of the eight outer sub-channels between the IN / OUT terminal and the central sub-channel ring is covered by a program gate terminal and a control gate terminal (1132). Another four gate terminals (1137) each cover a single one of the four sub-channel segments of the inner ring structure. These gates can divide the device into one to up to four electrically isolated structures.

[0096] Figure 12a shows a top view of an integrated circuit of two transistors according to the present invention, both of which have separate channels (1201) each sharing an OUT terminal (1230). The outer contact terminals (1231) of the device are provided with P and NOT(P) respectively. The program gate terminals (1233) of each circuit have reverse signals NOT(P) and P. Four gate terminals (1232) (input terminals) A, B, C, and D are applied to the circuit. The function of each transistor changes according to the signal of P. For P being binary 0, the circuit functions as an OR-AND-Invert (OAI) logic gate, and for P being binary 1, the circuit functions as an AND-OR-Invert (AOI) logic gate. Through Figure 12b the table in [reference] describes Figure 12a the binary function of the circuit in [reference].

[0097] Depending on the functions required for each specific application, various combinations of horizontal and vertical channels and channel sections can be implemented. For example, Figure 13a An n-integrated circuit is shown having hybrid vertical and horizontal channels and channel sections (1301), input / output terminals (1331), and gate terminals (1332). The channels or channel sections are vertically electrically isolated by a dielectric layer (1314), preferably a low-k dielectric. The gate terminals (1332) are electrically isolated from the channel sections (1301) by a gate dielectric layer (1304).

[0098] Figure 13b is Figure 13a A cross-section of the integrated circuit along the cutting axis A-A'. Two surrounding gate terminals gate a vertical channel section of a transistor. The lower gate terminal overlaps an adjacent lateral channel section of another transistor. Thus, a gate terminal is shared between the vertical and planar channel sections of two transistors of the integrated circuit.

[0099] Figure 14a A top view of an integrated circuit of two transistors according to the present invention is shown. Both are implementations of binary logic functions at the output terminals (1430), which can switch between performing the NAND function of the signal of P for binary 0 and the NOR function of P for binary 1 at the input gate terminals (1432) A, B, and C.

[0100] Metal contacts (1417) and wires (1416) are used for multiple terminals having a common potential. An efficient design distributes the input signals from the gate terminals A, B, and C to the corresponding gate terminals (1432), and distributes the program signals P and NOT(P) to the corresponding gate terminals (1439) and source terminals (1438), without area overhead for routing the input signals between the pull-up and pull-down networks. The shared planar gate-to-vertical gate contacts at the gate terminals B and C enable these direct signal routing geometries. In one embodiment, the required grid size is 10×10F 2 , including the side isolation area.

[0101] Figure 14b Shows Figure 14a A cross-sectional view of the integrated circuit of two transistors according to the present invention along the cutting axis S-S' as shown in. Two gate terminals (1433) surround a vertical sub-channel of a channel having vertical and horizontal portions (1401). The channel section is separated from the gate terminals by a gate dielectric (1404). One of the gate terminals extends over and covers a planar channel section of an adjacent second transistor. Thus, this gate is shared between the repeating and horizontal channels. The channel sections are electrically isolated by a dielectric material (1414), preferably a low-k dielectric.Figure 14c The table in Figure 14a describes the binary function of the circuit in

[0102] In one embodiment, as described below, the proposed transistor is built on top of a single straight semiconductor channel by three independent gate terminals at the top, without any nodes or intersections. The following detailed description is given by way of examples of forming the structure, and it is not intended to limit the present invention thereto. In different embodiments, as below, the proposed transistor is built on top of a semiconductor channel of four or more semiconductor sub-channels by four or more individual gate terminals, having two nodes or intersections and two ends. Generally, both the number of sub-channels and the shape of the resulting semiconductor vibrating channel region are arbitrary. With reference to the accompanying drawings, the general case with multiple sub-channels can be best understood, in which the same reference numerals denote the same elements and components.

[0103] According to the present invention, the following detailed description gives an integrated circuit that includes a transistor, which includes a semiconductor channel that includes one or more nodes electrically connecting three channel portions. In one embodiment, Schottky contacts are formed at each end of the channel, and gate contacts are positioned to control the Schottky barrier type of each Schottky contact of the channel. Additionally, the channel includes more than one gate contact to control the conductivity of the channel. In other embodiments, the following detailed description gives the formation of a transistor channel that includes one or more nodes that electrically connect three or more channel portions, and Ohmic contacts are formed at each end of the channel. One or more gate contacts are provided to control the conductivity of one channel portion or are provided to control the conductivity of the channel portions.

[0104] Additionally, according to the present invention, the integrated circuit includes a semiconductor transistor having two or more gate electrodes constructed above a lateral semiconductor channel. All gate contacts are electrically isolated from each other by a dielectric spacer material and have no electrical contact with the channel between the respective gate electrodes. The structure includes a raised semiconductor region that is separated from the spacer of the outermost gate structure; a metal-semiconductor alloy is present at each end of the channel end, at the top of the raised region, and between the raised region and the outermost gate structure. The metal alloy forms a Schottky contact or an Ohmic contact at all channel ends.

[0105] In one embodiment of the present invention, an integrated circuit includes a semiconductor transistor having a semiconductor channel and an isolation dielectric material over the semiconductor channel. Two or more gate contacts are located over the isolation dielectric material. Electrically, all the gate contacts are separated from each other by a dielectric spacer material. A raised semiconductor region is separated from the outermost gate structure by a spacer, and a conductive material is formed near the raised region up to each channel end. The conductive material forms a Schottky barrier contact located under the outermost gate contact.

[0106] In another specific embodiment, the conductive material forms an ohmic contact. Preferably, the conductive material is a metal alloy.

[0107] The illustrative method disclosed herein includes providing, for example, a semiconductor structure for a transistor of an integrated circuit, the transistor including three or more gate contacts and including one or more nodes electrically connecting three channel portions. The semiconductor structure includes a semiconductor channel material and a gate stack, the gate stack including a transistor dielectric over the channel material and a top electrode material over the gate dielectric (1504, 1604, 1704) (transistor dielectric), the top electrode material being structured into three or more gate structures, each gate structure being electrically isolated by a dielectric spacer material and ultimately being processed into a gate electrode or a more complex gate terminal. In another embodiment, the gate stack includes a gate insulating material on a substrate, a channel material on the gate insulating material, a transistor dielectric on the channel material, and a top electrode material on the transistor dielectric, the top electrode material being structured into three or more gate structures, each gate structure being electrically isolated by a dielectric spacer material and ultimately being processed into a gate electrode or a gate terminal.

[0108] Execute a first mask material. The first mask material masks the gate structures and defines a region beside the gate structures. The method further includes protecting the transistor dielectric material outside the region by the mask material. The method of processing the transistor further includes epitaxial growth on the channel material of the transistor, thereby forming raised source / drain regions from which the transistor dielectric has been removed.

[0109] Remove the mask material. In other embodiments, it is advantageous to leave the mask material between the gate structures. This method includes partially removing the mask material such that the mask material outside the region between the gate structures is completely removed so that the mask material remains between the gate structures.

[0110] Depositing a conductive material. In a specific embodiment, a metal is used as the deposited conductive material. A metal-semiconductor alloy is formed on top of the epitaxial growth region and on top of the channel material below the outer gate structure through a subsequent annealing step, and a Schottky or Ohmic contact is formed under the outer gate structure. The unalloyed portion of the conductive material is removed. In other embodiments, it is advantageous to form a metal alloy parallel to the top of the gate structure to form a metal alloy on the epitaxial growth region and the channel material. For such applications, the method includes forming a metal-semiconductor alloy on top of the semiconductor gate structure.

[0111] In another embodiment, advantageously, after forming a metal alloy at the source and drain, the gate metal or gate polysilicon and the gate dielectric material are removed, while the isolation material between the two separate gate structures is not removed. This step is followed by depositing a high-k dielectric into the opened channel portion and subsequently depositing a new gate metal deposition on the high-k dielectric.

[0112] In another illustrative method disclosed herein, a semiconductor transistor includes a semiconductor substrate and a stack including a gate insulating material on the substrate and a channel material on the gate insulating material. A first mask material masks the channel material on the gate isolation material in a defined region. Additionally, the method includes epitaxially growing on the channel material of the transistor that is not masked by the mask material to form raised source and drain regions. Depositing a conductive material. In a specific embodiment, a metal is used as the deposited conductive material.

[0113] Through a subsequent annealing step, a metal-semiconductor alloy is formed on top of the epitaxial growth region and on top of the channel material below the outer gate structure, and a Schottky or Ohmic contact is formed under the outer gate structure. The unalloyed portion of the conductive material is removed. The mask material is removed. The method includes further processing a gate structure from the gate stack on top of the metal-semiconductor alloy and the channel material such that the gate structure is located above the Schottky contact formed between the metal alloy and the channel electrode material.

[0114] Finally, the processing of the integrated circuit is completed by methods known to those of ordinary skill in the art.

[0115] In a more detailed embodiment of the present invention, as described in the present invention, the processing of a device or devices uses a planar semiconductor substrate or semiconductor body (1503) (wafer) (Figure 15). In other embodiments, the processing of the devices described in the present invention uses a pre-processed substrate that already includes other different devices partially covering the substrate, such as CMOS transistors or diodes. The semiconductor substrate can be silicon (Si), germanium (Ge), tin (Sn), a mixture of these materials, or a III-V material such as GaAs.

[0116] Figure 15aIt is a cross-sectional view of forming multiple (here three) gate terminals on a substrate depicting a first semiconductor channel region (1501) on top of at least a dielectric layer (1502) on top of a semiconductor body (1503). The gate structure (1505) (gate terminal) thus includes a metal or semiconductor contact having two adjacent dielectric spacers (1506), which is isolated from the channel region by at least one dielectric layer, typically a gate dielectric (1504) (high-k dielectric). The channel portion between two gate terminals is passivated by the same dielectric layer. Each gate terminal is isolated from each other by a certain distance.

[0117] On the surface of the substrate, there is a channel region (1501). The semiconductor channel region can be silicon (Si), germanium (Ge), carbon (C), tin (Sn), mixtures of these materials, III-V materials such as GaAs, or layered materials such as graphene or MoS2. The channel region can be single crystal, polycrystalline, or amorphous. The channel region is processed on top of a dielectric layer (1502) (buried oxide or electrically insulating layer). The dielectric layer (1502) (buried oxide layer) can be formed by ion implantation under the surface followed by a heat treatment (e.g., rapid thermal processing (RTP)). Through the RTP treatment, the dielectric layer (1502) (buried oxide layer) is formed, and a channel region (1501) is formed adjacent to this layer between the buried oxide and the substrate surface. In another embodiment, the buried oxide layer is processed by epitaxial growth of a dielectric layer (1502) (electrically isolating layer). Thereafter, the channel is grown by epitaxial growth or by other deposition techniques (e.g., CVD deposition) and a previous annealing (e.g., using RTP).

[0118] On top of the channel region (1501), a gate dielectric (1504), usually an oxide, is processed. In another embodiment, depending on the requirements of the device described in the present invention, no gate oxide is required, so there is no need to process a gate oxide. In other known applications, the gate oxide is processed after forming an electrically isolating layer (commonly referred to as a spacer (1506)) of the gate structure (1505) (gate contact). If needed or advantageous, different techniques can be used to process the gate dielectric (1504) (gate oxide). One technique is wet oxidation of the channel material by heat treatment. If needed, other techniques are CVD or ALD deposition followed by a heat treatment such as RTP. The gate dielectric material can be one of SiO2, Si x N Y 、Al2O3, and HfO2, GeO2, or TiO2. It can be a layer stack of especially the materials mentioned. And different dopants such as Si, Zr, Y, Sr, F, and La can be used.

[0119] In one embodiment of the present invention, the channel region is processed. The top view shape of any channel region is formed by lithography or other suitable techniques and transferred to the channel region by an etching process. The etching process can be wet etching, dry etching, such as reactive ion etching (RIE) or atomic layer etching (ALE), and the gate oxide is removed in regions where no further device formation is required. In another embodiment of the device of the present invention, after forming the gate structure (1505) (gate contact) and the electrical insulation of the gate contact (commonly referred to as the spacer (1506)), the channel region is structured.

[0120] Subsequently, in a subsequent step, according to a specific embodiment of the present invention, the respective gate structures (1505) (gate contacts) are patterned on top of the unstructured or structured gate oxide. The gate terminals themselves can be formed in a gate-first or gate-last manner. A small distance between the respective gates can be achieved by a lithography technique called the double (or quadruple) patterning method, such as double exposure, lithography-etching-lithography-etching, or self-aligned double patterning. Other methods are to use EUV or X-ray lithography. An etch stop must be achieved on the gate dielectric (1504) (gate oxide) to prevent damage to the channel region between the respective gates. The gate terminals isolated by self-aligned spacers (or gate spacers) adjacent to the gate terminals are generally perpendicular to the substrate surface. Depending on whether it is advantageous for the device of the present invention, two adjacent gate spacers can be processed so that there is no space between them. The spacers are generally made of Si x N y or SiO2.

[0121] In one embodiment of the present invention, after forming the gate terminals, raised source and drain regions (1507) are processed on the semiconductor surface channel by epitaxial growth of Si or SiGe ( Figure 15c ). In another embodiment of the present invention, especially if a technique is used in which the gate terminals are processed after processing the isolation gate spacers, the gate terminals are processed after processing the source and drain contacts. The epitaxial growth of Si or SiGe is processed by high-temperature CVD treatment or a similar technique. The thickness of the raised source and drain regions depends on the overall technical requirements and ranges from a few atomic layers to up to 100 nm or more. The raised source and drain regions directly depend on the overall technical requirements used for circuit processing. The typical diameter is 50 to 250 nm.

[0122] Figure 15bIt is a cross-sectional view showing selectively formed raised semiconductor materials on opposite sides of the outermost gate structure, whereby the raised source and drain regions (1507) do not directly contact the gate terminals or their adjacent dielectric spacers (1506). In this embodiment, this is achieved by adding a single spacer (1509) before epitaxially forming the raised source and drain connections for source and drain contacts to reach all the gate terminals.

[0123] One advantage of the transistor of the present invention is the source and drain contacts (1524), which in this embodiment are created by forming a lateral metal-to-semiconductor alloy (1523) along a channel parallel to the substrate surface. In other embodiments, if the channel region is formed perpendicular to the substrate surface, the lateral metal-to-semiconductor alloy formation still occurs along the channel, in which case it repeats on the surface of the substrate.

[0124] In one embodiment, the source and drain regions (1507) are processed using a lithography step, followed by a wet or dry etching process to open the source-drain contact regions so that the channel region (1501) (channel layer) between the source and drain regions (1507) and the spacers (1506) of the external gate structure (1505) (gate contact) can be accessed from the top. The addition and layout must be completed so that subsequently, the source and drain contacts (1524) are positioned according to requirements and as in the present invention close to their respective gate terminals.

[0125] Therefore, the process of forming the lateral metal-to-semiconductor alloy later must start near the semiconductor channel below the raised source and drain epitaxial regions typically used at the outermost gates of the structure to provide high controllability and reliability ( Figure 15b ). This requirement can be achieved by locally isolating the raised source and drain epitaxial regions. In some embodiments, the separation of the source and drain epitaxial regions can be accomplished by a blocking mask covering all the gates of the transistor or a self-aligned blocking spacer (1509). In the embodiment described with respect to this processing, the number of gates covered by the blocking mask and the self-aligned blocking spacer has an unequal number of gate terminals in a row, allowing the processing of the devices of the present invention using unequal numbers of gate terminals. Typical materials used as the blocking diaphragm are, for example, SiO2, Si x N y , Al2O3, HfO2, ZrO2, a photoresist-based mask, or a combination of such materials.

[0126] Meanwhile, contact filling or alloy formation between individual gates of a single transistor must be prevented. In some embodiments, contact filling can be prevented by a blocking mask or self-aligned blocking spacers that cover all the gates of the transistor. The same spacers of the blocking mask can achieve both effects simultaneously. Subsequently, as described above, the gate dielectric in the defined source-drain regions is removed by wet or dry etching, and raised source and drain regions can be formed using epitaxial growth of a semiconductor material. If the substrate is silicon, the material used to form the raised source and drain regions is, for example, silicon, Ge, SiGe, or SiC. If the substrate is germanium, the raised source-drain material is, for example, Ge or GeSi. If the substrate is GaAs, materials such as GaAs are used. The raised source and drain regions (1507) are processed by epitaxial growth or a CVD process and then thermally annealed.

[0127] In another embodiment, as described above, raised source and drain contacts are formed before the gate terminals. In this case, the required spacing between the raised source and drain contacts and the gate terminals is achieved through appropriate design or layout of the device or circuit.

[0128] The blocking spacers above the channel in the region between the source and drain regions and the outermost gate are removed using subsequent wet etching or isotropic dry etching. Figure 15c Preferably, this process does not remove all the isolators in the region between the individual gates, as this is advantageous for the devices of the present invention. Thus, the gate dielectric (1504) (gate oxide or dielectric) in the ungated region between the individual gates up to the channel interface is protected from etching damage, as Figure 15c shown, with some of the spacers (1509) (blocking mask) remaining.

[0129] Figure 15c is a cross-sectional view showing selectively forming raised semiconductor material on opposite sides of the outermost gate structure, whereby the raised source and drain regions (1507) do not make direct contact with the gate terminals or their adjacent dielectric spacers (1506) after removing the additional spacers. In this embodiment, this is accomplished by an isotropic etching process that removes the gate dielectric (1504) from the channel portion between the raised source-drain region (1507) and the spacers (1506) of the outermost gate terminal. At the same time, the gate dielectric (1504) between the two individual gate terminals is protected by the remaining dielectric spacers (1509).

[0130] In a subsequent step, a self-aligned metal-semiconductor alloy is performed. Figure 15d。The entire structure is subjected to the deposition of a metal layer (1511). The deposition can be conformal or directional. Typically, a PVD process such as sputtering or evaporation is used. CVD or ALD processing can also be used, especially in cases where a higher conformality rate is required. If the channel material is silicon, the material used is preferably a metal that forms a silicide, such as Ni, Co, and Ti. If the channel is germanium, materials that form an alloy with germanium, such as Ni, Mn, and Cu, can be used. If the channel is GaAs, materials that form an alloy with GaAs, such as Cr, Ni, Co, or a mixture of these materials, can be used. In all of the described embodiments, additional elements such as Pt or Al can be added to the alloy to alter the structural stability or electrical properties of the metal-semiconductor alloy.

[0131] Figure 15d is a cross-sectional view depicting the deposition of a metal layer (1511) over the entire structure including raised source and drain regions and gate terminals, thereby achieving direct contact of the metal layer (1511) (metal) to the channel region (1501) in the region between each external gate structure (1505) and the raised source and drain regions (1507), but no metal-semiconductor contact is formed in the semiconductor channel region beneath the protective remnants of the spacers (1509) between the gate structures (1505).

[0132] In one or more subsequent annealing steps, a metal-semiconductor alloy (1523) is formed, achieving a metal-semiconductor direct contact (1524). More importantly, the alloy is directly formed within the channel region between all raised source or drain regions and the gate spacers of their respective outermost gates. The formation of the metal alloy is characterized by a lateral diffusion component with respect to the channel direction. Self-limiting formation can be employed to set the interface between the semiconductor and the alloy at the desired location, typically beneath the gate. Self-limiting can be achieved through a limited metal source or a low-temperature budget annealing. After this process, the excess metal is removed by selective etching, thereby eliminating short circuits between the source, drain, and multiple independent gate terminals.

[0133] Figure 15e is a cross-sectional view depicting the final semiconductor device structure contemplated by the present invention. The metal-semiconductor alloy (1523) is directly formed near the two outer gate terminals of the semiconductor channel region (1501) and on top (1508) of the adjacent raised source and drain regions (1507), but not between the two adjacent gate terminals due to the spacers (1509) (dielectric protection layer) between the gate structures (1505). With this structure, the exact location of the metal-semiconductor alloy beneath the gate terminals can be adjusted and variations reduced. In this embodiment, a metal-semiconductor alloy (1510) is also formed on top of the gate structures (1505) (gate metal stack) to ensure electrical connection to other circuits.

[0134] According to the present invention, the metal-semiconductor contact of the reconfigurable field effect transistor is implemented as a source or drain contact of the Schottky barrier type position under the appropriate gate at the channel end Figure 15e ). For such a device, the annealing step of forming the metal-to-semiconductor is controlled, for example, by time or by the available materials, so that the contact of the Schottky barrier type is located under the appropriate gate terminal adjacent to the raised source or drain contact.

[0135] In another embodiment, the metal-semiconductor contact of the junctionless field effect transistor is implemented as its own source or drain contact at the channel end and is not located under the appropriate gate. For such devices, the annealing step of forming the metal-semiconductor contact is controlled, for example, by time or by the available materials, so that the contact of the Schottky barrier type is located between the raised source or drain contact and the appropriate gate terminal adjacent to the raised source or drain contact, for example, under the space between the raised source or drain contact and the gate terminal.

[0136] Simultaneously with the formation of the metal-semiconductor contact, upper alloy formation or the entire raised source-drain contact can be carried out. In one embodiment of the present invention, especially if the material of the gate structure (1505) (gate contact) is the same as the material selected for the raised source and drain regions (1507), and if the spacer (1509) (blocking mask) is completely removed above the gate contact material, then the upper or entire gate contact material forms a metal-semiconductor alloy (1510), for example, in the case of silicon, a silicide. In another embodiment, no alloy is formed on the top of the gate structure (1505) (gate contact material), especially if the gate structure (1505) (gate contact material) is still covered, for example, by the blocking mask material, or made of a material that does not form an alloy with the deposited metal layer (1511).

[0137] In the following steps, if the metal layer (1511) is only partially alloyed, the metal not used for alloying is removed by selective wet etching or dry etching so as not to remove the alloyed channel region, thereby still forming an electrical connection between the channel region (1501) and the top of the raised source and drain regions (1508). In another embodiment, the remaining metal layer can be removed by wet or dry etching to electrically isolate the raised source, drain or gate terminals. As long as there is no electrical connection between the source contact, the drain contact and the gate terminal, the residue of the metal film will remain.

[0138] In another embodiment, more specifically, especially in the process Figures 15a to 15eThe illustrated invention of the present disclosure describes device requirements for unequal numbers of gate terminals, using a semiconductor on an insulator substrate, and isolating the body of the semiconductor body (1503) (semiconductor substrate) from the unstructured semiconductor channel region (1501) by means of a dielectric layer (1502) (buried oxide). In this simple embodiment, a single straight sub-channel is patterned into the channel region ( Figure 15a ). In the case where a Schottky barrier device is to be formed, the channel region can be undoped silicon, or in the case of a junctionless device, the channel region can be doped silicon. Doping can be achieved, for example, with boron, arsenic, or phosphorus, and the doping concentration depends on the requirements of the device that the present invention is to implement.

[0139] An anisotropic etching process (such as reactive ion etching) can be used to structure the lithographically defined channel region. Subsequently, an atomic layer deposition process using a gate dielectric (1504) (a high-k dielectric material) (such as HfO2) is used to form a uniform conformal gate dielectric. Prior to this step, a SiO2 interface can be formed between the dielectric and the silicon channel, for example, by rapid thermal annealing, to obtain a defect-free channel surface. Three separate top gate structures (1505) (gate contacts) are patterned by a gate-first self-aligned double patterning process, in which the lateral features of the metal liner are transferred to the gate structures (1505) (gate contacts) by anisotropic etching. Etch stop on the high-k material can be achieved by a sacrificial nitride liner covering the entire high-k material. Gate spacers (1506) are formed by isotropic silicon nitride deposition followed by an anisotropic etching process. Subsequently, a self-aligned SiO2 blocking spacer (1509) is deposited, covering all the gates and the regions between the individual gates ( Figure 15b ). The gate dielectric material not covered by the blocking spacer is removed by wet or dry etching as previously described, and raised source and drain regions (1507) (source and drain contacts) are epitaxially grown from the opened channel surface. Preferably, the blocking spacer is used in such a way that the raised source and drain contacts are locally separated from the gate spacers of the outermost gate ( Figure 15c ).

[0140] Subsequently, isotropic wet etching is used to remove the blocking isolator above the channel in the region between the source and drain regions and the outermost gate. Thus, the spacers (1509) between the gate structures (1505) (individual gates) are not completely etched away, thereby protecting the high-k to channel interface in the ungated regions between the individual gates. As previously Figure 15d and Figure 15e for further processing.

[0141] In another specific example of the invention, the semiconductor channel is made of silicon on an insulator substrate, having a 6 nm channel region (1501) (highly doped silicon) on top of a 20 nm dielectric layer (1502) (buried silicon dioxide) on top of the semiconductor body (1503) (bulk silicon substrate). Figure 15a )。After the cleaning step, a 1 nm SiO2 interface is grown and a 4 nm HfO2 and 1 nm silicon nitride liner are deposited, which together serve as the gate dielectric (1504) (gate oxide or dielectric layer). A 20 nm wide TiN and polysilicon gate structure (1505) (gate contact) is patterned by reactive ion etching, with a 20 nm spacing between each gate contact, followed by self-aligned formation of a 5 nm thick silicon nitride dielectric spacer (1506). A SiO2 blocking spacer (1509) is used to fill the space between two separate gates, protecting the ungated regions from etching as well as contact filling and silicidation. Figure 15b )。

[0142] At the outermost gate, the SiO2 blocking spacer (1509) will be 10 nm wide on the Si3N4 dielectric spacer (1506) (gate spacer). After removing the HfO2 and SiO2 dielectrics from the channel portion over the source and drain regions by reactive ion etching, a 25 nm thick raised source and drain region (1507) is epitaxially grown. Figure 15b )。In this way, the epitaxially grown source and drain regions are locally separated from the gate isolators of the outermost gate. Subsequently, the SiO2 blocking spacer (1509) is removed by isotropic wet etching in such a way that it does not cover the ungated channel region between the raised epitaxial region and the outermost gate, while still protecting the ungated channels between each gate. Figure 15c )。Further processing is as previously described in Figure 15d and Figure 15e .

[0143] In another specific embodiment of the invention, after the metal alloy is formed, the conductive material and the gate dielectric material of all gate structures are removed. After removing the conductive material and the gate dielectric material, a new dielectric material and a new conductive material are deposited and structured by methods known in the art to form gate contacts using improved materials as before.

[0144] Figure 16 depicts Figure 15eAnother embodiment of the structure shown, in which the semiconductor device consists exactly of two gates, where the two gates are the outer gates mentioned. Source and drain contacts (1624) between the channel (1601) and the metal-semiconductor alloy (1623) are formed near the two outer gate terminals. The alloy is also formed on the raised source and drain contacts (1608), but not between the two adjacent gate terminals due to the dielectric protection layer between the gates (1609). In this embodiment, a raised source or drain region of the semiconductor device shares the adjacent source and drain contacts and its own MOSFET gate (1613) with an adjacent conventional MOSFET channel (1612). With this structure, it can be directly integrated into a standard CMOS circuit.

[0145] Figure 17 FIG. is a cross-sectional view showing another embodiment of the final semiconductor device structure contemplated by the present invention. Four separate gate contacts (1705) are used as the channel (1701) (semiconductor region) on a single straight sub-channel. A metal-semiconductor alloy (1723) is formed near the two outer gate terminals, but does not extend directly under the outer gate structure, and ohmic contacts (1724) are formed at the ends of the channel (1701). Using this one embodiment, a normally-on transistor with four independent gates is achieved. Obviously, the process description is not limited to the number of four gate terminals.

[0146] A metal-semiconductor alloy (1708) is also formed on top of the adjacent raised source and drain contacts (1707), but not between the spacers (1706) of the two adjacent gate terminals due to the dielectric protection layer between the gates (1709). Again, this structure can be used to adjust the exact position of the metal alloy-semiconductor contact (1724) and reduce variations. In this embodiment, a metal-semiconductor alloy (1710) is also formed on top of the gate contacts (1705) (gate metal stack).

[0147] The specific embodiments disclosed above are merely illustrative. The present invention can be modified and implemented in ways that are significantly different but equivalent to the present invention. For example, the above process steps can be performed in a different order.

Claims

1. An integrated circuit including a transistor, comprising: A semiconductor channel, comprising: Three or more sub-channels, each sub-channel having two ends; One or more nodes, each node being located at the ends of three or more sub-channels, and the ends of the three or more sub-channels being connected together to form an electrically continuous connection; and Channel ends, each of the channel ends being an end of a sub-channel separated from the node; Schottky contacts located at each channel end are separated from the nodes to form source or drain contacts; and Gate contacts provided at each Schottky contact to control the barrier conductivity of the corresponding Schottky contact.

2. The integrated circuit according to claim 1, including two or more nodes that electrically connect more than three channel portions.

3. The integrated circuit according to claim 1 or claim 2, including a gate contact provided to control the conductivity of one channel portion.

4. The integrated circuit according to claim 3, including two or more gate contacts positioned to control the conductivity of one channel portion.

5. The integrated circuit according to claim 3, including two or more gate contacts positioned to control the conductivity of the channel portion.

6. An integrated circuit including a transistor, the transistor comprising: A semiconductor channel, comprising: Three or more sub-channels, each sub-channel having two ends; One or more nodes, each node being located at the ends of three or more sub-channels, and the ends of the three or more sub-channels being connected together to form an electrically continuous connection; and Channel ends, each of the channel ends being an end of a sub-channel separated from the node; Ohmic contacts formed at each of the channel ends; A gate contact positioned to control the conductivity of one channel portion.

7. The integrated circuit according to claim 6, including two or more nodes that electrically connect more than three channel portions.

8. The integrated circuit according to claim 6 or 7, including two or more gate contacts positioned to control the conductivity of one channel portion.

9. The integrated circuit according to claim 6 or 7, including two or more gate contacts positioned to control the conductivity of the channel portion.

10. A semiconductor transistor, comprising: A semiconductor channel having channel ends; Isolation dielectric material located above the semiconductor channel; Multiple gates located above the isolation dielectric material above the semiconductor channel, the multiple gates including multiple outermost gates and at least one intermediate gate, each outermost gate being provided at a corresponding channel end, and each intermediate gate being provided between the outermost gates, and each gate being separated from each other by dielectric spacer material; Protruding semiconductor regions provided beside each outermost gate corresponding to the corresponding channel ends to form one of the drain contact and the source contact, wherein the region between two of the multiple gates does not include a protruding semiconductor region; A conductive material extends between each raised semiconductor region to a corresponding channel end to form a Schottky barrier contact under a corresponding outermost gate, such that only a single Schottky barrier contact is formed under each outermost gate; and each intermediate gate is surrounded by a dielectric to provide electrical isolation between two adjacent gates of the plurality of gates, such that the region between two adjacent gates of the plurality of gates does not include source and drain contacts.

11. The semiconductor transistor according to claim 10, wherein the conductive material is a metal semiconductor alloy.

12. An integrated circuit including a semiconductor transistor, comprising: A semiconductor channel, with an isolation dielectric material located above the semiconductor channel, Two or more gate contacts located above the isolation dielectric material; two adjacent gate contacts are electrically isolated from each other by a dielectric spacer material; Raised semiconductor regions arranged to be separated from the dielectric spacer material of the outermost gate contact; A conductive material adjacent to the raised semiconductor regions and extending to each channel end, the conductive material forming an ohmic contact.

13. The integrated circuit according to claim 12, wherein the conductive material is a metal semiconductor alloy.

14. A method of forming a semiconductor transistor structure, comprising: Disposing a transistor dielectric material on a semiconductor channel material; Forming a series of gate structures of conductive material surrounded by a dielectric spacer material on the transistor dielectric material; Depositing a masking material to mask the gate structures and a defined region beside the gate structures, and filling a spacer between two separate gate structures of the series of gate structures to protect the un-gated regions from etching; Removing the transistor dielectric material in the region beside the outermost gate structure not covered by the masking material; Forming raised regions by epitaxial growth on the semiconductor channel material beside the outermost gate structure from which the transistor dielectric material has been removed; Removing the masking material except for the portion between two separate gate structures of the series of gate structures; Depositing a conductive material layer over the transistor structure; And Forming a metal semiconductor alloy on the epitaxially grown raised regions on the semiconductor channel and on a portion of the semiconductor channel material through an annealing step.

15. The method according to claim 14, wherein the metal semiconductor alloy is formed from the channel material under the outermost gate terminal structure to form a Schottky contact.

16. The method according to claim 14, wherein the metal semiconductor alloy is formed from the channel material at the channel end of the outermost gate terminal structure to form an ohmic contact.

17. The method according to claim 14, further comprising retaining the masking material between some or all of the gate structures.

18. The method according to claim 14, wherein after the formation of the metal semiconductor alloy, the conductive material and the gate dielectric material of all the gate structures are removed; Then depositing a dielectric material and a conductive material.

Images