Semiconductor structure and method of fabricating the same

Abstract

Embodiments of the present disclosure relate to a semiconductor structure and a method of fabricating the same. A semiconductor structure can include a high voltage region, a first deep trench isolation structure electrically isolating the high voltage region from a plurality of low voltage regions of the semiconductor structure, and a second deep trench isolation structure electrically isolating the high voltage region from the plurality of low voltage regions of the semiconductor structure. The first deep trench isolation structure can include a plurality of dielectric sidewall spacers and a conductive fill material portion between the dielectric sidewall spacers. The second deep trench isolation structure can include only at least one dielectric material and can include a dielectric deep trench fill structure having a same material composition as the plurality of dielectric sidewall spacers and having a lateral thickness greater than a lateral thickness of the dielectric sidewall spacers and less than twice the lateral thickness of the dielectric sidewall spacers.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a semiconductor structure and a method of fabricating the same, and particularly, to a deep trench (or moat trench) isolation structure for a semiconductor structure and a method of forming the same. BACKGROUND

[0002] Bipolar / CMOS / DMOS (BCD) devices include a bipolar region that performs analog functions, a complementary metal oxide semiconductor (CMOS) region that performs digital functions, and a double diffused metal oxide semiconductor (DMOS) region that includes power and high voltage elements that provide power. BCD devices are used in communication applications (e.g., in smartphones and tablets) and in automotive applications, such as for mirror positioning, seat adjustment, etc. By integrating three different types of components on a single die, BCD technology can reduce the number of components in the bill of material (BoM). The reduction of chip components in the BoM further reduces the area on the board, thus reducing the cost. However, integrating different types of components that operate at different voltages can present challenges in electrical isolation. SUMMARY

[0003] Embodiments of the present disclosure provide a semiconductor structure including at least one first semiconductor device, at least one second semiconductor device, a first deep trench isolation structure, and a second deep trench isolation structure. The at least one first semiconductor device is located on a first semiconductor substrate material portion, the first semiconductor substrate material portion being located in a high voltage region. The at least one second semiconductor device is located on a second semiconductor substrate material portion, the second semiconductor substrate material portion being located outside of the high voltage region. The first deep trench isolation structure electrically isolates the first semiconductor substrate material portion from the second semiconductor substrate material portion. The second deep trench isolation structure electrically isolates the first semiconductor substrate material portion from the second semiconductor substrate material portion and laterally surrounds the first semiconductor substrate material portion and is laterally surrounded by the first deep trench isolation structure.

[0004] Embodiments of the present disclosure provide a semiconductor structure including at least one first semiconductor device, at least one second semiconductor device, and a set of at least two nested deep trench isolation structures. The at least one first semiconductor device is located on a first semiconductor substrate material portion, which is located in a high voltage region. The at least one second semiconductor device is located on a second semiconductor substrate material portion, which is located in a low voltage region. The set of at least two nested deep trench isolation structures laterally surrounds the high voltage region and electrically isolates the high voltage region from the low voltage region. Among them, a first deep trench isolation structure in the at least two nested deep trench isolation structures is filled with at least one dielectric material, and a second deep trench isolation structure in the at least two nested deep trench isolation structures includes an inner dielectric sidewall spacer, an outer dielectric sidewall spacer, and a conductive deep trench fill material portion located between the inner dielectric sidewall spacer and the outer dielectric sidewall spacer.

[0005] Embodiments of the present disclosure provide a method of fabricating a semiconductor structure, including: forming a patterned etch mask layer over a semiconductor device layer of a substrate; forming at least two deep trenches in the semiconductor device layer by transferring a pattern in the patterned etch mask layer into the semiconductor device layer using an anisotropic etching process, wherein the at least two deep trenches surround a first semiconductor substrate material portion of the semiconductor device layer and are laterally surrounded by a second semiconductor substrate material portion of the semiconductor device layer; forming a plurality of insulating sidewall spacers on a plurality of sidewalls of a first deep trench and simultaneously filling a second deep trench with a material of the plurality of insulating sidewall spacers; and filling a remaining empty space in the first deep trench with a conductive deep trench fill material. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure, together with details of an exemplary method as to how it can be implemented, will be more clearly understood from the following detailed description, when read in conjunction with the accompanying drawings. It is noted that the various features are not necessarily drawn to scale. In fact, the dimensions can be arbitrarily increased or decreased for the clarity of discussion. Accordingly, the drawings merely represent exemplary aspects. It should be understood that each feature can also exhibit a different feature, and thus not all features are necessary for every aspect.

[0007] Figure 1A is a partial perspective top view of a first exemplary structure including a double deep trench isolation structure according to some embodiments. For brevity, details of the semiconductor structure and its dielectric material layers are not illustrated.

[0008] Figure 1B is a partial perspective top view of a first exemplary structure including a double deep trench isolation structure according to some embodiments. For brevity, details of the semiconductor structure and its dielectric material layers are not illustrated. Figure 1A is a vertical cross-sectional view of the first exemplary structure of

[0009] Figure 2Ais a partial perspective top view of a second exemplary structure including a deep trench isolation structure according to some embodiments. For brevity, details of the semiconductor structure and its dielectric material layers are not illustrated.

[0010] Figure 2B is a vertical cross-sectional view of the second exemplary structure of Figure 2A

[0011] Figure 3 is a plan view of a semiconductor structure including a deep trench isolation structure according to some embodiments.

[0012] Figure 4 is a schematic diagram of the semiconductor structure of Figure 3

[0013] Figure 5 is a flowchart of a method of fabricating a deep trench isolation structure according to some embodiments.

[0014] Figures 6A to 6H is an explanatory schematic diagram of a method of fabricating a deep trench isolation structure according to some embodiments.

[0015] [Explanation of symbols]

[0016] 10: first exemplary semiconductor structure

[0017] 15: second exemplary semiconductor structure

[0018] 100: processing substrate

[0019] 102: buried insulator layer

[0020] 104A: semiconductor substrate material portion / first semiconductor substrate material portion

[0021] 104B: semiconductor substrate material portion / second semiconductor substrate material portion

[0022] 104C: semiconductor substrate material portion / third semiconductor substrate material portion

[0023] 104L: semiconductor device layer

[0024] 106: first deep trench isolation structure / deep trench isolation structure

[0025] 108: second deep trench isolation structure / deep trench isolation structure

[0026] 110: dielectric sidewall spacer

[0027] 110a: inner dielectric sidewall spacer / inner (insulating) dielectric sidewall spacer

[0028] ​​110b: outer dielectric sidewall spacer / outer (insulating) dielectric sidewall spacer

[0029] 110L: continuous insulating material layer

[0030] 111: dielectric deep trench fill structure

[0031] 112A: first diffusion barrier layer / diffusion barrier layer / first (conformal) diffusion barrier layer

[0032] 112B: second diffusion barrier layer / diffusion barrier layer / second (conformal) diffusion barrier layer

[0033] 112L: continuous diffusion barrier layer

[0034] 113: conductive deep trench fill material portion

[0035] 114: high voltage region

[0036] 115: contact via structure

[0037] 118: third deep trench isolation structure

[0038] 300: semiconductor structure

[0039] 302: lower voltage region / low voltage analog region

[0040] 304: lower voltage region / low voltage digital region

[0041] 402: bipolar analog device

[0042] 404: digital complementary metal oxide semiconductor device

[0043] 406: high voltage double diffused metal oxide semiconductor device

[0044] 500: method

[0045] 502, 504, 506, 507, 508, 510, 512, 514: steps

[0046] 610: silicon oxide interface layer

[0047] 611: etch mask layer

[0048] 612: silicon nitride hard mask layer

[0049] 710: first semiconductor device

[0050] 720: second semiconductor device

[0051] 760: contact level dielectric layer

[0052] w1: first width

[0053] w2: second width

[0054] w3: third width DETAILED DESCRIPTION

[0055] The following disclosure provides different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are set forth in order to provide a thorough understanding of the present disclosure. These are examples of only some embodiments and are not intended to be limiting. For example, in the following description, the formation of a first feature on top of or on a second feature can include embodiments where the first feature is formed directly on the second feature, and can also include embodiments where additional features can be formed between the first and second features such that the first and second features are not directly in contact. Additionally, the present disclosure can refer to reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity and is not intended to dictate a relationship of different described embodiments and / or configurations to each other.

[0056] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the structure in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0057] The structures and methods of the present disclosure can be used to provide electrical isolation between regions in a semiconductor chip that operate at different voltages. The development of 10 nanometer (nm) transistors has led to the breaking of Moore's Law. In response, semiconductor chip designers are focusing their efforts on integrating multiple semiconductor devices of different types on a single chip. For example, a single semiconductor chip (e.g., a BCD chip) can have an analog region including bipolar junction transistors, a digital logic region including complementary metal-oxide-semiconductor (CMOS) transistors, and a power region including double-diffused metal-oxide-semiconductor (DMOS) transistors. By combining functionality previously on separate chips into a single integrated chip, the number of chips can be reduced. As a result, substrate real estate on a circuit board can be freed up as fewer chips can be needed. As a result, assembly costs can also be reduced.

[0058] However, various semiconductor devices placed in close proximity to one another can utilize different voltages in operation. For example, in some embodiments, DMOS transistors can have an operating voltage in the range of 50 volts (V) to 1,000 V. In contrast, bipolar transistor devices or CMOS transistor devices can have an operating voltage of less than 50 V, and / or less than 24 V, and / or less than 12 V, and / or less than 6 V. As a high voltage device is placed in close proximity to a low voltage device, the low voltage device can experience severe damage. Accordingly, structures that isolate high voltage devices from low voltage devices can be employed to protect the low voltage devices.

[0059] Reference is made to Figure 1A and Figure 1B disclose a first exemplary semiconductor structure 10 including a double deep trench isolation structure in accordance with some embodiments. In one embodiment, the first exemplary structure 10 includes a handle substrate 100, a buried insulator layer 102, and a semiconductor device layer including various semiconductor substrate material portions (104A, 104B, 104C). At least two nested deep trenches can be formed to laterally (horizontally) divide the various semiconductor substrate material portions (104A, 104B, 104C). The at least two nested deep trenches include a first deep trench located on an outer side and a second deep trench located on an inner side. In one embodiment, the first deep trench can have a first width wl, and the second deep trench can have a second width w2. The first width wl can be greater than the second width w2. In one embodiment, the first width wl can be greater than twice the second width w2.

[0060] The various semiconductor substrate material portions (104A, 104B, 104C) can include a first semiconductor substrate material portion 104A laterally surrounded by the second deep trench, a second semiconductor substrate material portion 104B located outside the first deep trench, and a third semiconductor substrate material portion 104C located between the first deep trench and the second deep trench. When viewed in plan, each of the first deep trench and the second deep trench can have any annular shape, such as a rectangular annular shape, a rounded rectangular annular shape, a circular annular shape, an elliptical annular shape, or any two-dimensional annular shape. The buried insulator layer 102 can include an insulator material, such as silicon oxide, silicon nitride, or aluminum oxide. Other suitable materials within the contemplation of the present disclosure can also be used. The stack of the handle substrate 100, the buried insulator layer 102, and the semiconductor substrate material portions (104A, 104B, 104C) can be provided as a silicon-on-insulator substrate. The buried insulator layer 102 can have a thickness in the range of 50 nm to 500 nm, although greater and lesser thicknesses can also be used.

[0061] The region including the first semiconductor substrate material portion 104A can serve as a high voltage region of the semiconductor chip (i.e., the first exemplary semiconductor structure 10). The first semiconductor substrate material portion 104A can be laterally surrounded by the first deep trench isolation structure 106 filling the first deep trench and the second deep trench isolation structure 108 filling the second deep trench. In one embodiment, the second deep trench isolation structure 108 can have a second width w2 that is less than half of a first width wl of the first deep trench isolation structure 106.

[0062] In one embodiment, the first deep trench isolation structure 106 can include a plurality of dielectric sidewall spacers 110 having insulating material. The dielectric sidewall spacers 110 can include inner dielectric sidewall spacers 110a laterally surrounded by electrically conductive deep trench fill material portions 113 and outer dielectric sidewall spacers 110b laterally surrounding the electrically conductive deep trench fill material portions 113. Suitable insulating materials include, but are not limited to, silicon oxide. Other suitable materials within the scope of the present disclosure can also be used. The outer dielectric sidewall spacers 110b and the inner dielectric sidewall spacers 110a can have the same lateral width. The electrically conductive deep trench fill material portions 113 are located between the dielectric sidewall spacers 110 having insulating material in the first deep trench isolation structure 106. Each of the outer dielectric sidewall spacers 110b, the inner dielectric sidewall spacers 110a, and the electrically conductive deep trench fill material portions 113 can be topologically isomorphic to a torus, i.e., have a respective shape that can be deformed into a torus without forming a hole in any of its surfaces or without destroying a hole in any of its surfaces.

[0063] In one embodiment, the second deep trench isolation structure 108 includes a dielectric deep trench fill structure 111. The dielectric deep trench fill structure 111 can comprise the same material as the outer dielectric sidewall spacers 110b and the inner dielectric sidewall spacers 110a. According to embodiments of the present disclosure, the second deep trench isolation structure 108 can have a lateral width that is greater than the lateral width of each of the outer dielectric sidewall spacers 110b and the inner dielectric sidewall spacers 110a, and can be less than twice the lateral width of each of the outer dielectric sidewall spacers 110b and the inner dielectric sidewall spacers 110a. In one embodiment, the dielectric deep trench fill structure 111, the outer dielectric sidewall spacers 110b, and the inner dielectric sidewall spacers 110a can consist essentially of silicon oxide. The lateral thickness of the outer dielectric sidewall spacers 110b and the lateral thickness of the inner dielectric sidewall spacers 110a can be in the range of 50 nm to 300 nm, although smaller and larger thicknesses can also be used.

[0064] In one embodiment, a first diffusion barrier layer 112A can optionally be disposed between each of the inner and outer dielectric sidewall spacers 110a, 110b and the sidewalls of the second semiconductor substrate material portion 104B and the sidewalls of the third semiconductor substrate material portion 104C. The optional first diffusion barrier layer 112A can be formed by conformally depositing a dielectric diffusion-blocking material (e.g., silicon nitride) in the first deep trench and the second deep trench prior to depositing the insulating material of the inner and outer dielectric sidewall spacers 110a, 110b.

[0065] If the first diffusion barrier layer 112A is disposed in the first deep trench isolation structure 106, a second diffusion barrier layer 112B can be disposed in the second deep trench as a component of the second deep trench isolation structure 108. The second diffusion barrier layer 112B can be a continuous layer of material having the same material composition and the same thickness as the first diffusion barrier layer 112A. The first diffusion barrier layer 112A and the second diffusion barrier layer 112B comprise a diffusion-blocking dielectric material (e.g., silicon nitride) and can have a thickness in a range of 4 nm to 30 nm, although lesser and greater thicknesses can also be employed.

[0066] A plurality of first semiconductor devices 710 can be formed on and / or within portions of the first semiconductor substrate material portion 104A. A plurality of second semiconductor devices 720 can be formed on and / or within portions of the second semiconductor substrate material portion 104B. In one embodiment, the first semiconductor devices 710 comprise at least one bipolar / complementary metal-oxide semiconductor / bi- diffused metal-oxide semiconductor (BCD) device. In one embodiment, at least one of the first semiconductor devices 710 can have an operating voltage in a range of 50 volts to 1,000 volts. The area of the first semiconductor devices 710 can be a high voltage region, which can include a power region containing power semiconductor devices. The area of the second semiconductor devices 720 can be a low voltage region including a digital region and an analog region. In one embodiment, all of the second semiconductor devices 720 can have an operating voltage less than 50V, and / or less than 24V, and / or less than 12V, and / or less than 6V.

[0067] A contact-level dielectric layer 760 can be formed over the first semiconductor device 710 and the second semiconductor device 720. A plurality of contact via structures 115 can be formed through the contact-level dielectric layer 760 to contact top surfaces of the conductive deep trench fill material portions 113 in the first deep trench isolation structures 106.

[0068] Referring to Figure 2A and Figure 2B , a second exemplary semiconductor structure 15 is disclosed that includes a three deep trench isolation structure according to some embodiments. While the second exemplary structure illustrates embodiments that do not use a diffusion barrier layer (112A, 112B), embodiments that use a diffusion barrier layer (112A, 112B) in conjunction with the changes to the second exemplary structure relative to the first exemplary structure are expressly contemplated herein.

[0069] As in the first exemplary semiconductor structure 10, the second exemplary semiconductor structure 15 includes a first deep trench isolation structure 106 and a second deep trench isolation structure 108 that electrically isolate a high voltage region of the semiconductor chip from a lower voltage region. However, in this embodiment, a third deep trench isolation structure 118 is additionally provided within the second deep trench isolation structure 108. Like the second deep trench isolation structure 108, the third deep trench isolation structure 118 has a third width w3 that can be less than half of the first width wl of the first deep trench isolation structure 106. The third width w3 of the third deep trench isolation structure 118 can be the same as or can be different, i.e., larger or smaller, than the second width w2 of the second deep trench isolation structure 108. In other words, the width of the first deep trench isolation structure 106 can be at least twice the width of the second deep trench isolation structure 108 and / or the width of the third deep trench isolation structure 118. The addition of the third deep trench isolation structure 118 can provide additional electrical isolation relative to the embodiments illustrated in Figure 1A and Figure 1B The embodiments illustrated in and provide additional electrical isolation. In an aspect of this embodiment, additional additional deep trench isolation structures can be provided as needed.

[0070] Figure 3semiconductor structure 300 (e.g., a BCD device) including deep trench isolation structures according to some embodiments. The semiconductor structure 300 can have at least one high voltage region 114 and at least one lower voltage region 302, 304. The high voltage region 114 can contain devices that operate at voltages greater than 10V (e.g., greater than 50V, e.g., greater than 100V, e.g., greater than 200V). The lower voltage regions 302, 304 have devices that operate at voltages less than 10V. In one embodiment, the semiconductor structure 300 includes a lower voltage region (or low voltage analog region) 302, which typically includes bipolar junction transistors, and a lower voltage region (or low voltage digital region) 304, which includes CMOS field effect transistors. The high voltage region can include DMOS field effect transistors designed to distribute power to other regions of the semiconductor chip. Two deep trench isolation structures 106, 108 surround the high voltage region, which electrically isolates the low voltage analog region 302 and the low voltage digital region 304 from the high voltage region.

[0071] Figure 4 is a schematic illustration of a semiconductor structure 300 having more detail according to Figure 3 Figure 4 is a top portion of the schematic illustration of the semiconductor structure 300. Figure 4 is a bottom portion of the schematic illustration of the semiconductor structure 300.

[0072] Figure 5 is a flowchart of an embodiment method 500 of fabricating a deep trench isolation structure. Figures 6A to 6G illustrates sequential vertical cross-sectional views of an exemplary structure during an exemplary fabrication process using the embodiment method 500.

[0073] Figure 6A ​​At step 502 of the method described in FIG. 6, an etch mask layer 611 can be used to cover a substrate including the semiconductor device layer 104L. The substrate can include the handle substrate 100, the buried insulator layer 102, and the semiconductor device layer 104L. In one embodiment, the etch mask layer 611 can include a layer stack including, from bottom to top, a silicon oxide landing pad layer 610 and a silicon nitride hard mask layer 612. The silicon oxide landing pad layer 610 can have a thickness in a range from 5 nm to 50 nm, and the silicon nitride hard mask layer 612 can have a thickness in a range from 50 nm to 300 nm, although each of the silicon oxide landing pad layer 610 and the silicon nitride hard mask layer 612 can use lesser and greater thicknesses. As another option, the etch mask layer 611 can include a photoresist layer.

[0074] At step 504, the etch mask layer 611 can be patterned, as described in FIG. 6. Figure 6B If the etch mask layer 611 includes a stack of the silicon oxide landing pad layer 610 and the silicon nitride hard mask layer 612, a photoresist layer can be applied over the etch mask layer 611 and patterned in a photolithographic manner to form a pattern having a plurality of openings having a pattern that is the same as the pattern of the deep trench grooves described in FIGS. 5A-5C. Figure 1A Figure 1B Figure 2A and Figure 2B The unmasked portions of the silicon nitride hard mask layer 612 can be etched by an anisotropic etch process. The photoresist layer can then be removed, for example, by ashing. In embodiments where the etch mask layer 611 is a photoresist layer, the etch mask layer 611 can be patterned by photolithographic exposure and development.

[0075] At step 506, the patterned etch mask layer 611 can be used as an etch mask to etch the semiconductor device layer 104L and the buried insulator layer 102. Deep trench grooves including at least the first deep trench groove and the second deep trench groove can be formed through the semiconductor device layer 104L and the buried insulator layer 102. The semiconductor device layer 104L can be segmented into a plurality of semiconductor substrate material portions (104A, 104B, 104C) by an anisotropic etch process, for example, a reactive ion etch process.

[0076] At Figure 6D ​​In the optional step 507 described herein, an optional continuous diffusion barrier layer 112L may be deposited using a conformal deposition process. For example, the continuous diffusion barrier layer 112L may be deposited using a low-pressure chemical vapor deposition process. The continuous diffusion barrier layer 112L comprises a diffusion-blocking dielectric material (e.g., silicon nitride) and may have a thickness in the range of 4 nm to 40 nm, but smaller and larger thicknesses may also be used.

[0077] In step 508, a continuous insulating layer 110L can be deposited using a conformal deposition process. For example, the continuous insulating layer 110L can be deposited using a low-pressure chemical vapor deposition process. The continuous insulating layer 110L can fill the entire unfilled volume of the second deep trench and the entire unfilled volume of any additional deep trenches (if present), but not completely fill the first deep trench. The thickness of the continuous insulating layer 110L in the first deep trench can be in the range of 50 nm to 300 nm, but smaller and larger thicknesses can also be used. The continuous insulating layer 110L comprises an insulating material, such as silicon oxide. According to one aspect of this disclosure, since the second width w2 of the second deep trench and the width of any additional deep trenches are equal to or less than half the first width w1 of the first deep trench, the insulating material of the continuous insulating layer 110L can be used to fill the second deep trench and any additional deep trenches to form a dielectric deep trench filling structure (i.e., dielectric deep trench filling structure 111).

[0078] exist Figure 6E In step 510 described herein, an anisotropic etching process can be performed to remove the horizontal portion of the continuous insulating material layer 110L overlying the patterned etch mask layer 611 (in an embodiment where the patterned etch mask layer 611 includes a stack of silicon oxide pad layers 610 and silicon nitride hard mask layers 612). The annular horizontal portion of the continuous insulating material layer 110L located between the inner vertical extension portion and the outer vertical extension portion of the continuous insulating material layer 110L can be removed. Furthermore, the anisotropic etching process can remove the solid exposed portion of the continuous diffusion barrier layer 112L.

[0079] Each remaining portion of the continuous diffusion barrier layer 112L in the first deep trench groove constitutes a first (conformal) diffusion barrier layer 112A, and the remaining portions of the continuous diffusion barrier layer 112L in the second deep trench groove constitute a second (conformal) diffusion barrier layer 112B. The first (conformal) diffusion barrier layer 112A includes an inner conformal diffusion barrier layer contacting the sidewall of the third semiconductor substrate material portion 104C and the top surface of the process substrate 100, and an outer conformal diffusion barrier layer contacting the sidewall of the second semiconductor substrate material portion 104B and the top surface of the process substrate 100. The second (conformal) diffusion barrier layer 112B can be formed as a single continuous layer without any opening therethrough, and can contact the sidewall of the first semiconductor substrate material portion 104A, the sidewall of the third semiconductor substrate material portion 104C, and the top surface of the process substrate 100.

[0080] Each remaining portion of the continuous insulating material layer 110L in the first deep trench groove constitutes a dielectric sidewall spacer 110, and the remaining portions of the continuous insulating material layer 110L in the second deep trench groove constitute a dielectric deep trench fill structure 111. The dielectric sidewall spacer 110 includes an inner dielectric sidewall spacer 110a within the annular cavity in the first deep trench groove, and an outer dielectric sidewall spacer 110b outside the annular cavity in the first deep trench groove. The dielectric deep trench fill structure 111 can be formed as a continuous annular structure. The annular top surface of the process substrate 100 can be physically exposed at the bottom of the first deep trench groove between the inner dielectric sidewall spacer 110a and the outer dielectric sidewall spacer 110b.

[0081] In Figure 6FIn step 512, an electrically conductive deep trench fill material can be deposited in the annular cavity within the first deep trench groove directly on the physically exposed annular surface of the processing substrate 100. In one embodiment, the processing substrate 100 can include a semiconductor material, such as monocrystalline silicon. The electrically conductive deep trench fill material can include a doped semiconductor material (e.g., doped polysilicon), or can include at least one metallic material, such as a combination of an electrically conductive metal nitride (e.g., TiN, TaN, and / or WN) and an electrically conductive metal fill material (e.g., tungsten). Other suitable materials within the scope of the present disclosure can also be used. Excess portions of the electrically conductive deep trench fill material can be removed from above the top surface of the patterned etch mask layer 611. A recess etch can be used to vertically recess the electrically conductive deep trench fill material. An over-etch can be performed to vertically recess the remaining portion of the electrically conductive deep trench fill material within the first deep trench groove such that the remaining portion of the electrically conductive deep trench fill material in the first deep trench groove has an annular top surface that is below the topmost surface of the patterned etch mask layer 611 and at or above the level of the top surface of the first semiconductor substrate material portion 104A. Alternatively or additionally, a chemical mechanical planarization process can be used to recess the electrically conductive deep trench fill material. The remaining annular portion of the electrically conductive deep trench fill material in the first deep trench groove constitutes an electrically conductive deep trench fill material portion 113. The electrically conductive deep trench fill material portion 113 can be topologically homeomorphic to a torus. The set of all material portions in the first deep trench groove constitutes a first deep trench groove isolation structure 106, and the set of all material portions in the second deep trench groove constitutes a second deep trench groove isolation structure 108.

[0082] In a next step 514 and with reference to Figure 6G The patterned etch mask layer 611 can be selectively removed relative to the semiconductor substrate material portions (104A, 104B, 104C) and the deep trench groove isolation structures (106, 108). For example, the silicon nitride hard mask layer 612 can be removed by a wet etch process using hot phosphoric acid. The silicon oxide underlayer 610 can be removed by a wet etch process using hydrofluoric acid. A plurality of first semiconductor devices 710 can be formed over and / or in a portion of the first semiconductor substrate material portion 104A, and a plurality of second semiconductor devices 720 can be formed over and / or in a portion of the second semiconductor substrate material portion 104B.

[0083] With reference to Figure 6HA contact level dielectric layer 760 can be formed over the first semiconductor device 710 and the second semiconductor device 720. A plurality of contact via structures 115 can be formed through the contact level dielectric layer 760 directly on top surfaces of the electrically conductive deep trench fill material portions 113 in the first deep trench isolation structure 106. The contact via structures 115 can be used to electrically bias the electrically conductive deep trench fill material portions 113 and the handle substrate 100 to provide suitable electrical biasing and to electrically isolate the first semiconductor device 710.

[0084] Embodiments of the above structures and methods provide greater electrical isolation between high voltage and low voltage regions on the same chip. This allows different types of semiconductor devices to be integrated on the same chip. By combining functionality previously on separate chips into a single integrated chip, the number of chips for a given application can be reduced. Thus, substrate area on a circuit board can be freed up since fewer chips can be needed. Thus, assembly costs can also be reduced.

[0085] According to embodiments of the present disclosure, a semiconductor structure can be provided that includes at least one first semiconductor device 710 on a first semiconductor substrate material portion 104A, the first semiconductor substrate material portion 104A being in a high voltage region, at least one second semiconductor device 720 on a second semiconductor substrate material portion 104B, the second semiconductor substrate material portion 104B being outside of the high voltage region, a first deep trench isolation structure 106 electrically isolating the first semiconductor substrate material portion 104A from the second semiconductor substrate material portion 104B, and a second deep trench isolation structure 108 electrically isolating the first semiconductor substrate material portion 104A from the second semiconductor substrate material portion 104B and laterally surrounding the first semiconductor substrate material portion 104A and laterally surrounded by the first deep trench isolation structure 106.

[0086] According to another embodiment of the disclosure, a semiconductor structure can be provided, including: at least one first semiconductor device 710 on a first semiconductor substrate material portion 104A, the first semiconductor substrate material portion 104A being in a high voltage region; at least one second semiconductor device 720 on a second semiconductor substrate material portion 104B, the second semiconductor substrate material portion 104B being in a low voltage region; a set of at least two nested deep trench isolation structures (106, 108) laterally surrounding the high voltage region and electrically isolating the high voltage region from the low voltage region. One of the at least two deep trench isolation structures (106, 108) is filled with at least one dielectric material, and another of the at least two deep trench isolation structures (106, 108) includes an inner dielectric sidewall spacer 110a, an outer dielectric sidewall spacer 110b, and a conductive deep trench fill material portion 113 between the inner dielectric sidewall spacer 110a and the outer dielectric sidewall spacer 110b.

[0087] According to yet another embodiment of the disclosure, a method of fabricating a semiconductor structure is provided, including: forming a patterned etch mask layer 611 over a semiconductor device layer 104L of a substrate (100, 102, 104L); forming at least two deep trenches in the semiconductor device layer 104L by transferring a pattern in the patterned etch mask layer 611 into the semiconductor device layer 104L using an anisotropic etching process, wherein the at least two deep trenches surround a first semiconductor substrate material portion 104A of the semiconductor device layer (104A, 104B, 104C) and are laterally surrounded by a second semiconductor substrate material portion 104B of the semiconductor device layer (104A, 104B, 104C); forming insulating sidewall spacers 110a, 110b on sidewalls of the first deep trench while filling the second deep trench with an insulating sidewall spacer material; and filling a remaining empty space in the first deep trench with a conductive deep trench fill material portion 113.

[0088] According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes at least one first semiconductor device, at least one second semiconductor device, a first deep trench isolation structure, and a second deep trench isolation structure. The at least one first semiconductor device is located on a first semiconductor substrate material portion, the first semiconductor substrate material portion being located in a high voltage region. The at least one second semiconductor device is located on a second semiconductor substrate material portion, the second semiconductor substrate material portion being located outside of the high voltage region. The first deep trench isolation structure electrically isolates the first semiconductor substrate material portion from the second semiconductor substrate material portion. The second deep trench isolation structure electrically isolates the first semiconductor substrate material portion from the second semiconductor substrate material portion and laterally surrounds the first semiconductor substrate material portion and is laterally surrounded by the first deep trench isolation structure.

[0089] According to some embodiments, the semiconductor structure further includes a buried insulator layer in contact with a bottom surface of the first semiconductor substrate material portion, a bottom surface of the second semiconductor substrate material portion, a bottom surface of the first deep trench isolation structure, and a bottom surface of the second deep trench isolation structure. According to some embodiments, the semiconductor structure further includes a handle substrate located below the buried insulator layer, wherein the buried insulator layer comprises silicon oxide and has a thickness in a range from 50 nm to 500 nm. According to some embodiments, in the semiconductor structure, wherein the first deep trench isolation structure comprises a plurality of dielectric sidewall spacers and portions of conductive fill material located between the plurality of dielectric sidewall spacers. According to some embodiments, the semiconductor structure further includes a plurality of first conformal diffusion barriers located between a plurality of sidewalls of the first deep trench isolation structure and a respective one of the plurality of dielectric sidewall spacers. According to some embodiments, in the semiconductor structure, wherein the second deep trench isolation structure is filled with at least one dielectric material. According to some embodiments, in the semiconductor structure, wherein the second deep trench isolation structure comprises a dielectric deep trench fill structure having a same material composition as the plurality of dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the plurality of dielectric sidewall spacers and less than twice the lateral thickness of the plurality of dielectric sidewall spacers. According to some embodiments, in the semiconductor structure, wherein the at least one first semiconductor device comprises a bipolar-complementary metal-oxide-semiconductor-bi- diffused metal-oxide-semiconductor device and has an operating voltage in a range from 50 volts to 1,000 volts.

[0090] According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes at least one first semiconductor device, at least one second semiconductor device, and a set of at least two nested deep trench isolation structures. The at least one first semiconductor device is on a first semiconductor substrate material portion, which is in a high voltage region. The at least one second semiconductor device is on a second semiconductor substrate material portion, which is in a low voltage region. The set of at least two nested deep trench isolation structures laterally surrounds the high voltage region and electrically isolates the high voltage region from the low voltage region. Among the at least two nested deep trench isolation structures, a first deep trench isolation structure is filled with at least one dielectric material and a second deep trench isolation structure includes an inner dielectric sidewall spacer, an outer dielectric sidewall spacer, and a conductive deep trench fill material portion between the inner and outer dielectric sidewall spacers.

[0091] According to some embodiments, in the semiconductor structure, the conductive deep trench fill material portion includes polysilicon. According to some embodiments, in the semiconductor structure, a width of the second deep trench isolation structure among the at least two nested deep trench isolation structures is at least twice a width of the first deep trench isolation structure among the at least two nested deep trench isolation structures. According to some embodiments, in the semiconductor structure, the high voltage region includes a power supply region and the low voltage region includes a digital region and an analog region.

[0092] According to some embodiments, a method of fabricating a semiconductor structure is provided. The method includes forming a patterned etch mask layer over a semiconductor device layer of a substrate, forming at least two deep trench isolation structures in the semiconductor device layer by transferring a pattern in the patterned etch mask layer into the semiconductor device layer using an anisotropic etch process, wherein the at least two deep trench isolation structures surround a first semiconductor substrate material portion of the semiconductor device layer and are laterally surrounded by a second semiconductor substrate material portion of the semiconductor device layer, forming a plurality of insulating sidewall spacers on a plurality of sidewalls of a first deep trench isolation structure and simultaneously filling a second deep trench isolation structure with a material of the plurality of insulating sidewall spacers, and filling a remaining empty space in the first deep trench isolation structure with a conductive deep trench fill material.

[0093] According to some embodiments, in the method, wherein the substrate comprises a handle substrate, a buried insulator layer overlying the handle substrate, and the semiconductor device layer overlying the buried insulator layer; and the at least two deep trench grooves are formed to pass down through the semiconductor device layer and the buried insulator layer to a top surface of the handle substrate. According to some embodiments, the method further comprises removing portions of the electrically conductive deep trench fill material overlying a top surface of the semiconductor device layer, wherein remaining portions of the electrically conductive deep trench fill material constitute electrically conductive fill material portions in contact with the top surface of the handle substrate. According to some embodiments, the method further comprises forming a plurality of contact via structures on a top surface of the electrically conductive fill material portions. According to some embodiments, the method further comprises conformally depositing an insulating material in the first deep trench groove and the second deep trench groove, wherein the insulating material fills a cavity in the second deep trench groove, and after depositing the insulating material, there is a continuous cavity within the first deep trench groove laterally surrounding a plurality of inner sidewalls of the first deep trench groove. According to some embodiments, the method further comprises anisotropically etching the insulating material, wherein: portions of the insulating material in contact with the plurality of inner sidewalls of the first deep trench groove constitute inner dielectric sidewall spacers; and portions of the insulating material in contact with a plurality of outer sidewalls of the second deep trench groove constitute outer dielectric sidewall spacers. According to some embodiments, the method further comprises, prior to depositing the insulating material, depositing a conformal diffusion barrier layer; and after forming the inner dielectric sidewall spacers and the outer dielectric sidewall spacers, physically removing the top surface of the handle substrate. According to some embodiments, the method further comprises forming a plurality of first semiconductor devices on the first semiconductor substrate material portion; and forming a plurality of second semiconductor devices on the second semiconductor substrate material portion, wherein: the plurality of first semiconductor devices comprise bipolar-complementary metal-oxide-semiconductor-bi- diffused metal-oxide-semiconductor devices, and at least one of the plurality of first semiconductor devices has an operating voltage in a range of 50 volts to 1,000 volts.

[0094] The foregoing outlines features of a number of embodiments so that those skilled in the art can better understand the aspects of the disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that these and other equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, comprising: at least one first semiconductor device vertically on a first semiconductor substrate material portion, the first semiconductor substrate material portion in a high voltage region; at least one second semiconductor device vertically on a second semiconductor substrate material portion, the second semiconductor substrate material portion outside the high voltage region; a first deep trench isolation structure laterally surrounding the first semiconductor substrate material portion and electrically isolating the first semiconductor substrate material portion from the second semiconductor substrate material portion, wherein the first deep trench isolation structure has a first width, wherein the first deep trench isolation structure includes a plurality of dielectric sidewall spacers, a conductive fill material portion between the plurality of dielectric sidewall spacers, and a plurality of first conformal diffusion barriers between sidewalls of the first deep trench isolation structure and a respective one of the plurality of dielectric sidewall spacers, wherein the plurality of first conformal diffusion barriers extend to a bottom of a respective one of the plurality of dielectric sidewall spacers in contact with sidewalls of the conductive fill material portion; and a second deep trench isolation structure electrically isolating the first semiconductor substrate material portion from the second semiconductor substrate material portion and laterally surrounding the first semiconductor substrate material portion and laterally surrounded by the first deep trench isolation structure, wherein the second deep trench isolation structure has a second width and the first width is greater than the second width, wherein the second deep trench isolation structure includes a dielectric fill material portion and a second conformal diffusion barrier between sidewalls of the second deep trench isolation structure and the dielectric fill material portion, wherein the second conformal diffusion barrier extends continuously around sidewalls and a bottom of the dielectric fill material portion.

2. The semiconductor structure of claim 1, further comprising a buried insulator layer in contact with a bottom surface of the first semiconductor substrate material portion, a bottom surface of the second semiconductor substrate material portion, the first deep trench isolation structure, and the second deep trench isolation structure, wherein the first deep trench isolation structure and the second deep trench isolation structure vertically penetrate the buried insulator layer.

3. The semiconductor structure of claim 2, further comprising a handle substrate beneath the buried insulator layer, wherein the buried insulator layer comprises silicon oxide and has a thickness in a range from 50 nm to 500 nm.

4. The semiconductor structure of claim 1, wherein the first width is greater than twice the second width.

5. The semiconductor structure of claim 4, wherein a height of the plurality of first conformal diffusion barriers is greater than a height of the plurality of dielectric sidewall spacers, wherein a material of the plurality of first conformal diffusion barriers is different than a material of the plurality of dielectric sidewall spacers.

6. The semiconductor structure of claim 4, wherein a height of the second conformal diffusion barrier layer is greater than a height of the dielectric fill material portion. wherein a material of the second conformal diffusion barrier layer is different from a material of the dielectric fill material portion.

7. The semiconductor structure of claim 6, wherein the dielectric fill material portion comprises a dielectric deep trench fill structure having a same material composition as the plurality of dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the plurality of dielectric sidewall spacers and less than twice the lateral thickness of the plurality of dielectric sidewall spacers.

8. The semiconductor structure of claim 1, wherein: the at least one first semiconductor device comprises a bipolar-complementary metal-oxide-semiconductor-bi- diffused metal-oxide-semiconductor device and has an operating voltage in a range of 50 volts to 1,000 volts.

9. A semiconductor structure, comprising: at least one first semiconductor device vertically located on a first semiconductor substrate material portion, the first semiconductor substrate material portion located in a high voltage region; at least one second semiconductor device vertically located on a second semiconductor substrate material portion, the second semiconductor substrate material portion located in a low voltage region; and a set of at least two nested deep trench isolation structures laterally surrounding the first semiconductor substrate material portion and laterally surrounding the high voltage region and electrically isolating the high voltage region from the low voltage region, wherein a first deep trench isolation structure of the at least two nested deep trench isolation structures is filled with at least one dielectric material and a conformal diffusion barrier layer continuously extending on sidewalls and a bottom of the dielectric material and a second deep trench isolation structure of the at least two nested deep trench isolation structures comprises an inner dielectric sidewall spacer, an outer dielectric sidewall spacer, a conductive deep trench fill material portion located between the inner dielectric sidewall spacer and the outer dielectric sidewall spacer, an inner conformal diffusion barrier layer located between the inner dielectric sidewall spacer and sidewalls of the first deep trench isolation structure and extending to a bottom of the inner dielectric sidewall spacer in contact with sidewalls of the conductive deep trench fill material portion, and an outer conformal diffusion barrier layer located between the outer dielectric sidewall spacer and sidewalls of the first deep trench isolation structure and extending to a bottom of the outer dielectric sidewall spacer in contact with sidewalls of the conductive deep trench fill material portion, wherein the first deep trench isolation structure has a first width, the second deep trench isolation structure has a second width, and the first width is less than the second width, wherein the second deep trench isolation structure is laterally surrounded by the first deep trench isolation structure.

10. The semiconductor structure of claim 9, wherein the conductive deep trench fill material portion comprises polysilicon. ​ 11. The semiconductor structure of claim 9, wherein the second width of the second deep trench isolation structure of the at least two nested deep trench isolation structures is at least twice the first width of the first deep trench isolation structure of the at least two nested deep trench isolation structures.

12. The semiconductor structure of claim 9, wherein the high voltage region comprises a power region and the low voltage region comprises a digital region and an analog region.

13. A method of fabricating a semiconductor structure, comprising: forming a patterned etch mask layer over a semiconductor device layer of a substrate; forming at least two deep trenches in the semiconductor device layer by transferring a pattern in the patterned etch mask layer into the semiconductor device layer using an anisotropic etch process, wherein the at least two deep trenches encircle a first semiconductor substrate material portion of the semiconductor device layer and are laterally encircled by a second semiconductor substrate material portion of the semiconductor device layer, wherein the first semiconductor substrate material portion is in a high voltage region and the second semiconductor substrate material portion is in a low voltage region; depositing a first conformal diffusion barrier layer in a first deep trench of the at least two deep trenches and a second conformal diffusion barrier layer in a second deep trench of the at least two deep trenches; forming a plurality of insulative sidewall spacers on a plurality of sidewalls of the first deep trench of the at least two deep trenches and simultaneously filling the second deep trench of the at least two deep trenches with a material of the plurality of insulative sidewall spacers to form a dielectric deep trench fill material in the second deep trench; and filling a remaining empty space in the first deep trench with a conductive deep trench fill material, wherein the first deep trench has a first width, the second deep trench has a second width, and the first width is greater than the second width, wherein the first deep trench laterally encircles the first semiconductor substrate material portion and the second deep trench laterally encircles the first semiconductor substrate material portion and is laterally encircled by the first deep trench, wherein the first deep trench is filled with the plurality of insulative sidewall spacers, the conductive deep trench fill material between the plurality of insulative sidewall spacers, and the first conformal diffusion barrier layer between the plurality of insulative sidewall spacers and the plurality of sidewalls of the first deep trench and extending to a bottom of the plurality of insulative sidewall spacers in contact with sidewalls of the conductive deep trench fill material, wherein the second deep trench is filled with the dielectric deep trench fill material and the second conformal diffusion barrier layer continuously extending on sidewalls and a bottom of the dielectric deep trench fill material.

14. The method of claim 13, wherein: the substrate comprises a handle substrate, a buried insulator layer overlying the handle substrate, and the semiconductor device layer overlying the buried insulator layer; and The at least two deep trench grooves are formed to pass down through the semiconductor device layer and the buried insulator layer to a top surface of the handle substrate.

15. The method of claim 14, further comprising removing portions of the electrically conductive deep trench fill material overlying a top surface of the semiconductor device layer, wherein a remaining portion of the electrically conductive deep trench fill material includes an electrically conductive fill material portion in contact with the top surface of the handle substrate.

16. The method of claim 15, further comprising forming a plurality of contact via structures on a top surface of the electrically conductive fill material portion.

17. The method of claim 14, wherein forming the plurality of insulative sidewall spacers and forming the dielectric deep trench fill material includes conformally depositing an insulative material in the first deep trench groove and the second deep trench groove, wherein the insulative material fills a cavity in the second deep trench groove, and after depositing the insulative material, there is a continuous cavity within the first deep trench groove that laterally surrounds a plurality of inner sidewalls of the first deep trench groove.

18. The method of claim 17, further comprising anisotropically etching the insulative material, wherein: portions of the insulative material in contact with the plurality of inner sidewalls of the first deep trench groove comprise inner dielectric sidewall spacers; and portions of the insulative material in contact with a plurality of outer sidewalls of the first deep trench groove comprise outer dielectric sidewall spacers.

19. The method of claim 18, further comprising: after forming the inner dielectric sidewall spacers and the outer dielectric sidewall spacers, physically removing the top surface of the handle substrate.

20. The method of claim 13, further comprising: forming a plurality of first semiconductor devices on the first semiconductor substrate material portion; and forming a plurality of second semiconductor devices on the second semiconductor substrate material portion, wherein: the plurality of first semiconductor devices comprise bipolar-complementary metal-oxide-semiconductor-bi-diffused metal-oxide-semiconductor devices, and at least one of the plurality of first semiconductor devices has an operating voltage in a range of 50 volts to 1,000 volts.

21. A method of fabricating a semiconductor structure, comprising: covering a substrate with an etch mask layer, wherein the substrate comprises a handle substrate, a buried insulator layer, and a semiconductor layer; patterning the etch mask layer; etching the semiconductor layer and the buried insulator layer using the patterned etch mask layer to form a first deep trench groove and a second deep trench groove; conformally depositing a first diffusion barrier layer and a second diffusion barrier layer in the first deep trench groove and the second deep trench groove, respectively; conformally depositing an insulative material layer on the first diffusion barrier layer in the first deep trench groove to partially fill the first deep trench groove; ​ depositing the layer of insulating material conformally on the second diffusion barrier in the second deep trench, such that the second deep trench is completely filled with the layer of insulating material, forming a second deep trench isolation structure, wherein the second deep trench isolation structure includes a dielectric fill material portion and the second diffusion barrier between sidewalls of the second deep trench and the dielectric fill material portion, wherein the second diffusion barrier continuously extends from sidewalls to a bottom of the dielectric fill material portion, wherein the second deep trench isolation structure has a second width; forming a plurality of dielectric sidewall spacers in the first deep trench, and exposing a ring-shaped top surface of the process substrate at a bottom of the first deep trench; depositing a conductive material in the first deep trench to form a first deep trench isolation structure, wherein the first deep trench isolation structure includes the plurality of dielectric sidewall spacers, a conductive fill material portion between the plurality of dielectric sidewall spacers, and a first diffusion barrier between sidewalls of the first deep trench and the conductive fill material portion, wherein the first diffusion barrier extends to a bottom of the plurality of dielectric sidewall spacers in contact with sidewalls of the conductive fill material portion, wherein the first deep trench isolation structure has a first width, and the first width is greater than the second width; forming a plurality of first semiconductor devices vertically on the first semiconductor substrate material portion of the semiconductor layer, wherein the first semiconductor substrate material portion is in a high voltage region, the first deep trench laterally surrounds the first semiconductor substrate material portion, and the second deep trench laterally surrounds the first semiconductor substrate material portion and is laterally surrounded by the first deep trench; and forming a plurality of second semiconductor devices vertically on the second semiconductor substrate material portion of the semiconductor layer, wherein the second semiconductor substrate material portion is in a low voltage region.

22. The method of claim 21, wherein: etching the semiconductor layer and the buried insulator layer to form the first deep trench and the second deep trench includes performing a reactive ion etch process.

23. The method of claim 21, wherein: the first diffusion barrier deposited in the first deep trench contacts sidewalls of the second semiconductor substrate material portion and sidewalls of a third semiconductor substrate material portion; and the second diffusion barrier deposited in the second deep trench contacts sidewalls of the first semiconductor substrate material portion and sidewalls of the third semiconductor substrate material portion.

24. The method of claim 23, wherein the first diffusion barrier in the first deep trench and the second diffusion barrier in the second deep trench include silicon nitride and are conformally deposited using a low pressure chemical vapor deposition process.

25. The method of claim 23, further comprising: ​ ​ vertically recessing the conductive material in the first deep trench to have a ring-shaped top surface below a top surface of the patterned etch mask layer.

26. The method of claim 25, further comprising: removing the patterned etch mask layer selective to the substrate prior to forming the plurality of first semiconductor devices and forming the plurality of second semiconductor devices.

27. The method of claim 25, further comprising: depositing a contact level dielectric layer on the plurality of first semiconductor devices and the plurality of second semiconductor devices; and forming a plurality of contact via structures through the contact level dielectric layer on a top surface of the conductive material in the first deep trench.

28. A method of fabricating a semiconductor structure, comprising: covering a substrate with an etch mask layer, wherein the substrate comprises a handle substrate, a buried insulator layer, and a semiconductor layer; patterning the etch mask layer; etching the semiconductor layer and the buried insulator layer using the patterned etch mask layer to form a first deep trench, a second deep trench, and a third deep trench; conformally depositing a first diffusion barrier layer, a second diffusion barrier layer, and a third diffusion barrier layer in the first deep trench, the second deep trench, and the third deep trench, respectively; conformally depositing an insulating material layer on the first diffusion barrier layer in the first deep trench to partially fill the first deep trench; conformally depositing the insulating material layer on the second diffusion barrier layer in the second deep trench and on the third diffusion barrier layer in the third deep trench to completely fill the second deep trench and the third deep trench with the insulating material layer to form a second deep trench isolation structure and a third deep trench isolation structure, wherein the second deep trench isolation structure comprises a dielectric fill material portion and the second diffusion barrier layer between sidewalls of the second deep trench and the dielectric fill material portion, wherein the second diffusion barrier layer continuously extends sidewalls and a bottom of the dielectric fill material portion, wherein the second deep trench isolation structure has a second width; forming a plurality of dielectric sidewall spacers in the first deep trench and exposing a ring-shaped top surface of the handle substrate at a bottom of the first deep trench; depositing a conductive material in the first deep trench to form a first deep trench isolation structure, wherein the first deep trench isolation structure comprises the plurality of dielectric sidewall spacers, a conductive fill material portion between the plurality of dielectric sidewall spacers, and a first diffusion barrier layer between sidewalls of the first deep trench and the conductive fill material portion, wherein the first diffusion barrier layer extends to a bottom of the plurality of dielectric sidewall spacers to contact sidewalls of the conductive fill material portion, wherein the first deep trench isolation structure has a first width, and the first width is greater than the second width; ​ forming a plurality of first semiconductor devices on a first semiconductor substrate material portion, wherein the first semiconductor substrate material portion is located in a high voltage region, the first deep trench isolation structure laterally surrounds the first semiconductor substrate material portion, and the second deep trench isolation structure laterally surrounds the first semiconductor substrate material portion and is laterally surrounded by the first deep trench isolation structure; forming a plurality of second semiconductor devices on a second semiconductor substrate material portion, wherein the second semiconductor substrate material portion is located in a low voltage region; and forming a plurality of third semiconductor devices on a third semiconductor substrate material portion.

29. The method of claim 28, wherein forming the first deep trench isolation structure is forming the first deep trench isolation structure to have the first width that is at least twice the second width of the second deep trench isolation structure.

30. The method of claim 29, wherein the first width of the first deep trench isolation structure is at least twice a third width of the third deep trench isolation structure.

31. The method of claim 28, wherein forming the plurality of first semiconductor devices on the first semiconductor substrate material portion comprises forming a plurality of high voltage semiconductor devices.

32. The method of claim 31, wherein forming the plurality of second semiconductor devices on the second semiconductor substrate material portion comprises forming a plurality of low voltage semiconductor devices.

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