System-on-chip with ferroelectric random access memory and tunable capacitor

Abstract

The present disclosure relates to a system-on-chip having a ferroelectric random access memory and a tunable capacitor. A semiconductor device includes: a substrate; a first dielectric layer located above the substrate; memory cells located above the substrate in a first region of the semiconductor device, wherein the memory cells include a first ferroelectric structure in the first dielectric layer, wherein the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer therebetween; and a tunable capacitor located above the substrate in a second region of the semiconductor device, wherein the tunable capacitor includes a second ferroelectric structure, wherein the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer therebetween, wherein at least a portion of the second ferroelectric structure is located in the first dielectric layer.

Description

Technical Field

[0001] The present invention generally relates to semiconductor devices, and in particular embodiments relates to semiconductor devices (e.g., system-on-chip devices) having a ferroelectric random access memory (FRAM or FeRAM) in a memory device region of the device and a tunable capacitor (e.g., a capacitor having a ferroelectric film between a top electrode and a bottom electrode of the capacitor) in a radio frequency (RF) circuit region of the device. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography and etching techniques to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size is reduced, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of the present disclosure, there is provided a semiconductor device, comprising: a substrate; a first dielectric layer located over the substrate; memory cells located over the substrate in a first region of the semiconductor device, wherein the memory cells include a first ferroelectric structure in the first dielectric layer, wherein the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer therebetween; and a tunable capacitor located over the substrate in a second region of the semiconductor device, wherein the tunable capacitor includes a second ferroelectric structure, wherein the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer therebetween, wherein at least a portion of the second ferroelectric structure is located in the first dielectric layer.

[0005] According to another embodiment of the present disclosure, there is provided a semiconductor device, comprising: a substrate; a memory device located over a first region of the substrate, wherein the memory device includes a first ferroelectric structure, the first ferroelectric structure including a first top electrode, a first ferroelectric film, and a first bottom electrode; and a radio frequency (RF) device located over a second region of the substrate, wherein the RF device includes a tunable capacitor having a second ferroelectric structure, wherein the second ferroelectric structure includes a second top electrode, a second ferroelectric film, and a second bottom electrode.

[0006] According to another embodiment of the present disclosure, a method of forming a semiconductor device is provided, the method comprising: forming a first dielectric layer over a substrate, the first dielectric layer extending from a first device region to a second device region of the semiconductor device; forming a memory cell of a memory device over the substrate in the first device region, wherein forming the memory cell includes forming a first ferroelectric structure in the first dielectric layer, and forming the first ferroelectric structure includes sequentially forming a first bottom electrode, a first ferroelectric layer, and a first top electrode over the substrate; and forming a tunable capacitor of a radio frequency (RF) circuit over the substrate in the second device region, wherein forming the tunable capacitor includes forming a second ferroelectric structure in the first dielectric layer, and forming the second ferroelectric structure includes sequentially forming a second bottom electrode, a second ferroelectric layer, and a second top electrode over the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction Figure 1 with the following detailed description, various aspects of the present disclosure are best understood. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figure 1 A cross-sectional view of a semiconductor device having ferroelectric random access memory (FRAM or FeRAM) cells and tunable capacitors in an embodiment is shown.

[0009] Figures 2 - 9 A cross-sectional view of a portion of a semiconductor device in an embodiment at various manufacturing stages is shown. Figure 1 is shown.

[0010] Figure 10 Various operating states of a tunable capacitor in an embodiment are shown.

[0011] Figure 11 A cross-sectional view of a semiconductor device having FRAM memory cells and tunable capacitors in an embodiment is shown.

[0012] Figure 12 A cross-sectional view of a semiconductor device having FRAM memory cells and two different tunable capacitors in an embodiment is shown.

[0013] Figures 13A - 13C Various views of a tunable capacitor in an embodiment are shown.

[0014] Figure 14 A semiconductor device having FeRAM memory cells and Figures 13A - 13CCross-sectional view of a semiconductor device with a tunable capacitor.

[0015] Figures 15 - 19 Shows a cross-sectional view of a part of the semiconductor device in various manufacturing stages in the embodiment. Figure 14 of a semiconductor device.

[0016] Figure 20 Perspective view of a wafer including a plurality of semiconductor die in the embodiment.

[0017] Figure 21 Shows in the embodiment Figure 20 block diagram of a semiconductor die in.

[0018] Figure 22 Is a flowchart of a method for forming a semiconductor device in the embodiment. Detailed Description

[0019] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Throughout the description herein, unless otherwise specified, the same reference numerals in different figures refer to the same or similar components formed of the same or similar materials by the same or similar methods.

[0020] In addition, spatially relative terms (such as, "beneath", "below", "lower", "above", "upper", etc.) may be used herein to facilitate describing the relationship of one element or feature shown in the figures to another (one or more) element or (one or more) feature. These spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0021] Ferroelectric random access memory (FeRAM / FRAM) (e.g., embedded FeRAM) has emerged as a candidate for next-generation non-volatile memory due to its fast read / write speed and small size. Typical FeRAM applications and RF / microwave applications are regarded as different applications in semiconductor manufacturing, and devices for FeRAM memory applications and RF / microwave applications are fabricated separately. When using ferroelectric materials, the application fields (e.g., memory applications and high-frequency applications such as RF filters and oscillators) are decoupled. Thus, products with both applications (e.g., memory and high-frequency applications) and characteristics are typically implemented in different chips (e.g., memory chips and RF circuit chips) fabricated with different processes.

[0022] In the present disclosure, a FeRAM process is used to fabricate tunable capacitors so that memory and high-frequency functions can be used for different applications on the same chip (e.g., system-on-chip (SoC)). In one embodiment, the ferroelectric tunable capacitor is fabricated at the same level as the ferroelectric structure of the FeRAM (e.g., in the same dielectric layer above the substrate), but in different regions of the same chip. For example, FeRAM is formed in the memory device region of the chip, and the tunable capacitor is formed in the RF circuit region of the chip (e.g., for high-frequency applications).

[0023] Figure 1 A cross-sectional view of a semiconductor device 100 having a ferroelectric random access memory (FRAM or FeRAM) cell and a tunable capacitor in an embodiment is shown. As an example, the semiconductor device 100 can be a semiconductor die (also referred to as a die or chip) having a memory device (e.g., FeRAM) and a radio frequency (RF) circuit integrated on the same semiconductor substrate. For simplicity, Figure 1 only a part of the semiconductor device is shown, rather than Figure 1 showing all the features of the semiconductor device 100.

[0024] Refer to Figure 1, the semiconductor device 100 has a plurality of electrical components (e.g., 103, 104) formed in and / or on a substrate 101. The electrical components 103 / 104 can be, for example, transistors, although other suitable electrical components such as resistors, capacitors, or inductors can also be formed. The substrate 101 can be a semiconductor substrate (e.g., doped or undoped silicon), or the active layer of a semiconductor-on-insulator (SOI) substrate. The substrate 101 can include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used.

[0025] An interconnect structure is formed over the substrate 101 and the electrical components 103 / 104 to connect the electrical components 103 / 104 to form a functional circuit. The interconnect structure can be formed, for example, by forming a metallization pattern in one or more dielectric layers over the substrate 101. For example, Figure 1 Dielectric layers 107 / 110 and conductive features 105 / 111 / 113 (e.g., vias and conductive lines) in the dielectric layers 107 / 110 are shown as part of the interconnect structure. The conductive features 105 / 111 / 113 electrically couple the electrical components 103 / 104 to a structure / circuit formed subsequently over the dielectric layer 110.

[0026] Figure 1 A ferroelectric structure 126 in a first region 200 (which can also be referred to as a first device region) of the semiconductor device 100, and a ferroelectric structure 122A in a second region 300 (which can also be referred to as a second device region) of the semiconductor device 100 are shown. In the illustrated embodiment, the first region 200 is a memory device region for forming a memory device (e.g., a FRAM device), and the second region 300 is a radio frequency (RF) circuit region for forming an RF circuit (e.g., an oscillator, an RF filter). The RF circuit here refers to a circuit designed for high-frequency applications, such as RF applications and / or microwave applications. In the following discussion, the ferroelectric structures (e.g., 126, 122A) can also be referred to as ferroelectric devices.

[0027] As Figure 1 shown, each of the ferroelectric structures 126 / 122A includes a bottom electrode 121, a ferroelectric layer 123, and a top electrode 125. In Figure 1In the example, a ferroelectric structure 126 / 122A is formed in a dielectric layer 120 on a substrate 101, where the upper surface of the top electrode 125 is flush with the upper surface of the dielectric layer 120, and the lower surface of the bottom electrode 121 is flush with the lower surface of the dielectric layer 120. Details regarding the materials and formation methods of the semiconductor device 100 are discussed below.

[0028] The bottom electrode 121, ferroelectric layer 123, and top electrode 125 of the ferroelectric structure 126 have the same dimensions (e.g., the same dimensions or surface area in a top view), such that the corresponding sidewalls of the bottom electrode 121, the corresponding sidewalls of the ferroelectric layer 123, and the corresponding sidewalls of the top electrode 125 are aligned in Figure 1 a cross-sectional view. In contrast, the top electrode 125 and the ferroelectric layer 123 of the ferroelectric structure 122A have the same dimensions, but the bottom electrode 121 of the ferroelectric structure 122A is larger than the top electrode 125 of the ferroelectric structure 122A. In particular, in Figure 1 it, the left sidewall of the bottom electrode 121, the ferroelectric layer 123, and the top electrode 125 are aligned, but the right sidewall of the bottom electrode 121 extends beyond the lateral extent of the top electrode 125 (or the lateral extent of the ferroelectric layer 123).

[0029] Figure 1 Also shown is a dielectric layer 130 formed on the dielectric layer 120, and conductive features 131 / 133 / 135 / 137 (e.g., vias or conductive lines) formed in the dielectric layer 130. In Figure 1 the example, the top electrode 125 of the ferroelectric structure 126 is electrically coupled to the conductive feature 135 (e.g., a conductive line) through the conductive feature 133 (e.g., a via), and the bottom electrode 121 of the ferroelectric structure 126 is electrically coupled to the source / drain of, for example, a transistor 104 through the conductive features 113 / 111 / 105, thereby forming a 1T-1C memory cell, where T represents a transistor and C represents a capacitor. In a 1T-1C memory cell, the polarization direction of the ferroelectric layer 123 is set to one of, for example, two polarization directions by an external electric field to indicate a "0" or "1" stored in the memory cell. The external electric field can be generated by applying a positive voltage or a negative voltage to the top electrode 125 and the bottom electrode 121. Thus, in a 1T-1C memory cell, the ferroelectric structure 126 serves as a memory element for storing information, for example, storing a bit "0" or bit "1" by changing the polarization direction of the ferroelectric layer 123. In the memory cell, the ferroelectric structure 126 does not function as a tunable capacitor (e.g., a capacitor with a tunable capacitance).

[0030] Still referring to Figure 1, the top electrode 125 of the ferroelectric structure 122A is electrically coupled to the conductive feature 135 (e.g., a conductive line) through a conductive feature 133 (e.g., a via). The upper surface of the bottom electrode 121 contacts (e.g., physically contacts) the conductive feature 131 (e.g., a via) and is electrically coupled to the conductive feature 137 (e.g., a conductive line) through the conductive feature 131. The lower surface of the bottom electrode contacts (e.g., physically contacts) the conductive feature 113 (e.g., a via) and is electrically coupled to the electrical component 103 (e.g., a transistor, a resistor, or an inductor) through the conductive features 113 / 111 / 105. Note that the bottom electrode 121 of the ferroelectric structure 122A has two circuit paths, e.g., an upper path connected to the conductive feature 137 and a lower path connected to the electrical component 103. As will be discussed in more detail below, the upper path is used for fine-tuning (e.g., adjusting) the capacitance of the ferroelectric structure 122A, and the lower path is used to form an RF circuit including the ferroelectric structure 122A. Thus, the ferroelectric structure 122A in the second region 300 serves as a tunable capacitor in the RF circuit and can be referred to as the tunable capacitor 122A.

[0031] In some embodiments, the dielectric constant of the ferroelectric layer 123 exhibits a dependence on the voltage applied to the ferroelectric layer 123 and / or the frequency at which the ferroelectric layer 123 operates. Thus, the ferroelectric structure 122A can be used as a tunable capacitor for RF / microwave applications. For example, the ferroelectric structure 122A can be used as a tunable capacitor in a voltage-controlled oscillator (VCO) circuit or an RF filter circuit having an adjustable filter bandwidth. In some embodiments, the ferroelectric structure 122A serves as a tunable capacitor in an RF circuit that includes the electrical component 103, the ferroelectric structure 122A, and other parts of the RF circuit (e.g., see Figure 10 143 in Figure 10 ). In other words, the ferroelectric structure 122A, the electrical component 103, and other parts of the RF circuit (e.g.,

[0032] [[ID=!0]]143 in

[0033] Figures 2 - 9 form a complete RF circuit that provides a designed RF function (e.g., as an oscillator circuit or an RF filter). Figure 1 ). Specifically, Figures 2 - 9 only showsFigure 1 includes a second region 300 including a ferroelectric structure 122A, and the first region 200 in Figure 1 is not shown. Those skilled in the art will readily understand that the corresponding features (such as the ferroelectric structure 126) in the first region 200 are formed using the same or similar material(s) in the same or similar processing steps after reading this disclosure.

[0034] Now referring to Figure 2 , electrical components 103 such as transistors, resistors, inductors, etc. are formed in / on a substrate 101. A dielectric layer 107 and 110 are formed over the substrate 101 using a suitable formation method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. The dielectric layers 107 and 110 may include silicon oxide, silicon nitride, etc. Conductive features 105, 111, and 113 (e.g., vias or conductive lines) including a conductive material such as copper, aluminum, etc. are formed in the dielectric layers 107 / 110 by patterning the dielectric layers 107 / 110 and forming a conductive material in the pattern of the dielectric layers 107 / 110 using a suitable formation method such as electroplating, damascene, dual damascene, etc.

[0035] Next, in Figure 3 , a dielectric layer 120 is formed over the dielectric layer 110. The dielectric layer 120 may include the same or similar material as the dielectric layer 110 and may be formed using the same or similar formation method, so details are not repeated. Next, openings are formed in the dielectric layer 120 using, for example, photolithography and patterning techniques. Next, a bottom electrode layer 121, a ferroelectric layer 123, and a top electrode layer 125 are sequentially formed in the openings. The bottom electrode layer 121 is electrically coupled to the underlying conductive feature 113 and contacts (e.g., physically contacts) the underlying conductive feature 113.

[0036] In some embodiments, the bottom electrode layer 121 includes a conductive material such as TiN, TaN, W, Ru, Co, Cu, etc. and is formed by a suitable deposition method such as PVD, CVD, plasma enhanced CVD (PECVD), etc. In some embodiments, the thickness of the bottom electrode layer 121 is between about 20 nm and about 50 nm.

[0037] Next, a ferroelectric layer 123 is formed over the bottom electrode layer 121. In the illustrated embodiment, the ferroelectric layer 123 includes a ferroelectric material. In some embodiments, the ferroelectric material is a hafnium (Hf)-based material (also referred to as a hafnium-containing material), such as HfZrO, HfAlO, HfLaO, HfON, or HfO2. As an example, the thickness of the hafnium-based material can be between about 5 nm and about 50 nm. In some embodiments, the ferroelectric layer 123 comprises a lead-based material (also referred to as a lead-containing material), such as lead zirconate titanate (PZT) or strontium bismuth tantalate (SBT). The thickness of the lead-based material can be between about 100 nm and about 5 μm. An appropriate deposition method (e.g., atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), CVD, etc.) can be used to form the ferroelectric layer 123.

[0038] Next, a top electrode layer 125 is formed over the ferroelectric layer 123. The top electrode layer 125 can be formed of the same or similar material as the bottom electrode layer 121 using the same or similar formation method, and thus the details are not repeated. As an example, the thickness of the top electrode layer 125 can be between about 20 nm and about 500 nm. After forming the top electrode layer 125, a planarization process such as chemical mechanical planarization (CMP) can be performed to remove the excess portions of the materials (e.g., 121, 123, 125) from the upper surface of the dielectric layer 120 and achieve a coplanar upper surface between the top electrode layer 125 and the dielectric layer 120.

[0039] Next, in Figure 4 a portion of the top electrode layer 125 and a portion of the ferroelectric layer 123 are removed to form an opening 117 in the dielectric layer 120 that exposes the bottom electrode layer 121. For example, a patterned mask layer (e.g., a patterned photoresist) is formed over the dielectric layer 120 and used as an etch mask in an anisotropic etching process to form the opening 117. After the etching process for forming the opening 117, the remaining portion of the top electrode layer 125 forms the top electrode 125 of the ferroelectric structure 122A, the remaining portion of the ferroelectric layer 123 forms the ferroelectric layer 123 of the ferroelectric structure 122A, and the bottom electrode layer 121 is referred to as the bottom electrode 121 of the ferroelectric structure 122A.

[0040] Those skilled in the art will recognize that in order to form a ferroelectric structure 126 in the Figure 1 first region 200, the same or similar processing steps as in Figure 2 and Figure 3 can be performed, and the processing in Figure 4 (e.g., forming the opening 117) can be omitted.

[0041] Next, in Figure 5In [description], a dielectric layer 130 is formed over the dielectric layer 120. The dielectric layer 130 also fills the opening 117. The dielectric layer 130 may include the same or similar materials as the dielectric layer 110 and may be formed using the same or similar formation methods, so details will not be repeated.

[0042] Next, in Figure 6 In [description], trench openings 135T and 137T are formed in the dielectric layer 130. In some embodiments, the trench openings 135T and 137T are formed by forming a patterned mask layer (e.g., a patterned photoresist layer) over the dielectric layer 130 and then performing an anisotropic etching process to remove portions of the dielectric layer 130 exposed by the patterned mask layer. Then, after forming the trench openings, the patterned mask layer is removed, for example, by lift-off or ashing.

[0043] Next, in Figure 7 In [description], a via opening 133V is formed that extends from the bottom of the trench opening 135T to the top electrode 125. In other words, the top electrode 125 is exposed through the via opening 133V. The via opening 133V can be formed by similar processing steps as those for forming the trench opening 135T, so details will not be repeated.

[0044] Next, in Figure 8 In [description], a via 131V is formed that extends from the bottom of the trench opening 137T to the bottom electrode 121. In other words, the bottom electrode 121 is exposed through the via 131V.

[0045] Next, in Figure 9 In [description], conductive features (e.g., vias 131 / 133 and conductive lines 135 / 137) are respectively formed in the via openings 131V / 133V and the trench openings 135T / 137T. The conductive features include conductive materials such as copper, aluminum, etc. and are formed using suitable formation methods such as electroplating, damascene, dual damascene, etc. After formation, the conductive feature 135 is electrically coupled to the top electrode 125 through the conductive feature 133, and the conductive feature 137 is electrically coupled to the upper surface of the bottom electrode 121 through the conductive feature 131.

[0046] As will be readily appreciated by those skilled in the art, additional features may be formed in additional processing steps to complete the fabrication of the semiconductor device 100. For example, additional dielectric layers, additional conductive features, and / or additional electrical components may be formed and electrically coupled to the Figure 9 structure shown to complete the fabrication of the semiconductor device 100. For simplicity, details are not discussed here.

[0047] In an embodiment, Figure 10Shows various operating states of the tunable capacitor 122A. The tunable capacitor 122A can be Figure 1 the ferroelectric structure 122A in Figure 10 For simplicity, Figure 9 only the tunable capacitor 122A and its electrical connections are shown, while

[0048] In some embodiments, when used in an RF circuit, the tunable capacitor 122A operates in two states, such as an initialization state and a normal operating state. In the initialization state, the capacitance of the tunable capacitor 122A is set by applying a positive or negative voltage to the top electrode 125 and the bottom electrode 121. The positive or negative voltage sets the polarization direction of the ferroelectric layer 123, thereby setting the nominal capacitance of the tunable capacitor 122A. The capacitance of the tunable capacitor 122A can be further finely tuned by applying a modulation voltage at the bottom electrode 121, as described below.

[0049] Figure 10 Shows a switch S1, which is electrically coupled to the top electrode 125 through, for example, a conductive feature 135. The switch S1 can be any suitable switch, such as a transistor switch integrated in a semiconductor device. During the initialization state, the switch S1 is electrically coupled to a voltage source 141 (e.g., a +5V voltage source), such that the top electrode 125 has the same voltage as the voltage source 141. During the normal operating state, the switch S1 is electrically coupled to an RF circuit 143 (e.g., an oscillator or an RF filter), as Figure 10 shown by the dashed line in

[0050] In Figure 10 the lower surface of the bottom electrode 121 is electrically coupled to an electrical component 103 (e.g., a transistor), and the upper surface of the bottom electrode 121 is electrically coupled to a modulation voltage source 145 through, for example, a conductive feature 137. Since the dielectric constant of the ferroelectric layer 123 shows a dependence on the applied voltage, in some embodiments, the capacitance of the tunable capacitor 122A can be finely tuned (e.g., adjusted) by applying a modulation voltage at the bottom electrode 121 through the conductive feature 137.

[0051] The operation of the tunable capacitor 122A is described below using examples. For instance, consider the tunable capacitor 122A having a ferroelectric layer 123 that changes its polarization direction from a first polarization direction to a second polarization direction at +3V. Assume that during the initialization state, the ferroelectric layer 123 needs to be set to the second polarization direction. Thus, during the initialization state, the switch S1 is electrically coupled to a voltage source 141 that provides a voltage of, for example, +5V to the top electrode 125. Assuming that the bottom electrode 121 has a zero voltage due to its electrical connection in the circuit, the voltage difference between the top electrode 125 and the bottom electrode 121 is +5V, which is higher than the +3V required to switch the polarization direction of the ferroelectric layer 123. To finely tune the capacitance of the tunable capacitor 122A, the modulation voltage source 145 can apply a modulation voltage to the bottom electrode 121, for example, a voltage between 0V and +2V. In the case of applying such a modulation voltage, the voltage difference between the top electrode 125 and the bottom electrode 121 is still higher than +3V, but may vary between +3V and +5V. The voltage change causes a change in the dielectric constant of the ferroelectric layer 123, thereby changing the capacitance of the tunable capacitor 122A. In other words, by changing the modulation voltage, the tunable capacitor 122A can provide multiple (e.g., 3, 4, or more) different capacitance values. In some embodiments, by changing the modulation voltage (e.g., continuously), the tunable capacitor 122A provides continuously varying capacitance values within an adjustment range. For example, the capacitance of the tunable capacitor 122A can be between about 0.5C 最大 and C 最大 where C 最大 is the maximum capacitance value of the tunable capacitor 122A.

[0052] In some embodiments, the modulation voltage is applied during the initialization state and maintained (e.g., applied) during the normal operation state. The value of the modulation voltage can be adjusted (e.g., increased or decreased) during the normal operation state (e.g., based on user settings) to provide dynamically (e.g., in real-time or on-demand) tunable capacitance for the tunable capacitor 122A. In some embodiments, the modulation voltage is not applied during the initialization state, but is applied during the normal operating state. In still some other embodiments, the modulation voltage source 145 is omitted, and thus, the conductive feature 137 is not connected to the modulation voltage source, in which case, the tunable capacitor 122A behaves similar to a non-tunable capacitor with a fixed value.

[0053] Figure 11 A cross-sectional view of a semiconductor device 100A in an embodiment is shown, which has FeRAM memory cells in a first region 200 and a tunable capacitor in a second region 300. The semiconductor device 100A is similar to Figure 1 the semiconductor device 100, butFigure 11 The tunable capacitor includes two capacitances coupled in parallel. Specifically, Figure 11 the tunable capacitor includes capacitance 122A and another capacitance 122B. Figure 11 The capacitance 122A in [[e.g., the tunable capacitor]] is the same as Figure 1 the tunable capacitance 122A in Figure 11 The capacitance 122B in has a structure that is the same as or similar to the ferroelectric structure 126 in the first region 200. In some embodiments, the capacitance 122B is in parallel with the tunable capacitance 122A to increase Figure 11 the capacitance of the tunable capacitor. Figure 11 Shows the conductive feature 111 that electrically couples the bottom electrodes 121 of the capacitances 122A / 122B together. The top electrodes 125 of the capacitances 122A / 122B can be coupled together by a conductive feature (not shown) formed over the dielectric layer 130.

[0054] Figure 12 Shows a cross-sectional view of a semiconductor device 100B in an embodiment having a FeRAM memory cell and two different tunable capacitors. Figure 12 The FeRAM memory cell in the first region 200 of is the same as Figure 1 the FeRAM memory cell in Figure 12 In the second region 300 of , two tunable capacitors are shown. The tunable capacitor 122A to the left of the second region 300 is the same as Figure 1 the tunable capacitor 122A in Figure 11 Another tunable capacitor (including two capacitances coupled in parallel) is the same as the tunable capacitor in

[0055] Figures 13A - 13C Shows various views (e.g., perspective view, cross-sectional view) of the tunable capacitor 122C in an embodiment. Figure 13A Shows a perspective view of the tunable capacitor 122C, Figure 13B Shows a cross-sectional view of the tunable capacitor 122C along Figure 13A the cross-section A-A in Figure 13C Shows a cross-sectional view of the tunable capacitor 122C along Figure 13B the cross-section B-B in Figures 13A - 13C Further shows the conductive features 135 / 137 (e.g., vias or conductive lines) connected to the tunable capacitor 122C.

[0056] As in Figures 13A - 13CAs shown, unlike the tunable capacitor 122A having parallel plate-like top and bottom electrodes 125 and 121, the tunable capacitor 122C has a cylindrical top electrode 125 and a bottom electrode 121. Specifically, the bottom electrode 121 has a hollow cylindrical shape. The top electrode 125 has a central portion 125C having a cylindrical shape. The central portion 125C extends into the bottom electrode 121 and is surrounded by the bottom electrode 121. The top electrode 125 also has a top portion 125T that is located above the central portion 125C and is connected to the central portion 125C. The ferroelectric layer 123 is located between the top electrode 125 and the bottom electrode 121 and surrounds the cylindrical central portion 125C of the top electrode 125. The conductive features 135, 137, and 111 are electrically coupled to the top electrode 125, the upper surface of the bottom electrode 121, and the lower surface of the bottom electrode 121, respectively.

[0057] Figure 14 A cross-sectional view of a semiconductor device 100C in an embodiment is shown, the semiconductor device 100C having a FeRAM memory cell and Figures 13A - 13C the tunable capacitor 122C in. In Figure 14 the FeRAM memory cells in the first region 200 are the same as those in Figure 1 . In the example of Figure 14 , a ferroelectric structure 126 is provided in the dielectric layer 120. The bottom electrode 121 of the ferroelectric structure 126 faces the lower surface of the substrate 101 and is flush with the lower surface of the dielectric layer 120, and the upper surface of the top electrode 125 of the ferroelectric structure 126 is flush with the upper surface of the dielectric layer 120 facing away from the substrate 101.

[0058] The tunable capacitor 122C is at least partially formed in the dielectric layer 120. As Figure 14 shown, the bottom electrode 121 of the tunable capacitor 122C has a first portion 121A, a second portion 121B, and a third portion 121C. The first portion 121A extends along the upper surface of the dielectric layer 120 away from the substrate 101. The second portion 121B extends from the upper surface of the dielectric layer 120 to the lower surface of the dielectric layer 120 facing the substrate 101. The third portion 121C is provided at the lower surface of the dielectric layer 120 and extends parallel to the lower surface of the dielectric layer 120. The third portion 121C connects the second portion 121B provided along the opposite inner sidewalls of the dielectric layer 120.

[0059] Still referring to Figure 14, the ferroelectric layer 123 of the tunable capacitor 122C extends conformally along the upper surface of the bottom electrode 121. Accordingly, the ferroelectric layer 123 of the tunable capacitor 122C has a first portion that extends along a first portion 121A of the bottom electrode 121, a second portion that extends along a second portion 121B of the bottom electrode 121, and a third portion that extends along a third portion 121C of the bottom electrode 121.

[0060] The top electrode 125 of the tunable capacitor 122C has a central portion 125C that extends into the dielectric layer 120 and is surrounded by the ferroelectric layer 123. The top electrode 125 of the tunable capacitor 122C also has a top portion 125T that is disposed above the central portion 125C and covers (e.g., physically contacts) the upper surface of the ferroelectric layer 123.

[0061] As Figure 14 shown, the bottom surface of the bottom electrode 121 of the tunable capacitor 122C that faces the lowermost surface of the substrate 101 (e.g., the lower surface of the third portion 121C) is flush with the lower surface of the dielectric layer 120, and the upper surface of the top electrode 125 of the tunable capacitor 122C that faces away from the substrate 101 extends more from the substrate 101 than the upper surface of the dielectric layer 120. In other words, a portion of the tunable capacitor 122C extends above the upper surface of the dielectric layer 120. Accordingly, compared with the tunable capacitors in Figure 1 , Figure 11 and Figure 12 , the cylindrical structure of the tunable capacitor 122C provides an additional dimension (e.g., the vertical dimension in Figure 14 ) to adjust the capacitance of the tunable capacitor 122C. For example, the height H of the central portion 125C of the top electrode 125 can be adjusted (e.g., increased or decreased) to change the area between the top electrode 125 and the bottom electrode 121, thereby changing the capacitance of the tunable capacitor 122C. Accordingly, the tunable capacitor 122C can also be referred to as having a three-dimensional (3D) structure or having a 3D cylindrical structure.

[0062] The tunable capacitor 122C can operate in two operating phases, e.g., an initialization state and a normal operating state, similar to those discussed above with reference to Figure 10 . Accordingly, the details are not repeated here.

[0063] Figures 15 - 19 Shows a cross-sectional view of a portion of the semiconductor device 100 in various manufacturing stages in an embodiment. Specifically, Figure 14 only shows the second region 300 including the tunable capacitor 122C in Figures 15 - 19 , while Figure 14 includes the tunable capacitor 122C, and Figure 14The first region 200 in Figure 14 is not shown. Additionally, for simplicity,

[0064] certain layers in Figure 15 (e.g., 101, 107) are not shown. Those skilled in the art will readily appreciate that the corresponding features (e.g., ferroelectric structure 126) in the first region 200 are formed using the same or similar material(s) in the same or similar processing steps.

[0065] Next, referring to Figure 16 , conductive features 111 / 113 are formed in dielectric layer 110. Next, a dielectric layer 120 is formed over dielectric layer 110, and an opening 124 is formed in dielectric layer 120 using, for example, photolithography and etching techniques. The opening 124 exposes the upper surface of the conductive feature 113.

[0066] Next, in Figure 17 , a bottom electrode layer 121 is formed to line the upper surface of the dielectric layer 120 and the sidewalls and bottom of the lined opening 124. For example, a conformal deposition method such as ALD can be used to form the bottom electrode layer 121. After forming the bottom electrode layer 121, a ferroelectric layer 123 and a top electrode layer 125 are successively conformally formed over the bottom electrode layer 121 using, for example, a conformal deposition method such as ALD.

[0066] Next, in Figure 17 , a bottom electrode layer 121 is formed to line the upper surface of the dielectric layer 120 and the sidewalls and bottom of the lined opening 124. For example, a conformal deposition method such as ALD can be used to form the bottom electrode layer 121. After forming the bottom electrode layer 121, a ferroelectric layer 123 and a top electrode layer 125 are successively conformally formed over the bottom electrode layer 121 using, for example, a conformal deposition method such as ALD.

[0066] Next, in Figure 17 , a bottom electrode layer 121 is formed to line the upper surface of the dielectric layer 120 and the sidewalls and bottom of the lined opening 124. For example, a conformal deposition method such as ALD can be used to form the bottom electrode layer 121. After forming the bottom electrode layer 121, a ferroelectric layer 123 and a top electrode layer 125 are successively conformally formed over the bottom electrode layer 121 using, for example, a conformal deposition method such as ALD.

[0067] Next, in Figure 18 , a portion of the top electrode layer 125 and a portion of the ferroelectric layer 123 are removed to expose the bottom electrode layer 121. An anisotropic etching process using a patterned etching mask can be performed to remove the portion of the top electrode layer 125 and the portion of the ferroelectric layer 123. An additional etching process can be performed to pattern the bottom electrode layer 121. After the (one or more) etching processes, the remaining portion of the top electrode layer 125 forms the top electrode 125 of the tunable capacitor 122C, the remaining portion of the ferroelectric layer 123 forms the ferroelectric layer 123 of the tunable capacitor 122C, and the remaining portion of the bottom electrode layer 121 forms the bottom electrode 121 of the tunable capacitor 122C.

[0067] Next, in Figure 18 , a portion of the top electrode layer 125 and a portion of the ferroelectric layer 123 are removed to expose the bottom electrode layer 121. An anisotropic etching process using a patterned etching mask can be performed to remove the portion of the top electrode layer 125 and the portion of the ferroelectric layer 123. An additional etching process can be performed to pattern the bottom electrode layer 121. After the (one or more) etching processes, the remaining portion of the top electrode layer 125 forms the top electrode 125 of the tunable capacitor 122C, the remaining portion of the ferroelectric layer 123 forms the ferroelectric layer 123 of the tunable capacitor 122C, and the remaining portion of the bottom electrode layer 121 forms the bottom electrode 121 of the tunable capacitor 122C.

[0067] Next, in Figure 18 , a portion of the top electrode layer 125 and a portion of the ferroelectric layer 123 are removed to expose the bottom electrode layer 121. An anisotropic etching process using a patterned etching mask can be performed to remove the portion of the top electrode layer 125 and the portion of the ferroelectric layer 123. An additional etching process can be performed to pattern the bottom electrode layer 121. After the (one or more) etching processes, the remaining portion of the top electrode layer 125 forms the top electrode 125 of the tunable capacitor 122C, the remaining portion of the ferroelectric layer 123 forms the ferroelectric layer 123 of the tunable capacitor 122C, and the remaining portion of the bottom electrode layer 121 forms the bottom electrode 121 of the tunable capacitor 122C.

[0068] Next, in Figure 19 , conductive lines 135 / 137 and vias 133 / 131 are formed in the trench openings 135T / 137T and via openings 133V / 131V, respectively. Thus, as shown in Figure 14The tunable capacitor 122C shown and the conductive features connected thereto.

[0069] Figure 20 A perspective view of a wafer 400 including a plurality of semiconductor dies 303 in an embodiment is shown. Each of the semiconductor dies 303 may include a memory region (e.g., a FeRAM device region) and an RF circuit region (e.g., having a tunable capacitor), such as Figure 1 、 11 those shown in 12 and 14.

[0070] Figure 21 A block diagram of a semiconductor die 303 in an embodiment is shown. As Figure 21 shown, the semiconductor die 303 includes a FeRAM device region (e.g., having a ferroelectric structure 126 to form a 1T-1C memory cell) and an RF / microwave circuit region (e.g., having a tunable capacitor, such as a combination of 122A, 122A, and 122B, or 122C). The semiconductor die 303 may also include other device regions, such as a logic device region and a region for other functional blocks.

[0071] Figure 22 is a flowchart of a method 1000 for forming a semiconductor device in an embodiment. It should be understood that Figure 22 the embodiment method shown is only an example of many possible embodiment methods. Those of ordinary skill in the art can recognize many variations, alternatives, and modifications. For example, various steps shown may be added, removed, replaced, rearranged, or repeated Figure 22 as shown.

[0072] Now referring to Figure 22 , in step 1010, a first dielectric layer is formed over a substrate, the first dielectric layer extending from a first device region of the semiconductor device to a second device region of the semiconductor device. In step 1020, a memory cell of a memory device is formed over the substrate of the first device region, wherein forming the memory cell includes forming a first ferroelectric structure in the first dielectric layer, and wherein forming the first ferroelectric structure includes sequentially forming a first bottom electrode, a first ferroelectric layer, and a first top electrode over the substrate. In step 1030, a tunable capacitor of a radio frequency (RF) circuit is formed over the substrate of the second device region, wherein forming the tunable capacitor includes forming a second ferroelectric structure in the first dielectric layer, and wherein forming the second ferroelectric structure includes sequentially forming a second bottom electrode, a second ferroelectric layer, and a second top electrode over the substrate.

[0073] Embodiments can achieve advantages. For example, in the present disclosure, an existing FeRAM process used to form an FeRAM memory cell in a memory device region of a semiconductor device is also used to form a tunable capacitor in an RF circuit region of the semiconductor region, thereby allowing memory and high-frequency functions to be used for various applications (e.g., FeRAM and high-frequency tunable circuits) on the same chip (e.g., SoC). The tunable capacitor in the disclosed RF circuit region and the ferroelectric structure in the FeRAM memory cell can be formed in the same dielectric layer using the same (one or more) processing steps and the same (one or more) materials, thereby reducing manufacturing costs and allowing for easy integration into existing manufacturing processes.

[0074] According to an embodiment, a semiconductor device includes: a substrate; a first dielectric layer located above the substrate; memory cells located above the substrate in a first region of the semiconductor device, wherein the memory cells include a first ferroelectric structure in the first dielectric layer, wherein the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer therebetween; and a tunable capacitor located above the substrate in a second region of the semiconductor device, wherein the tunable capacitor includes a second ferroelectric structure, wherein the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer therebetween, wherein at least a portion of the second ferroelectric structure is located in the first dielectric layer. In an embodiment, the first region is a memory device region including a memory device, and the second region is an RF circuit region including an RF circuit. In an embodiment, the first ferroelectric structure is configured as part of the memory device, and the second ferroelectric structure is configured as part of the RF circuit. In an embodiment, the first top electrode and the first bottom electrode have the same size, wherein the second top electrode is smaller than the second bottom electrode. In an embodiment, the semiconductor device further includes: a first conductive feature and a second conductive feature located above the substrate in the first region of the semiconductor device, wherein the first conductive feature is located above and in contact with the first top electrode, and the second conductive feature is located below and in contact with the first bottom electrode; a third conductive feature, a fourth conductive feature, and a fifth conductive feature located above the substrate in the second region of the semiconductor device, wherein the third conductive feature is located above and in contact with the second top electrode, the fourth conductive feature is located above and in contact with the upper surface of the second bottom electrode away from the substrate, and the fifth conductive feature is located below and in contact with the lower surface of the second bottom electrode facing the substrate. In an embodiment, the third conductive feature is configured to be coupled to a voltage source during an initialization state of the tunable capacitor, wherein the third conductive feature is configured to be coupled to an RF circuit during a normal operating state of the tunable capacitor. In an embodiment, the fourth conductive feature is configured to be coupled to a modulation voltage source for finely tuning the capacitance of the tunable capacitor during a normal operating state. In an embodiment, the modulation voltage provided by the modulation voltage source is configured to vary during a normal operating state. In an embodiment, the first top electrode and the second top electrode have upper surfaces coplanar with the first dielectric layer, wherein the first bottom electrode and the second bottom electrode have lower surfaces coplanar with the first dielectric layer. In an embodiment, the second bottom electrode has: a first portion extending along the upper surface of the first dielectric layer away from the substrate; a second portion extending from the upper surface of the first dielectric layer to the lower surface of the first dielectric layer facing the substrate; and a third portion located at the lower surface of the first dielectric layer, connecting the second portion and extending parallel to the lower surface of the first dielectric layer.In an embodiment, the second ferroelectric layer extends conformally along the upper surface of the second bottom electrode, wherein the second top electrode has: a first portion that extends into the first dielectric layer and is surrounded by the second ferroelectric layer; and a second portion that is above the first portion and covers the upper surface of the second ferroelectric layer.

[0075] According to an embodiment, a semiconductor device includes: a substrate; a memory device located over a first region of the substrate, wherein the memory device includes a first ferroelectric structure that includes a first top electrode, a first ferroelectric film, and a first bottom electrode; and a radio frequency (RF) device located over a second region of the substrate, wherein the RF device includes a tunable capacitor having a second ferroelectric structure, wherein the second ferroelectric structure includes a second top electrode, a second ferroelectric film, and a second bottom electrode. In an embodiment, the first ferroelectric structure is disposed in a first dielectric layer over the substrate, wherein the second ferroelectric structure is at least partially disposed in the first dielectric layer. In an embodiment, the lower surface of the first bottom electrode facing the substrate is flush with the lower surface of the second bottom electrode facing the substrate. In an embodiment, the upper surface of the first top electrode facing away from the substrate is flush with the upper surface of the second top electrode facing away from the substrate. In an embodiment, the upper surface of the first top electrode facing away from the substrate is flush with the upper surface of the first dielectric layer facing away from the substrate, and wherein the upper surface of the second top electrode facing away from the substrate extends further from the substrate than the upper surface of the first dielectric layer.

[0076] According to an embodiment, a method of forming a semiconductor device includes: forming a first dielectric layer over a substrate, the first dielectric layer extending from a first device region of the semiconductor device to a second device region of the semiconductor device; forming memory cells of a memory device over the substrate in the first device region, wherein forming the memory cells includes forming a first ferroelectric structure in the first dielectric layer, wherein forming the first ferroelectric structure includes sequentially forming a first bottom electrode, a first ferroelectric layer, and a first top electrode over the substrate; and forming a tunable capacitor of a radio frequency (RF) circuit over the substrate in the second device region, wherein forming the tunable capacitor includes forming a second ferroelectric structure in the first dielectric layer, wherein forming the second ferroelectric structure includes sequentially forming a second bottom electrode, a second ferroelectric layer, and a second top electrode over the substrate. In an embodiment, the first ferroelectric structure and the second ferroelectric structure are formed in the same processing step. In an embodiment, the first bottom electrode and the second bottom electrode are formed of a first conductive material using the same forming method, wherein the first ferroelectric layer and the second ferroelectric layer are formed of a ferroelectric material using the same forming method, and wherein the first top electrode and the second top electrode are formed of a second conductive material using the same forming method. In an embodiment, the method further includes: forming a first conductive feature over and in contact with an upper surface of the second bottom electrode remote from the substrate; and forming a second conductive feature under and in contact with a lower surface of the second bottom electrode facing the substrate.

[0077] Although the invention has been described with reference to illustrative embodiments, the description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments of the invention, as well as other embodiments, will be apparent to persons skilled in the art upon reference to the specification. Accordingly, the appended claims encompass any such modifications or embodiments.

[0078] Example 1 is a semiconductor device including: a substrate; a first dielectric layer over the substrate; memory cells over the substrate in a first region of the semiconductor device, wherein the memory cells include a first ferroelectric structure in the first dielectric layer, wherein the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer therebetween; and a tunable capacitor over the substrate in a second region of the semiconductor device, wherein the tunable capacitor includes a second ferroelectric structure, wherein the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer therebetween, wherein at least a portion of the second ferroelectric structure is located in the first dielectric layer.

[0079] Example 2 is the semiconductor device described in Example 1, wherein the first region is a memory device region including a memory device, and the second region is an RF circuit region including a radio frequency (RF) circuit.

[0080] Example 3 is the semiconductor device described in Example 1, wherein the first ferroelectric structure is configured as part of a memory device, and the second ferroelectric structure is configured as part of a radio frequency (RF) circuit.

[0081] Example 4 is the semiconductor device described in Example 1, wherein the first top electrode and the first bottom electrode have the same size, and wherein the second top electrode is smaller than the second bottom electrode.

[0082] Example 5 is the semiconductor device described in Example 4, further comprising: a first conductive feature and a second conductive feature, above the substrate in the first region of the semiconductor device, wherein the first conductive feature is above and in contact with the first top electrode, and the second conductive feature is below and in contact with the first bottom electrode; a third conductive feature, a fourth conductive feature, and a fifth conductive feature, above the substrate in the second region of the semiconductor device, wherein the third conductive feature is above and in contact with the second top electrode, the fourth conductive feature is above and in contact with the upper surface of the second bottom electrode away from the substrate, and the fifth conductive feature is below and in contact with the lower surface of the second bottom electrode facing the substrate.

[0083] Example 6 is the semiconductor device described in Example 5, wherein the third conductive feature is configured to be coupled to a voltage source during an initialization state of the tunable capacitor, and wherein the third conductive feature is configured to be coupled to a radio frequency (RF) circuit during a normal operating state of the tunable capacitor.

[0084] Example 7 is the semiconductor device described in Example 6, wherein the fourth conductive feature is configured to be coupled to a modulation voltage source for finely tuning the capacitance of the tunable capacitor during the normal operating state.

[0085] Example 8 is the semiconductor device described in Example 7, wherein the modulation voltage provided by the modulation voltage source is configured to vary during the normal operating state.

[0086] Example 9 is the semiconductor device described in Example 1, wherein the first top electrode and the second top electrode have upper surfaces coplanar with the first dielectric layer, and wherein the first bottom electrode and the second bottom electrode have lower surfaces coplanar with the first dielectric layer.

[0087] Example 10 is the semiconductor device described in Example 1, wherein the second bottom electrode has: a first portion extending along the upper surface of the first dielectric layer away from the substrate; a second portion extending from the upper surface of the first dielectric layer to the lower surface of the first dielectric layer facing the substrate; and a third portion located at the lower surface of the first dielectric layer, connecting the second portion and extending in parallel with the lower surface of the first dielectric layer.

[0088] Example 11 is the semiconductor device described in Example 10, wherein the second ferroelectric layer extends conformally along the upper surface of the second bottom electrode, and wherein the second top electrode has: a first portion extending into the first dielectric layer and surrounded by the second ferroelectric layer; and a second portion above the first portion and covering the upper surface of the second ferroelectric layer.

[0089] Example 12 is a semiconductor device, comprising: a substrate; a memory device located above a first region of the substrate, wherein the memory device includes a first ferroelectric structure including a first top electrode, a first ferroelectric film, and a first bottom electrode; and a radio frequency (RF) device located above a second region of the substrate, wherein the RF device includes a tunable capacitor having a second ferroelectric structure, and wherein the second ferroelectric structure includes a second top electrode, a second ferroelectric film, and a second bottom electrode.

[0090] Example 13 is the semiconductor device described in Example 12, wherein the first ferroelectric structure is disposed in a first dielectric layer above the substrate, and wherein the second ferroelectric structure is at least partially disposed in the first dielectric layer.

[0091] Example 14 is the semiconductor device described in Example 13, wherein the lower surface of the first bottom electrode facing the substrate is flush with the lower surface of the second bottom electrode facing the substrate.

[0092] Example 15 is the semiconductor device described in Example 14, wherein the upper surface of the first top electrode facing away from the substrate is flush with the upper surface of the second top electrode facing away from the substrate.

[0093] Example 16 is the semiconductor device described in Example 14, wherein the upper surface of the first top electrode facing away from the substrate is flush with the upper surface of the first dielectric layer facing away from the substrate, and wherein the upper surface of the second top electrode facing away from the substrate extends further from the substrate than the upper surface of the first dielectric layer.

[0094] Example 17 is a method of forming a semiconductor device, the method comprising: forming a first dielectric layer over a substrate, the first dielectric layer extending from a first device region of the semiconductor device to a second device region of the semiconductor device; forming memory cells of a memory device over the substrate in the first device region, wherein forming the memory cells includes forming a first ferroelectric structure in the first dielectric layer, wherein forming the first ferroelectric structure includes sequentially forming a first bottom electrode, a first ferroelectric layer, and a first top electrode over the substrate; and forming a tunable capacitor of a radio frequency (RF) circuit over the substrate in the second device region, wherein forming the tunable capacitor includes forming a second ferroelectric structure in the first dielectric layer, wherein forming the second ferroelectric structure includes sequentially forming a second bottom electrode, a second ferroelectric layer, and a second top electrode over the substrate.

[0095] Example 18 is the method of Example 17, wherein the first ferroelectric structure and the second ferroelectric structure are formed in the same processing step.

[0096] Example 19 is the method of Example 18, wherein the first bottom electrode and the second bottom electrode are formed of a first conductive material using the same formation method, wherein the first ferroelectric layer and the second ferroelectric layer are formed of a ferroelectric material using the same formation method, and wherein the first top electrode and the second top electrode are formed of a second conductive material using the same formation method.

[0097] Example 20 is the method of Example 19, further comprising: forming a first conductive feature over and in contact with an upper surface of the second bottom electrode remote from the substrate; and forming a second conductive feature under and in contact with a lower surface of the second bottom electrode facing the substrate.

Claims

1. A semiconductor device, comprising: A substrate; A first dielectric layer, located above the substrate; A memory cell, located above the substrate in a first region of the semiconductor device, wherein the memory cell includes a first ferroelectric structure in the first dielectric layer, wherein the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer therebetween; and A tunable capacitor, located above the substrate in a second region of the semiconductor device, wherein the tunable capacitor includes a second ferroelectric structure, wherein the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer therebetween, wherein at least a portion of the second ferroelectric structure is located in the first dielectric layer, Wherein the first top electrode and the first bottom electrode have the same size, and wherein the second top electrode is smaller than the second bottom electrode, Wherein the semiconductor device further includes: A first conductive feature and a second conductive feature, located above the substrate in the first region of the semiconductor device, wherein the first conductive feature is located above and in contact with the first top electrode, and the second conductive feature is located below and in contact with the first bottom electrode; A third conductive feature, a fourth conductive feature, and a fifth conductive feature, located above the substrate in the second region of the semiconductor device, wherein the third conductive feature is located above and in contact with the second top electrode, the fourth conductive feature is located above and in contact with the upper surface of the second bottom electrode away from the substrate, and the fifth conductive feature is located below and in contact with the lower surface of the second bottom electrode facing the substrate.

2. The semiconductor device according to claim 1, wherein, The first region is a memory device region including a memory device, and the second region is an RF circuit region including a radio frequency (RF) circuit.

3. The semiconductor device according to claim 1, wherein, The first ferroelectric structure is configured as part of a memory device, and the second ferroelectric structure is configured as part of an RF circuit.

4. The semiconductor device according to claim 1, wherein, The third conductive feature is configured to be coupled to a voltage source during an initialization state of the tunable capacitor, wherein the third conductive feature is configured to be coupled to an RF circuit during a normal operating state of the tunable capacitor.

5. The semiconductor device according to claim 4, wherein, The fourth conductive feature is configured to be coupled to a modulation voltage source for finely tuning the capacitance of the tunable capacitor during the normal operating state.

6. The semiconductor device according to claim 5, wherein, The modulation voltage provided by the modulation voltage source is configured to vary during the normal operating state.

7. The semiconductor device according to claim 1, wherein, The first top electrode and the second top electrode have upper surfaces coplanar with the first dielectric layer, and the first bottom electrode and the second bottom electrode have lower surfaces coplanar with the first dielectric layer.

8. The semiconductor device according to claim 1, wherein, The second bottom electrode has: a first portion, extending along the upper surface of the first dielectric layer away from the substrate; A second portion extending from the upper surface of the first dielectric layer to the lower surface of the first dielectric layer facing the substrate; And a third portion located at the lower surface of the first dielectric layer, connecting the second portion and extending parallel to the lower surface of the first dielectric layer.

9. The semiconductor device according to claim 8, wherein, The second ferroelectric layer extends conformally along the upper surface of the second bottom electrode, wherein the second top electrode has: a first portion extending into the first dielectric layer and surrounded by the second ferroelectric layer; and a second portion above the first portion and covering the upper surface of the second ferroelectric layer.

10. A semiconductor device, comprising: A substrate; A memory device located above a first region of the substrate, wherein the memory device includes a first ferroelectric structure including a first top electrode, a first ferroelectric film, and a first bottom electrode; and A radio frequency (RF) device located above a second region of the substrate, wherein the RF device includes a tunable capacitor having a second ferroelectric structure, and the second ferroelectric structure includes a second top electrode, a second ferroelectric film, and a second bottom electrode, Wherein the first top electrode and the first bottom electrode have the same size, and the second top electrode is smaller than the second bottom electrode, Wherein the semiconductor device further includes: A first conductive feature and a second conductive feature located above the first region of the substrate, wherein the first conductive feature is located above and in contact with the first top electrode, and the second conductive feature is located below and in contact with the first bottom electrode; A third conductive feature, a fourth conductive feature, and a fifth conductive feature located above the second region of the substrate, wherein the third conductive feature is located above and in contact with the second top electrode, the fourth conductive feature is located above and in contact with the upper surface of the second bottom electrode away from the substrate, and the fifth conductive feature is located below and in contact with the lower surface of the second bottom electrode facing the substrate.

11. The semiconductor device according to claim 10, wherein, The first ferroelectric structure is disposed in a first dielectric layer above the substrate, and the second ferroelectric structure is at least partially disposed in the first dielectric layer.

12. The semiconductor device according to claim 11, wherein, The lower surface of the first bottom electrode facing the substrate is flush with the lower surface of the second bottom electrode facing the substrate.

13. The semiconductor device according to claim 12, wherein, The upper surface of the first top electrode facing away from the substrate is flush with the upper surface of the second top electrode facing away from the substrate.

14. The semiconductor device according to claim 12, wherein, The upper surface of the first top electrode facing away from the substrate is flush with the upper surface of the first dielectric layer facing away from the substrate, and the upper surface of the second top electrode facing away from the substrate extends further from the substrate than the upper surface of the first dielectric layer.

15. A method of forming a semiconductor device, the method comprising: Forming a first dielectric layer above a substrate, the first dielectric layer extending from a first device region of the semiconductor device to a second device region of the semiconductor device; Form memory cells of a memory device over the substrate in the first device region, wherein forming the memory cells includes forming a first ferroelectric structure in the first dielectric layer, and wherein forming the first ferroelectric structure includes sequentially forming a first bottom electrode, a first ferroelectric layer, and a first top electrode over the substrate; and Form a tunable capacitor of a radio frequency (RF) circuit over the substrate in the second device region, wherein forming the tunable capacitor includes forming a second ferroelectric structure in the first dielectric layer, and wherein forming the second ferroelectric structure includes sequentially forming a second bottom electrode, a second ferroelectric layer, and a second top electrode over the substrate, wherein the first top electrode and the first bottom electrode have the same size, and wherein the second top electrode is smaller than the second bottom electrode, wherein the method further includes: Forming a first conductive feature over and in contact with an upper surface of the second bottom electrode remote from the substrate; and Forming a second conductive feature under and in contact with a lower surface of the second bottom electrode facing the substrate.

16. The method according to claim 15, wherein, The first ferroelectric structure and the second ferroelectric structure are formed in the same processing step.

17. The method according to claim 16, wherein The first bottom electrode and the second bottom electrode are formed of a first conductive material using the same forming method, wherein the first ferroelectric layer and the second ferroelectric layer are formed of a ferroelectric material using the same forming method, and wherein the first top electrode and the second top electrode are formed of a second conductive material using the same forming method.

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