Memory structure, memory device and method for forming the same

Abstract

The present disclosure is directed to an SRAM bit cell with reduced coupling capacitance. In the vertical direction, the word line "WL" and the bit line "BL" of the SRAM cell are stacked away from each other to reduce the coupling capacitance between WL and BL. In one embodiment, WL is vertically spaced apart from BL by one or more metallization levels, and neither WL nor BL is formed by one or more metallization levels. A connecting island structure or a jumper structure is provided to connect the upper one of WL or BL to the transistor of the SRAM cell. Embodiments of the present application also relate to a memory structure, a memory device, and a method of forming a memory device.

Description

Technical Field

[0001] The present application relates to a memory structure, a memory device and a method for forming the same. Background Art

[0002] Static random access memory ("SRAM") arrays provide storage without the need for refresh cycles. SRAM arrays typically require more silicon area than dynamic random access memory ("DRAM") because each bit cell is typically a latch formed by six transistors (6T) or more. However, as long as sufficient power supply voltage is present, the SRAM cell will retain data. In addition, SRAM is advantageous because the access time is faster than DRAM, which makes SRAM cells particularly attractive for use as temporary registers or working data storage devices, such as cache memory for processors. System-on-a-chip ("SOC") designs typically include one or more processing "cores." These processor cores are designed for various data processing purposes, and each processor core is typically configured with a level 1 cache memory of SRAM cells that are arranged close to or adjacent to the corresponding processor core. Such specialized SRAM cells enable very fast processor operation.

[0003] To meet the needs of portable electronic devices and high-speed computing, it is desirable to integrate more data storage cells including cross-coupled inverters into a single SRAM chip and reduce its power consumption. For example, fin field effect transistors ("FinFETs") are used to implement SRAMs with smaller size and lower power consumption. Summary of the invention

[0004] According to one aspect of the present application, a memory structure is provided, comprising: a substrate; a first transistor of a memory cell, formed above the substrate, the first transistor comprising a first terminal and a second terminal; a first metallization level, located above the first transistor, the first metallization level comprising a first metal line structure and a metal island structure separated from the first metal line structure, the first metal line structure being oriented along a first lateral direction length and connected to the first terminal of the first transistor, the metal island structure being connected to the second terminal of the first transistor; a second metallization level, located above the first metallization level, the second metallization level comprising a first metal jumper structure, the first metal jumper structure being connected to the metal island structure and being positioned non-overlapping with the first metal line structure; and a third metallization level, located above the second metallization level, the third metallization level comprising a second metal line structure, the second metal line structure being oriented along a second lateral direction length different from the first lateral direction, the second metal line structure being connected to the first metal jumper structure.

[0005] According to another aspect of the present application, a memory device is also provided, including: a substrate; a transfer gate transistor located above the substrate, the transfer gate transistor including a first terminal and a second terminal; a first signal line positioned in a first metallization level above the transfer gate transistor, the first signal line connected to the first terminal of the transfer gate transistor; a metal island structure positioned in the first metallization level, the metal island structure being laterally separated from the first signal line; a second signal line positioned in the second metallization level; a third metallization level vertically positioned between the first metallization level and the second metallization level; and a first metal jumper structure positioned in the third metallization level, the first metal jumper structure being connected to both the second signal line and the metal island structure.

[0006] According to another aspect of the present application, a method for forming a memory device is also provided, comprising: forming a first metallization level above a wafer, the wafer comprising a first transistor of a memory cell located above a substrate, the first transistor comprising a first terminal and a second terminal, the first metallization level comprising a first metal line structure and a metal island structure laterally separated from the first metal line structure, the first metal line structure being oriented along a first lateral direction length and connected to the first terminal of the first transistor, the metal island structure being connected to the second terminal of the first transistor; forming a second metallization level above the first metallization level, the second metallization level comprising a first metal jumper structure, the first metal jumper structure being connected to the metal island structure and being positioned non-overlapping with the first metal line structure; and forming a third metallization level above the second metallization level, the third metallization level comprising a second metal line structure, the second metal line structure being oriented along a second lateral direction length different from the first lateral direction, the second metal line structure being connected to the first metal jumper structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 is a circuit diagram of an example SRAM cell according to an example embodiment of the present disclosure;

[0009] Figure 2 yes Figure 1 An example layout diagram of an example SRAM cell;

[0010] FIG. 3A to FIG. 3C The BEOL metallization structure is shown in Figure 1-Figure 2 An example of signal lines of an SRAM cell;

[0011] FIG. 4A to FIG. 4B The BEOL metallization structure is shown in Figure 1-Figure 2 Alternative embodiments of signal lines of example SRAM cells;

[0012] Figure 5 is a circuit diagram of another example SRAM cell according to an example embodiment of the present disclosure;

[0013] Figure 6 is a flow chart of an example process according to an example embodiment of the present disclosure; and

[0014] Figure 7-Figure 11 is based on Figure 6 An example process view of a wafer at various stages of fabrication. DETAILED DESCRIPTION

[0015] The following content of the present invention provides many different embodiments or examples for implementing different features of different embodiments. The specific examples of components and configurations are described below to simplify the present invention. Of course, this is only an example and is not intended to limit the present invention. In addition, the implementation of the first process before the second process in the specification may include an embodiment in which the second process is directly implemented after the first process, and also includes an embodiment in which an additional process can be implemented between the first and second processes. For the purpose of simplicity and clarity, each component can be drawn in different proportions at will. Moreover, the first component formed on or on the second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not itself specify the relationship between the various embodiments and / or structures described.

[0016] For ease of description, spatial relative position terms such as "below," "beneath," "below," "above," "on," and the like may be used herein to describe the relationship between one element or component and another (or other) elements or components as shown in the drawings. It should be understood that these spatial relative position terms are intended to include different orientations of the device in use or operation, in addition to the orientations described in the figures. For example, if the device in the drawings is flipped, elements described as being "below" or "below" other elements or components will be oriented as being "above" the other elements or components. Therefore, the exemplary term "below" may include both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and therefore the spatial relative position descriptors used herein are interpreted in the same way.

[0017] A hybrid transistor type SRAM bit cell with reduced coupling capacitance is provided. In the vertical direction, the word line "WL" and the bit line "BL" of the SRAM cell are stacked away from each other to reduce the coupling capacitance between WL and BL. In one embodiment, one of BL or WL (e.g., WL) is vertically spaced apart from the other of BL or WL (e.g., BL) using one or more metallization levels, and neither WL or BL is formed by the one or more metallization levels. That is, the metallization level of WL (referred to as "WL metal layer" for the purpose of description) and the metallization level of BL (referred to as "BL metal layer" for the purpose of description) are vertically spaced apart by at least one additional metal layer between each other. In one embodiment, one or more metal island structures (referred to as "jumper structure") are formed in the additional metallization level and connected to the one of WL or BL located above. Each jumper structure does not overlap with the one of WL or BL located below, so that the coupling capacitance between the jumper structure and the one of WL or BL located below is minimized (if any). The distance between WL and BL is greatly increased, so that the coupling capacitance between WL and BL is greatly reduced. To this extent, the width of WL can be increased to reduce resistance. The size of the jumper structure is optimally configured to maintain a certain balance between minimizing coupling capacitance and minimizing resistance in the connection path between WL and the gate of the transistor connected to WL.

[0018] Figure 1 is an example SRAM bit cell 100 in a six-transistor ("6T") arrangement. Figure 1 In the embodiment, a pair of MOS transmission gates PG1 and PG2 are respectively coupled to one of a pair of data lines called "bit lines" BL1, BL2 to invert the associated storage nodes SN1 and SN2, respectively. In one embodiment, the transmission gate transistors PG1 and PG2 are formed by NMOS transistors. Depending on the technology node, the first voltage node V dd A voltage ranging from about 0.6 V to about 3.0 V is provided. Pull-up transistors PU1, PU2 are each formed of a PMOS transistor and are coupled between a first power supply node Vdd and one of storage nodes SN1, SN2 depending on the state of the SRAM cell 100.

[0019] The second voltage V ss can provide a voltage higher than the first voltage node V dd Depending on the state of the SRAM cell 100, the two pull-down transistors PD1, PD2 are both formed by NMOS transistors and are coupled to the second voltage node V ss and one of the storage nodes SN1 and SN2. The 6T SRAM bit cell 100 is a latch. ddThe latch will retain its data state indefinitely, which is sufficient for the correct operation of the circuit. The two CMOS inverters formed by PU1, PD1 and PU2, PD2 are "cross-coupled" and serve to continuously enhance the stored charge on the storage nodes SN1, SN2. Figure 1 As shown, the two storage nodes SN1 and SN2 are inverted with each other. When SN1 is at a high voltage level (eg, logic "1"), SN2 is at a low voltage level (eg, logic "0"), and vice versa.

[0020] When the SRAM bit cell 100 is written, complementary write data signals are placed on the bit line pair BL1 and BL2. A positive control signal on the word line WL is coupled to the gates of the pass gates PG1, PG2. The transistors PU1, PD1 and PU2, PD2 are sized in such a way that the data on the bit lines BL1, BL2 can overwrite the stored data and thus write or program the SRAM bit cell 100.

[0021] When reading from the SRAM bit cell 100, a positive voltage is placed on the word line WL, and the pass gates PG1 and PG2 allow the bit lines BL1 and BL2 to be coupled to receive data from the storage nodes SN1 and SN2, respectively. Unlike dynamic memory cells, if the power supply voltage V dd If maintained at a high enough level, the SRAM bit cell 100 does not lose its storage state during a read operation.

[0022] Figure 2 is an example bit cell layout of a single port of the 6T bit cell 100 in the XY plane. Figure 2 , the dashed area depicts the gate structure. The gate structure is located above the semiconductor region / structure 210. Transistors PG-1, PG-2, PU-1, PU-2, PD-1 and PD-2 are labeled at their respective gate structures. Cell 100 has a pitch in the Y direction labeled as Y1-pitch and a pitch in the X direction labeled as X1-pitch. For illustrative purposes, example contacts are shown as "X" and are labeled with appropriate signals. Word line WL contacts are formed to the gates of the PG-1, PG-2 transistors. Bit line contacts are formed to the source / drain terminals of the PG-1, PG-2 transistors. Power supply V dd 、V ss Contacts are formed to the source / drain terminals of the PU-1, PU-2, PD-1, PD-2 transistors. Storage node contacts are formed to the storage nodes SN1 and SN2, respectively. The pull-up transistors PU-1, PU-2 are different types of transistors than the pull-down transistors PD-1, PD-2. In an example embodiment, as Figure 2As shown, the pull-up transistors PU-1, PU-2 are formed in a doped region, such as an N-type well 220, and the pull-down transistors are formed in a P-type substrate 230. Other example embodiments, such as a dual well configuration, are possible and within the scope of the present disclosure.

[0023] In one embodiment, the semiconductor structure 210 is a fin-shaped semiconductor structure, and the gate structures each wrap around a corresponding fin-shaped semiconductor structure 210 .

[0024] FIG. 3A to FIG. 3C The structure 300 includes an exemplary bit cell 100 and metal lines of a word line WL and bit lines BL1, BL2, a first power supply voltage V dd and the second power supply V ss . Figure 3A It is a layout diagram in the XY plane. Figure 3B is a cross-sectional view of the metallization levels of structure 300 taken along cut line BB. Figure 3C is a cross-sectional view of the metallization levels of structure 300 taken along cut line CC.

[0025] like FIG. 3A to FIG. 3C As shown, bit lines BL1, BL2 are metal lines formed as part of a lower level metallization (referred to as "M0" for descriptive purposes) within a lower inter-level dielectric "ILD" layer ILD0. The BL1, BL2 metal lines may be longitudinal in the XY plane and oriented along the y-axis direction.

[0026] The word lines WL are metal lines formed as part of the upper level metallization M3 within the upper level ILD (ILD3). The WL metal lines may be longitudinal and oriented along an x-axis direction orthogonal to the y-axis direction.

[0027] There is at least one interlayer dielectric layer (shown as two ILD1, ILD2) vertically placed between ILD0 and ILD3. For description purposes, ILD0 is also referred to as the BL level, and for description purposes, ILD3 is also referred to as the WL level. For description purposes, ILD2, ILD1 vertically placed between the BL level ILD0 and the WL level ILD3 are also referred to as "jumping wire ILD". In some embodiments, a jumper wire ILD layer is added to increase the distance between the word line WL and the bit lines BL1, BL2. The number "0" is used as an example to indicate the lower level of the ILD and the lower level of metallization relative to ILD3 or metallization level M3. That is, ILD0 is two layers lower than ILD3. "ILD0" does not necessarily indicate that the ILD is the first ILD layer formed in the BEOL process, or that the ILD is any specific ILD layer formed in the BEOL process. Similarly, “M0” does not necessarily indicate that the metallization level is the first metallization level formed in the BEOL process, or that the metallization level is any particular metallization level formed in the BEOL process.

[0028] The gates of transistors PG-1 and PG-2 ( Figure 3B 1 and 2 (not shown) are connected to WL by a series of interconnect components (referred to as "interconnect components") 310-1, 310-2, respectively. Interconnect component 310-1 includes one or more jumper structures 322, shown as 322(1), 322(2) formed in jumper ILD layers ILD1, ILD2, respectively. Interconnect component 310-2 includes one or more jumper structures 320, shown as jumper structures 320(1), 320(2) formed in jumper ILD layers ILD1, ILD2, respectively. In one embodiment, each of the jumper structures 320, 322 does not overlap vertically with the adjacent bit lines BL1, BL2. Specifically, for example, the jumper structures 320(1), 320(2) are separated from BL2 on the x-axis by gap spaces 324(1), 324(2), respectively. The gap spaces 324(1), 324(2) ensure that coupling capacitance, if any, between the jumper structures 320(1), 320(2) to the bit line BL2 is minimized or reduced.

[0029] Thus, in one embodiment, the size of each jumper structure 320, 322 in the x-axis direction is minimized depending on the minimum area rule defined by the process design. For example, the minimum area rule stipulates that the x-axis size of the jumper structure 320, 322 is large enough to ensure contact or connection with the corresponding connecting via. In one embodiment, the x-axis size of the jumper structure 320, 322 can be designed based on the vertical distance between the jumper structure 320, 322 and the adjacent bit lines BL1, BL2. Specifically, the jumper structure 320, 322 located vertically away from the bit lines BL1, BL2 can include a larger x-axis size than the jumper structure 320, 322 located vertically close to the bit lines BL1, BL2. For example, the jumper structure 320(2) formed as part of the M2 metallization in the ILD2 layer can include a larger x-axis size than the jumper structure 320(1) formed as part of the M1 metallization in the ILD1 layer because the jumper structure 320(2) is vertically away from the adjacent bit line BL2. The longer distance may at least somewhat compensate for the increased x-axis dimension of jumper structure 320(2) compared to jumper structure 320(1).

[0030] In one embodiment, the size of each jumper structure 320, 322 in the y-axis direction is minimized depending on the minimum area rule defined by the process design. For example, the minimum area rule stipulates that the y-axis size of the jumper structure 320, 322 is large enough to ensure contact or connection with the corresponding connecting via. In one embodiment, the y-axis size of the jumper structure 320, 322 can be designed based on the vertical distance between the jumper structure 320, 322 and the adjacent bit lines BL1, BL2. Specifically, the jumper structure 320, 322 located vertically away from the bit lines BL1, BL2 can include a larger y-axis size than the jumper structure 320, 322 located vertically close to the bit lines BL1, BL2. For example, the jumper structure 320(2) formed as part of the M2 metallization in the ILD2 layer can include a larger y-axis size than the jumper structure 320(1) formed as part of the M1 metallization in the ILD1 layer because the jumper structure 320(2) is vertically away from the adjacent bit line BL2. The longer distance may compensate, at least to some extent, for the increased y-axis dimension of jumper structure 320(2) compared to jumper structure 320(1).

[0031] In an example embodiment, the bit lines BL1, BL2 are longitudinal and oriented along the y-axis direction. That is, the increase in the y-axis dimension will not affect whether the jumper line structures 320, 322 overlap vertically with the adjacent bit lines BL1, BL2. Thus, in some embodiments, the y-axis dimension of the jumper line structures 320, 322 can be designed more flexibly than its x-axis dimension.

[0032] It should be noted that the surface area of ​​the jumper structures 320, 322 may not be rectangular, and may include a circle, an ellipse, another polygonal shape, or an irregular shape. The above description of the x-axis size and / or y-axis size of the jumper structures 320, 322 may also be similarly applied to such non-rectangular shapes.

[0033] In addition, the description herein about the size of the x-axis or y-axis of the jumper structures 320, 322 may be similarly applied to the size of the surface area of ​​the jumper structures 320, 322. For example, the size of the surface area of ​​the jumper structures 320, 322 in the XY plane may be designed based on the vertical distance between the jumper structures 320, 322 and the adjacent bit lines BL1, BL2. The jumper structures 320, 322 located away from the bit lines BL1, BL2 may include a larger surface area than the jumper structures 320, 322 located close to the bit lines BL1, BL2. For example, the jumper structure 320(2) may include a larger surface area than the jumper structure 320(1) because the jumper structure 320(2) is located vertically away from the adjacent bit line BL2.

[0034] The WL is connected to the connection island structure 330 through the jumper structures 320, 322 and the through-hole structure 340 (here, 340(1), 340(2), 340(3) formed in the dielectric layers ILD1, ILD2, ILD3, respectively), and the connection island structure 330 is part of the M0 metallization in the ILD0 layer. The description about the size and / or surface area of ​​the jumper structures 320, 322 also applies similarly to the through-hole structure 340. FIG. 3A to FIG. 3C The jumper structure is shown to be larger in x-axis and y-axis dimensions than the adjacent connecting via structure, which does not limit the scope of the present disclosure. In some embodiments, the connecting via 340 can include one or more of a larger x-axis dimension, a larger y-axis dimension, or a larger XY plane surface area than the adjacent jumper structures 320, 322.

[0035] Figure 4A and Figure 4B is an alternative embodiment. Figure 4A is an XY plane graph. Figure 4B As shown, the width W2 of WL is greater than Figure 3C The width W1 of WL is reduced by reducing the coupling capacitance between word line WL and bit lines BL1 and BL2. Figure 4BThe larger width W2 of the example. The XY plane surface area of ​​the jumper structure 420(2), 420(1) and the island structure 430 increases in the upward direction of the z-axis. Specifically, the XY plane surface area of ​​the jumper structure 420(2) is greater than the XY plane surface area of ​​the jumper structure 420(1). The XY plane surface area of ​​the jumper structure 420(1) is greater than the XY plane surface area of ​​the island structure 430. In one embodiment, the surface area ratio between the island structure 430, the jumper structure 420(1) and the jumper structure 420(2) is approximately between 1:1.1:1.15 and approximately 1:1.3:1.4. In one embodiment, the jumper structures 420(1), 420(2) include substantially the same size on the x-axis to avoid overlapping with the adjacent bit line BL2, while the jumper structure 420(2) includes a larger size on the y-axis than the jumper structure 420(1). That is, the surface area ratio between the island structure 430, the jumper structure 420(1), and the jumper structure 420(2), or the surface area ratio among the three is mainly attributed to the variation of their y-axis dimensions.

[0036] In one embodiment, Figure 4A The jumper structures 420, 422 do not vertically overlap the adjacent bit lines BL2, BL1, respectively. Following minimum area design rules, such as via closure rules and minimum area rules for jumper structures, the surface area of ​​the jumper structure 420(1) located in the ILD1 directly above the M1 metallization of the bit lines BL1, BL2 is designed to have a minimum XY plane surface area.

[0037] Similar to the surface area, the x-axis or y-axis dimensions of the island structure 430, the jumper structure 420(1) and the jumper structure 420(2) can also increase in the upward direction of the z-axis. Specifically, the x-axis dimension of the jumper structure 420(2) is larger than the x-axis dimension of the jumper structure 420(1). The x-axis dimension of the jumper structure 420(1) is larger than the x-axis dimension of the island structure 430. Specifically, the y-axis dimension of the jumper structure 420(2) is larger than the y-axis dimension of the jumper structure 420(1). The y-axis dimension of the jumper structure 420(1) is larger than the y-axis dimension of the island structure 430.

[0038] The metallization levels M0, M1, M2, M3 may be one or more of copper, gold, silver, aluminum, cobalt, tungsten or other suitable conductive materials. The ILD layers ILD0, ILD1, ILD2, ILD3 are silicon oxide, silicon nitride, low-k dielectric materials, or other suitable dielectric materials.

[0039] The word line WL is vertically spaced apart from the bit lines BL1 and BL2 by at least one jumper ILD layer, and WL or BL1 and BL2 are not formed in the jumper ILD layer. In this way, the coupling capacitance between WL and BL1 and BL2 is reduced. The width or surface area of ​​the word line WL can be increased to reduce the signal line resistance. The surface area of ​​the jumper structure can be balanced between reducing the coupling capacitance between the jumper structure and the adjacent bit lines and reducing the interconnect line resistance. The jumper structure positioned vertically close to the adjacent bit lines can include the smallest size and surface area, while the jumper structure positioned vertically away from the adjacent bit lines can include a larger size and / or surface area. In this way, the coupling capacitance and the signal line resistance can be optimized in a balanced manner. The signal transmission delay time can be greatly reduced.

[0040] In the description herein, for simplicity, the dielectric layer surrounding each metallization level M1, M2, M3 and the dielectric layer surrounding the corresponding interconnect structures 340(1), 340(2), 340(3) formed directly below the corresponding metallization level M1, M2, M3 are described as one ILD layer. Specifically, for example, ILD1 surrounds the M1 level including the jumper structure 320(1) and the via structure 340(1); ILD2 surrounds the M2 level including the jumper structure 320(2) and the via structure 340(2); ILD3 surrounds the M3 level including the word line WL and the via structure 340(3). It should be understood that, depending on the specific process for forming the via structures 340(1), 340(2), 340(3), the dielectric layer surrounding the via structures 340(1), 340(2), 340(3) may be separate from the dielectric layer surrounding the metallization levels M1, M2, M3, which are formed directly above the respective via structures 340(1), 340(2), 340(3). That is, each of ILD1, ILD2, ILD3 described herein may include two or more dielectric layers.

[0041] In the right Figure 1-4B In the description of , 6T SRAM cell is used as an example for illustration. The disclosed technology is not limited to 6TSRAM and may include other SRAM cell designs and / or other types of memory cells. For example, Figure 5 This is an example of 8T SRAM design. Figure 5, the 8T SRAM cell 500 includes a first pull-up transistor PU1 and a first pull-down transistor PD1 forming a first inverter INV1, and a second pull-up transistor PU2 and a second pull-down transistor PD2 forming a second inverter INV2. The first inverter INV1 and the second inverter INV2 are cross-coupled to each other and coupled to write bit lines WBL, WBLB through first and second pass gate transistors PG1 and PG2, and the write bit lines WBL, WBLB are respectively configured to write data to be stored by the cross-coupled first and second inverters INV1 and INV2. The read pull-down transistor RPD and the read pass gate transistor RPG form a read port RP to access the data stored by the cross-coupled first and second inverters INV1 and INV2.

[0042] Specifically, drains of the first pull-up transistor PU1, the first pull-down transistor PD1 and the first pass-gate transistor PG1 are electrically connected at the first data storage node ND11. Drains of the second pull-up transistor PU2, the second pull-down transistor PD2 and the second pass-gate transistor PG2 are electrically connected at the second data storage node ND12.

[0043] The gate electrodes of the second pull-up transistor PU2 and the second pull-down transistor PD2 are electrically connected to the drain electrodes of the first pull-down transistor PD1, the first pass-gate transistor PG1, and the first pull-down transistor through the first data storage node ND11. The gate electrodes of the first pull-up transistor PU1 and the first pull-down transistor PD1 are electrically connected to the drain electrodes of the second pull-down transistor PD2, the second pass-gate transistor PG2, and the second pull-up transistor PU2 through the second data storage node ND12.

[0044] The source electrodes of the first and second pull-down transistors PD1 and PD2 are connected to the first power supply node V ss , while the source electrodes of the first and second pull-up transistors PU1 and PU2 are connected to the second power supply node V dd According to one embodiment, the first power supply node V ss is electrically connected to ground, and the second power supply node V dd Electrically connected to a positive potential supplied from a power supply circuit (not shown) of the SRAM.

[0045] The gate electrodes of the first and second pass-gate transistors PG1 and PG2 are connected to the write word line WWL. The source electrodes of the first and second pass-gate transistors PG1 and PG2 are connected to the first and second write bit lines WBL and WBLB, respectively.

[0046] The read pass gate transistor RPG and the read pull-down transistor RPD are connected in series between the read bit line RBL and the first power supply node V ssThe read pull-down transistor RPD has a gate electrode electrically connected to the second data storage node ND12. The gate electrode of the read pass gate transistor RPG is connected to a read word line RWL configured to control the reading of data stored by the cross-coupled first inverter INV1 and the second inverter INV2 by the conduction state of the read pull-down transistor RPD to the read bit line RBL.

[0047] The word line WL and the pair of bit lines BL1, BL2 are vertically separated by at least one jumper ILD layer other than the ILD layer ILD3 of the word line or the ILD layer ILD0 of the pair of bit lines. Figure 3B and Figure 3C The first and second write bit lines WBL, WBLB are formed on a metallization level M0, which is separated from the metallization level M3 by two metallization levels M1, M2. The read word line RWL is also formed in a metallization level at least two levels away from the metallization level of the read bit line RBL. That is, at least one additional metallization level is vertically positioned between the metallization level of RWL and the metallization level of RBL.

[0048] Figure 6 is an example process in which is manufactured. Figure 7-Figure 11 Shown in Figure 6 Wafer 700 at various stages of fabrication under an example process.

[0049] Reference Figure 6 , while referring to Figure 7 In example operation 610, a wafer 700 is received. The wafer 700 includes a substrate 702 and a FEOL layer 704 formed over the substrate 702. In some embodiments, the FEOL layer 704 includes transistors of a SRAM cell, such as Figure 1 6T SRAM cell or Figure 5 In one embodiment, the wafer 700 has completed the front-end device manufacturing process of forming transistors on the substrate 702 .

[0050] Wafer 700 may also have completed a mid-end process that forms a pre-metal dielectric layer ("PMD") and contact structures (e.g., vias) that directly contact transistor terminals (e.g., gate and source / drain structures of FET transistors).

[0051] In example operation 620, while referring to Figure 8, forming a lower level metallization 820 above wafer 700. Lower level metallization 820 may include a bit line structure 822 and a connection island structure 824. The bit line structure 822 and the island 824 may be connected to respective interconnect structures (e.g., vias, omitted for simplicity) to connect to the respective terminals of the transistors in IC block 704. For example, the bit line structure 822 is ultimately connected to the source / drain terminal of the transistor, and the island 824 is ultimately connected to the gate of the same transistor. Lower level metallization 820 may be a first metallization level formed above the metal pre-dielectric layer "PMD", or may be any metallization level above the first metallization level. The metallization level 820 is formed in a dielectric layer 826.

[0052] In example operation 630, while referring to Fig. 9 , a first intermediate metallization level 930 is formed above the dielectric layer 826 and the metallization level 820. The metallization level 930 includes a jumper structure 932. The jumper structure 932 is connected to the island structure 824 through an interconnection structure 934. The jumper structure 932 and the interconnection structure 934 are formed in the dielectric layer 936. Neither the jumper structure 932 nor the interconnection structure 934 overlaps the bit line structure 822 in the vertical direction (here, the z-axis direction). The dielectric layer 936 can be formed by a thin film process, for example, a CVD or PVD process or other suitable thin film process. The metallization level 930 can be blanket-formed on the wafer surface and then patterned to obtain the jumper structure 932. The jumper structure 932 can also be formed using other metal deposition and patterning processes such as a damascene process or a lift-off process. The interconnection structure 934 is a metal structure formed using a damascene process or a lift-off process.

[0053] In example operation 640, while referring to Fig.10 , a second intermediate metallization level 1040 is formed above the dielectric layer 936 and the metallization level 930. The metallization level 1040 includes a jumper structure 1042. The jumper structure 1042 is connected to the jumper structure 932 through an interconnect structure 1044. The jumper structure 1042 and the interconnect structure 1044 are formed in the dielectric layer 1046. Neither the jumper structure 1042 nor the interconnect structure 1044 overlaps the bit line structure 822 in the vertical direction (here, the z-axis direction).

[0054] In example operation 650, while referring to Fig.11, an upper metallization level 1150 is formed above the dielectric layer 1046 and the metallization level 1040. The metallization level 1150 includes a word line structure 1152. The word line structure 1152 is connected to the jumper structure 1042 through an interconnect structure 1154. The word line structure 1152 and the interconnect structure 1154 are formed in the dielectric layer 1156. The interconnect structure 1154 does not overlap with the bit line structure 822 in the vertical direction (here, the z-axis direction). Through the jumper structure 1042, 932 and the island 824, the word line structure 1152 is ultimately connected to the gate of the transistor. Although the word line structure 1152 overlaps with the bit line structure 822, the word line structure 1152 is vertically spaced apart from the bit line structure 822 by at least one metallization level, and neither the word line structure 1152 nor the bit line structure 822 is formed by the at least one metallization level. The increased vertical distance between the word line structure 1152 and the bit line structure 822 reduces the coupling capacitance between the word line structure 1152 and the bit line structure 822 when electrical signals are provided to both the word line structure 1152 and the bit line structure 822 .

[0055] In some embodiments, the method 600 can be used to manufacture the SRAM cell 100, 500, or other SRAM cells. Fig.11 The word line structure 1152 can be configured as FIG. 3A to FIG. 3C The jumper structures 932 and 1042 can be configured as FIG. 3A to FIG. 3C The island structure 824 can be configured as FIG. 3A to FIG. 3C The bit line structure 822 can be configured as FIG. 3A to FIG. 3C The second bit line BL2.

[0056] In the description herein, for the purpose of describing an example SRAM memory cell, a FET transistor is used as an illustrative example, for example, Figure 1 6T SRAM cells and Figure 5 It should be noted that other types of transistors (eg, bipolar transistors) may also be used to form SRAM cells, which are all included in the present disclosure.

[0057] In the description herein, certain specific details are set forth to provide a thorough understanding of various embodiments of the present disclosure. However, those skilled in the art will appreciate that the present disclosure may be practiced without these specific details. In other cases, known structures associated with electronic components and manufacturing techniques are not described in detail to avoid unnecessary descriptions that would make the embodiments of the present disclosure unclear.

[0058] Unless the context requires otherwise, in this specification and claims, the word "comprise" and variations such as "include" and "comprising" are to be interpreted in an open, inclusive sense, ie, "including, but not limited to."

[0059] The use of ordinal numbers such as first, second, and third does not necessarily imply a sense of ordered hierarchy, but only serves to distinguish between multiple instances of behavior or structure.

[0060] Throughout this specification, references to "one embodiment" or "an embodiment" mean that a particular component, structure, or feature described in connection with that embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification do not necessarily all refer to the same embodiment. Furthermore, particular components, structures, or features may be combined in any suitable manner in one or more embodiments.

[0061] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its sense including "and / or" unless the context clearly dictates otherwise.

[0062] The finFET or gate-all-around (GAA) structure may be patterned by any suitable method. For example, the structure may be patterned using one or more lithography processes including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines lithography and self-aligned process phases, allowing for the creation of patterns having, for example, a pitch that is smaller than that obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the finFET or GAA structure.

[0063] The present disclosure can be further understood through the description of the following embodiments:

[0064] In a structural embodiment, the structure includes a substrate and a first transistor of a memory cell formed above the substrate. The first transistor includes a first terminal and a second terminal. A first metallization level is formed above the first transistor. The first metallization level includes a first metal line structure and a metal island structure separated from the first metal line structure. The first metal line structure is oriented in length along a first lateral direction and is connected to the first terminal of the first transistor. The metal island structure is connected to the second terminal of the first transistor. A second metallization level is formed above the first metallization level. The second metallization level includes a first metal jumper structure. The first metal jumper structure is connected to the metal island structure and is positioned without overlapping with the first metal line structure. A third metallization level is formed above the second metallization level. The third metallization level includes a second metal line structure. The second metal line structure is oriented in length along a second lateral direction different from the first lateral direction. The second metal line structure is connected to the first metal jumper structure.

[0065] In the above memory structure, the second lateral direction is orthogonal to the first lateral direction.

[0066] In the above memory structure, the first metal jumper structure is connected to the metal island structure at least through a first interconnect structure directly below the first metal jumper structure.

[0067] In the above memory structure, the first interconnect structure does not overlap with the first metal line structure.

[0068] In the above-mentioned memory structure, it also includes a fourth metallization level positioned vertically between the second metallization level and the third metallization level, and the fourth metallization level includes a second metal jumper structure connected to the first metal jumper structure, and the second metal jumper structure includes a larger surface area in a lateral plane than the first metal jumper structure.

[0069] In the above memory structure, the second metal jumper structure includes a larger dimension in the first lateral direction than the first metal jumper structure while including the same dimension in the second lateral direction as the first metal jumper structure.

[0070] In the above memory structure, the second metal jumper structure is connected to the first metal jumper structure at least through a second interconnect structure located directly below the second metal jumper structure.

[0071] In the above memory structure, the second interconnect structure includes a larger surface area in a lateral plane than the first interconnect structure.

[0072] In the above memory structure, the first interconnect structure and the second interconnect structure do not overlap with the first metal line structure respectively.

[0073] In the above memory structure, the first metal jumper structure comprises a larger surface area in a lateral plane than the metal island structure.

[0074] In another embodiment, a memory device includes a substrate and a pass-gate transistor located above the substrate. The pass-gate transistor includes a first terminal and a second terminal. A first signal line is located in a first metallization level above the pass-gate transistor. The first signal line is connected to the first terminal of the pass-gate transistor. A metal island structure is located in the first metallization level. The metal island structure is laterally separated from the first signal line. A second signal line is located in the second metallization level. A third metallization level is vertically located between the first metallization level and the second metallization level. A first metal jumper structure is located in the third metallization level. The first metal jumper structure is connected to both the second signal line and the metal island structure.

[0075] In the above memory device, the first metal jumper structure does not overlap with the first signal line.

[0076] In the above memory device, the first metal jumper structure includes a larger surface area in a lateral plane than the metal island structure.

[0077] In the above memory device, the first metal jumper structure is connected to the metal island structure through a first interconnect structure, and the first interconnect structure does not overlap with the first signal line.

[0078] In the above memory device, the first signal line is long along a first lateral direction, and wherein the size of the first metal jumper structure in a second lateral direction orthogonal to the first lateral direction is minimized subject to a threshold determined based on the size of the first interconnect structure.

[0079] In the above memory device, the first signal line is long along the first lateral direction, and wherein a size of the first metal jumper structure in the first lateral direction is larger than a size of the metal island structure in the first lateral direction.

[0080] In a method embodiment, a method includes forming a first metallization level above a wafer. The wafer includes a first transistor of a memory cell located above a substrate. The first transistor includes a first terminal and a second terminal. The first metallization level includes a first metal line structure and a metal island structure laterally separated from the first metal line structure. The first metal line structure is oriented along a first lateral direction length and is connected to the first terminal of the first transistor. The metal island structure is connected to the second terminal of the first transistor. A second metallization level is formed above the first metallization level. The second metallization level includes a first metal jumper structure. The first metal jumper structure is connected to the metal island structure and is positioned non-overlapping with the first metal line structure. A third metallization level is formed above the second metallization level. The third metallization level includes a second metal line structure. The second metal line structure is oriented along a second lateral direction length different from the first lateral direction. The second metal line structure is connected to the first metal jumper structure.

[0081] In the above method, a first metal jumper structure is formed to be connected to the metal island structure at least through a first interconnect structure directly below the first metal jumper structure.

[0082] In the above method, the first interconnect structure is positioned without overlapping the first metal line structure.

[0083] In the above method, it also includes forming a fourth metallization level after forming the second metallization level and before forming the third metallization level, the fourth metallization level including a second metal jumper structure connected to the first metal jumper structure, and the second metal jumper structure includes a larger surface area in a lateral plane than the first metal jumper structure.

[0084] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that this equivalent construction does not deviate from the spirit and scope of the present invention, and that they can make multiple changes, substitutions and changes herein without departing from the spirit and scope of the present invention.

Claims

1. A memory structure comprising: substrate; A first transistor of a memory cell is formed above the substrate, the first transistor comprising a first terminal and a second terminal; a first metallization level located above the first transistor, the first metallization level comprising a first metal line structure and a metal island structure separated from the first metal line structure, the first metal line structure being oriented lengthwise in a first lateral direction and connected to the first terminal of the first transistor, the metal island structure being connected to the second terminal of the first transistor; a second metallization level located above the first metallization level, the second metallization level comprising a first metal jumper structure connected to the metal island structure and positioned non-overlapping with the first metal line structure, wherein the first metal line structure is a bit line; as well as a third metallization level located above the second metallization level, the third metallization level comprising a second metal line structure oriented lengthwise along a second lateral direction different from the first lateral direction, the second metal line structure connected to the first metal jumper structure; The memory structure further includes a second metal jumper structure connected to the first metal jumper structure, The second metal jumper structure is positioned non-overlappingly with the first metal line structure, the second metal jumper structure is vertically farther away from the first metal line structure than the first metal jumper structure, and the second metal jumper structure includes a larger dimension than the first metal jumper structure in a second lateral direction orthogonal to the first lateral direction.

2. The memory structure according to claim 1, wherein: A surface area ratio between the metal island structure and the first metal jumper structure is between 1:1.1 and 1:1.

3.

3. The memory structure according to claim 1, wherein: The first metal jumper structure is connected to the metal island structure through at least a first interconnect structure directly below the first metal jumper structure.

4. The memory structure according to claim 3, wherein: The first interconnect structure does not overlap the first metal line structure.

5. The memory structure of claim 3 , further comprising a fourth metallization level positioned vertically between the second metallization level and the third metallization level, the fourth metallization level comprising the second metal jumper structure connected to the first metal jumper structure, the second metal jumper structure comprising a larger surface area in a lateral plane than the first metal jumper structure.

6. The memory structure according to claim 5, wherein: The second metal jumper structure comprises a larger dimension in the first lateral direction than the first metal jumper structure.

7. The memory structure according to claim 5, wherein: The second metal jumper structure is connected to the first metal jumper structure through at least a second interconnect structure located directly below the second metal jumper structure.

8. The memory structure according to claim 7, wherein: The second interconnect structure comprises a larger surface area in the lateral plane than the first interconnect structure.

9. The memory structure according to claim 8, wherein: The first interconnect structure and the second interconnect structure do not overlap with the first metal line structure, respectively.

10. The memory structure according to claim 1, wherein: The first metal jumper structure comprises a larger surface area in a lateral plane than the metal island structure.

11. A memory device comprising: substrate; a transfer gate transistor located above the substrate, the transfer gate transistor comprising a first terminal and a second terminal; a first signal line positioned in a first metallization level above the pass-gate transistor, the first signal line connected to the first terminal of the pass-gate transistor, the first signal line oriented lengthwise along a first lateral direction; a metal island structure located in the first metallization level, the metal island structure being laterally separated from the first signal line; a second signal line positioned in a second metallization level; a third metallization level vertically positioned between the first metallization level and the second metallization level; as well as a first metal jumper structure located in the third metallization level, the first metal jumper structure connected to both the second signal line and the metal island structure; The first metal jumper structure does not overlap with the first signal line, and the memory device further includes a second metal jumper structure connected to the first metal jumper structure. The second metal jumper structure does not overlap with the first signal line, the second metal jumper structure is vertically farther away from the first signal line structure than the first metal jumper structure, and the second metal jumper structure includes a larger dimension in a second lateral direction orthogonal to the first lateral direction than the first metal jumper structure.

12. The memory device according to claim 11, wherein: The surface area of ​​the first metal jumper structure has a non-rectangular shape.

13. The memory device according to claim 11, wherein: The first metal jumper structure comprises a larger surface area in a lateral plane than the metal island structure.

14. The memory device according to claim 11, wherein: The first metal jumper structure is connected to the metal island structure through a first interconnect structure, and the first interconnect structure does not overlap with the first signal line.

15. The memory device according to claim 14, wherein: The first signal line is long along a first lateral direction, and wherein a dimension of the first metal jumper structure in a second lateral direction orthogonal to the first lateral direction is minimized subject to a threshold determined based on a dimension of the first interconnect structure.

16. The memory device according to claim 14, wherein: The first signal line is long along a first lateral direction, and wherein a dimension of the first metal jumper structure in the first lateral direction is greater than a dimension of the metal island structure in the first lateral direction.

17. A method of forming a memory device, comprising: forming a first metallization level over a wafer, the wafer comprising a first transistor of a memory cell located over a substrate, the first transistor comprising a first terminal and a second terminal, the first metallization level comprising a first metal line structure and a metal island structure laterally separated from the first metal line structure, the first metal line structure being oriented lengthwise along a first lateral direction and connected to the first terminal of the first transistor, the metal island structure being connected to the second terminal of the first transistor; forming a second metallization level over the first metallization level, the second metallization level comprising a first metal jumper structure connected to the metal island structure and positioned non-overlapping with the first metal line structure, wherein the first metal line structure is a bit line; and forming a third metallization level over the second metallization level, the third metallization level comprising a second metal line structure oriented lengthwise along a second lateral direction orthogonal to the first lateral direction, the second metal line structure connected to the first metal jumper structure; A fourth metallization level is formed after forming the second metallization level and before forming the third metallization level, the fourth metallization level comprising a second metal jumper structure connected to the first metal jumper structure, wherein the second metal jumper structure is positioned non-overlapping with the first metal line structure, the second metal jumper structure is vertically farther away from the first metal line structure than the first metal jumper structure, and the second metal jumper structure comprises a larger dimension in the second lateral direction than the first metal jumper structure.

18. The method according to claim 17, wherein: The first metal jumper structure is formed to be connected to the metal island structure through at least a first interconnect structure directly below the first metal jumper structure.

19. The method according to claim 18, wherein: The first interconnect structure is positioned non-overlapping with the first metal line structure.

20. The method according to claim 17, wherein: The second metal jumper structure comprises a larger surface area in a transverse plane than the first metal jumper structure.

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