Three-dimensional semiconductor memory devices

Abstract

A three-dimensional semiconductor memory device includes: a peripheral circuit structure on a first substrate; a second substrate on the peripheral circuit structure; an electrode structure on the second substrate, the electrode structure including stacked electrodes; and a vertical channel structure penetrating the electrode structure. The peripheral circuit structure includes a pseudo-interconnect structure beneath the second substrate. The pseudo-interconnect structure includes stacked pseudo-interconnect lines and pseudo-vias connecting the top surface of the uppermost pseudo-interconnect line to the bottom surface of the second substrate.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0005384, filed on January 15, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The exemplary embodiments of the present invention relate to a semiconductor device, and more specifically, to a three-dimensional (3D) semiconductor memory device with improved electrical properties. Background Technology

[0004] Semiconductor devices have been increasingly integrated to provide improved performance and / or lower manufacturing costs. The integration density of semiconductor devices directly impacts their cost, leading to a demand for more highly integrated devices. The integration density of typical two-dimensional (2D) or planar semiconductor devices is primarily determined by the area occupied by a unit memory cell. Therefore, the integration density of typical 2D semiconductor devices is influenced by the technology used to form finer patterns. However, the integration density of 2D semiconductor devices continues to increase, but remains limited, due to the need for more expensive equipment to form finer patterns. Therefore, three-dimensional (3D) semiconductor memory devices have been developed to overcome these limitations. 3D semiconductor memory devices can include memory cells arranged in three dimensions. Summary of the Invention

[0005] Exemplary embodiments of the present invention can provide a three-dimensional (3D) semiconductor memory device with improved electrical properties.

[0006] On one hand, a 3D semiconductor memory device may include: a peripheral circuit structure on a first substrate; a second substrate on the peripheral circuit structure; an electrode structure on the second substrate, the electrode structure including stacked electrodes; and a vertical channel structure penetrating the electrode structure. The peripheral circuit structure may include a pseudo-interconnect structure beneath the second substrate. The pseudo-interconnect structure may include: stacked pseudo-interconnect lines; and pseudo-vias connecting the top surface of the uppermost pseudo-interconnect line to the bottom surface of the second substrate.

[0007] On one hand, a 3D semiconductor memory device may include: a peripheral circuit structure on a first substrate; a second substrate on the peripheral circuit structure; an electrode structure on the second substrate, the electrode structure including stacked electrodes; and a vertical channel structure penetrating the electrode structure. The peripheral circuit structure may include a pseudo-interconnect structure beneath the second substrate. The pseudo-interconnect structure may include stacked interconnect layers. The uppermost interconnect layer may include a first pseudo-interconnect and a second pseudo-interconnect. The first and second pseudo-interconnects are electrically connected to the second substrate. The first and second pseudo-interconnects may be spaced apart from each other by an interlayer insulating layer between them.

[0008] On one hand, a 3D semiconductor memory device may include: a peripheral circuit structure on a first substrate, the peripheral circuit structure including peripheral transistors on the first substrate, interconnect structures on the peripheral transistors, and pseudo-interconnect structures adjacent to the interconnect structures; a second substrate on the peripheral circuit structure; an electrode structure on the second substrate, the electrode structure including stacked electrodes; a plurality of vertical channel structures penetrating the electrode structures and electrically connected to the second substrate; a plurality of conductive pads respectively located on the plurality of vertical channel structures; an interlayer insulating layer covering the electrode structures; a plurality of bit lines located on the interlayer insulating layer and electrically connected to the plurality of conductive pads respectively; and through contacts penetrating the interlayer insulating layer to connect to the interconnect structures. Each of the plurality of vertical channel structures may include: a filling insulating pattern having a columnar shape; a vertical semiconductor pattern covering the outer surface of the filling insulating pattern; and a data storage layer located between the vertical semiconductor pattern and the plurality of electrodes. The pseudo-interconnect structure may include: a first interconnect layer and a second interconnect layer on the first interconnect layer, the second interconnect layer being between the first interconnect layer and a second substrate; a first pseudo-via connecting the first interconnect layer vertically to the second interconnect layer; and a second pseudo-via connecting the second interconnect layer vertically to the second substrate.

[0009] On one hand, a 3D semiconductor memory device may include: a peripheral circuit structure on a first substrate; a second substrate on the peripheral circuit structure, the second substrate having a first inner sidewall and a second inner sidewall facing each other in a first direction; a dicing hole extending through the second substrate in the first direction between the first inner sidewall and the second inner sidewall, the dicing hole defining an inner sidewall of the second substrate; a first conductive spacer on the inner sidewall; an electrode structure on the second substrate, the electrode structure including stacked electrodes; and a vertical channel structure through the electrode structure. Attached Figure Description

[0010] The concept of the invention will become clearer with reference to the accompanying drawings and detailed description.

[0011] Figure 1 This is a schematic perspective view illustrating some example embodiments of a three-dimensional (3D) semiconductor memory device according to the present invention.

[0012] Figure 2 This is a schematic plan view illustrating some example embodiments of a 3D semiconductor memory device according to the present invention.

[0013] Figure 3 This is a plan view illustrating some example embodiments of a 3D semiconductor memory device according to a concept of the present invention.

[0014] Figure 4A and Figure 4B They are along Figure 3 The sectional view taken from lines I-I' and II-II'.

[0015] Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A It is along Figure 3 The cross-sectional view taken along line I-I' illustrates a method for manufacturing a 3D semiconductor memory device according to some exemplary embodiments of the invention.

[0016] Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B and Figure 11B It is along Figure 3 The cross-sectional view taken along line II-II' illustrates a method for manufacturing a 3D semiconductor memory device according to some exemplary embodiments of the invention.

[0017] Figure 12 It is along Figure 3 The cross-sectional view taken along line I-I' illustrates a 3D semiconductor memory device according to some exemplary embodiments of the concept of the present invention.

[0018] Figure 13 and Figure 14 yes Figure 12 An enlarged cross-sectional view of section 'M'.

[0019] Figure 15 , Figure 16 and Figure 17 It is along Figure 3 The cross-sectional view taken along line II-II' illustrates a 3D semiconductor memory device according to some exemplary embodiments of the concept of the present invention.

[0020] Figure 18 This is a plan view illustrating some example embodiments of a 3D semiconductor memory device according to a concept of the present invention.

[0021] Figure 19 It is along Figure 18 A sectional view taken from line I-I'.

[0022] Figure 20 It is along Figure 18 The cross-sectional view taken along line I-I' illustrates a 3D semiconductor memory device according to some exemplary embodiments of the concept of the present invention.

[0023] Figure 21 This is a plan view illustrating some example embodiments of a 3D semiconductor memory device according to a concept of the present invention.

[0024] Figure 22 It is along Figure 3 The cross-sectional view taken along line II-II' illustrates a 3D semiconductor memory device according to some exemplary embodiments of the concept of the present invention.

[0025] Figure 23 It is along Figure 3 The cross-sectional view taken along line I-I' illustrates a 3D semiconductor memory device according to some exemplary embodiments of the concept of the present invention.

[0026] Figure 24 It is along Figure 3 The cross-sectional view taken along line I-I' illustrates a method for manufacturing a 3D semiconductor memory device according to some exemplary embodiments of the invention. Detailed Implementation

[0027] Figure 1 This is a schematic perspective view illustrating some example embodiments of a three-dimensional (3D) semiconductor memory device according to the present invention.

[0028] Reference Figure 1 A 3D semiconductor memory device according to some exemplary embodiments of the present invention may include a peripheral circuit structure PS, a cell array structure CS on the peripheral circuit structure PS, and / or a through-contact (not shown) perpendicularly connecting the cell array structure CS to the peripheral circuit structure PS. When viewed in a plan view, the cell array structure CS may overlap with the peripheral circuit structure PS.

[0029] In some example embodiments, the peripheral circuit structure PS may include peripheral logic circuitry, including row and column decoders, page buffers, and / or control circuitry. The peripheral logic circuitry constituting the peripheral circuit structure PS may be integrated on a semiconductor substrate.

[0030] A cell array structure CS may include a cell array comprising a plurality of memory cells arranged in three dimensions. For example, a cell array structure CS may include a plurality of memory blocks BLK0 to BLKn. Each of the memory blocks BLK0 to BLKn may include memory cells arranged in three dimensions.

[0031] Figure 2 This is a schematic plan view illustrating some example embodiments of a 3D semiconductor memory device according to the present invention.

[0032] Reference Figure 1 and Figure 2 , refer to Figure 1 The described peripheral circuit structure PS and cell array structure CS can be disposed on the first substrate SUB.

[0033] In each of the chip regions 10, constitutes Figure 1 The peripheral circuit structure of the PS, including the row decoder ROWDEC, column decoder COLDEC, page buffer PBR, and control circuit, can be set on the first substrate SUB.

[0034] constitute Figure 1 Multiple pads MT of the cell array structure CS can be disposed on a first substrate SUB. The pads MT can be arranged in a first direction D1 and a second direction D2. Each of the pads MT may include the above-mentioned references. Figure 1 The memory blocks BLK0 to BLKn are described.

[0035] The pad MT can be connected to the external circuit structure PS (see...) Figure 1 Overlapping. According to some exemplary embodiments of the present invention, the peripheral circuit structure PS (see...) is constructed... Figure 1 The peripheral logic circuits can be freely placed under the pad MT.

[0036] Figure 3 This is a plan view illustrating some example embodiments of a 3D semiconductor memory device according to a concept of the present invention. Figure 4A and Figure 4B They are along Figure 3 The sectional view taken from lines I-I' and II-II'. Figure 3 The pad MT of a 3D semiconductor memory device, as shown in some example embodiments of the concept according to the present invention, is illustrated. Figure 2 )one.

[0037] Reference Figure 3 , Figure 4A and Figure 4BThe peripheral circuit structure PS, including the peripheral transistor PTR, can be disposed on the first substrate SUB. The cell array structure CS, including the electrode structure ST, can be disposed on the peripheral circuit structure PS. The first substrate SUB may include a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a single-crystal silicon substrate. The first substrate SUB may include an active region defined by a device isolation layer DIL.

[0038] The peripheral circuit structure PS may include a plurality of peripheral transistors PTR disposed on the active region of the first substrate SUB. The peripheral transistors PTR may constitute the aforementioned peripheral logic circuit including row decoders and column decoders, page buffers and / or control circuitry.

[0039] The peripheral circuit structure PS may include an interconnect structure IS disposed on the peripheral transistor PTR. The interconnect structure IS may include multiple interconnect layers stacked on the first substrate SUB. For example, the interconnect layers may include: a first interconnect layer including a first interconnect line INL1; a second interconnect layer including a second interconnect line INL2; and a third interconnect layer including a third interconnect line INL3. A peripheral contact PCNT may be disposed between the first interconnect line INL1 and the peripheral transistor PTR to electrically connect the first interconnect line INL1 to the peripheral transistor PTR.

[0040] For example, the first interconnect INL1 may extend parallel to each other in the second direction D2. The second interconnect INL2 may extend parallel to each other in the first direction D1, which intersects the second direction D2. The third interconnect INL3 may extend parallel to each other in the second direction D2. The first interconnect INL1 may be arranged with a first spacing in the first direction D1. The second interconnect INL2 may be arranged with a second spacing in the second direction D2. The third interconnect INL3 may be arranged with a third spacing in the first direction D1. The first to third spacings may be the same or different from each other. The widths of the first interconnect INL1, the second interconnect INL2, and the third interconnect INL3 may be the same or different from each other.

[0041] The interconnect structure IS may further include a first via VI1 disposed between the first interconnect line INL1 and the second interconnect line INL2, and a second via VI2 disposed between the second interconnect line INL2 and the third interconnect line INL3. The first interconnect line to the third interconnect line INL1, INL2 and INL3 can be vertically connected to each other through the first via VI1 and the second via VI2.

[0042] The peripheral circuit structure PS may also include a pseudo-interconnect structure DIS. The pseudo-interconnect structure DIS may include portions of the first to third interconnect layers described above in the interconnect structure IS. The pseudo-interconnect structure DIS may include a first pseudo-interconnect INLd1 disposed in the first interconnect layer, a second pseudo-interconnect INLd2 disposed in the second interconnect layer, and a third pseudo-interconnect INLd3 disposed in the third interconnect layer. The detailed description of the first to third pseudo-interconnects INLd1, INLd2, and INLd3 may be the same as or substantially the same as described above for the first to third interconnects INL1, INL2, and INL3. However, unlike the first interconnect INL1 described above, the first pseudo-interconnect INLd1 may not be connected to the peripheral transistor PTR. In other words, the pseudo-interconnect structure DIS may not be connected to the peripheral transistor PTR and may be a pseudo-structure that does not perform a specific circuit function.

[0043] The pseudo-interconnect structure DIS may also include a first pseudo-via VId1 disposed between the first pseudo-interconnect INLd1 and the second pseudo-interconnect INLd2, a second pseudo-via VId2 disposed between the second pseudo-interconnect INLd2 and the third pseudo-interconnect INLd3, and a third pseudo-via VId3 disposed between the third pseudo-interconnect INLd3 and the lower semiconductor layer LSL, which will be described later.

[0044] The first pseudo-interconnect to the third pseudo-interconnect, INLd1, INLd2, and INLd3, can be vertically connected to each other via the first pseudo-via VId1 and the second pseudo-via VId2. The pseudo-interconnect structure DIS can be connected to the lower semiconductor layer LSL via at least one third pseudo-via VId3. For example, the third pseudo-via VId3 can connect the top surface of the third pseudo-interconnect INLd3 to the bottom surface of the lower semiconductor layer LSL.

[0045] When viewed in a planar view, multiple pseudo-interconnect structures (DIS) can be arranged below the second substrate (SL). These multiple pseudo-interconnect structures (DIS) can be distributed substantially uniformly below the second substrate (SL). The pseudo-interconnect structures (DIS) can be used to ensure uniform pattern density during the formation of interconnect structures (IS). When the pattern density is uniform, process failures during photolithography can be reduced or minimized.

[0046] The interconnect structure IS and the pseudo-interconnect structure DIS can be formed simultaneously using the same process. Each of the interconnect structure IS and the pseudo-interconnect structure DIS may include a metal such as tungsten, copper, or aluminum. Since the pseudo-interconnect structure DIS is electrically connected to the underlying semiconductor layer LSL through at least one third pseudo-via VId3, the second substrate SL can achieve the effect of metal attachment on its bottom, for example, the drag reduction effect described later.

[0047] The peripheral circuit structure PS may also include a first interlayer insulating layer ILD1 covering the peripheral transistor PTR, the interconnect structure IS, and the pseudo-interconnect structure DIS. The first interlayer insulating layer ILD1 may include stacked insulating layers. For example, the first interlayer insulating layer ILD1 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a low-k dielectric layer. The first interlayer insulating layer ILD1 may be disposed between third pseudo-interconnects INLd3, so that adjacent third pseudo-interconnects INLd3 can be separated from each other by the first interlayer insulating layer ILD1 (see...). Figure 4B The first interlayer insulating layer ILD1 can be disposed between the third pseudo-vias VId3, so adjacent third pseudo-vias VId3 can be separated from each other through the first interlayer insulating layer ILD1 (see...). Figure 4B ).

[0048] The cell array structure CS can be disposed on the first interlayer insulating layer ILD1 of the peripheral circuit structure PS. The cell array structure CS will be described in more detail below. A second interlayer insulating layer ILD2 and a second substrate SL can be disposed on the first interlayer insulating layer ILD1. The second substrate SL can be disposed within the second interlayer insulating layer ILD2. For example, the second substrate SL can have a rectangular plate shape forming the lower part of the pad MT. The second substrate SL can support the electrode structure ST disposed thereon.

[0049] The second substrate SL may comprise a lower semiconductor layer LSL, a source semiconductor layer SSL, and / or an upper semiconductor layer USL, stacked sequentially. Each of the lower semiconductor layer LSL, the source semiconductor layer SSL, and / or the upper semiconductor layer USL may comprise a semiconductor material (e.g., silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or any combination thereof). Each of the lower semiconductor layer LSL, the source semiconductor layer SSL, and / or the upper semiconductor layer USL may be single-crystal, amorphous, and / or polycrystalline. For example, each of the lower semiconductor layer LSL, the source semiconductor layer SSL, and the upper semiconductor layer USL may comprise an N-type polycrystalline silicon layer doped with impurities. The dopant concentrations of the lower semiconductor layer LSL, the source semiconductor layer SSL, and the upper semiconductor layer USL may differ from each other.

[0050] The source semiconductor layer SSL can be positioned between the lower semiconductor layer LSL and the upper semiconductor layer USL. The lower semiconductor layer LSL and the upper semiconductor layer USL can be electrically connected to each other through the source semiconductor layer SSL. For example, when viewed in a plan view, the upper semiconductor layer USL and the source semiconductor layer SSL can overlap with the lower semiconductor layer LSL.

[0051] Reference Figure 3When viewed in a plan view, the lower semiconductor layer LSL may include first sidewalls SW1 to fourth sidewalls SW4. First sidewalls SW1 and second sidewalls SW2 may extend in a first direction D1. First sidewalls SW1 and second sidewalls SW2 may be opposite to each other in a second direction D2. Third sidewalls SW3 and fourth sidewalls SW4 may extend in the second direction D2. Third sidewalls SW3 and fourth sidewalls SW4 may be opposite to each other in the first direction D1.

[0052] The second substrate SL may include a cell array region CAR, a connection region CNR, and / or a source connection region SCR. The cell array region CAR may be disposed in the middle portion of the second substrate SL. A pair of connection regions CNR may be disposed on both sides of the cell array region CAR. The pair of connection regions CNR may extend in a first direction D1. A pair of source connection regions SCR may be disposed adjacent to a first sidewall SW1 and a second sidewall SW2 of the lower semiconductor layer LSL. The pair of source connection regions SCR may extend in the first direction D1.

[0053] Reference Figure 3 and Figure 4B The lower semiconductor layer LSL may have multiple diced holes CHO. Each of the diced holes CHO may have a stripe extending in a second direction D2. The diced holes CHO may be arranged in a first direction D1. Each of the diced holes CHO may pass through the lower semiconductor layer LSL. The bottom surface of the second interlayer insulating layer ILD2, which fills the diced holes CHO, may contact the top surface of the first interlayer insulating layer ILD1. The through-contact region TVR of the cell array structure CS may be defined by the diced holes CHO.

[0054] A first conductive spacer CSP1 may be disposed on the first sidewalls SW1 to SW4 of the lower semiconductor layer LSL. A second conductive spacer CSP2 may be disposed on the inner sidewall ISW of the lower semiconductor layer LSL defined by the dicing hole CHO. The first conductive spacer CSP1 may selectively cover the first sidewalls SW1 to SW4 of the lower semiconductor layer LSL. The second conductive spacer CSP2 may selectively cover the inner sidewall ISW of the lower semiconductor layer LSL. The first conductive spacer CSP1 and the second conductive spacer CSP2 may not cover the bottom surface and the top surface of the lower semiconductor layer LSL. The first conductive spacer CSP1 and the second conductive spacer CSP2 may comprise a metal such as tungsten, copper, or aluminum.

[0055] Refer to Figure 4BThe third insulating layer IL3, the lower sacrificial layer LHL, and the fourth insulating layer IL4 can be sequentially stacked on the through-contact region TVR. The third insulating layer IL3, the lower sacrificial layer LHL, and the fourth insulating layer IL4 can be positioned at the same horizontal level as the source semiconductor layer SSL. For example, the bottom surface of the third insulating layer IL3 can be coplanar with the bottom surface of the source semiconductor layer SSL, and the top surface of the fourth insulating layer IL4 can be coplanar with the top surface of the source semiconductor layer SSL.

[0056] A fifth insulating layer IL5 can be disposed on the through-contact region TVR. The fifth insulating layer IL5 can also be disposed on the fourth insulating layer IL4. The fifth insulating layer IL5 can be disposed at the same horizontal height as the upper semiconductor layer USL. For example, the bottom surface of the fifth insulating layer IL5 can be coplanar with the bottom surface of the upper semiconductor layer USL, and the top surface of the fifth insulating layer IL5 can be coplanar with the top surface of the upper semiconductor layer USL. Figure 4A As shown, the fifth insulating layer IL5 can also be disposed on the second interlayer insulating layer ILD2 of the source connection region SCR. The bottom surface of the fifth insulating layer IL5 of the source connection region SCR can be located at a lower horizontal height than the bottom surface of the upper semiconductor layer USL.

[0057] Reference Figure 3 , Figure 4A and Figure 4B An electrode structure ST can be disposed on a second substrate SL. The electrode structure ST may include electrodes EL stacked on the second substrate SL in a vertical direction (e.g., third direction D3). The electrode structure ST may also include a first insulating layer IL1 that separates the stacked electrodes EL from each other. The first insulating layer IL1 and the electrodes EL of the electrode structure ST may be stacked alternately in the third direction D3.

[0058] The electrode structure ST can extend from the cell array region CAR of the second substrate SL to the connection region CNR of the second substrate SL. The electrode structure ST can have a stepped structure STS on the connection region CNR. The height of the stepped structure STS of the electrode structure ST can decrease from the cell array region CAR toward the source connection region SCR.

[0059] The bottom electrode EL of the ST electrode structure can be the bottom select line. The top electrode EL of the ST electrode structure can be the top select line. All other electrodes EL besides the bottom and top select lines can be word lines.

[0060] Electrode EL may include a conductive material. For example, electrode EL may include at least one of a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), or a transition metal (e.g., titanium or tantalum). For example, each of the first insulating layers IL1 may include a silicon oxide layer.

[0061] The electrode structure ST on the cell array region CAR may further include a second insulating layer IL2. The second insulating layer IL2 may be selectively disposed on the cell array region CAR, but may not be disposed on the connection region CNR. The thickness of the second insulating layer IL2 may be greater than the thickness of the first insulating layer IL1. The second insulating layer IL2 may include the same insulating material as the first insulating layer IL1. For example, the second insulating layer IL2 may include a silicon oxide layer.

[0062] Multiple vertical channel structures VS extending through the electrode structure ST can be disposed on the cell array region CAR. The vertical channel structures VS can be arranged in the second direction D2. Each of the vertical channel structures VS may include a vertical insulating pattern VP, a vertical semiconductor pattern SP, and / or a fill insulating pattern VI. The vertical semiconductor pattern SP can be disposed between the vertical insulating pattern VP and the fill insulating pattern VI. Conductive pads PAD can be disposed on each of the vertical channel structures VS.

[0063] The filling insulating pattern VI can be cylindrical. The vertical semiconductor pattern SP can cover the surface of the filling insulating pattern VI and can extend from the lower semiconductor layer LSL to the conductive pad PAD in the third direction D3. The vertical semiconductor pattern SP can be tubular with an open top. The vertical insulating pattern VP can cover the outer surface of the vertical semiconductor pattern SP and can extend from the lower semiconductor layer LSL to the top surface of the second insulating layer IL2 in the third direction D3. The vertical insulating pattern VP can also be tubular with an open top. The vertical insulating pattern VP can be disposed between the electrode structure ST and the vertical semiconductor pattern SP.

[0064] The vertical insulating pattern VP can be formed from a single layer or multiple layers. In some example embodiments, the vertical insulating pattern VP may include a data storage layer. For example, the vertical insulating pattern VP may be a data storage layer of a NAND flash memory device and may include a tunnel insulating layer, a charge storage layer, and a barrier insulating layer.

[0065] For example, the charge storage layer may include a trapping insulating layer, a floating gate electrode, and / or an insulating layer comprising conductive nanodots. The charge storage layer may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, or a stacked trapping layer. The tunnel insulating layer may include a material with a band gap larger than that of the charge storage layer. For example, the tunnel insulating layer may include at least one of a high-k dielectric layer (e.g., an alumina layer or a hafnium oxide layer) or a silicon oxide layer. The barrier insulating layer may include at least one of a high-k dielectric layer (e.g., an alumina layer or a hafnium oxide layer) or a silicon oxide layer.

[0066] Vertical semiconductor patterns (SPs) may include semiconductor materials such as silicon (Si), germanium (Ge), or combinations thereof. Additionally, vertical semiconductor patterns (SPs) may include semiconductor materials doped with dopants or intrinsically semiconductor materials without dopants. Vertical semiconductor patterns (SPs) comprising semiconductor materials can be used as channels for transistors constituting NAND cell strings.

[0067] The conductive pad (PAD) can cover the top surface of the vertical semiconductor pattern (SP) and the top surface of the insulating pattern (VI). The conductive pad (PAD) can comprise doped semiconductor material and / or conductive material. The bit line contact plug (BPLG) can be electrically connected to the vertical semiconductor pattern (SP) via the conductive pad (PAD).

[0068] The source semiconductor layer SSL can be in direct contact with the lower sidewall of each of the vertical semiconductor patterns SP. The source semiconductor layer SSL can electrically connect multiple vertical semiconductor patterns SP to each other. In other words, the vertical semiconductor patterns SP can be electrically connected together to the second substrate SL. The second substrate SL can be used as a source for memory cells. A common source voltage can be applied to the second substrate SL, as described later.

[0069] Multiple discrete structures SPS can extend through the electrode structure ST. The discrete structures SPS can extend parallel to each other in a second direction D2. For example, each of the electrodes EL in the electrode structure ST can be horizontally divided into multiple electrodes EL by the discrete structures SPS. The multiple electrodes EL divided by the discrete structures SPS can extend parallel to each other in the second direction D2. The discrete structures SPS may include an insulating material such as silicon oxide.

[0070] The 3D semiconductor memory device according to some exemplary embodiments of the present invention can be a 3D NAND flash memory device. The NAND cell string can be integrated on an electrode structure ST on the lower semiconductor layer LSL. In other words, the electrode structure ST and the vertical channel structure VS penetrating the electrode structure ST can constitute memory cells arranged three-dimensionally on a second substrate SL. The electrode EL of the electrode structure ST can be used as the gate electrode of a transistor.

[0071] Reference Figure 4B The electrode structure ST may include a molded structure MO disposed on each of the through-contact regions TVR. When viewed in a plan view, the molded structure MO may extend along the through-contact regions TVR in a second direction D2.

[0072] The molded structure MO may include a sacrificial layer HL stacked on a fifth insulating layer IL5 on a third-direction D3. The molded structure MO may also include a first insulating layer IL1 that separates the stacked sacrificial layers HL from each other. The first insulating layer IL1 and the sacrificial layer HL of the molded structure MO may be stacked alternately on a third-direction D3.

[0073] The sacrificial layer HL can be positioned at the same horizontal height as the electrodes EL of the electrode structure ST. In other words, the sacrificial layer HL of the molded structure MO can be physically connected to the electrodes EL that are adjacent to each other in the first direction D1. The sacrificial layer HL may comprise an insulating material such as silicon nitride or silicon oxynitride. Since the first insulating layer IL1, the second insulating layer IL2, and the sacrificial layer HL are formed of insulating material, the molded structure MO can be an insulator.

[0074] Reference Figure 3 , Figure 4A and Figure 4B The third interlayer insulating layer ILD3 can be disposed on the second substrate SL. The third interlayer insulating layer ILD3 can cover the stepped structure STS of the electrode structure ST. The fourth interlayer insulating layer ILD4 can be disposed on the third interlayer insulating layer ILD3.

[0075] Bit line contact plugs (BPLGs) can penetrate the fourth interlayer insulating layer (ILD4) to connect to conductive pads (PADs). Multiple bit lines (BLs) can be disposed on the fourth interlayer insulating layer (ILD4). The bit lines (BLs) can extend parallel to each other in the first direction (D1). Each of the bit lines (BLs) can be electrically connected to the vertical semiconductor pattern (SP) via the bit line contact plug (BPLG).

[0076] The unit contact plug PLG can penetrate the third interlayer insulating layer ILD3 and the fourth interlayer insulating layer ILD4 to connect to the electrodes EL that constitute the stepped structure STS, respectively. Multiple upper interconnect lines UIL can be disposed on the fourth interlayer insulating layer ILD4. Each of the upper interconnect lines UIL can be electrically connected to the electrode EL via the unit contact plug PLG.

[0077] Reference Figure 4B At least one through-contact TVS can be configured to pass through each of the through-contact regions TVR. The through-contact TVS of the through-contact region TVR can pass through the fourth interlayer insulation layer ILD4, the molded structure MO, the fifth insulation layer IL5, the fourth insulation layer IL4, the lower sacrificial layer LHL, the third insulation layer IL3, and the second interlayer insulation layer ILD2 to electrically connect to the third interconnect line INL3 of the peripheral circuit structure PS. For example, the through-contact TVS of the through-contact region TVR can electrically connect the bit line BL to the peripheral circuit structure PS.

[0078] Reference Figure 3 and Figure 4A Multiple common source contacts (CSCs) can be disposed on the source connection region SCR. The common source contacts (CSCs) can be adjacent to the first sidewall SW1 and the second sidewall SW2 of the lower semiconductor layer LSL. The common source contacts (CSCs) can be arranged in a first direction D1. Each of the common source contacts (CSCs) can penetrate the fourth interlayer insulating layer ILD4 and the third interlayer insulating layer ILD3 to connect to the second substrate SL.

[0079] The through-contact TVS can also be disposed on the source connection region SCR. The through-contact TVS of the source connection region SCR can be adjacent to the common source contact CSC in the second direction D2. The through-contact TVS of the source connection region SCR can penetrate the fourth interlayer insulation layer ILD4, the third interlayer insulation layer ILD3, the fifth insulation layer IL5, and the second interlayer insulation layer ILD2 to electrically connect to the third interconnect line INL3 of the peripheral circuit structure PS.

[0080] The peripheral transistor PTR located below the source connection region SCR can form a common source line driver for supplying the common source voltage. In other words, the through-contact TVS of the source connection region SCR can be directly connected to the common source line driver of the peripheral circuit structure PS.

[0081] The upper interconnect UIL on the source connection region SCR can connect the adjacent common source contact CSC and through-hole contact TVS. As a result, the common source line driver of the peripheral circuit structure PS can be electrically connected to the second substrate SL via the through-hole contact TVS, the upper interconnect UIL, and the common source contact CSC. A common source voltage can be applied to portions of the first sidewall SW1 and the second sidewall SW2 adjacent to the lower semiconductor layer LSL via the common source line driver.

[0082] The vertical channel structure VS, located at the center of the cell array region CAR, can be relatively far from the first sidewall SW1 or the second sidewall SW2 of the underlying semiconductor layer LSL. Because the common source voltage is applied to portions adjacent to the first and second sidewalls SW1 and SW2 of the underlying semiconductor layer LSL, the electrical path through which the common source voltage is transmitted to the vertical channel structure VS at the center of the cell array region CAR can be relatively long. This relatively long electrical path can increase resistance. Due to the increased resistance, the electrical characteristics of the semiconductor memory device can deteriorate.

[0083] However, according to Figure 3In an exemplary embodiment of the inventive concept, a second conductive spacer CSP2 formed of a low-resistance metallic material can be disposed on the inner sidewall ISW of the lower semiconductor layer LSL. Since the second conductive spacer CSP2 extends in the second direction D2 between the first sidewall SW1 and the second sidewall SW2 of the lower semiconductor layer LSL, the resistance of the electrical path can be reduced by the second conductive spacer CSP2.

[0084] A pseudo-interconnect structure DIS formed of a low-resistivity metallic material can be disposed below the lower semiconductor layer LSL. The pseudo-interconnect structure DIS can be distributed substantially uniformly below the second substrate SL, thus reducing the resistance of the second substrate SL.

[0085] As a result, according to the exemplary embodiments of the present invention, the resistance of the second substrate SL can be reduced to decrease noise that may occur when a common source voltage is transmitted. Furthermore, the common source voltage can be uniformly applied to the vertical channel structure VS connected to the second substrate SL. Therefore, the electrical characteristics of the 3D semiconductor memory device according to the exemplary embodiments of the present invention can be improved.

[0086] Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A It is along Figure 3 The cross-sectional view taken along line I-I' illustrates a method for manufacturing a 3D semiconductor memory device according to some exemplary embodiments of the invention. Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B and Figure 11B It is along Figure 3 The cross-sectional view taken along line II-II' illustrates a method for manufacturing a 3D semiconductor memory device according to some exemplary embodiments of the invention.

[0087] Reference Figure 3 , Figure 5A and Figure 5B The peripheral circuit structure PS can be formed on the first substrate SUB. The formation of the peripheral circuit structure PS may include: forming a peripheral transistor PTR on the first substrate SUB; forming an interconnect structure IS on the peripheral transistor PTR; and forming a pseudo-interconnect structure DIS on the peripheral transistor PTR. The pseudo-interconnect structure DIS may further include a third pseudo-via VId3 formed on a third pseudo-interconnect line INLd3.

[0088] For example, the formation of a peripheral transistor (PTR) may include: forming a device isolation layer (DIL) in a first substrate (SUB) to define an active region; forming a gate insulating layer and a gate electrode on the active region; and implanting a dopant into the active region to form a source / drain region.

[0089] A first interlayer insulating layer (ILD1) can be formed covering the peripheral transistor PTR, the interconnect structure IS, and / or the pseudo-interconnect structure DIS. A lower semiconductor layer (LSL) can be formed on the first interlayer insulating layer ILD1. The lower semiconductor layer LSL may include a semiconductor material such as polysilicon.

[0090] Reference Figure 3 , Figure 6A and Figure 6B The lower semiconductor layer (LSL) can be patterned to form a plurality of diced vias (CHOs) extending through the LSL. The diced vias (CHOs) can extend in a second direction D2. The diced vias (CHOs) can be arranged in a first direction D1. The area exposed through the diced vias (CHOs) can be defined as a through-contact region (TVR). The patterning process can also include patterning the lower semiconductor layer (LSL) in the form of a rectangular plate.

[0091] First conductive spacer CSP1 and second conductive spacer CSP2 may be formed on the lower semiconductor layer LSL. First conductive spacer CSP1 may be formed on the first sidewall SW1 to the fourth sidewall SW4 of the lower semiconductor layer LSL. Second conductive spacer CSP2 may be formed in each of the diced vias CHO of the lower semiconductor layer LSL. Second conductive spacer CSP2 may cover the inner sidewall ISW of the lower semiconductor layer LSL. For example, the formation of first conductive spacer CSP1 and second conductive spacer CSP2 may include: conformally forming a conductive layer on the lower semiconductor layer LSL; and anisotropically etching the conductive layer until the top surface of the lower semiconductor layer LSL is exposed. The conductive layer may include a metal such as tungsten, copper, or aluminum.

[0092] Reference Figure 3 , Figure 7A and Figure 7B A second interlayer insulating layer ILD2 can be formed on the lower semiconductor layer LSL to fill the diced via CHO, and the second interlayer insulating layer ILD2 can be planarized to expose the lower semiconductor layer LSL. A third insulating layer IL3, a lower sacrificial layer LHL, and / or a fourth insulating layer IL4 can be formed sequentially stacked on the lower semiconductor layer LSL. When viewed in a planar view, the lower sacrificial layer LHL can be formed to overlap with the lower semiconductor layer LSL. For example, each of the third insulating layer IL3 and the fourth insulating layer IL4 may include a silicon oxide layer, and the lower sacrificial layer LHL may include a silicon nitride layer or a silicon oxynitride layer.

[0093] An upper semiconductor layer USL can be formed on the fourth insulating layer IL4. The upper semiconductor layer USL can be formed to overlap with the lower semiconductor layer LSL. The upper semiconductor layer USL can be patterned to expose the through-hole contact region (TVR). A fifth insulating layer IL5 can be formed to fill the patterned area of ​​the upper semiconductor layer USL that exposes the TVR. Alternatively, the fifth insulating layer IL5 can also be formed on the second interlayer insulating layer ILD2 of the source connection region SCR. The fifth insulating layer IL5 may include an insulating material such as a silicon oxide layer.

[0094] A molded structure MO can be formed on the upper semiconductor layer USL. For example, a first insulating layer IL1 and a sacrificial layer HL can be alternately stacked on the upper semiconductor layer USL to form the molded structure MO. A second insulating layer IL2 can be formed on the topmost layer of the molded structure MO.

[0095] A first insulating layer IL1, a sacrificial layer HL, and / or a second insulating layer IL2 can be deposited using thermochemical vapor deposition (thermal CVD), plasma-enhanced CVD, physical CVD, and / or atomic layer deposition (ALD). For example, each of the first insulating layers IL1 may include a silicon oxide layer, and each of the sacrificial layers HL may include a silicon nitride layer or a silicon oxynitride layer.

[0096] A stepped structure STS can be formed at the molded structure MO on the connection region CNR. For example, a loop process can be performed on the molded structure MO to form the stepped structure STS on the connection region CNR. The formation of the stepped structure STS may include: forming a mask pattern (not shown) on the molded structure MO; and repeatedly performing a loop using the mask pattern. The loop may include: a process of using the mask pattern as an etching mask to etch a portion of the molded structure MO; and a trimming process of reducing the size of the mask pattern.

[0097] A third interlayer insulating layer ILD3 can be formed on the molded structure MO. The formation of the third interlayer insulating layer ILD3 may include: forming a thick insulating layer covering the molded structure MO; and performing a planarization process on the thick insulating layer until the second insulating layer IL2 is exposed.

[0098] Reference Figure 3 , Figure 8A and Figure 8B A channel via CH penetrating the molded structure MO can be formed on the cell array region CAR. The channel via CH can expose the lower semiconductor layer LSL. The bottom surface of each of the channel via CHs can be located at a horizontal height between the bottom and top surfaces of the lower semiconductor layer LSL. For example, the formation of the channel via CH may include: forming a mask pattern (not shown) on the molded structure MO having openings defining the channel via CHs; and anisotropically etching the molded structure MO using the mask pattern as an etching mask.

[0099] When viewed in a planar view, the channel holes (CH) can be arranged in a line or zigzag pattern in one direction. The anisotropic etching process used to form the channel holes (CH) can be plasma etching, reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE), or ion beam etching (IBE).

[0100] The vertical channel structure VS can be formed separately in the channel hole CH. The formation of the vertical channel structure VS may include: sequentially forming a vertical insulating layer, a vertical semiconductor layer, and a filling insulating layer on the inner surface of the channel hole CH; and performing a planarization process until the top surface of the second insulating layer IL2 is exposed. The vertical insulating layer and the vertical semiconductor layer can be formed conformally.

[0101] More specifically, a vertical insulating pattern VP can be formed covering the inner surface of the channel via CH. The vertical insulating pattern VP can have a tubular shape with an open top. The vertical insulating pattern VP can include a data storage layer. A vertical semiconductor pattern SP can be formed covering the inner surface of the vertical insulating pattern VP. The vertical semiconductor pattern SP can have a tubular shape with an open top. A fill insulating pattern VI can be formed filling the interior of the tubular shape of the vertical semiconductor pattern SP. The vertical insulating pattern VP, the vertical semiconductor pattern SP, and / or the fill insulating pattern VI can constitute a vertical channel structure VS. Conductive pads PAD can be formed on each of the vertical channel structure VS.

[0102] Reference Figure 3 , Figure 9A and Figure 9B A fourth interlayer insulating layer ILD4 can be formed on the molded structure MO and the third interlayer insulating layer ILD3. The fourth interlayer insulating layer ILD4 and the molded structure MO can be patterned to form a trench TR that penetrates the fourth interlayer insulating layer ILD4 and the molded structure MO. The trench TR can extend parallel to each other in the second direction D2.

[0103] The trench TR exposes the lower semiconductor layer LSL. The trench TR exposes the sidewalls of the sacrificial layer HL. The trench TR exposes the sidewalls of the third insulating layer IL3, the sidewalls of the lower sacrificial layer LHL, and the sidewalls of the fourth insulating layer IL4.

[0104] Reference Figure 3 , Figure 10A and Figure 10BThe lower sacrificial layer LHL exposed by the trench TR can be replaced by the source semiconductor layer SSL. Specifically, the lower sacrificial layer LHL exposed through the trench TR can be selectively removed. Removing the lower sacrificial layer LHL can expose the lower portion of the vertical insulating pattern VP of each of the vertical channel structures VS. In this case, the lower sacrificial layer LHL on the through-contact area TVR does not need to be removed.

[0105] The exposed lower portion of the vertical insulating pattern VP can be selectively removed. Therefore, the lower portion of the vertical semiconductor pattern SP can be exposed. During the removal of the lower portion of the vertical insulating pattern VP, the third insulating layer IL3 and the fourth insulating layer IL4 can be removed together.

[0106] The source semiconductor layer SSL can be formed in the space created by removing the third insulating layer IL3, the lower sacrificial layer LHL, and the fourth insulating layer IL4. The source semiconductor layer SSL can be in direct contact with the exposed lower portion of the vertical semiconductor pattern SP. The source semiconductor layer SSL can be in direct contact with the lower semiconductor layer LSL below it. The source semiconductor layer SSL can be in direct contact with the upper semiconductor layer USL above it. The lower semiconductor layer LSL, the source semiconductor layer SSL, and the upper semiconductor layer USL can constitute a second substrate SL.

[0107] Reference Figure 3 , Figure 11A and Figure 11B The sacrificial layer HL exposed through the trench TR can be replaced by electrodes EL, thus forming the electrode structure ST. Specifically, the sacrificial layer HL exposed through the trench TR can be selectively removed. Electrodes EL can be formed in the spaces created by removing the sacrificial layer HL. The sacrificial layer HL on the through-contact region TVR can be left unremoved. Therefore, the molded structure MO on the through-contact region TVR can be retained.

[0108] Refer to Figure 3 , Figure 4A and Figure 4B A through-hole contact (TVS) can be formed on the through-hole contact region (TVR) and the source connection region (SCR). The through-hole contact (TVS) can extend from the fourth interlayer insulating layer (ILD4) to the peripheral circuit structure (PS). The formation of the through-hole contact (TVS) may include: performing an anisotropic etching process on the fourth interlayer insulating layer (ILD4) to form a via that exposes the third interconnect line (INL3) of the peripheral circuit structure (PS); and filling the via with a conductive material.

[0109] Bit line contact plugs (BPLG) can be formed through the fourth interlayer insulating layer (ILD4). BPLG can be connected to conductive pads (PADs). Unit contact plugs (PLGs) can be formed through the third and fourth interlayer insulating layers (ILD3 and ILD4). PLG can be connected to electrodes (ELs). Bit lines (BL) and upper interconnects (UILs) can be formed on the fourth interlayer insulating layer (ILD4). Bit lines (BL) can be electrically connected to bit line contact plugs (BPLGs), and upper interconnects (UILs) can be electrically connected to unit contact plugs (PLGs).

[0110] Figure 12 It is along Figure 3 The cross-sectional view taken along line I-I' illustrates a 3D semiconductor memory device according to some exemplary embodiments of the concept of the present invention. Figure 13 and Figure 14 yes Figure 12 An enlarged cross-sectional view of area 'M'. In the current example embodiment, for ease of explanation, the relationship between... Figure 3 , Figure 4A and Figure 4B The description of the same components and technical features as in the example embodiments. In other words, the following will primarily describe the current example embodiments and... Figure 3 , Figure 4A and Figure 4B Differences between example embodiments.

[0111] Reference Figure 3 and Figure 12 The through-contact TVS of the source junction region SCR can contact the first conductive spacer CSP1. Therefore, the common source voltage can be directly applied to the lower semiconductor layer LSL through the through-contact TVS via the first conductive spacer CSP1. The first conductive spacer CSP1 and the through-contact TVS can correspond to the metal components attached to the second substrate SL, thus reducing the resistance of the second substrate SL.

[0112] Reference Figure 13 The through-contact TVS may have a first width W1 at a first horizontal height LV1 on the top surface of the lower semiconductor layer LSL. The through-contact TVS may have a second width W2 at a second horizontal height LV2 on the bottom surface of the lower semiconductor layer LSL. The through-contact TVS may have a third width W3 at a third horizontal height LV3 between the lower semiconductor layer LSL and the third interconnect INL3. The first width W1 may be greater than the third width W3. The third width W3 may be greater than the second width W2. The formation of the through-contact TVS according to the present example embodiment may include: forming a via by an anisotropic etching process; and performing a wet etching process in the via to expand the via.

[0113] In some example embodiments, reference is made to Figure 14 The third width W3 can be equal to or greater than the second width W2, and can be less than 150% of the second width W2. The first width W1 can be greater than 150% of the third width W3. References may be omitted in the process of forming the through-contact TVS according to the present example embodiment. Figure 13 The wet etching process is described.

[0114] Figure 15 , Figure 16 and Figure 17 It is along Figure 3 A cross-sectional view taken along line II-II' is provided to illustrate a 3D semiconductor memory device according to some exemplary embodiments of the concept of the present invention. In the current exemplary embodiment, for ease of explanation, the details of the connection to the original concept are omitted. Figure 3 , Figure 4A and Figure 4B The description of the same components and technical features as in the example embodiments. In other words, the following will primarily describe the current example embodiments and... Figure 3 , Figure 4A and Figure 4B Differences between example embodiments.

[0115] In some example embodiments, reference is made to Figure 3 and Figure 15 The inner sidewall ISW of the lower semiconductor layer LSL defining the cut hole CHO can be inclined. For example, the first angle θ1 between the inner sidewall ISW and the top surface of the first interlayer insulating layer ILD1 can be in the range of 70 degrees to 89 degrees. The second conductive spacer CSP2 can cover the inclined inner sidewall ISW.

[0116] In some example embodiments, reference is made to Figure 3 and Figure 16 The dicing hole CHO can be recessed further towards the first substrate SUB, thus forming a recessed region RS in the first interlayer insulating layer ILD1. The bottom surface of the recessed region RS can be lower than the bottom surface of the lower semiconductor layer LSL. The second conductive spacer CSP2 can partially fill the recessed region RS. The bottom surface of the second conductive spacer CSP2 can be lower than the bottom surface of the lower semiconductor layer LSL. The volume of the second conductive spacer CSP2 can be relatively increased through the recessed region RS. Therefore, the resistance of the second substrate SL can be further reduced.

[0117] In some example embodiments, reference is made to Figure 3 and Figure 17The second angle θ2 between the inner sidewall ISW and the top surface of the first interlayer insulating layer ILD1 can be in the range of 91 degrees to 120 degrees. The second conductive spacer CSP2 can cover the inclined inner sidewall ISW. Because the inner sidewall ISW is inclined, the width of the second conductive spacer CSP2 in the first direction D1 can gradually increase towards the first substrate SUB. Because the inner sidewall ISW is inclined, the volume of the second conductive spacer CSP2 formed on the inner sidewall ISW can be relatively increased. Therefore, the resistance of the second substrate SL can be further reduced.

[0118] Figure 18 This is a plan view illustrating some example embodiments of a 3D semiconductor memory device according to a concept of the present invention. Figure 19 It is along Figure 18 A cross-sectional view taken by line I-I'. In the current example embodiment, for ease of explanation, the pair with... Figure 3 , Figure 4A and Figure 4B The description of the same components and technical features as in the example embodiments. In other words, the following will primarily describe the current example embodiments and... Figure 3 , Figure 4A and Figure 4B Differences between example embodiments.

[0119] Reference Figure 18 and Figure 19 The electrode structure ST may include a pseudo-step structure STSd. The pseudo-step structure STSd may be adjacent to the third sidewall SW3 or the fourth sidewall SW4. The pseudo-step structure STSd may extend in the second direction D2. The aforementioned unit contact plug PLG may not be disposed on the pseudo-step structure STSd.

[0120] A conductive pattern CCP can be disposed in a lower semiconductor layer LSL beneath the pseudo-step structure STSd. For example, the lower semiconductor layer LSL may include a plurality of vias HO formed beneath the pseudo-step structure STSd. The vias HO may be arranged in a second direction D2. The fourth width of the vias HO in a first direction D1 may be greater than the maximum width of the first conductive spacer CSP1, but may be less than twice the maximum width. The conductive pattern CCP may be disposed in each of the vias HO. The top surface of the conductive pattern CCP may be substantially coplanar with the top surface of the lower semiconductor layer LSL. The conductive pattern CCP may comprise a metal such as tungsten, copper, or aluminum.

[0121] Because the conductive pattern CCP is disposed in the lower semiconductor layer LSL, the amount of metal components attached to the second substrate SL can be further increased. As a result, the conductive pattern CCP can reduce the resistance of the second substrate SL.

[0122] Figure 20 It is along Figure 18 A cross-sectional view taken along line I-I' to illustrate a 3D semiconductor memory device according to some exemplary embodiments of the concept of the present invention. (Refer to...) Figure 20 The aperture HO can be recessed further toward the first substrate SUB, so the bottom surface of the aperture HO can be at a lower horizontal level than the bottom surface of the lower semiconductor layer LSL. Therefore, the bottom surface of the conductive pattern CCP can be lower than the bottom surface of the lower semiconductor layer LSL. Figure 20 The volume of the conductive pattern CCP shown can be greater than Figure 19 The volume of the conductive pattern CCP shown can be reduced, thus further reducing the resistance of the second substrate SL.

[0123] Figure 21 This is a plan view illustrating some exemplary embodiments of a 3D semiconductor memory device according to a concept proposed in this invention. In the current exemplary embodiments, for ease of explanation, the details of the connection between the two devices will be omitted. Figure 3 , Figure 4A and Figure 4B The description of the same components and technical features as in the example embodiments. In other words, the following will primarily describe the current example embodiments and... Figure 3 , Figure 4A and Figure 4B Differences between example embodiments.

[0124] Reference Figure 21 The through-contact area TVR may include a first through-contact area TVR1 and a second through-contact area TVR2. Each of the first through-contact areas TVR1 may have a linear shape extending in a second direction D2. Each of the second through-contact areas TVR2 may have a quadrilateral point shape. The second through-contact areas TVR2 may be arranged in the second direction D2.

[0125] The second conductive spacer CSP2 can be disposed in each of the first through-contact regions TVR1. The second conductive spacer CSP2 can be disposed on the sidewall of the first cut hole CHO1 that defines the first through-contact region TVR1.

[0126] The third conductive spacer CSP3 may be disposed in each of the second through-contact regions TVR2. The third conductive spacer CSP3 may be disposed on the sidewall of the second cut hole CHO2 that defines the second through-contact region TVR2.

[0127] The distances between adjacent first through-contact areas TVR1 can be different. For example, the distance between some adjacent first through-contact areas TVR1 in the first direction D1 can be a first distance DI1. The distance between other adjacent first through-contact areas TVR1 in the first direction D1 can be a second distance DI2. The second distance DI2 can be greater than the first distance DI1.

[0128] The second through-contact areas TVR2 can be arranged at various intervals. For example, some second through-contact areas TVR2 can be arranged at a first interval P1 in the second direction D2. Other second through-contact areas TVR2 can be arranged at a second interval P2 in the second direction D2. The second interval P2 can be greater than the first interval P1.

[0129] The third conductive spacer CSP3 can be disposed in the second through-contact region TVR2, thus the amount of metal components attached to the second substrate SL can be further increased. As a result, the third conductive spacer CSP3 can effectively reduce the resistance of the second substrate SL.

[0130] Figure 22 It is along Figure 3 A cross-sectional view taken along line II-II' is provided to illustrate a 3D semiconductor memory device according to some exemplary embodiments of the concept of the present invention. In the current exemplary embodiment, for ease of explanation, the details of the connection to the original concept are omitted. Figure 3 , Figure 4A and Figure 4B The description of the same components and technical features as in the example embodiments. In other words, the following will primarily describe the current example embodiments and... Figure 3 , Figure 4A and Figure 4B Differences between example embodiments.

[0131] Reference Figure 22 In some example embodiments, the second conductive spacer CSP2 may include a metal pattern MP and a barrier pattern BP. The barrier pattern BP may be disposed between the metal pattern MP and the inner sidewall ISW of the lower semiconductor layer LSL. The barrier pattern BP may also be disposed between the metal pattern MP and the top surface of the first interlayer insulating layer ILD1.

[0132] Barrier patterns (BP) can improve the bond strength between the metal pattern (MP) and the lower semiconductor layer (LSL), as well as the bond strength between the metal pattern (MP) and the first interlayer insulating layer (ILD1). Barrier patterns (BP) can reduce or prevent metal diffusion in the metal pattern (MP). For example, the barrier pattern (BP) may include at least one of Ti, TiN, or WN.

[0133] Figure 23 It is along Figure 3A cross-sectional view taken along line I-I' is provided to illustrate a 3D semiconductor memory device according to some exemplary embodiments of the concept of the present invention. In the current exemplary embodiment, for ease of explanation, the details of the connection to the circuit will be omitted. Figure 3 , Figure 4A and Figure 4B The description of the same components and technical features as in the example embodiments. In other words, the following will primarily describe the current example embodiments and... Figure 3 , Figure 4A and Figure 4B Differences between example embodiments.

[0134] Reference Figure 23 At least one of the pseudo-interconnect structures DIS may further include at least one ground contact GCNT. The ground contact GCNT may be disposed between the first pseudo-interconnect INLd1 and the first substrate SUB to electrically connect the first pseudo-interconnect INLd1 to the first substrate SUB. In other words, at least one pseudo-interconnect structure DIS may be connected to both the first substrate SUB and the second substrate SL. The second substrate SL may be electrically connected to the first substrate SUB via at least one pseudo-interconnect structure DIS.

[0135] At least one of the pseudo-interconnect structures DIS may not include the ground contact GCNT. In other words, at least one pseudo-interconnect structure DIS may be connected to the second substrate SL, but may not be connected to the first substrate SUB.

[0136] Figure 24 It is along Figure 3 The cross-sectional view taken along line I-I' illustrates a method for manufacturing a 3D semiconductor memory device according to some exemplary embodiments of the invention.

[0137] Reference Figure 24 The channel hole CH can be formed in the above reference. Figure 3 , Figure 7A and Figure 7B In the resulting structure described above, the channel hole CH can be formed using an anisotropic etching process employing high-power plasma. In the anisotropic etching process, positive charges induced by ions ION and / or free radicals included in the plasma can charge the second substrate SL exposed through the channel hole CH.

[0138] Although a 3D semiconductor memory device according to the present example embodiment is fabricated, the first substrate SUB may be located on a support (not shown) of a semiconductor manufacturing apparatus. During the anisotropic etching process for forming the channel via CH, a ground voltage may be applied from the support to the first substrate SUB.

[0139] The pseudo-interconnect structure DIS can electrically connect the second substrate SL to the first substrate SUB via the ground contact GCNT. Therefore, in anisotropic etching processes, a ground voltage can be applied to the second substrate SL from the support and the first substrate SUB. Consequently, in plasma-based anisotropic etching processes (e.g., during the formation of channel vias CH), positive charges induced by ions ION and / or free radicals can be discharged outward through the first substrate SUB. According to exemplary embodiments of the present invention, arcing during the formation of channel vias CH can be reduced or prevented.

[0140] According to exemplary embodiments of the present invention, metal components of various shapes can be connected to the second substrate of the cell array structure, thereby reducing the resistance of the second substrate. Consequently, the common source voltage can be smoothly applied to the channel of the cell array structure. As a result, the electrical characteristics of the 3D semiconductor memory device according to the present invention can be improved.

[0141] While the inventive concept has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the inventive concept. Therefore, it should be understood that the above exemplary embodiments are not restrictive but illustrative. Consequently, the scope of the inventive concept should be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be limited or restricted by the foregoing description.

Claims

1. A three-dimensional semiconductor memory device, comprising: The peripheral circuit structure is located on the first substrate; A second substrate is located on the peripheral circuit structure; An electrode structure comprising a plurality of electrodes stacked on the second substrate; as well as A vertical channel structure that penetrates the electrode structure. The peripheral circuit structure includes a pseudo-interconnect structure beneath the second substrate. This pseudo-interconnect structure is a pseudo-structure that does not perform circuit functions. The pseudo-interconnect structure includes: At least one pseudo interconnect; and Multiple pseudo-vias connect the top surface of the at least one pseudo-interconnect to the bottom surface of the second substrate.

2. The three-dimensional semiconductor memory device according to claim 1, wherein, The at least one pseudo-interconnect includes a first pseudo-interconnect and a second pseudo-interconnect that are adjacent to each other, and The first pseudo interconnect and the second pseudo interconnect are spaced apart from each other by a first interlayer insulating layer between them.

3. The three-dimensional semiconductor memory device according to claim 1, wherein, The peripheral circuit structure also includes peripheral transistors that constitute the peripheral logic circuit, and The pseudo-interconnect structure is not connected to the peripheral transistor.

4. The three-dimensional semiconductor memory device according to claim 1, further comprising: A cut hole that penetrates the second substrate, the cut hole extending in one direction and defining an inner sidewall of the second substrate; as well as The first conductive spacer is located on the inner sidewall.

5. The three-dimensional semiconductor memory device according to claim 4, wherein, The electrode structure also includes a molded structure on the cut hole. The three-dimensional semiconductor memory device further includes through-contacts that penetrate the molding structure to connect to the peripheral circuit structure.

6. The three-dimensional semiconductor memory device according to claim 1, wherein, The second substrate includes a lower semiconductor layer and a source semiconductor layer on the lower semiconductor layer, and The vertical channel structure is connected to the source semiconductor layer.

7. The three-dimensional semiconductor memory device of claim 6, further comprising a conductive pattern in a hole penetrating the lower semiconductor layer. in, The top surface of the conductive pattern is coplanar with the top surface of the lower semiconductor layer, and The conductive pattern includes metal.

8. The three-dimensional semiconductor memory device according to claim 1, wherein, The plurality of electrodes of the electrode structure and the vertical channel structure passing through the plurality of electrodes constitute a three-dimensionally arranged memory cell.

9. The three-dimensional semiconductor memory device according to claim 1, wherein, The second substrate has a cell array region, a connection region, and a source connection region. The connection region is located between the cell array region and the source connection region. The vertical channel structure is located on the unit array region, and The electrode structure has a stepped structure on the connection area.

10. The three-dimensional semiconductor memory device according to claim 9, further comprising: A second interlayer insulating layer covers the electrode structure; A common source contact that penetrates the second interlayer insulation layer to connect to the source connection region; A through-contact that penetrates the second interlayer insulation layer to connect to the peripheral circuit structure below the source connection region; as well as An upper interconnect, located on the second interlayer insulation layer, connects the common source contact to the through contact.

11. The three-dimensional semiconductor memory device according to claim 10, further comprising: The second conductive spacer is located on one sidewall of the second substrate. Wherein, the source connection region is adjacent to one sidewall of the second substrate, and The through-contact element is in contact with the second conductive spacer.

12. A three-dimensional semiconductor memory device, comprising: The peripheral circuit structure is located on the first substrate; A second substrate is located on the peripheral circuit structure; An electrode structure comprising a plurality of electrodes stacked on the second substrate; as well as A vertical channel structure that penetrates the electrode structure. The peripheral circuit structure includes a pseudo-interconnect structure beneath the second substrate. This pseudo-interconnect structure is a pseudo-structure that does not perform any circuit function. The pseudo-interconnect structure includes at least one interconnect layer. The at least one interconnect layer includes a first pseudo interconnect and a second pseudo interconnect. Wherein, the first pseudo-interconnect and the second pseudo-interconnect are electrically connected to the second substrate, and The first pseudo interconnect and the second pseudo interconnect are spaced apart from each other by an interlayer insulating layer between them.

13. The three-dimensional semiconductor memory device according to claim 12, wherein, The first pseudo interconnect and the second pseudo interconnect have a line shape that extends parallel to each other.

14. The three-dimensional semiconductor memory device according to claim 12, wherein, The pseudo-interconnect structure also includes multiple pseudo-vias between the second substrate and the first pseudo-interconnect line, and The plurality of pseudo vias connect the top surface of the first pseudo interconnect to the bottom surface of the second substrate.

15. The three-dimensional semiconductor memory device according to claim 12, wherein, The peripheral circuit structure also includes: Peripheral transistors, which constitute peripheral logic circuits; and Interconnection structure, which is connected to the peripheral transistor, The pseudo-interconnect structure is not connected to the peripheral transistor.

16. The three-dimensional semiconductor memory device according to claim 15, further comprising: A cut hole that penetrates the second substrate; A conductive spacer is located on the inner sidewall of the second substrate defined by the cut hole; as well as A through-contact element extends through the electrode structure in the cut hole to connect to the interconnect structure.

17. A three-dimensional semiconductor memory device, comprising: A peripheral circuit structure is located on a first substrate. The peripheral circuit structure includes a peripheral transistor on the first substrate, an interconnect structure on the peripheral transistor, and a pseudo interconnect structure adjacent to the interconnect structure. The pseudo interconnect structure is a pseudo structure that does not perform circuit functions. A second substrate is located on the peripheral circuit structure; An electrode structure comprising a plurality of electrodes stacked on the second substrate; Multiple vertical channel structures extend through the electrode structure, and the multiple vertical channel structures are electrically connected to the second substrate; Multiple conductive pads are respectively located on the multiple vertical channel structures; An interlayer insulating layer that covers the electrode structure; Multiple bit lines are located on the interlayer insulating layer and are electrically connected to the multiple conductive pads, respectively; as well as A through-contact element, which penetrates the interlayer insulation layer, is used to connect to the interconnect structure. Each of the plurality of vertical channel structures includes: Filled with an insulating pattern, which is cylindrical; A vertical semiconductor pattern covering the outer surface of the filled insulating pattern; and A data storage layer is located between the vertical semiconductor pattern and the plurality of electrodes. The pseudo-interconnect structure includes: At least one interconnect layer is located between the first substrate and the second substrate; and Multiple pseudo vias connect the at least one interconnect layer to the second substrate.

18. The three-dimensional semiconductor memory device of claim 17, wherein the plurality of pseudo-vias connect the top surface of the pseudo-interconnects of the at least one interconnect layer to the bottom surface of the second substrate.

19. The three-dimensional semiconductor memory device according to claim 17, further comprising: A cut hole extends through the second substrate, the cut hole extending in one direction and defining an inner sidewall of the second substrate; as well as A conductive spacer is located on the inner sidewall.

20. The three-dimensional semiconductor memory device according to claim 17, wherein, The second substrate has a cell array region, a connection region, and a source connection region. The connection region is located between the cell array region and the source connection region. The plurality of vertical channel structures are located on the unit array region, and The electrode structure has a stepped structure on the connection region. The three-dimensional semiconductor memory device further includes: A common source contact that penetrates the interlayer insulation layer to connect to the source connection region; and An upper interconnect, located on the interlayer insulation layer, connects the common source contact to the through contact.

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