Semiconductor device

Abstract

A semiconductor device includes: an active pattern extending in a first direction; a channel pattern on the active pattern and including a vertically stacked semiconductor pattern; a source / drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each semiconductor pattern; and a gate spacer covering side surfaces of the gate electrode and having an opening toward the semiconductor pattern, wherein the source / drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer including outer side surfaces and inner side surfaces opposite to each other, and each of the outer side surfaces and the inner side surfaces is a curved surface that is convexly curved toward the gate electrode.

Description

[0001] Cross-references to related applications

[0002] Korean Patent Application No. 10-2020-0005365, entitled "Semiconductor Device", filed on January 15, 2020 with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0003] The examples involve semiconductor devices. Background Technology

[0004] Semiconductor devices are considered essential components in the electronics industry due to their small size, versatility, and / or low cost. Semiconductor devices are categorized into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices that combine both storage and logic elements. With the development of the electronics industry, the demand for semiconductor devices with improved characteristics continues to grow. For example, there is a growing need for semiconductor devices with high reliability, high performance, and / or versatility. To meet this demand, the complexity and / or integration density of semiconductor devices are constantly increasing. Summary of the Invention

[0005] An embodiment can be implemented by providing a semiconductor device comprising: a first active pattern on a first active region of a substrate, the first active pattern extending in a first direction; a first channel pattern on the first active pattern, the first channel pattern comprising vertically stacked semiconductor patterns; a first source / drain pattern in a recess in the upper portion of the first active pattern; a gate electrode on the first active pattern extending in a second direction intersecting the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each semiconductor pattern; and a gate spacer covering the side surface of the gate electrode and having an opening into the semiconductor pattern, wherein the first source / drain pattern includes a buffer layer covering the inner side of the recess, the buffer layer comprising an outer surface and an inner surface opposite to each other when viewed in a plan view, and each of the outer surface and the inner surface is a curved surface that is convexly curved toward the gate electrode closest to the buffer layer.

[0006] Embodiments can be realized by providing a semiconductor device including: a first active pattern on a first active region of a substrate, the first active pattern extending in a first direction. A first channel pattern on the first active pattern, the first channel pattern including a vertically stacked semiconductor pattern; a first source / drain pattern in a recess of an upper portion of the first active pattern; a gate electrode on the first active pattern and extending in a second direction crossing the first direction; and a gate spacer covering side surfaces of the gate electrode and having an opening to the semiconductor pattern, wherein the first source / drain pattern includes: a buffer layer covering an inner side of the recess; a main layer on the buffer layer to fill the recess; and an intermediate layer between the buffer layer and the main layer, the gate spacer includes: a first spacer sidewall facing the first direction; and a second spacer sidewall, the second spacer sidewall being an inner sidewall of the opening, the buffer layer covering the second spacer sidewall when viewed in a plan view, and the second spacer sidewall being spaced apart from the main layer.

[0007] Embodiments can be realized by providing a semiconductor device including: a substrate including a first active region and a second active region; a first active pattern on the first active region of the substrate and extending in a first direction; a first source / drain pattern in a first recess of an upper portion of the first active pattern; a second active pattern on the second active region of the substrate and extending in the first direction; a second source / drain pattern in a second recess of an upper portion of the second active pattern; a gate electrode on a first channel pattern of the upper portion of the first active pattern and a second channel pattern of the upper portion of the second active pattern and extending in a second direction crossing the first direction, each of the first channel pattern and the second channel pattern including a vertically stacked semiconductor pattern, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; a gate spacer covering side surfaces of the gate electrode and having an opening to the semiconductor pattern; an active contact connected to the first source / drain pattern and the second source / drain pattern; a plurality of interconnection lines connected to the active contact; a plurality of vias disposed below the interconnection lines; and an interlayer insulating layer covering the active contact, the interconnection lines, and the vias, wherein the first source / drain pattern includes a buffer layer covering an inner side of the recess, an intermediate layer on the buffer layer, and a main layer on the intermediate layer to fill a remaining space of the recess, the buffer layer including an outer side surface and an inner side surface opposite each other when viewed in a plan view, and the outer side surface and the inner side surface being curved surfaces convexly curved toward the gate electrode closest to the buffer layer. BRIEF DESCRIPTION OF DRAWINGS

[0008] Features will become apparent to those of ordinary skill in the art upon examination of the following details. It is also intended that any conclusions reached for two or more examples are not to be taken as limiting.

[0009] Figure 1 is a plan view showing a semiconductor device according to an embodiment.

[0010] Figure 2 , Figure 3 and Figure 4 are cross-sectional views taken along lines A-A', B-B' and C-C' of Figure 1 , respectively.

[0011] Figure 5 , Figure 6 and Figure 7 are enlarged cross-sectional views showing a portion "M" of Figure 2 .

[0012] Figure 8 is a cross-sectional view taken along a line orthogonal to line D-D' of Figure 2 .

[0013] Figure 9 is an enlarged cross-sectional view showing a portion "Y" of Figure 8 .

[0014] Figure 10 , Figure 13 , Figure 16 , Figure 19 and Figure 22 are plan views of respective stages in a method of manufacturing a semiconductor device according to an embodiment.

[0015] Figure 11 , Figure 14 , Figure 17 , Figure 20 and Figure 23 are cross-sectional views taken along line A-A' of Figure 10 , Figure 13 , Figure 16 , Figure 19 and Figure 22 , respectively.

[0016] Figure 12 , Figure 15 , Figure 18 , Figure 21 and Figure 24 are cross-sectional views taken along line D-D' of Figure 11 , Figure 14 , Figure 17 , Figure 20 and Figure 23 , respectively.

[0017] Figure 25 is a plan view showing a semiconductor device according to an embodiment.

[0018] Figure 26 and Figure 27 are cross-sectional views taken along line A-A' of Figure 25are cross-sectional views taken along lines A-A' and B-B' of

[0019] Figure 28 is a plan view showing a semiconductor device according to an embodiment.

[0020] Figure 29 and Figure 30 are cross-sectional views taken along lines C-C' and D-D' of Figure 28 DETAILED DESCRIPTION

[0021] Figure 1 is a plan view showing a semiconductor device according to an embodiment. Figures 2 to 4 are cross-sectional views taken along lines A-A', B-B' and C-C' of Figure 1 Figures 5 to 7 is an enlarged cross-sectional view showing a portion "M" of Figure 2 Figure 8 is a cross-sectional view taken along a line orthogonal to line D-D' of Figure 2 Figure 9 is an enlarged cross-sectional view showing a portion "Y" of Figure 8

[0022] Referring to Figures 1 to 4 , a substrate 100 including a first active region RG1 can be provided. The substrate 100 can be a semiconductor substrate (e.g., a substrate of silicon, germanium or silicon germanium) or a compound semiconductor substrate. In one embodiment, the substrate 100 can be a silicon wafer.

[0023] In one embodiment, the first active region RG1 can be a logic cell region on which logic transistors constituting a logic circuit of a semiconductor device are arranged. In one embodiment, the logic transistors constituting the logic circuit can be on the logic cell region of the substrate 100. Some of the logic transistors can be on the first active region RG1. The first active region RG1 can be a PMOSFET region or an NMOSFET region. In one embodiment, the substrate 100 can further include a second active region RG2 (see Figure 28 ). In the case where the first active region RG1 is a PMOSFET region, the second active region RG2 can be an NMOSFET region, and in the case where the first active region RG1 is an NMOSFET region, the second active region RG2 can be a PMOSFET region.

[0024] ​​​​​A second trench TR2 can be formed in an upper portion of the substrate 100 to define a first active region RG1. The first active region RG1 can extend (e.g., lengthwise) in a first direction D1 that intersects the second direction D2. A first active pattern AP1 can be provided on the first active region RG1. The first active pattern AP1 can extend in the second direction D2 and can be parallel to each other. The first active pattern AP1 can be a portion of the substrate 100 that protrudes in a vertical direction. A first trench TR1 can be formed in an upper portion of the substrate 100 to define the first active pattern AP1. The first trench TR1 can be shallower than the second trench TR2.

[0025] A device isolation layer ST can fill the first trench TR1 and the second trench TR2. The device isolation layer ST can be formed of or include silicon oxide. An upper portion of the first active pattern AP1 can have a shape that protrudes vertically (e.g., in a vertical third direction D3) above the device isolation layer ST (e.g., see Figure 4 ). Each top surface of the first active pattern AP1 can be flat. The device isolation layer ST can not cover the top surface of the first active pattern AP1. The device isolation layer ST can cover a lower sidewall of the first active pattern AP1.

[0026] A first source / drain pattern SD1 can be on the first active pattern AP1. The first source / drain pattern SD1 can be an impurity region of a first conductivity type (e.g., p-type). A recess RS can be formed on the first active pattern AP1, and the first source / drain pattern SD1 can be provided to fill the recess RS of the first active pattern AP1, respectively. A first channel pattern CH1 can be on the first active pattern AP1. Each first channel pattern CH1 can be between an adjacent pair of first source / drain patterns SD1. The first channel pattern CH1 can connect the adjacent pair of first source / drain patterns SD1 to each other. The first channel pattern CH1 can include a plurality of semiconductor patterns CP1, CP2, and CP3. The semiconductor patterns can include, for example, a first semiconductor pattern CP1, a second semiconductor pattern CP2, and a third semiconductor pattern CP3 that are vertically stacked. The first to third semiconductor patterns CP1, CP2, and CP3 can be spaced apart from each other in a third direction D3 that is perpendicular to both the first direction D1 and the second direction D2. When viewed in a plan view (e.g., when viewed from above along the third direction D3), the first to third semiconductor patterns CP1, CP2, and CP3 can overlap each other.

[0027] The first source / drain pattern SD1 can be an epitaxial pattern formed by a selective epitaxial growth process. In one embodiment, a top surface of the first source / drain pattern SD1 can be coplanar with a top surface of the first channel pattern CH1. In one embodiment, a top surface of the first source / drain pattern SD1 can be higher than a top surface of the first channel pattern CH1.

[0028] The first source / drain pattern SD1 can be formed of or include a semiconductor material (e.g., SiGe) having a lattice constant greater than a lattice constant of the semiconductor substrate 100. Accordingly, the first source / drain pattern SD1 can exert a compressive stress on the first channel pattern CH1.

[0029] The gate electrode GE can cross the first active pattern AP1 and can extend in the second direction D2. The gate electrodes GE can be spaced apart from each other in the first direction D1. When viewed in a plan view, the gate electrodes GE can overlap the first channel pattern CH1, respectively.

[0030] Referring again to Figure 4 , the gate electrode GE can be on a top surface, at least one side surface, and a bottom surface of each of the first to third semiconductor patterns CP1, CP2, and CP3. In one embodiment, the gate electrode can surround the top surface, at least one side surface, and the bottom surface of each of the semiconductor patterns CP1, CP2, and CP3. The transistor according to the present embodiment can be a three-dimensional field effect transistor (e.g., a multi-bridge channel field effect transistor (MBCFET)) in which the gate electrode GE three-dimensionally surrounds the channel pattern CH1 or CH2.

[0031] Referring again to Figures 1 to 4 , a pair of gate spacers GS can be on two side surfaces of each gate electrode GE. The gate spacers GS can extend along the gate electrode GE and in the second direction D2. A top surface of the gate spacer GS can be higher than a top surface of the gate electrode GE (e.g., can be further away from the substrate 100 in the third direction D3). The top surface of the gate spacer GS can be coplanar with a top surface of the first interlayer insulating layer 110, which will be described below. The gate spacer GS can include, for example, SiCN, SiCON, or SiN. In one embodiment, the gate spacer GS can be a multi-layer structure including at least two of SiCN, SiCON, or SiN. As used herein, the term “or” is not an exclusive term, for example, “A or B” includes A, B, or both A and B.

[0032] The gate cover pattern GP can be on each gate electrode GE. The gate cover pattern GP can extend along the gate electrode GE and in the second direction D2. The gate cover pattern GP can be formed of or include a material having etch selectivity with respect to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described below. In one embodiment, the gate cover pattern GP can be formed of or include, for example, SiON, SiCN, SiCON, or SiN.

[0033] The gate dielectric pattern GI can be between the gate electrode GE and the first active pattern AP1. The gate dielectric pattern GI can extend along the gate electrode GE in the second direction D2. The gate dielectric pattern GI can surround each first channel pattern CH1. The gate dielectric pattern GI can cover a top surface of the device isolation layer ST (see, for example, Figure 4 ).

[0034] In one embodiment, the gate dielectric pattern GI can be formed of or include a high-k dielectric material having a dielectric constant higher than that of a silicon oxide layer. In one embodiment, the high-k dielectric material can include, for example, hafnium oxide, hafnium silicon oxide, zirconium hafnium oxide, tantalum hafnium oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, titanium strontium barium oxide, titanium barium oxide, titanium strontium oxide, lithium oxide, aluminum oxide, tantalum scandium lead oxide, or lead zinc niobate.

[0035] In one embodiment, the gate dielectric pattern GI can be formed of or include a ferroelectric material. The gate dielectric pattern GI including the ferroelectric material can be used as a negative capacitor. In one embodiment, due to the movement of dipoles in the ferroelectric material that occurs when an external voltage is applied to the ferroelectric material, a negative capacitance effect can occur in which the phase of the ferroelectric material changes to a state different from its initial polarization state. In this case, the total capacitance of the transistor including the ferroelectric material can be increased, and this makes it possible to improve the subthreshold swing characteristics of the transistor and reduce the operating voltage.

[0036] The gate electrode GE can include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern can be on the gate dielectric pattern GI and can be adjacent to the first channel pattern CH1 and the second channel pattern CH2. The first metal pattern can include a work function metal, which can be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor having a desired threshold voltage can be realized.

[0037] The first metal pattern can include a metal nitride layer. In one embodiment, the first metal pattern can include nitrogen, and can further include titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), or molybdenum (Mo). In one embodiment, the first metal pattern can further include carbon (C). The first metal pattern can include a plurality of work function metal layers stacked.

[0038] The second metal pattern can include a metal material having a lower resistance than the first metal pattern. In one embodiment, the second metal pattern can include, for example, tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0039] A first interlayer insulating layer 110 can be on the substrate 100. The first interlayer insulating layer 110 can cover the gate spacers GS and the first source / drain pattern SD1. A top surface (e.g., a surface facing away from the substrate 100 in the third direction D3) of the first interlayer insulating layer 110 can be substantially coplanar with a top surface of the gate cover pattern GP and a top surface of the gate spacers GS. A second interlayer insulating layer 120 can be on the first interlayer insulating layer 110 to cover the gate cover pattern GP. A third interlayer insulating layer 130 can be on the second interlayer insulating layer 120. In one embodiment, the first through third interlayer insulating layers 110, 120, and 130 can be formed of or include silicon oxide.

[0040] The active contacts AC can penetrate the first and second interlayer insulating layers 110 and 120, and can be electrically connected to the first source / drain pattern SD1, respectively. Each active contact AC can be between a pair of gate electrodes GE.

[0041] The active contacts AC can be self-aligned contacts. In one embodiment, the active contacts AC can be formed in a self-aligned manner using the gate cover pattern GP and the gate spacers GS. In one embodiment, the active contacts AC can cover at least a portion of a side surface of the gate spacers GS. In one embodiment, the active contacts AC can cover a portion of a top surface of the gate cover pattern GP.

[0042] The silicide pattern SC can be between the active contacts AC and the first source / drain pattern SD1, and between the active contacts AC and the second source / drain pattern SD2. The active contacts AC can be electrically connected to the source / drain patterns SD1 and SD2 via the silicide pattern SC. The silicide pattern SC can be formed of or include a metal silicide material (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide). In one embodiment, at least one gate contact can penetrate the second interlayer insulating layer 120 and the gate cover pattern GP, and can be electrically connected to the gate electrode GE.

[0043] Each of the active contact AC and the gate contact GC can include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. In one embodiment, the conductive pattern FM can include a metallic material (e.g., aluminum, copper, tungsten, molybdenum, or cobalt). The barrier pattern BM can cover side surfaces and a bottom surface of the conductive pattern FM. The barrier pattern BM can include a metallic layer or a metallic nitride layer. The metallic layer can include titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metallic nitride layer can include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0044] The first interconnection layer can be in the third interlayer insulating layer 130. The first interconnection layer can include a plurality of interconnection lines IL and a plurality of vias VI under the interconnection lines IL (e.g., the vias VI can be between the interconnection lines IL and the substrate 100 in the third direction D3). The interconnection lines IL can extend in the second direction D2 and can be parallel to each other. The interconnection lines IL can be arranged (e.g., spaced apart from each other) in the first direction D1.

[0045] The via VI can be between a first interconnection line which is one of the interconnection lines IL and the active contact AC. The first interconnection line can be electrically connected to the active contact AC through the via VI. The via VI can also be between a second interconnection line which is another one of the interconnection lines IL and the gate contact GC. The second interconnection line can be electrically connected to the gate contact GC through the via VI.

[0046] In one embodiment, a plurality of interconnection layers can be additionally stacked on the first interconnection layer. The logic units can be connected to each other through the first interconnection layer and the additionally stacked interconnection layers to constitute a logic circuit.

[0047] Hereinafter, a semiconductor device will be described in more detail with reference to Figures 5 to 9 and Figures 1 to 4 The first source / drain pattern SD1 will be described in more detail.

[0048] Figures 5 to 7 is an enlarged cross-sectional view illustrating a portion "M" of Figure 2 . Figure 8 is a cross-sectional view taken along a line orthogonal to the line D-D' of Figure 2 . Figure 8 is a cross-sectional view taken along a line orthogonal to the line D-D' in the third direction D3 of Figure 9 . Figure 8 is an enlarged cross-sectional view illustrating a portion "Y" of

[0049] will be described with reference toFigures 5 to 7 and Figure 9 to describe a cross-sectional shape of the first source / drain pattern SD1 in the second direction D2. Here, the cross-section in the second direction D2 can mean a cross-section perpendicular to the second direction D2. The recess RS can include a pair of inner side surfaces RSa opposite to each other, and a bottom surface RSb between the pair of inner side surfaces RSa to connect the pair of inner side surfaces RSa to each other. The recess RS can expose a side surface of the first channel pattern CH1. Due to the presence of the recess RS, the gate electrode GE can have an opening OP (see, for example, Figure 9 ) exposing the first channel pattern CH1. The gate spacer GS can include a first spacer sidewall GSw1 exposed in the first direction D1, and a second spacer sidewall GSw2 corresponding to an inner side surface of the opening OP and exposed in the second direction D2.

[0050] Referring to Figure 5 , the first source / drain pattern SD1 can include a buffer layer SL1, an intermediate layer SL2 on the buffer layer SL1, a main layer SL3 on the intermediate layer SL2, and a cap layer CL on the main layer SL3. In one embodiment, the buffer layer SL1 can cover the pair of inner side surfaces RSa and the bottom surface RSb of the recess RS. The buffer layer SL1 can have a “U”-shaped cross-section when viewed in the second direction D2. In one embodiment, the buffer layer SL1 can include a pair of side portions on the inner side surfaces RSa and a center portion on the bottom surface RSb. The intermediate layer SL2 can be on the buffer layer SL1 to cover inner surfaces, e.g., inner side surfaces and the bottom surface, of the buffer layer SL1. The intermediate layer SL2 can have a “U”-shaped cross-section when viewed in the second direction D2.

[0051] The main layer SL3 can be on the intermediate layer SL2 to cover inner surfaces, e.g., inner side surfaces, of the intermediate layer SL2. The main layer SL3 can fill a remaining space of the recess RS. A top surface of the main layer SL3 can be substantially coplanar with or lower than a top surface of the third semiconductor pattern CP3 (e.g., closer to the substrate 100 than the top surface of the third semiconductor pattern CP3 in the third direction D3).

[0052] The cap layer CL can be on the main layer SL3. The cap layer CL can cover exposed surfaces of the main layer SL3. The cap layer CL can be conformally formed on the exposed surfaces of the main layer SL3. The cap layer CL can help protect the main layer SL3.

[0053] Each of the buffer layer SL1, the intermediate layer SL2, and the main layer SL3 can be formed of or include a semiconductor material having a lattice constant larger than that of a semiconductor element of the substrate 100. In a case where the substrate 100 includes silicon (Si), the buffer layer SL1, the intermediate layer SL2, and the main layer SL3 can be formed of or include silicon germanium (SiGe). The lattice constant of germanium (Ge) can be larger than that of silicon (Si).

[0054] In one embodiment, the buffer layer SL1 can contain a relatively low concentration of germanium (Ge). In one embodiment, the concentration of germanium (Ge) in the buffer layer SL1 can be in a range of 10 at% to 20 at%. The concentration of germanium (Ge) in the intermediate layer SL2 can be higher than the concentration of germanium (Ge) in the buffer layer SL1. The concentration of germanium (Ge) in the intermediate layer SL2 can be in a range of 30 at% to 40 at%. The main layer SL3 can contain a relatively high concentration of germanium (Ge). The concentration of germanium (Ge) in the main layer SL3 can be higher than the concentration of germanium (Ge) in the intermediate layer SL2. The concentration of germanium (Ge) in the main layer SL3 can be in a range of 60 at% to 80 at%. The buffer layer SL1, the intermediate layer SL2, and the main layer SL3 can contain an impurity (e.g., boron), thereby causing the first source / drain pattern SD1 to have a p-type.

[0055] The buffer layer SL1 and the intermediate layer SL2 can help prevent a stacking fault between the substrate 100 and the main layer SL3. If a stacking fault occurs, a channel resistance can increase. The stacking fault can most frequently occur on the bottom surface RSb of the recess RS. To help reduce the likelihood of a stacking fault or prevent a stacking fault, the third thickness of the central portion of the buffer layer SL1 should be greater than a certain value. If this thickness of the buffer layer SL1 is to be increased to help prevent a stacking fault, the volume of the main layer SL3 filling the recess RS can be reduced. If the volume of the main layer SL3 is to be reduced, the performance of the PMOSFET can deteriorate.

[0056] Reference Signs List Figure 6 The first source / drain pattern SD1 can include the buffer layer SL1, the intermediate layer SL2 on the buffer layer SL1, the main layer SL3 on the intermediate layer SL2, and the cap layer CL on the main layer SL3. For the sake of brevity in the description, elements previously described with reference to Figure 5 The elements described previously with reference to

[0057] In one embodiment, the buffer layer SL1 may cover a pair of inner surfaces RSa and a bottom surface RSb of the recess RS. When viewed along the second direction D2, the buffer layer SL1 may have a "U" shaped cross-section. Specifically, the buffer layer SL1 may include a pair of side portions SL11 on the inner surface RSa, a central portion SL12 on the bottom surface RSb, and an edge portion SL13 connecting the side portions SL11 to the central portion SL12.

[0058] The side portion SL11 may have a first thickness TK1 measured at a first level LV1 (e.g., measured at a first distance from the substrate 100 in the third direction D3). The side portion SL11 may have a maximum width in the first direction D1 at the first level LV1. The edge portion SL13 may have a second thickness TK2 in the first direction D1 and at a second level LV2. The first level LV1 may be higher than the second level LV2 (e.g., farther from the substrate 100 in the third direction D3 than the second level LV2), and the first thickness TK1 may be greater than the second thickness TK2.

[0059] The central portion SL12 may have a third thickness TK3 on the third direction D3. The third thickness TK3 can be adjusted by changing the etching process conditions. In one embodiment, the third thickness TK3 may be 5% to 40% of the total height of the recess RS.

[0060] The intermediate layer SL2 may be on the inner surface of the buffer layer SL1. The intermediate layer SL2 may cover both the inner surface and the bottom surface of the buffer layer SL1. When viewed in or along the second direction D2 (e.g., as shown in the image), Figure 6 As shown), the intermediate layer SL2 can have a "U" shaped cross section. The thickness of the intermediate layer SL2 can increase as the distance to the bottom surface RSb of the recess RS decreases (for example, the portion of the intermediate layer SL2 near the bottom surface RSb of the recess RS can be thicker than the portion of the intermediate layer SL2 away from the bottom surface RSb of the recess RS).

[0061] The primary layer SL3 can be placed on the intermediate layer SL2 to cover the inner surface of the intermediate layer SL2. The cover layer CL can be placed on the primary layer SL3. The primary layer SL3 and the cover layer CL can have the same characteristics as the reference layer. Figure 5 The features described are basically the same.

[0062] In one implementation, reference Figure 7 The first source / drain pattern SD1 may include a buffer layer SL1, an intermediate layer SL2 on the buffer layer SL1, a main layer SL3 on the intermediate layer SL2, and a capping layer CL on the main layer SL3. For the sake of brevity, the previous references Figure 5 and Figure 6The elements described can be identified by the same reference numerals in the drawings without further description.

[0063] In one embodiment, the buffer layer SL1 can cover the pair of inner side surfaces RSa of the recess RS (e.g., and can not cover the bottom surface RSb of the recess RS). The buffer layer SL1 can have a shape like a "11" in cross-section when viewed along the second direction D2. In one embodiment, the buffer layer SL1 can include a pair of side portions on the inner side surfaces RSa, and can expose or not cover the bottom surface RSb of the recess RS. The side portions can be spaced apart from each other in the first direction D1. The side portions can cover the inner side surfaces RSa and can not cover the bottom surface RSb. The inner side surfaces of the side portions can be vertically aligned with or vertically aligned to the side surfaces of the gate spacers GS.

[0064] The intermediate layer SL2 can cover the inner side surfaces of the buffer layer SL1 and the bottom surface RSb of the recess RS. The thickness of the intermediate layer SL2 can increase as the distance to the bottom surface RSb decreases. The main layer SL3 can be on the intermediate layer SL2 to fill the remaining space of the recess RS. The cover layer CL can be on the main layer SL3. The main layer SL3 and the cover layer CL can have the same features as the reference Figure 5 Features described substantially the same.

[0065] Referring to Figure 8 and Figure 9 Due to the formation of the recess RS, the gate spacer GS can have an opening OP (e.g., in the gate spacer GS). In one embodiment, the gate spacer GS can have a first spacer sidewall GSw1 that is exposed or faces in the first direction D1, and the gate spacer GS can have a second spacer sidewall GSw2 that corresponds to an inner sidewall of the opening OP and is exposed or faces in the second direction D2.

[0066] The buffer layer SL1 (e.g., the pair of side portions SL11) can fill the opening OP. In one embodiment, the buffer layer SL1 can completely cover the second spacer sidewall GSw2. The buffer layer SL1 can include an outer side surface OS and an inner side surface IS opposite each other, and each of the outer side surface OS and the inner side surface IS can be convexly curved toward the gate electrode GE closest or nearest to the buffer layer SL1. The inner side surface IS can be connected to or continuous with the first spacer sidewall GSw1.

[0067] The buffer layer SL1 can have a sidewall center thickness Tsc at the center of the opening OP and a sidewall edge thickness Tse at the edge of the opening OP when viewed in a plan view. The sidewall center thickness Tsc can be equal to the sidewall edge thickness Tse. The side portions SL11 can have a second distance WT2 or be spaced apart by the second distance WT2 in the first direction D1 at the center of the opening OP when viewed in a plan view. The side portions SL11 can be spaced apart by a first distance WT1 from each other at an edge portion of the opening OP adjacent to the gate spacer GS when measured in the first direction D1. The outer side surface OS and the inner side surface IS can be convexly curved toward the gate electrode GE, and the second distance WT2 can be greater than the first distance WT1.

[0068] The intermediate layer SL2 can be on the inner side surface IS of the buffer layer SL1. In one embodiment, as shown in FIG. 1A, the intermediate layer SL2 can cover the inner side surface IS of the buffer layer SL1 and can cover a portion of the first spacer sidewall GSw1 adjacent to the opening OP. Referring back to FIG. 1A, the main layer SL3 can be between the pair of side portions SL11. The main layer SL3 can cover the intermediate layer SL2 and at least a portion of the first spacer sidewall GSw1 and can be spaced apart from the second spacer sidewall GSw2. Figure 9 Figure 8 The intermediate layer SL2 can be on the inner side surface IS of the buffer layer SL1. In one embodiment, as shown in FIG. 1A, the intermediate layer SL2 can cover the inner side surface IS of the buffer layer SL1 and can cover a portion of the first spacer sidewall GSw1 adjacent to the opening OP. Referring back to FIG. 1A, the main layer SL3 can be between the pair of side portions SL11. The main layer SL3 can cover the intermediate layer SL2 and at least a portion of the first spacer sidewall GSw1 and can be spaced apart from the second spacer sidewall GSw2.

[0069] If the thickness of the buffer layer SL1 filling the opening OP decreases as the distance from the edge of the opening OP decreases when viewed in a plan view, a leakage current can occur between the gate electrode GE and the first source / drain pattern SD1, and this can cause reliability degradation of the semiconductor device. According to an embodiment, the side portions SL11 of the buffer layer SL1 can be formed by filling the entire area of the recess RS with the buffer layer SL1 and performing an etching process. Thus, each of the side portions SL11 can have a uniform thickness and can completely cover the first spacer sidewall GSw1 of the gate spacer GS adjacent to the side portion SL11 when viewed in a plan view, and thus a leakage current can be prevented. Thus, a semiconductor device with improved reliability can be implemented.

[0070] Manufacturing method

[0071] Figure 10 Figure 13 Figure 16 Figure 19 Figure 22 are plan views showing stages in a method of manufacturing a semiconductor device according to an embodiment. Figure 11 Figure 14 Figure 17 Figure 20 Figure 23 are cross-sectional views taken along lines Figure 10 Figure 13 , respectively.​​​​​​​​​​Figure 16 , Figure 19 and Figure 22 a cross-sectional view taken along line A-A' of Figure 12 , Figure 15 , Figure 18 , Figure 21 and Figure 24 are cross-sectional views taken along line D-D' of Figure 11 , Figure 14 , Figure 17 , Figure 20 and Figure 23 .

[0072] Referring to FIGS. 1A to 1C in conjunction with FIG. 1D, a substrate 100 including a first active region RG1 can be provided. Sacrificial layers 111 and semiconductor layers 112 can be alternately and repeatedly stacked on the substrate 100. In one embodiment, as shown in FIG. 1A, three semiconductor layers 112 can be alternately and repeatedly stacked on the substrate 100. The sacrificial layers 111 can be formed of or include a material having etch selectivity with respect to the semiconductor layers 112. In one embodiment, the semiconductor layers 112 can be formed of or include a material that is not substantially etched in a process of etching the sacrificial layers 111. In one embodiment, the sacrificial layers 111 can be formed of or include silicon germanium (SiGe) or germanium (Ge), and the semiconductor layers 112 can be formed of or include silicon (Si). Figures 3 to 4 Figures 10 to 12 Referring to FIGS. 1A to 1C in conjunction with FIG. 1D, a substrate 100 including a first active region RG1 can be provided. Sacrificial layers 111 and semiconductor layers 112 can be alternately and repeatedly stacked on the substrate 100. In one embodiment, as shown in FIG. 1A, three semiconductor layers 112 can be alternately and repeatedly stacked on the substrate 100. The sacrificial layers 111 can be formed of or include a material having etch selectivity with respect to the semiconductor layers 112. In one embodiment, the semiconductor layers 112 can be formed of or include a material that is not substantially etched in a process of etching the sacrificial layers 111. In one embodiment, the sacrificial layers 111 can be formed of or include silicon germanium (SiGe) or germanium (Ge), and the semiconductor layers 112 can be formed of or include silicon (Si). Figure 11

[0073] Each of the sacrificial layers 111 and the semiconductor layers 112 can be formed by an epitaxial growth process using the substrate 100 as a seed layer. The sacrificial layers 111 and the semiconductor layers 112 can be continuously formed in the same chamber. The sacrificial layers 111 and the semiconductor layers 112 can be conformally grown on the substrate 100.

[0074] Next, the sacrificial layers 111 and the semiconductor layers 112 can be patterned to form a first preliminary pattern PAP1 on the first active region RG1 of the substrate 100. A patterning process can be performed to etch an upper portion of the substrate 100, and in this case, a first trench TR1 and a second trench TR2 can be formed in the upper portion of the substrate 100. The first trench TR1 can define a first active pattern AP1 of the substrate 100, and the second trench TR2 can define the first active region RG1 of the substrate 100.

[0075] ​​The patterned first preliminary pattern PAP1 can be on the first active pattern AP1. The first preliminary pattern PAP1 can overlap the first active pattern AP1, respectively, when viewed in a plan view. The first preliminary pattern PAP1 and the first active pattern AP1 can be linear patterns or bar patterns extending along the first direction D1.

[0076] The sacrificial pattern PP can span the first preliminary pattern PAP1. The sacrificial pattern PP can be a linear pattern or a bar pattern extending in the second direction D2 (e.g., lengthwise).

[0077] The formation of the sacrificial pattern PP can include forming a sacrificial layer on the substrate 100, forming a mask pattern on the sacrificial layer, and etching the sacrificial layer using the mask pattern as an etch mask. The sacrificial layer can be formed of or include polysilicon. The mask pattern can be formed of or include silicon oxide, silicon nitride, or silicon oxynitride.

[0078] A pair of gate spacers GS can be formed on two sidewalls of each sacrificial pattern PP. The gate spacer GS can be formed of or include SiCN, SiCON, or SiN. The formation of the gate spacer GS can include forming a spacer layer on the substrate 100 using a deposition process (e.g., CVD or ALD), and performing an anisotropic etching process on the spacer layer.

[0079] Referring to Figures 13 to 15 The first preliminary pattern PAP1 can be etched to form a recess RS on the first active pattern AP1. In one embodiment, a pair of recesses RS can be formed at two sides of each sacrificial pattern PP. The formation of the recess RS can include etching the first preliminary pattern PAP1 using the hard mask pattern MA and the gate spacer GS as etch masks.

[0080] The first source / drain pattern SD1 can be formed to fill the recess RS. The first source / drain pattern SD1 can be formed of or include a second semiconductor material having a lattice constant greater than a lattice constant of a first semiconductor material of the substrate 100. In one embodiment, the first semiconductor element can be silicon (Si), and the second semiconductor element can be germanium (Ge). The first source / drain pattern SD1 can be formed of a plurality of stacked semiconductor layers.

[0081] In one embodiment, the formation of the first source / drain pattern SD1 can include forming a buffer layer SL1 to fill an entire area of the recess, etching the buffer layer SL1 to form a temporary recess RS’ (see FIG. 11B), and etching the first semiconductor material of the substrate 100 using the temporary recess RS’ as an etch mask. Figure 17), an intermediate layer SL2 is formed on the etched buffer layer SL1 to cover the temporary recess RS', and a main layer SL3 is formed to fill the remaining space of the recess RS.

[0082] The buffer layer SL1 can be formed by a first selective epitaxial growth process, in which the inner sidewall of the recess RS of the first active pattern AP1 is used as a seed layer. The first selective epitaxial growth process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process. The buffer layer SL1 can include a low concentration of a second semiconductor element. The buffer layer SL1 can be doped to include a low concentration of an impurity. In one embodiment, the buffer layer SL1 can include a silicon germanium (SiGe) layer doped with boron (B). The concentration of germanium (Ge) in the buffer layer SL1 can be in the range of 10 at% to 20 at%.

[0083] Referring to Figure 14 and Figure 15 The buffer layer SL1 can be formed to cover the pair of inner side surfaces and the bottom surface of the recess RS. The buffer layer SL1 can be formed to fill the inner space of the recess RS. The top surface of the buffer layer SL1 can be disposed at substantially the same level as the top surface of the topmost layer of the semiconductor layer 112. The buffer layer SL1 can fill the opening of the gate spacer GS or the opening in the gate spacer GS. In one embodiment, the buffer layer SL1 can cover at least a portion of the first spacer sidewall GSw1 of the gate spacer GS, and can completely cover the second spacer sidewall GSw2.

[0084] Referring to Figures 16 to 18 The temporary recess RS' can be formed by etching a portion of the buffer layer SL1. The temporary recess RS' can be formed by an etching process. The etching process can include a dry etching process or a wet etching process. The etching process can include etching the buffer layer SL1 using the gate spacer GS and the hard mask pattern MA as etching masks. Accordingly, the buffer layer SL1 can have a pair of inner side surfaces opposite each other when viewed in a plan view.

[0085] Referring to Figures 19 to 21 The intermediate layer SL2 and the main layer SL3 can be formed on the buffer layer SL1. The intermediate layer SL2 can be formed by a second selective epitaxial growth process, in which the buffer layer SL1 is used as a seed layer. The intermediate layer SL2 can cover the inner side surfaces of the buffer layer SL1. The concentration of germanium in the intermediate layer SL2 can be in the range of 30 at% to 40 at%. The main layer SL3 can be formed on the intermediate layer SL2.

[0086] The main layer SL3 can be formed by a third selective epitaxial growth process, in which the intermediate layer SL2 serves as a seed layer. The third selective epitaxial growth process can be performed at a temperature condition lower than that of the first and second epitaxial growth processes. In one embodiment, the third selective epitaxial growth process can be performed at a temperature condition of 300°C to 900°C. The main layer SL3 can include a high concentration of the second semiconductor element. The concentration of the second semiconductor element of the main layer SL3 can be higher than that of the buffer layer SL1. The main layer SL3 can be doped to have a higher doping concentration than the doping concentration of the buffer layer SL1 and the intermediate layer SL2. In one embodiment, the main layer SL3 can include a silicon germanium (SiGe) layer doped with boron (B). The concentration of germanium (Ge) in the main layer SL3 can be in a range of 60 at% to 80 at%.

[0087] The cap layer CL (see Figure 23 ) can be formed by the third selective epitaxial growth process, in which the main layer SL3 serves as a seed layer. The cap layer CL can be formed to conformally cover the surface of the main layer SL3. The cap layer CL can include the first semiconductor element identical to that in the substrate 100. In one embodiment, the cap layer CL can include single crystalline silicon (Si). The concentration of silicon (Si) in the cap layer CL can be in a range of 95 at% to 100 at%.

[0088] Referring to Figures 22 to 24 , the first interlayer insulating layer 110 can be formed to cover the first source / drain pattern SD1, the gate spacers GS, and the mask pattern MA. In one embodiment, the first interlayer insulating layer 110 can be formed of or include silicon oxide.

[0089] A planarization process can be performed on the first interlayer insulating layer 110 to expose the top surface of the sacrificial pattern PP. The planarization of the first interlayer insulating layer 110 can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. As a result, the first interlayer insulating layer 110 can have a top surface substantially coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0090] Each of the sacrificial patterns PP can be replaced with a gate electrode GE and a gate dielectric pattern GI. In one embodiment, a blank space can be formed by selectively removing the exposed sacrificial pattern PP. The gate dielectric pattern GI can be formed in the blank space formed by the removal of the sacrificial pattern PP. The gate electrode GE can be formed on the gate dielectric pattern GI to fill the blank space.

[0091] The gate dielectric pattern GI can be formed conformally by an atomic layer deposition (ALD) and / or a chemical oxidation process. The gate dielectric pattern GI can be formed of or include a high-k dielectric material. In one embodiment, the gate dielectric pattern GI can be formed of or include a ferroelectric material.

[0092] Formation of the gate electrode GE can include forming a gate electrode layer on the gate dielectric pattern GI and planarizing the gate electrode layer. In one embodiment, the gate electrode layer can include a first gate electrode layer including a metal nitride and a second gate electrode layer including a low-resistance metal.

[0093] An upper portion of the gate electrode GE can be selectively etched to recess the gate electrode GE. A top surface of the recessed gate electrode GE can be lower than a top surface of the first interlayer insulating layer 110 and a top surface of the gate spacer GS. A gate cap pattern GP can be formed on the recessed gate electrode GE. Formation of the gate cap pattern GP can include forming a gate cap layer to cap the recessed gate electrode GE and planarizing the gate cap layer to expose the top surface of the first interlayer insulating layer 110. In one embodiment, the gate cap layer can be formed of or include SiON, SiCN, SiCON, or SiN.

[0094] Referring back to Figures 1 to 4 , a second interlayer insulating layer 120 can be formed on the first interlayer insulating layer 110. An active contact AC can be formed to penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 and electrically connected to the first source / drain pattern SD1. A gate contact can be formed to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP and electrically connected to the gate electrode GE. Formation of the active contact AC and the gate contact can include forming a barrier pattern BM to fill a contact hole and forming a conductive pattern FM on the barrier pattern BM.

[0095] A silicide pattern SC can be formed between the active contact AC and the first source / drain pattern SD1. Formation of the silicide pattern SC can include performing a silicidation process on the first source / drain pattern SD1. In one embodiment, the silicide pattern SC can be formed of or include titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide.

[0096] A third interlayer insulating layer 130 can be formed on the second interlayer insulating layer 120. A first interconnection layer can be formed in the third interlayer insulating layer 130. The formation of the first interconnection layer can include forming an interconnection line IL and forming a via VI under the interconnection line IL. The interconnection line IL and the via VI can be formed by a damascene process or a dual damascene process. The semiconductor device according to the embodiment can be manufactured by the above-described method.

[0097] Figure 25 is a plan view showing a semiconductor device according to an embodiment. Figure 26 and Figure 27 are cross-sectional views taken along lines A-A' and B-B' of Figure 25 , respectively. For the sake of brevity of the description, elements previously described with reference to Figures 1 to 9 may be identified by the same reference numerals, without further elaboration.

[0098] Referring to Figure 25 , the substrate 100 can include a second active region RG2 in addition to the first active region RG1. In one implementation, the first active region RG1 and the second active region RG2 can be logic cell regions in which logic transistors constituting logic circuits of the semiconductor device are arranged. In one implementation, the first active region RG1 can be a PMOSFET region and the second active region RG2 can be an NMOSFET region. The first active region RG1 and the second active region RG2 can be defined by a second trench TR2 formed in an upper portion of the substrate 100.

[0099] A second active pattern AP2 can be on the second active region RG2. The second active region RG2 can extend in the first direction D1. A second source / drain pattern SD2 can be on the second active pattern AP2. The second source / drain pattern SD2 can be an impurity region of a second conductivity type (e.g., n-type). A recess RS can be formed on the second active pattern AP2, and the second source / drain pattern SD2 can be formed to fill the recess RS of the second active pattern AP2, respectively.

[0100] A second channel pattern CH2 can be on the second active pattern AP2. The second channel pattern CH2 can be between a pair of second source / drain patterns SD2 adjacent to each other. The second channel pattern CH2 can connect the pair of adjacent second source / drain patterns SD2 to each other. The second channel pattern CH2 can include semiconductor patterns CP1, CP2, and CP3. The semiconductor patterns can include, for example, a first semiconductor pattern CP1, a second semiconductor pattern CP2, and a third semiconductor pattern CP3 stacked vertically. The first to third semiconductor patterns CP1, CP2, and CP3 can be spaced apart from each other in a third direction D3 perpendicular to both the first and second directions D1 and D2. The first to third semiconductor patterns CP1, CP2, and CP3 can overlap each other when viewed in a plan view.

[0101] A gate electrode GE can be provided to span the first and second active patterns AP1 and AP2 and extend in the second direction D2. The gate electrodes GE can be spaced apart from each other in the first direction D1. The gate electrodes GE can overlap the first and second channel patterns CH1 and CH2 when viewed in a plan view. A pair of gate spacers GS can be disposed on opposite side surfaces of the gate electrode GE. A gate cap pattern GP can be disposed on the gate electrode GE.

[0102] A gate dielectric pattern GI can be between the gate electrode GE and the second active pattern AP2. The gate dielectric pattern GI can extend in the second direction D2 and along the gate electrode GE. The gate dielectric pattern GI can surround each second channel pattern CH2. The gate dielectric pattern GI can encapsulate the second channel pattern CH2. The gate dielectric pattern GI can cover a top surface of the device isolation layer ST.

[0103] On the second active region RG2, an insulating pattern IP can be between the gate dielectric pattern GI and the second source / drain pattern SD2. The gate electrode GE can be spaced apart from the second source / drain pattern SD2 by the gate dielectric pattern GI and the insulating pattern IP. In one embodiment, the insulating pattern IP can be omitted on the first active region PR.

[0104] A first interlayer insulating layer 110 and a second interlayer insulating layer 120 can be on the substrate 100. An active contact AC can penetrate the first and second interlayer insulating layers 110 and 120 and can be connected to the first and second source / drain patterns SD1 and SD2, respectively. A gate contact GC can penetrate the second interlayer insulating layer 120 and the gate cap pattern GP and can be connected to the gate electrode GE.

[0105] A third interlayer insulating layer 130 can be on the second interlayer insulating layer 120. A first interconnect layer including interconnect lines IL and vias VI can be in the third interlayer insulating layer 130.

[0106] Fin Field Effect Transistor, FINFET

[0107] Figure 28 is a plan view showing a semiconductor device according to an embodiment. Figure 29 and Figure 30 are cross-sectional views taken along lines C-C' and D-D' of Figure 28 , respectively. For the sake of brief description, the elements described previously with reference to Figures 1 to 9 may be identified by the same reference numerals, without further elaboration.

[0108] Referring to Figures 28 to 30 , a substrate 100 including a first active region PR and a second active region NR can be provided. In one implementation, the first active region PR and the second active region NR can be logic cell regions on which logic transistors are to be formed, and here, the logic transistors can constitute logic circuits of the semiconductor device. The first active region PR can be a PMOSFET region, and the second active region NR can be an NMOSFET region.

[0109] The first active region PR and the second active region NR can be defined by a second trench TR2 formed in an upper portion of the substrate 100. The second trench TR2 can be located between the first active region PR and the second active region NR.

[0110] A first active pattern AP1 and a second active pattern AP2 can be on the first active region PR and the second active region NR, respectively. The first active pattern AP1 and the second active pattern AP2 can extend in the second direction D2 and can be parallel to each other. The first active pattern AP1 and the second active pattern AP2 can be vertical protrusions of the substrate 100. First trenches TR1 can be defined between adjacent first active patterns of the first active pattern AP1 and between adjacent second active patterns AP2 of the second active pattern AP2. The first trenches TR1 can be shallower than the second trench TR2.

[0111] A device isolation layer ST can fill the first trenches TR1 and the second trench TR2. The device isolation layer ST can be formed of or include silicon oxide. Upper portions of the first active pattern AP1 and the second active pattern AP2 can vertically protrude above the device isolation layer ST (see, for example, Figure 30 ). Each of the upper portions of the first active pattern AP1 and the second active pattern AP2 can be formed as a fin. The device isolation layer ST can not cover the upper portions of the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST can cover lower sidewalls of the first active pattern AP1 and the second active pattern AP2.

[0112] The first source / drain pattern SD1 can be on an upper portion of the first active pattern AP1. The first source / drain pattern SD1 can be an impurity region of a first conductivity type (e.g., p-type). The first channel pattern CH1 can be between a pair of the first source / drain patterns SD1. The second source / drain pattern SD2 can be on an upper portion of the second active pattern AP2. The second source / drain pattern SD2 can be an impurity region of a second conductivity type (e.g., n-type). The second channel pattern CH2 can be between a pair of the second source / drain patterns SD2.

[0113] The gate electrode GE can span the first active pattern AP1 and the second active pattern AP2, and can extend in the first direction D1. Each gate electrode GE can surround a top surface and two side surfaces of each of the first channel pattern CH1 and the second channel pattern CH2.

[0114] The gate electrode GE can be on at least one of a first top surface TS1 of the first channel pattern CH1 and a first sidewall SW1 of the first channel pattern CH1. The gate electrode GE can be on at least one of a second top surface TS2 of the second channel pattern CH2 and a second sidewall SW2 of the second channel pattern CH2. In one embodiment, the transistor according to the present embodiment can be a three-dimensional field effect transistor (e.g., FinFET) in which the gate electrode GE three-dimensionally surrounds the channel pattern CH1 or CH2.

[0115] According to an embodiment, a semiconductor device can include a buffer layer of a source / drain pattern of a PMOSFET for reducing or preventing a stacking fault between a main layer of the source / drain pattern and an active pattern. Accordingly, a channel resistance of the PMOSFET can be reduced. Further, a volume of the main layer of the source / drain pattern can be maintained to be greater than a certain value, and thus a performance of the PMOSFET can be improved.

[0116] One or more embodiments can provide a semiconductor device including a field effect transistor and a method of manufacturing the same.

[0117] One or more embodiments can provide a semiconductor device having improved electrical characteristics.

[0118] Example embodiments have been disclosed herein and, although the use of particular nomenclature and / or specific terms has been presented herein for the purpose of knowledge, they are only to be interpreted as being descriptive and not for limitation purposes. In some instances, features, attributes, and / or elements described in conjunction with a particular embodiment are not required in all embodiments. Thus, for example, where a particular feature, structure, attribute, or characteristic is described in connection with an embodiment, it is submitted that it is within the purview of one of ordinary skill in the art to effect such feature, structure, attribute, or characteristic in connection with another embodiment whether or not such features, structures, attributes, or characteristics are described in the entirety of the disclosure. Thus, various changes and modifications can be made to the form and details of the embodiments without departing from the spirit and scope of the application as set forth in the following claims.

Claims

1. A semiconductor device comprising: a first active pattern on a first active region of a substrate, the first active pattern extending in a first direction; a first channel pattern on the first active pattern, the first channel pattern including vertically-stacked semiconductor patterns; a first source / drain pattern in a recess in an upper portion of the first active pattern; a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering side surfaces of the gate electrode and having an opening to the semiconductor patterns, wherein: the first source / drain pattern includes a buffer layer covering inner sides of the recess, when viewed in plan view, the buffer layer includes an outer side surface and an inner side surface opposite each other, and each of the outer side surface and the inner side surface is a curved surface convexly curved toward the gate electrode closest to the buffer layer.

2. The semiconductor device of claim 1, wherein: the gate spacer includes a first spacer sidewall facing the first direction and a second spacer sidewall as an inner sidewall of the opening, and when viewed in plan view, the buffer layer completely covers the second spacer sidewall.

3. The semiconductor device of claim 2, wherein: the first source / drain pattern further includes a main layer on the buffer layer to fill the recess, and the main layer covers at least a portion of the first spacer sidewall of the gate spacer and is spaced apart from the second spacer sidewall. the inner side surface of the buffer layer is continuous with the first spacer sidewall of the gate spacer.

4. The semiconductor device of claim 2, wherein, 5. The semiconductor device of claim 2, wherein: when viewed in plan view, the first source / drain pattern further includes an intermediate layer on the inner side surface of the buffer layer, the second spacer sidewall includes a first surface and a second surface facing the opening and opposite each other, the buffer layer fills the opening and covers the first surface and the second surface, and the first surface and the second surface are spaced apart from the intermediate layer.

6. The semiconductor device of claim 1, wherein: the buffer layer fills the opening, when viewed in plan view, the buffer layer has a sidewall center thickness at a center of the opening and a sidewall edge thickness at an edge of the opening, and the sidewall center thickness is equal to the sidewall edge thickness.

7. The semiconductor device of claim 1, wherein: the recess has a pair of inner side surfaces and a bottom surface connecting the inner side surfaces, the buffer layer includes a pair of side portions on the pair of inner side surfaces and a center portion connected with the pair of side portions and on the bottom surface of the recess, when viewed in plan view, at a center portion of the opening, the side portions are spaced apart from each other by a first distance in the first direction, ​ at an edge portion of the opening adjacent to the gate spacer, the side portions are spaced apart from each other by a second distance in the first direction, and the first distance is greater than the second distance.

8. The semiconductor device of claim 1, wherein: the first source / drain pattern further includes a main layer on the buffer layer to fill the recess, and a concentration of germanium Ge in the main layer ranges from 60 at% to 80 at%.

9. The semiconductor device of claim 1, wherein: the recess has a pair of inner side surfaces and a bottom surface connecting the inner side surfaces, the buffer layer covers the pair of inner side surfaces of the recess and exposes the bottom surface of the recess, and inner side surfaces of the buffer layer are vertically aligned with side surfaces of the gate spacer.

10. The semiconductor device of claim 1, wherein: the recess includes a pair of inner side surfaces and a bottom surface connecting the inner side surfaces, the buffer layer includes side portions on the pair of inner side surfaces of the recess, a center portion on the bottom surface of the recess, and edge portions connecting the side portions to the center portion, and a thickness of the edge portions is less than a maximum thickness of each of the side portions.

11. The semiconductor device of claim 1, wherein: the recess includes a pair of inner side surfaces and a bottom surface connecting the inner side surfaces, the buffer layer includes side portions on the pair of inner side surfaces of the recess and a center portion on the bottom surface of the recess, each of the side portions has a first thickness at a first level and a second thickness at a second level lower than the first level, the side portions have a maximum width in the first direction at the first level, and the first thickness is greater than the second thickness.

12. A semiconductor device, comprising: a first active pattern on a first active region of a substrate, the first active pattern extending in a first direction; a first channel pattern on the first active pattern, the first channel pattern including a vertically-stacked semiconductor pattern; a first source / drain pattern in a recess of an upper portion of the first active pattern; a gate electrode on the first active pattern and extending in a second direction intersecting the first direction; and a gate spacer covering side surfaces of the gate electrode and having an opening to the semiconductor pattern, wherein: the first source / drain pattern includes a buffer layer covering inner sides of the recess, a main layer on the buffer layer to fill the recess, and an intermediate layer between the buffer layer and the main layer, the gate spacer includes a first spacer sidewall facing the first direction and a second spacer sidewall, the second spacer sidewall being an inner sidewall of the opening, when viewed in a plan view, the buffer layer covers the second spacer sidewall, and the second spacer sidewall is spaced apart from the main layer.

13. The semiconductor device of claim 12, wherein: when viewed in a plan view, the buffer layer includes an outer side surface and an inner side surface opposite to each other, and the first spacer sidewall is closer to the outer side surface than to the inner side surface. The inner side surface is continuous with the first spacer sidewall.

14. The semiconductor device of claim 13, wherein, Each of the outer side surface and the inner side surface is a curved surface that is convexly curved toward a gate electrode closest to the buffer layer.

15. The semiconductor device of claim 12, wherein: The buffer layer fills the opening, The buffer layer has a sidewall center thickness at a center of the opening and a sidewall edge thickness at an edge of the opening when viewed in plan view, and The sidewall center thickness is equal to the sidewall edge thickness.

16. The semiconductor device of claim 12, wherein: The recess has a pair of inner side surfaces and a bottom surface connecting the inner side surfaces, The buffer layer has a pair of side portions on the pair of inner side surfaces and a center portion connected to the pair of side portions and on the bottom surface, The side portions are spaced apart from each other by a first distance in the first direction at a center portion of the opening when viewed in plan view, The side portions are spaced apart from each other by a second distance in the first direction at an edge portion of the opening adjacent to the gate spacer, and The first distance is greater than the second distance.

17. The semiconductor device of claim 12, wherein: The recess has a pair of inner side surfaces and a bottom surface connecting the inner side surfaces, The buffer layer covers the pair of inner side surfaces of the recess and exposes the bottom surface of the recess, and Inner side surfaces of the buffer layer are vertically aligned with side surfaces of the gate spacer.

18. The semiconductor device of claim 12, wherein: The recess includes a pair of inner side surfaces and a bottom surface connecting the inner side surfaces, The buffer layer includes a side portion on the pair of inner side surfaces of the recess and a center portion on the bottom surface of the recess, Each of the side portions has a first thickness at a first level and a second thickness at a second level lower than the first level, The side portions have a maximum width in the first direction at the first level, and The first thickness is greater than the second thickness.

19. A semiconductor device, comprising: a substrate including a first active region and a second active region; a first active pattern on the first active region of the substrate and extending in a first direction; a first source / drain pattern in a first recess of an upper portion of the first active pattern; a second active pattern on the second active region of the substrate and extending in the first direction; a second source / drain pattern in a second recess of an upper portion of the second active pattern; a gate electrode on a first channel pattern of an upper portion of the first active pattern and a second channel pattern of an upper portion of the second active pattern and extending in a second direction crossing the first direction, each of the first channel pattern and the second channel pattern including a vertically stacked semiconductor pattern, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns, a gate spacer covering the side surfaces of the gate electrode and having an opening toward the semiconductor pattern. an active contact connected to the first source / drain pattern and the second source / drain pattern; a plurality of interconnection lines connected to the active contact; a plurality of vias disposed below the interconnection lines; and an interlayer insulating layer covering the active contact, the interconnection lines, and the vias, wherein: the first source / drain pattern includes a buffer layer covering an inner side of the recess, an intermediate layer on the buffer layer, and a main layer on the intermediate layer to fill a remaining space of the recess; when viewed in a plan view, the buffer layer includes an outer side surface and an inner side surface opposite each other, and the outer side surface and the inner side surface are curved surfaces convexly curved toward a gate electrode closest to the buffer layer.

20. The semiconductor device according to claim 19, wherein: the buffer layer fills the opening, when viewed in a plan view, the buffer layer has a side wall center thickness at a center of the opening and a side wall edge thickness at an edge of the opening, and the side wall center thickness is equal to the side wall edge thickness. ​

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