Pfm controller for multilevel converter with flying capacitor voltage monitor

Abstract

The invention is entitled "PFM controller for multi-level converter utilizing flying capacitor voltage monitor." An interleaved buck-boost converter is disclosed. The interleaved buck-boost converter includes a multi-level direct current (DC) to DC converter (MLDC converter), a flying capacitor monitor, and a voltage level controller. The MLDC converter includes an IMPM, and the IMPM includes a flying capacitor. The flying capacitor monitor is in signal communication with the flying capacitor, and the voltage level controller is in signal communication with the flying capacitor monitor. The flying capacitor monitor compares a flying capacitor voltage of the flying capacitor, and switches an operating state of the MLDC converter if the flying capacitor voltage is less than a first flying capacitor reference voltage.

Description

BACKGROUND 1. TECHNICAL FIELD

[0002] The present application relates to multi-level power converters, and more particularly to multi-level power converters with regulated output voltage.

[0003] 2. Prior art

[0004] Typical computing power supplies for laptops and related devices such as tablets use a combination of lithium-ion (Li-Ion) batteries, which are typically arranged in groups of two cells in series, producing a maximum voltage of approximately 10 volts (V). Such relatively high supply voltages are not suitable for modem integrated circuits, so mobile personal computers (PCs) typically include a step-down converter to regulate the battery supply voltage from the series-connected batteries to an internal supply voltage such as 1 V for powering the integrated circuits within the device.

[0005] A single-stage multi-phase step-down converter would require high-voltage components to step down from such relatively high battery supply voltages to a relatively low internal supply voltage. The use of such high-voltage components requires a large die area to achieve a suitable drain-to-source resistance, and also results in higher gate drive losses and voltage-current overlap switching losses for the power switches. Thus, single-stage multi-phase step-down converters are not very efficient in applications where the output voltage is stepped down substantially from, for example, about 10 V to 1 V.

[0006] To improve efficiency, multi-level step-down converters with multiple stages have been used. The first stage includes a step-down switched capacitor (charge pump) stage that converts the input voltage from the battery to an intermediate charge pump output voltage. The second stage converts the intermediate charge pump output voltage to a regulated internal supply voltage. But such multi-stage power converters have problems with efficiency at low output loads and / or higher step-up outputs.

[0007] In addition, additional switches are needed in multi-level step-down converters with increased regulation complexity due to the non-linear conversion function, and proper loop compensation of these types of converters is also problematic at high duty cycles. Furthermore, many known multi-level step-down converters need to be individually configured with different functional operating modes to cover specified input and output voltages, as there is a lack of an efficient mechanism to detect and regulate the multi-level step-down converter over a wide voltage range during system operation. SUMMARY

[0008] An interleaved buck-boost converter is disclosed. The interleaved buck-boost converter includes an input voltage terminal, an output filter, a main switch stage, a slave switch stage, and a controller. The input voltage terminal is configured to provide an input voltage from a voltage source, and the output filter includes an inductor having an input terminal and an output capacitor for an output voltage. The main switch stage includes a first flying capacitor, and the slave switch stage includes a second flying capacitor. The controller is configured to configure the main switch stage to a main magnetization switch state during a boost mode of operation in which the input terminal is charged to a first multiple of the input voltage in response to the output voltage being less than a first threshold voltage. The controller is further configured to configure the slave switch stage to a slave demagnetization switch state in which the input terminal is charged to a second multiple of the input voltage in response to a first flying capacitor voltage of the first flying capacitor being less than a second threshold voltage. The second multiple of the input voltage is less than the first multiple of the input voltage.

[0009] In an example of operation, the IMPFM power converter performs a method including monitoring a flying capacitor voltage of a flying capacitor with a flying capacitor monitor, comparing the flying capacitor voltage to the first flying capacitor reference voltage, and switching an operating state of the MLDC converter if the flying capacitor voltage is less than the first flying capacitor reference voltage.

[0010] The present disclosure also discloses a control system for controlling an IMPFM power converter. The control system includes a flying capacitor monitor and a voltage level controller. The flying capacitor monitor is configured to compare a flying capacitor voltage of the flying capacitor and to switch an operating state of the MLDC converter if the flying capacitor voltage is less than a first flying capacitor reference voltage.

[0011] To those skilled in the art, other apparatuses, devices, systems, methods, features and advantages of the application will be or will become apparent upon inspection of the following drawings and detailed description. It is intended to cover all such BRIEF DESCRIPTION OF DRAWINGS

[0012] The application can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the application. In the drawings, like reference numerals designate corresponding parts throughout the various views.

[0013] Figure 1is a system block diagram of an example of an implementation of an interleaved multi-level pulse frequency modulation (IMPFM) power converter according to the present disclosure.

[0014] Figure 2A is a plot of an example of an operating waveform of a reference voltage utilized by an Figure 1 IMPFM power converter shown in FIG. 1.

[0015] Figure 2B is a plot of an example of an operating waveform of a selected voltage range of output regulation of an Figure 1 IMPFM power converter shown in FIG. 1.

[0016] Figure 3 is a system block diagram of an example of an implementation of a 3-level IMPFM power converter acting as a 3-level PFM buck-boost converter according to the present disclosure.

[0017] Figure 4 is a plot of an example of an operating waveform of a reference voltage utilized by an Figure 1 IMPFM power converter shown in FIG. 1. DETAILED DESCRIPTION

[0018] Interleaved buck-boost converters are disclosed. The interleaved buck-boost converters include an input voltage terminal, an output filter, a main switch stage, a slave switch stage, and a controller. The input voltage terminal is configured to provide an input voltage from a voltage source, and the output filter includes an inductor having an input terminal and an output capacitor for an output voltage. The main switch stage includes a first flying capacitor, and the slave switch stage includes a second flying capacitor. The controller is configured to configure the main switch stage to a main magnetization switch state during a boost mode of operation in which the input terminal is charged to a first multiple of the input voltage in response to the output voltage being less than a first threshold voltage. The controller is further configured to configure the slave switch stage to a slave demagnetization switch state in which the input terminal is charged to a second multiple of the input voltage in response to a first flying capacitor voltage of the first flying capacitor being less than a second threshold voltage. The second multiple of the input voltage is less than the first multiple of the input voltage.

[0019] In the example, the controller may be further configured to configure the slave switching stage to a slave magnetization switch state during buck operation, in which the input terminal is charged to the input voltage in response to the output voltage being less than a third threshold voltage. Furthermore, the controller may be further configured to configure the master switching stage to a master demagnetization switch state, in which the input terminal discharges to ground in response to the second flying capacitor voltage being less than a fourth threshold voltage.

[0020] In the example, the interleaved buck-boost converter is shown as an interleaved multilevel pulse frequency modulation (IMPFM) power converter, and the master switching stage and the slave switching stage are shown as an interleaved multilevel power module (IMPM), wherein the master switching stage is shown as a first IMPM and the slave switching stage is shown as a second IMPM. The IMPM is also shown as part of a multilevel DC-DC MLDC converter (MLDC converter).

[0021] Specifically, turn to Figure 1 The diagram illustrates a system block diagram of an example implementation of an IMPFM power converter 100 according to the present disclosure. The IMPFM power converter 100 includes an MLDC converter 102 and a voltage level controller 104. The MLDC converter 102 includes multiple (N) switching stages (i.e., IMPFM), each having its own flying capacitor 110. For clarity, only the first flying capacitor CF1 110-1 and the Nth flying capacitor CF1 are shown in the MLDC converter 102. N 110-N. Generally, the voltage level controller 104 monitors the flying capacitor voltages, wherein if one of the selected flying capacitor voltages is less than the first flying capacitor reference voltage, the voltage level controller 104 switches the operating mode of the MLDC converter 102. The voltage level controller 104 also includes a voltage digital-to-analog converter (VDAC) 106.

[0022] The IMPFM 100 also includes a pulse frequency modulation (PFM) controller 108, and a series of sensors from CF1 monitor 112-1 to the Nth CF1 monitor. N The monitors 112-N include multiple flying capacitor monitors, an analog multiplexer (AMUX) 114, and a level indication controller 116. Furthermore, each flying capacitor has a corresponding flying capacitor voltage. For example, CF1 110-1 has a first flying capacitor voltage V. CF_1 118, and CF N 110-N has a flying capacitor voltage V CF_N 120.

[0023] In this example, the CF1 monitor 112-1 is in signal communication with the CF1 110-1, which electrically connects the CF1 monitor 112-1 to both the top plate and the bottom plate of the CF1 110-1. The CF N monitor 112-N is in signal communication with the CF N 110-N, which electrically connects the CF N monitor 112-N to both the top plate and the bottom plate of the CF N 110-N. Similarly, other flying capacitor monitors (not shown) of the plurality of flying capacitor monitors are also individually electrically connected to the top plate and the bottom plate of the corresponding flying capacitor. N 110-N. Similarly, other flying capacitor monitors (not shown) of the plurality of flying capacitor monitors are also individually electrically connected to the top plate and the bottom plate of the corresponding flying capacitor.

[0024] Each flying capacitor monitor measures the corresponding flying capacitor voltage of the corresponding flying capacitor and outputs the measured corresponding flying capacitor voltage to the AMUX 114. The AMUX 114 is a multiplexer that selects between a plurality of received analog input signals (i.e., the measured corresponding flying capacitor voltages) and forwards the selected measured flying capacitor voltage (V CF_DV ) 122 to the voltage level controller 104. The AMUX 114 selects V CF_DV 122 based on a selection signal 124 generated by the level indication controller 116. The level indication controller 116 also generates a voltage range of operating signals (V-range) 126 to drive the voltage range of operation of the MLDC converter 102.

[0025] Furthermore, in this example, the MLDC converter 102 is in signal communication with an input voltage source (V IN ) 128 and an output filter 130 at a LXO output node 132. The output filter 130 generates an output voltage (V Out ) 134 and includes an output inductor 136 and an output capacitor 138, and is in signal communication with a load that draws a load current (I L ) 140. Generally, V Out 134 is a filtered version of a switching node voltage (V LXO 139) at the LXO output node 132.

[0026] Furthermore, the voltage level controller 104 includes a first comparator 142 and a second comparator 144. The comparator 142 is configured to compare the flying capacitor voltage V CF_DV 122 to a reference flying capacitor voltage (V CF_Ref_1)146 and, in response, generates a flying capacitor comparison signal (COMP) 148 that is output to the PFM controller 108. The PFM controller 108 then sends a control signal 150 to the MLDC converter 102 to control and potentially switch the operating state of the MLDC converter 102. The second comparator 144 is configured to compare the output voltage V Out 134 to a reference output voltage (V Ref )152 and, in response, generates an output comparison signal (V U_N )154 that is also output to the PFM controller 108.

[0027] The voltage level controller 104 can include or be in signal communication with the VDAC 106. For example, the VDAC 106 can be in signal communication with the first threshold detector 142 and the optional second threshold detector 144. The VDAC 106 is configured to receive a control code 156 and, in response, generate the flying capacitor reference voltage V CF_Ref_1 146 and output the reference voltage V Ref 152.

[0028] In this example, the control system 158 is a PFM control loop that utilizes a timing-based method that utilizes a decreasing flying capacitor voltage (i.e., V CF_DV 118 to V CF_1 120 when selected as V CF_N 122 by the AMUX 114) to define a first switching interval for a discharge phase of a flying capacitor (i.e., CI 138) or a magnetization phase of LI 136 and enables the completion of the entire PFM control loop operating cycle through valley detection of the output of the MLDC converter 102 by the output filter 130 that includes the LC filter section (i.e., LI 136 and CI 138). This PFM control loop timing-based method defines a control scheme used by the level indication controller 116 to perform a level indication process for robust output regulation of the IMPFM power converter 100 over a range of available voltages. This allows the IMPFM power converter 100 to be configured over a wide power range where the ratio of V IN 128 to the output power V Out 134 can vary. By utilizing this method, the on-time of the IMPFM power converter 100 is controlled by the flying capacitor regulation (i.e., COMP 148) while the off-time is regulated by the outer loop output voltage regulation (i.e., V U_N154) Regulation. This allows for maintaining flying capacitor regulation over a wide range of operating conditions for the IMPFM power converter 100. Specifically, the timing-based method of this PFM control loop can be applied to higher operating voltage levels of the IMPFM power converter 100.

[0029] Furthermore, in this example, the level indicator controller 116 may optionally select different flying capacitor voltages via a selection signal 124 applied to the AMUX 114, the V-range 126 being determined by the level indicator controller 116 based on V... Ref 152 confirmed, V Ref 152 can be determined by VDAC 106 using control code 156, and V IN The 128 detector (not shown) can be combined with the VDAC 106 and control code 156 to generate V... IN A 128-level level indication method. Furthermore, if the voltage difference between the flying capacitor and the discharge cycle is kept as small as possible, the efficiency of the IMPFM power converter 100 can be maintained at approximately its maximum value.

[0030] As an example of operation, the MLDC converter 102 is controlled by the PFM controller 108 based on the detection results of two comparators (i.e., a first threshold detector 142 and an optional second threshold detector 144), which respectively generate an undervoltage condition indicating the output of the MLDC converter 102 (i.e., V at LXO node 132). LXO COMP 148 of 139) and V, which indicates the decreasing voltage of the flying capacitor during the magnetization (i.e., the discharge of the flying capacitor) cycle. U_N 154.

[0031] When the discharge of the flying capacitor (e.g., C) F1 110-1) Presents a value higher than the predefined threshold V CF_Ref_1 146 lower voltages (e.g., V) CF_1 At time 118), the first threshold detector switches and terminates the magnetization cycle. Therefore, the operation of the MLDC converter 102 is switched to the demagnetization cycle. When V Out 134 drops to reference voltage V Ref When the voltage drops below 152, the optional second threshold detector 144 (which acts as an undervoltage comparator) switches its logic state, and then the PFM control logic within the PFM controller 108 initiates a new operating cycle for the new magnetization cycle.

[0032] In this example, the IMPFM power converter 100 is shown as having multiple flying capacitor monitors (i.e., CF1 monitor 112-1 to CF1). NMultiple flying capacitors (i.e., CF1 110-1 to CF1) for signal communication with monitor 112-N N An interleaved scheme (110-N) is used. Therefore, in this interleaved scheme, the control system 158 can monitor multiple flying capacitors. As previously described, the level indication controller 116 specifies the active voltage range (i.e., V-range 126) for output regulation, and also selects (i.e., selection signal 124) AMUX 114 to adjust the voltage corresponding to the detected flying capacitor (i.e., V... CF_DV 122) Connected to the first threshold detector 142 of the magnetization cycle.

[0033] exist Figure 2A The diagram shows an example of an operating waveform 200 of a reference voltage utilized by an IMPFM power converter 100 according to this disclosure. The axis of the graph represents the reference voltage (i.e., V). Ref 152) and time 202. In this example, V Ref 152 can be used at the first reference voltage (V) REF_1 )204 and the second reference voltage (V REF_2 The variation is between 206.

[0034] Go to Figure 2B A graph illustrating an example of the operating waveform 208 for a selected voltage range of output regulation for an IMPFM power converter 100 according to this disclosure is shown. The axis of the graph is voltage (i.e., V). LXO 139) and time 202. In this example, the level indication controller 116 utilizes level indication technology, where control code 156 of VDAC 106 is used to specify the voltage range between two consecutive voltage levels for output regulation. In this example, at the LXO 132 output node, these two consecutive voltage levels are shown as for V REF_1 204 of V K 210 and V K-1 212 and the first average output voltage (V) Out_1 )214. Furthermore, at the LXO 132 output node, two other consecutive voltage levels are also shown for V. REF_2 206 of V K-2 216 and V K-3 218 and the second average output voltage (V) Out_2 )220.

[0035] In this example, V K 210 is greater than V REF_1 204, and V REF_1 204 is greater than V K-1 212. Furthermore, V K-2 216 is greater than VREF_2 206, and V REF_2 206 is greater than V K-3 218. From the figures, it should be understood that at points 222 and 224 the circuit (i.e., the IMPM) is being magnetized, and at points 226 and 228 the circuit is being demagnetized. Whenever the reference voltage (i.e., V REF_1 204 or V REF_2 206) is updated, the new voltage level will be assigned to the IMPM for the next voltage regulation period. In this example, the highest (or lowest) voltage of the specified level will be the LXO voltage (i.e., V LXO 139) for the magnetization (or demagnetization) period.

[0036] Figure 3 is a system block diagram of an example of a specific implementation of a 3-level IMPFM power converter 300 that functions as a 3-level PFM buck-boost converter in accordance with the present disclosure. In this example, the MLDC converter 102 of the 3-level IMPFM power converter 300 includes a first IMPM 302 and a second IMPM 304, where the first IMPM 302 can function as a "master" IMPM and the second IMPM 304 can function as a "slave" IMPM. The first IMPM 302 includes a first switch (SI) 306, a second switch (S2) 308, a third switch (S3) 310, a fourth switch (S4) 312, a fifth switch (S5) 314, and a CF1 110-1. The second IMPM 304 includes a first slave switch (S 1S ) 316, a second slave switch (S 2S ) 318, a third slave switch (S 3S ) 320, a fourth slave switch (S 4S ) 322, a fifth slave switch (S 5S ) 324, and a second flying capacitor (CF2) 110-2. The MLDC converter 102 also includes a sixth switch (S T ) having a conversion voltage (V T ) that passes between the CF1 110-1 and the CF2 110-2.

[0037] Similar to the example described with respect to Figure 1 , in this example, the V CF_1 monitor 112-1 monitors the V CF_1 118 of the CF1 110-1 and the second flying capacitor monitor (V CF_2 monitor) monitors the second flying capacitor voltage (V CF_2)326. The PFM controller 108 generates switching control signals 328 that control the operation of the switches in the first IMPM 302 and the second IMPM 304. Specifically, the PFM controller 108 can generate a first control signal (S S1 )330, a second control signal (S S2 )332, a third control signal (S S3 )334, a fourth control signal (not shown) that controls S4 312, a fifth control signal (not shown) that controls S5 314, a sixth control signal (not shown) that controls S 1S 316, a seventh control signal (not shown) that controls S 2S 318, an eighth control signal (not shown) that controls S 3S 320, and a ninth control signal (S 4S 322) that controls S S4S )336.

[0038] In this example, two flying capacitor voltage monitors V CF_1 monitor 112-1 and V CF_2 monitor 112-2 are introduced and multiplexed into a comparator (e.g., first threshold detector 142) within the voltage level controller 104 for a difference comparison of V CF_DV 122 and V CF_REF_1 146. In this example, only the corresponding IMPM that supports the magnetization cycle will be monitored for decreasing voltage of its corresponding flying capacitor.

[0039] When the VDAC 106 control code 156 is updated for a new V Out 134, two voltage levels are specified as the voltage range designated for output regulation (i.e., V-range 126). Table 1 shows the configuration of a 3-level IMPFM power converter 300 defined by the disclosed level indication method.

[0040]

[0041] Table 1

[0042] In this table, M is equal to the number of levels of the IMPFM power converter, and D is equal to the duty cycle. In Table 2, a truth table for the PFM control logic of the 3-level IMPFM power converter 300 is shown. The PFM control logic controls the power switch control within the two possible voltage ranges of output regulation. As shown in Table 2, when VOut 134 is between twice V In 118 and V In118 between, CF1 110-1 is monitored and switched for PFM operation in the output range between V In 118 and 0V.

[0043]

[0044] Table 2

[0045] Turning to Figure 4 FIG. 4 shows a flowchart of an example of a method 400 performed by the IMPFM power converter 100 according to the present disclosure.

[0046] The method 400 begins by monitoring 402 a flying capacitor voltage of a flying capacitor of an IMPM of the MLDC converter 102 with a flying capacitor monitor. The method 400 then compares 404 the flying capacitor voltage to a first flying capacitor reference voltage and switches 406 an operating state of the MLDC converter 102 if the flying capacitor voltage is less than the first flying capacitor reference voltage. The method 400 then ends.

[0047] It is to be understood that the various aspects or details of the disclosure can be changed without departing from the scope of the disclosure. Furthermore, the foregoing description is for the purpose of illustration only, and not for the purpose of limitation, as the disclosure is readily susceptible to other variations and embodiments as would be understood by those skilled in the art. The elements and acts of which the disclosure, including

[0048] As used in this document, the terms "includes," "including," "has," "having," and "contains," and variations thereof, are intended to be inclusive in a manner similar to the term "comprising" as an open transition word. Additionally, conditional language used herein, such as, among others, "can," "could," "might," or "may," unless specifically stated otherwise, are understood to present that certain examples include certain features, elements, and / or steps while other examples do not. Therefore, the use of such conditional language is not taken to mean that certain features, elements, and / or steps are in any way required in one or more examples. Unless otherwise noted, conjunctive language such as the phrase "at least one of' is understood to present that an item, term, etc. can be any one of the items, terms, etc. listed or a combination thereof.

[0049] In some alternative examples of implementations, one or more functions noted in a block can not occur in the order noted in the figure. For example, two blocks shown in succession can in some cases be executed substantially concurrently, or the two blocks can sometimes be executed in the reverse order, depending upon the functionality involved. Also, other blocks can be added in addition to the blocks shown in flowchart or block diagram. Further, the operations of the example processes can be illustrated in individual blocks or combined into several blocks, and / or some of the operations can be combined in a single operation. In some examples, the operations of the example processes can be performed in the order shown in the figures, in a different order, or concurrently. The operations of the processes depicted can also repeat with the same iteration or with different iterations. The example processes can be implemented using hardware, software, or combinations thereof, such as in hardware logic circuitry including discrete elements, such as logic gates, and / or any other hardware, software, firmware, or combination thereof. In software, the operations can be stored on one or more computer-readable media, which can be used to store the instructions to perform each of the operations. A computer-readable medium can be any available medium or combination of media that can be accessed by a computer. By way of example, and not limitation, computer-readable media can comprise RAM, ROM, EEPROM, FLASH memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of computer-executable instructions or data structures and that can be accessed by a computer. Computer-readable media also can be distributed over network-coupled computer systems so that the computer-readable media can be stored and executed using a distributed system of computers.

[0050] All of the methods and processes described above can be embodied in, and fully automated via, software code modules executed by one or more general purpose computers or processors. The code modules can be stored in any type of computer-readable storage medium or other computer storage device. Alternatively, some or all of the methods can be embodied in specialized computer hardware.

Claims

1. An interleaved buck-boost converter, comprising: An input voltage terminal, configured to receive an input voltage from a voltage source; An output filter, the output filter including an inductor having an input terminal and an output capacitor for an output voltage; The main switching stage includes a first flying capacitor; From the switching stage, the switching stage includes a second flying capacitor; and A controller configured to configure the main switching stage to a main magnetization switching state during boost operation mode, wherein the input terminals are charged to a first multiple of the input voltage in response to the output voltage being less than a first threshold voltage, and The controller is further configured to switch the slave stage to a slave demagnetization switch state, in which the input terminal is charged to a second multiple of the input voltage in response to the first flying capacitor voltage being less than a second threshold voltage. The second multiple of the input voltage is less than the first multiple of the input voltage.

2. The interleaved buck-boost converter according to claim 1, The controller is further configured to configure the slave switch stage to a slave magnetized switch state during buck operation, in which the input terminal is charged to the input voltage in response to the output voltage being less than a third threshold voltage, and The controller is further configured to configure the main switch stage to a main demagnetization switch state, in which the input terminal discharges to ground in response to the second flying capacitor voltage of the second flying capacitor being less than a fourth threshold voltage.

3. The interleaved buck-boost converter according to claim 1, wherein the controller comprises: A first comparator is configured to compare the output voltage with the first threshold voltage; and A second comparator is configured to compare the voltage of the first flying capacitor with the second threshold voltage.

4. The interleaved buck-boost converter according to claim 1, The main switch stage is a four-switch main switch stage, and The slave switch stage mentioned above is a four-switch slave switch stage.

5. The interleaved buck-boost converter according to claim 1, The first multiple of the input voltage is equal to twice the input voltage, and The second multiple of the input voltage is equal to one times the input voltage.

6. The interleaved buck-boost converter according to claim 1, The first multiple of the input voltage is equal to three times the input voltage, and The second multiple of the input voltage is equal to twice the input voltage.

7. The interleaved buck-boost converter according to claim 3, Also includes: A first flying capacitor monitor is configured to measure the voltage of the first flying capacitor; A second flying capacitor monitor is configured to measure the voltage of the second flying capacitor; and Analog multiplexer The controller includes a voltage level controller, which comprises a first comparator and a second comparator. The analog multiplexer communicates with the first flying capacitor monitor, the second flying capacitor monitor, and the voltage level controller. The analog multiplexer is configured to receive a measured first flying capacitor voltage and a second flying capacitor voltage, and to transmit the selected measured flying capacitor voltage to the voltage level controller.

8. The interleaved buck-boost converter according to claim 7, The controller further includes a pulse frequency modulation controller that communicates with the master switch stage, the slave switch stage, and the voltage level controller. During the boost operation mode, the pulse frequency modulation controller is configured to receive an output comparison signal generated by the voltage level controller, and in response, generate a first control signal input to the main switching stage. The output comparison signal is generated by comparing the output voltage with a first threshold voltage, and the first control signal configures the main switching stage to the main magnetizing switch state. The pulse frequency modulation controller is further configured to receive a flying capacitor comparison signal generated by the voltage level controller, and in response to generate a second control signal input to the slave switch stage, wherein the flying capacitor comparison signal is generated in response to the first flying capacitor voltage being less than the second threshold voltage, and the second control signal configures the slave switch stage to the slave demagnetization switch state.

9. The interleaved buck-boost converter according to claim 8, The pulse frequency modulation controller is further configured to switch the slave stage to a slave magnetized switch state during buck operation mode, and The pulse frequency modulation controller is further configured to configure the main switching stage to the main demagnetization switch state.

10. The interleaved buck-boost converter of claim 9, further comprising a voltage digital-to-analog converter (DAC) in signal communication with the voltage level controller, wherein the DAC is configured to receive control codes and, in response, generate a reference flying capacitor voltage.

11. The interleaved buck-boost converter of claim 10, wherein the first comparator is a first threshold detector and the second comparator is a second threshold detector.

12. The interleaved buck-boost converter according to claim 2, The main switching stage is a first interleaved multilevel power supply module, and the slave switching stage is a second interleaved multilevel power supply module. The first interleaved multilevel power supply module and the second interleaved multilevel power supply module are part of a multilevel DC-DC converter, and The multilevel DC-to-DC converter includes more interleaved multilevel power modules than the first interleaved multilevel power module and the second interleaved multilevel power module.

13. A control system for controlling an interleaved multilevel pulse frequency modulation power converter, the interleaved multilevel pulse frequency modulation power converter having an input voltage terminal configured to provide an input voltage from a voltage source, wherein the interleaved multilevel pulse frequency modulation power converter communicates with an output filter, the output filter including an inductor having an input terminal and an output capacitor for an output voltage, the control system comprising: A first flying capacitor monitor communicates with the first flying capacitor of the first interleaved multilevel power module of the multilevel DC-to-DC converter of the interleaved multilevel pulse frequency modulation power converter, wherein the first interleaved multilevel power module is the main switching stage. A second flying capacitor monitor communicates with the second flying capacitor of the second interleaved multilevel power module of the multilevel DC-DC converter, wherein the second interleaved multilevel power module is from the switching stage; A controller configured to configure the first interleaved multilevel power module to a main magnetization switch state during boost operation mode, wherein the input terminal is charged to a first multiple of the input voltage in response to the output voltage being less than a first threshold voltage, and The controller is further configured to configure the second interleaved multilevel power supply module to a demagnetization switch state, in which the input terminal is charged to a second multiple of the input voltage in response to the first flying capacitor voltage being less than a second threshold voltage, and The second multiple of the input voltage is less than the first multiple of the input voltage.

14. The control system according to claim 13, The controller is further configured to configure the slave switch stage to a slave magnetized switch state during buck operation, in which the input terminal is charged to the input voltage in response to the output voltage being less than a third threshold voltage, and The controller is further configured to configure the main switch stage to a main demagnetization switch state, in which the input terminal discharges to ground in response to the second flying capacitor voltage of the second flying capacitor being less than a fourth threshold voltage.

15. The control system of claim 14, wherein the controller comprises: A first comparator is configured to compare the output voltage with the first threshold voltage; and A second comparator is configured to compare the voltage of the first flying capacitor with the second threshold voltage.

16. The control system according to claim 13, The first multiple of the input voltage is equal to twice the input voltage, and The second multiple of the input voltage is equal to one times the input voltage.

17. The control system according to claim 13, The first multiple of the input voltage is equal to three times the input voltage, and The second multiple of the input voltage is equal to twice the input voltage.

18. The control system according to claim 15, Also includes: A first flying capacitor monitor is configured to measure the voltage of the first flying capacitor; A second flying capacitor monitor is configured to measure the voltage of the second flying capacitor; and Analog multiplexer The controller includes a voltage level controller, which comprises a first comparator and a second comparator. The analog multiplexer communicates with the first flying capacitor monitor, the second flying capacitor monitor, and the voltage level controller. The analog multiplexer is configured to receive a measured first flying capacitor voltage and measure a second flying capacitor voltage, and to transmit a selected measured flying capacitor voltage (122) to the voltage level controller.

19. The control system according to claim 18, The controller further includes a pulse frequency modulation controller that communicates with the master switch stage, the slave switch stage, and the voltage level controller. During the boost operation mode, the pulse frequency modulation controller is configured to receive an output comparison signal generated by the voltage level controller, and in response, generate a first control signal input to the main switching stage, wherein the output comparison signal is generated by comparing the output voltage with a first threshold voltage, and the first control signal configures the main switching stage to the main magnetizing switch state. The pulse frequency modulation controller is further configured to receive a flying capacitor comparison signal generated by the voltage level controller, and in response to generate a second control signal input to the slave switching stage, wherein the flying capacitor comparison signal is generated in response to the first flying capacitor voltage being less than the second threshold voltage, and the second control signal configures the slave switching stage to the slave demagnetization switch state. The pulse frequency modulation controller is further configured to configure the slave switch stage to the slave magnetized switch state during the buck operation mode, and The pulse frequency modulation controller is further configured to configure the main switching stage to the main demagnetization switch state.

20. The control system of claim 19, further comprising a voltage digital-to-analog converter (DAC) in signal communication with the voltage level controller, wherein the DAC is configured to receive control codes and, in response, generate a reference flying capacitor voltage.

21. A method for controlling an interleaved multilevel pulse frequency modulation power converter, the method comprising: The voltage of the first flying capacitor in the main switching stage is monitored using a first flying capacitor monitor. The voltage of the second flying capacitor from the switching stage is monitored using a second flying capacitor monitor. The main switching stage is configured to a main magnetization switching state, in which the input terminal is charged to a first multiple of the input voltage in response to the output voltage being less than a first threshold voltage, wherein the input terminal is part of an output filter having an inductor and an output capacitor for generating the output voltage, wherein the output filter communicates with the interleaved multilevel pulse frequency modulation power converter. The switch stage is configured to a demagnetization switch state, in which the input terminal is charged to a second multiple of the input voltage in response to the first flying capacitor voltage being less than a second threshold voltage, and The second multiple of the input voltage is less than the first multiple of the input voltage.

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