MMC type VSC-HVDC system full-bridge sub-module capacitor voltage improved equalization control method and system
By setting the allowable fluctuation range of capacitor voltage in the MMC-type VSC-HVDC system and performing voltage balancing control in the case of redundancy or insufficiency of bridge arm submodules, the problem of excessively high switching frequency in the traditional strategy is solved, and capacitor voltage balancing and switching frequency reduction are achieved.
Patent Information
- Application Number
- CN202511352015.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-22
- Publication Date
- 2025-12-12
AI Technical Summary
In MMC-type VSC-HVDC systems, traditional submodule capacitor voltage balancing strategies result in excessively high switching frequencies, causing significant switching losses and failing to effectively balance the conflict between submodule capacitor voltage and reducing switching frequency.
An improved equalization control method for the capacitor voltage of the full-bridge submodule is adopted. By setting the allowable fluctuation range of the capacitor voltage, and when there is redundancy or insufficiency in the bridge arm submodule, the over-limit submodule is positively or negatively connected respectively. Voltage equalization is performed in combination with the direction of the bridge arm current, thereby reducing the switching frequency.
Without adding extra hardware circuitry, the switching frequency of the switching devices was effectively reduced, and the capacitor voltage of the submodule was kept within the allowable fluctuation range, thus achieving capacitor voltage balance.
Smart Images
Figure CN121124589A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electrical engineering technology, and in particular to an improved equalization control method and system for the capacitor voltage of the full-bridge submodule in an MMC-type VSC-HVDC system. Background Technology
[0002] Modular multilevel converters (MMCs) are widely used in medium- and high-voltage high-power applications (such as flexible DC transmission systems, flexible multi-state switches in distribution networks, power routers, and offshore wind power grid-connected devices) due to their modular design, excellent harmonic suppression characteristics, low switching frequency operation, no need for additional filters, and strong engineering scalability. As MMC-HVDC technology develops towards higher voltage levels and larger capacities, the number of sub-modules (SMs) increases exponentially, making sub-module capacitor voltage balancing control a core technical challenge in MMC engineering applications. MMCs rely on a large number of series-connected sub-modules (SMs) for operation, and the average value of the floating capacitor voltage of each sub-module must be stabilized at its rated value to ensure system stability. However, there is a contradiction between achieving good capacitor voltage balancing and reducing the switching frequency of insulated-gate bipolar transistors (IGBTs). Traditional capacitor voltage balancing strategies are as follows: 1) Detecting the capacitor voltage value of each SM using a voltage sensor; 2) Detecting the current direction of each bridge arm using a current sensor; 3) Controlling the number of modules N that are connected in real-time according to the valve group level control output bridge arm. ref Assume that over a period of time, the arm current of phase a charges the submodule connected in that arm. In one control cycle, the controller charges the N phase with the lowest voltage. ref One submodule is charged to increase its voltage, while the remaining submodules are disconnected and their voltages remain unchanged. Due to the balancing control and the very short switching cycle, the voltage difference between the submodules is small, resulting in the charging submodules having a higher voltage than the disconnected submodules in this cycle. In the next control cycle, after voltage sorting, the N submodules with the lowest new voltages will be charged. ref Each submodule is charged, while previously disconnected submodules are put into operation in the current cycle. Clearly, this strategy causes the switching frequency of each submodule to approach the control cycle, resulting in significant switching losses. The controller sorts the bridge arm voltages. Traditional voltage balancing strategies unilaterally pursue the ultimate balance of capacitor voltages in the bridge arm submodules, without considering the switching frequency of the submodules. Summary of the Invention
[0003] In view of this, the purpose of the present invention is to provide an improved equalization control method and system for the full-bridge submodule capacitor voltage of an MMC-type VSC-HVDC system, which can significantly reduce the module switching frequency while strictly limiting the submodule capacitor voltage within its allowable fluctuation range.
[0004] To achieve the above objectives, the present invention adopts the following technical solution: an improved equalization control method for capacitor voltage of a full-bridge submodule in an MMC-type VSC-HVDC system, comprising a converter, wherein the converter comprises multiple bridge arms, each bridge arm comprises multiple identical full-bridge submodules, and each full-bridge submodule comprises a capacitor; the control method includes the following steps:
[0005] Step 1: Set the allowable fluctuation range of capacitor voltage to U. c_rate (100±ε)%, where U c_rate The capacitor voltage rating is given, and ε represents the allowable fluctuation error; the holding factor h is set to be higher than U. c_rate (100+ε)% of the number of full-bridge submodules N high and higher than U c_rate (100-ε)% of the number of full-bridge submodules N low ;
[0006] Step 2: If the bridge arm current charges the bridge arm full-bridge submodule and NN high -N ref If the voltage is ≥0, then the full-bridge sub-module with the lower capacitor voltage will be triggered first, and the full-bridge sub-module with the voltage higher than the specified range will be negatively connected; N ref Indicates the number of full-bridge sub-modules deployed in real time;
[0007] Step 3: If the bridge arm current charges the bridge arm full-bridge submodule and NN high -N ref If the voltage is less than 0, the full-bridge sub-module with the lower capacitor voltage will be triggered first, and the full-bridge sub-module with the voltage higher than the limit range will be partially negatively connected;
[0008] Step 4: If the bridge arm current discharges to the bridge arm full-bridge submodule and NN low -N ref If the voltage is ≥0, then the full-bridge sub-module with the higher capacitor voltage will be triggered first, and the full-bridge sub-module with the voltage below the limit range will be partially positively connected;
[0009] Step 5: If the bridge arm current discharges to the bridge arm full-bridge submodule and NN low -N ref If the voltage is ≥0, then the full-bridge sub-module with the higher capacitor voltage will be triggered first, and the full-bridge sub-module with the voltage below the limit range will be partially positively connected.
[0010] In a preferred embodiment, step 2 specifically includes: for capacitor voltages lower than U c_rate The (100-ε)% full-bridge submodule capacitor has its voltage value treated with a holding factor h to ensure its priority positive connection; for capacitor voltages between U... c_rate (100-ε)%~U c_rateFor full-bridge submodule capacitors with voltages between (100+ε)% and not activated in the previous control cycle, their voltage values are multiplied by a holding factor h, thereby reducing the likelihood of them being activated in the next control cycle; for capacitors with voltages higher than U... c_rate The voltage value of the (100+ε)% full-bridge submodule capacitor is multiplied by -h and used as a negative input to reduce the full-bridge submodule capacitor voltage; after sorting the processed capacitor voltage values, N... ref +min(NN high -N ref N high The full-bridge submodule with the smallest capacitor voltage is positively connected, and min(NN) is used. high -N ref N high () Full-bridge submodules with negative capacitor voltage values are negatively connected.
[0011] In a preferred embodiment, step 3 specifically includes: for capacitor voltages lower than U c_rate The (100-ε)% full-bridge submodule capacitors have their voltage values treated with a holding factor h to ensure priority positive input; for capacitors with voltages higher than U... c_rate For full-bridge submodule capacitors that are (100-ε)% and not activated in the previous control cycle, their voltage values are multiplied by a holding factor h to reduce the likelihood of them being activated in the next control cycle; after sorting the processed capacitor voltage values, N... ref The full-bridge submodule with the lowest capacitor voltage is put into operation.
[0012] In a preferred embodiment, step 4 specifically includes: for capacitor voltages higher than U c_rate (100+ε)% of the full-bridge submodule capacitors, their voltage values divided by the holding factor h ensure their priority activation; for capacitor voltages between U... c_rate (100-ε)%~U c_rate For full-bridge submodule capacitors with voltages between (100+ε)% and not activated in the previous control cycle, their voltage values are divided by the holding factor h, thereby reducing the likelihood of them being activated in the next control cycle; for capacitors with voltages below U... c_rate The voltage value of the (100-ε)% full-bridge submodule capacitor is multiplied by -h and used as a negative input to reduce the full-bridge submodule capacitor voltage; after sorting the processed capacitor voltage values, N... ref +min(NN low -N ref N low The full-bridge submodule with the largest capacitor voltage is positively connected, and min(NN) is used. low -N ref N low () Full-bridge submodules with negative capacitor voltage values are negatively connected.
[0013] In a preferred embodiment, step 5 specifically includes: for capacitor voltages higher than U c_rate (100+ε)% of the full-bridge submodule capacitors, their voltage values divided by the holding factor h ensure their priority activation; for capacitors with voltages greater than U... c_rate For full-bridge submodule capacitors that are (100+ε)% and not activated in the previous control cycle, their voltage values are divided by the holding factor h to reduce the likelihood of them being activated in the next control cycle; after sorting the processed capacitor voltage values, N... ref The full-bridge submodule with the largest capacitor voltage is being put into operation.
[0014] This invention also provides an improved equalization control system for the full-bridge submodule capacitor voltage of an MMC-type VSC-HVDC system, which runs the improved equalization control method for the full-bridge submodule capacitor voltage of the MMC-type VSC-HVDC system; the converter includes 6 bridge arms; each bridge arm is composed of N identical full-bridge submodules, inductors and equivalent resistances connected in series.
[0015] In a preferred embodiment, the full-bridge submodule includes a first insulated-gate bipolar transistor (IGBT) T3, a second IGBT T4, a third IGBT T5, a fourth IGBT T6, a first anti-parallel diode D3, a second anti-parallel diode D4, a third anti-parallel diode D5, a fourth anti-parallel diode D6, and a full-bridge submodule capacitor C0; the first anti-parallel diode D3, the second anti-parallel diode D4, the third anti-parallel diode D5, and the fourth anti-parallel diode D6 are respectively connected in parallel to the first IGBT... Transistor T3, second insulated-gate bipolar transistor T4, third insulated-gate bipolar transistor T5, and fourth insulated-gate bipolar transistor T6; first insulated-gate bipolar transistor T3 and second insulated-gate bipolar transistor T4 are connected in series; third insulated-gate bipolar transistor T5 and fourth insulated-gate bipolar transistor T6 are connected in series; the full-bridge submodule capacitor C0 is connected in parallel between the first insulated-gate bipolar transistor T3 and the second insulated-gate bipolar transistor T4 and the third insulated-gate bipolar transistor T5 and the fourth insulated-gate bipolar transistor T6.
[0016] In a preferred embodiment, the full-bridge submodule has four operating states: positive engagement state, negative engagement state, bypass state, and locked state.
[0017] When the first insulated-gate bipolar transistor T3 and the fourth insulated-gate bipolar transistor T6 are given an on signal, and the second insulated-gate bipolar transistor T4 and the third insulated-gate bipolar transistor T5 are given an off signal, the system is in the positive input state. Based on the current flow direction of the full-bridge submodule, there are two operating modes: mode (a) and mode (b). In mode (a), the first anti-parallel diode D3 and the fourth anti-parallel diode D6 are turned on, while the first insulated-gate bipolar transistor T3 and the fourth insulated-gate bipolar transistor T6 are subjected to reverse voltage, despite the application of... When the signal is turned on, the current of the full-bridge submodule is still off. The current charges the capacitor through the first anti-parallel diode D3 and the fourth anti-parallel diode D6, and the output voltage is the capacitor voltage. In mode (b), the first insulated-gate bipolar transistor T3 and the fourth insulated-gate bipolar transistor T6 are turned on. The first anti-parallel diode D3 and the fourth anti-parallel diode D6 are turned off due to reverse voltage. The current of the full-bridge submodule discharges the capacitor through the first insulated-gate bipolar transistor T3 and the fourth insulated-gate bipolar transistor T6, and the output voltage is the capacitor voltage.
[0018] In a preferred embodiment, when the second insulated-gate bipolar transistor T4 and the third insulated-gate bipolar transistor T5 are given an on signal, and the first insulated-gate bipolar transistor T3 and the fourth insulated-gate bipolar transistor T6 are given an off signal, this is called the negative input state. Based on the current flow direction of the full-bridge submodule, this state is divided into two operating modes: mode (c) and mode (d). In mode (c), the second insulated-gate bipolar transistor T4 and the third insulated-gate bipolar transistor T5 are turned on, while the second anti-parallel diode D4 and the third anti-parallel diode D5 are subjected to reverse current. In mode (d), although the circuit is in the off state when the turn-on signal is applied, the current of the full-bridge submodule charges the capacitor through the second insulated-gate bipolar transistor T4 and the third insulated-gate bipolar transistor T5, and the output voltage is the negative capacitor voltage. In mode (d), the second anti-parallel diode D4 and the third anti-parallel diode D5 are turned on, and the second insulated-gate bipolar transistor T4 and the third insulated-gate bipolar transistor T5 are in the off state due to the reverse voltage. The current of the full-bridge submodule discharges the capacitor through the second anti-parallel diode D4 and the third anti-parallel diode D5, and the output voltage is the negative capacitor voltage.
[0019] In a preferred embodiment, when the second insulated-gate bipolar transistor T4 and the fourth insulated-gate bipolar transistor T6 are turned off and the first insulated-gate bipolar transistor T3 and the third insulated-gate bipolar transistor T5 are turned on, or when the first insulated-gate bipolar transistor T3 and the third insulated-gate bipolar transistor T5 are turned off and the second insulated-gate bipolar transistor T4 and the fourth insulated-gate bipolar transistor T6 are turned on, this is called the bypass state; according to the switching state, there are two operating modes, namely mode (e) and mode (f); for mode (e), when current flows in from point A, the first anti-parallel diode D3 and the third insulated-gate bipolar transistor T5 are turned on, while the first insulated-gate bipolar transistor T3 and the third anti-parallel diode D5 are turned off due to reverse voltage, the full-bridge submodule current bypasses the capacitor, and the output voltage is 0; when When current flows out from point A, the first insulated-gate bipolar transistor T3 and the third anti-parallel diode D5 are turned on. Because they are under reverse voltage, the first anti-parallel diode D3 and the third insulated-gate bipolar transistor T5 are turned off, and the full-bridge submodule current bypasses the capacitor, resulting in an output voltage of 0. In mode (f), when current flows in from point A, the second insulated-gate bipolar transistor T4 and the fourth anti-parallel diode D6 are turned on. Because they are under reverse voltage, the second anti-parallel diode D4 and the fourth insulated-gate bipolar transistor T6 are turned off, and the full-bridge submodule current bypasses the capacitor, resulting in an output voltage of 0. When current flows out from point A, the second anti-parallel diode D4 and the fourth insulated-gate bipolar transistor T6 are turned on. Because they are under reverse voltage, the second insulated-gate bipolar transistor T4 and the fourth anti-parallel diode D6 are turned off, and the full-bridge submodule current bypasses the capacitor, resulting in an output voltage of 0.
[0020] When a turn-off signal is applied to the first insulated-gate bipolar transistor T3, the second insulated-gate bipolar transistor T4, the third insulated-gate bipolar transistor T5, and the fourth insulated-gate bipolar transistor T6, this is called the latch-up state. Based on the current flow direction of the full-bridge submodule, there are two operating modes: mode (g) and mode (h). In mode (e), when current flows in from point A, the first anti-parallel diode D3 and the fourth anti-parallel diode D6 are turned on, while the first insulated-gate bipolar transistor T3 and the fourth insulated-gate bipolar transistor T6 are subjected to reverse voltage. Although the applied turn-on signal is still in the off state, the full-bridge submodule current charges the capacitor through the first anti-parallel diode D3 and the fourth anti-parallel diode D6, and the output voltage is the capacitor voltage; for mode (h), the second anti-parallel diode D4 and the third anti-parallel diode D5 are turned on, and the second insulated-gate bipolar transistor T4 and the third insulated-gate bipolar transistor T5 are in the off state due to reverse voltage, and the full-bridge submodule current discharges the capacitor through the second anti-parallel diode D4 and the third anti-parallel diode D5, and the output voltage is the negative capacitor voltage.
[0021] Compared with the prior art, the present invention has the following beneficial effects: The present invention focuses on voltage balancing of the over-limit submodule capacitor voltage. When there is redundancy in the bridge arm submodule, the over-limit submodule is positively or negatively connected to balance the submodule capacitor voltage. When the bridge arm submodule redundancy is insufficient, some over-limit submodules are voltage balanced according to the bridge arm current direction according to rules. Thus, the voltage of the bridge arm submodule is effectively balanced while reducing the switching frequency. Without adding additional hardware circuits, the traditional voltage sorting method is adjusted in a simple way, which greatly reduces the switching frequency of the switching devices while strictly limiting the full bridge submodule capacitor voltage within the allowable fluctuation range. Attached Figure Description
[0022] Figure 1 This is a converter topology diagram of a preferred embodiment of the present invention;
[0023] Figure 2 This is a topology diagram of the full-bridge submodule of a preferred embodiment of the present invention;
[0024] Figure 3 This is a schematic diagram of the full-bridge submodule in the active state of a preferred embodiment of the present invention, wherein (a) is T3=1, T4=0, T5=0, T6=1, and (b) is T3=1, T4=0, T5=0, T6=1;
[0025] Figure 4 This is a schematic diagram of the negative input state of the full-bridge submodule according to a preferred embodiment of the present invention; wherein, (c) is T3=0, T4=1, T5=1, T6=0, and (d) is T3=0, T4=1, T5=1, T6=0;
[0026] Figure 5 This is a schematic diagram of the bypass state of the full-bridge submodule according to a preferred embodiment of the present invention; wherein, (e) is T3=1, T4=0, T5=1, T6=0, and (f) is T3=0, T4=1, T5=0, T6=1;
[0027] Figure 6 This is a schematic diagram of the locked state of the full-bridge submodule according to a preferred embodiment of the present invention; wherein, (g) is T3=0, T4=0, T5=0, T6=0, and (h) is T3=0, T4=0, T5=0, T6=0. Detailed Implementation
[0028] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0029] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0030] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations according to this application; as used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise; furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.
[0031] An improved equalization control method for the capacitor voltage of the full-bridge submodule in an MMC-type VSC-HVDC system (reference) Figure 1-6 The system includes a converter, which comprises six bridge arms; each bridge arm consists of N identical full-bridge submodules, inductors, and equivalent resistances connected in series; each full-bridge submodule includes a capacitor; the control method includes the following steps:
[0032] Step 1: Set the allowable fluctuation range of capacitor voltage to U. c_rate (100±ε)%, where U c_rate The capacitor voltage rating is given, and ε represents the allowable fluctuation error; a holding factor h (h is a constant slightly greater than 1) is set, which is higher than U. c_rate The number of submodules N (100+ε)% high and higher than U c_rate The number of submodules N (100-ε)% low .
[0033] Step 2: If the bridge arm current charges the bridge arm submodule and NN high -N ref If the voltage is ≥0, then the submodule with the lower capacitor voltage will be triggered first, and the submodule with the voltage higher than the limit range will be negatively connected. For capacitor voltages lower than U... c_rate The (100-ε)% submodule capacitor has its voltage value adjusted by a retention factor h to ensure its priority positive connection. For capacitor voltages between U... c_rate (100-ε)%~U c_rate For submodule capacitors with voltages between (100+ε)% and not activated in the previous control cycle, their voltage values are multiplied by a holding factor h, thereby reducing the likelihood of them being activated in the next control cycle. For capacitors with voltages higher than U... c_rate The voltage value of the (100+ε)% submodule capacitor is multiplied by -h and used as a negative input to reduce the submodule capacitor voltage. After sorting the processed capacitor voltage values, N... ref +min(NN high-N ref N high The submodule with the smallest capacitor voltage is positively connected, and min(NN) is used. high -N ref N high Submodules with negative capacitor voltage values are negatively connected.
[0034] Step 3: If the bridge arm current charges the bridge arm submodule and NN high -N ref If the value is less than 0, then the submodule with the lower capacitor voltage will be triggered first, and the submodule with the voltage higher than the specified range will be partially negatively connected. For submodules with capacitor voltage lower than U... c_rate The (100-ε)% submodule capacitor has its voltage value adjusted by a retention factor h to ensure priority positive input. For capacitors with voltages higher than U... c_rate For submodule capacitors that are (100-ε)% and not activated in the previous control cycle, their voltage values are multiplied by a holding factor h, thereby reducing the likelihood of them being activated in the next control cycle. After sorting the processed capacitor voltage values, N... ref The submodule with the lowest capacitor voltage is put into operation.
[0035] Step 4: If the bridge arm current discharges to the bridge arm submodule and NN low -N ref If the voltage is ≥0, the submodule with the higher capacitor voltage will be triggered first, and submodules with voltages below the specified range will be partially positively connected. For submodules with capacitor voltages higher than U... c_rate For submodule capacitors with a voltage of (100+ε)%, the voltage value divided by the holding factor h ensures their priority activation. For capacitors with a voltage between U... c_rate (100-ε)%~U c_rate For submodule capacitors with voltages between (100+ε)% and not activated in the previous control cycle, their voltage values are divided by the holding factor h, thus reducing the likelihood of them being activated in the next control cycle. For capacitors with voltages below U... c_rate The voltage value of the (100-ε)% submodule capacitor is multiplied by -h and used as a negative input to reduce the submodule capacitor voltage. After sorting the processed capacitor voltage values, N... ref +min(NN low -N ref N low The submodule with the largest capacitor voltage is positively connected, and min(NN) is used. low -N ref N low Submodules with negative capacitor voltage values are negatively connected.
[0036] Step 5: If the bridge arm current discharges to the bridge arm submodule and NN low -Nref If the voltage is ≥0, the submodule with the higher capacitor voltage will be triggered first, and submodules with voltages below the specified range will be partially positively connected. For submodules with capacitor voltages higher than U... c_rate For submodule capacitors with a voltage of (100+ε)%, the voltage value divided by the holding factor h ensures their priority activation. For capacitors with a voltage greater than U... c_rate For submodule capacitors that are (100+ε)% and not activated in the previous control cycle, their voltage values are divided by the holding factor h, thus reducing the likelihood of them being activated in the next control cycle. After sorting the processed capacitor voltage values, N... ref The submodule with the largest capacitor voltage is put into operation.
[0037] The above describes the full-bridge submodule capacitor voltage optimization and balancing strategy for a three-phase modular multilevel converter DC transmission system proposed in this invention. This balancing strategy focuses on the voltage of submodule capacitors that exceed the limit. When there is redundancy in the bridge arm submodules, the over-limit submodules are connected positively or negatively to balance their capacitor voltages. When the bridge arm submodules lack redundancy, some over-limit submodules are balanced according to rules based on the direction of the bridge arm current. This effectively balances the voltage of the bridge arm submodules while reducing the switching frequency.
[0038] exist Figure 2 In the diagram, T3, T4, T5, and T6 represent the first, second, third, and fourth insulated-gate bipolar transistors (IGBTs), respectively; D3, D4, D5, and D6 represent the first, second, third, and fourth anti-parallel diodes, respectively; and C0 represents the submodule's DC capacitor. c Represents capacitor voltage, u sm i represents the voltage across the submodule. sm This represents the current flowing into the submodule. (By...) Figure 2 It is evident that each submodule is connected to the main circuit topology via AB series connection, and the MMC supports the bus voltage through the capacitor voltage in each submodule.
[0039] Analysis by Figures 3-6 As shown, the full-bridge submodule has four operating states: positive input state, negative input state, bypass state, and locked state.
[0040] When an on signal is applied to T3 and T6, and an off signal is applied to T4 and T5, this is called the positive on state. Based on the direction of current flow in the submodule, it can be divided into two operating modes: mode (a) and mode (b). In mode (a), D3 and D6 are on, while T3 and T6 are subjected to reverse voltage. Despite the applied on signal, they remain off. The submodule current charges the capacitor through D3 and D6, and the output voltage is the capacitor voltage. In mode (b), T3 and T6 are on, while D3 and D6 are off due to the reverse voltage. The submodule current discharges the capacitor through T3 and T6, and the output voltage is the capacitor voltage.
[0041] When an on signal is applied to T4 and T5, and an off signal is applied to T3 and T6, this is called the negative on state. Based on the direction of current flow in the submodule, this can be divided into two operating modes: mode (c) and mode (d). In mode (c), T4 and T5 are on, while D4 and D5 are subjected to reverse voltage. Despite the applied on signal, they remain off. The submodule current charges the capacitors through T4 and T5, resulting in a negative capacitor voltage at output. In mode (d), D4 and D5 are on, while T4 and T5 are off due to the reverse voltage. The submodule current discharges the capacitors through D4 and D5, resulting in a negative capacitor voltage at output.
[0042] When a turn-off signal is applied to T4 and T6 while an on signal is applied to T3 and T5, or vice versa, this is called the bypass state. Based on the switching state, there are two operating modes: mode (e) and mode (f). In mode (e), when current flows into point A, D3 and T5 are turned on, while T3 and D5 are turned off due to reverse voltage. The submodule current bypasses the capacitor, and the output voltage is 0. When current flows out of point A, T3 and D5 are turned on, but are turned off due to reverse voltage. The submodule current bypasses the capacitor, and the output voltage is 0. In mode (f), when current flows into point A, T4 and D6 are turned on, while D4 and T6 are turned off due to reverse voltage. The submodule current bypasses the capacitor, and the output voltage is 0. When current flows out from point A, D4 and T6 are turned on, while T4 and D6 are turned off due to reverse voltage. The submodule current bypasses the capacitor, and the output voltage is 0.
[0043] When a turn-off signal is applied to T3, T4, T5, and T6, this is called the latched state. Based on the direction of current flow in the submodule, it can be divided into two operating modes: mode (g) and mode (h). In mode (e), when current flows in from point A, D3 and D6 are turned on, while T3 and T6 are subjected to reverse voltage. Despite the applied turn-on signal, they remain in the off state. The submodule current charges the capacitor through D3 and D6, and the output voltage is the capacitor voltage. In mode (h), D4 and D5 are turned on, while T4 and T5 are in the off state due to reverse voltage. The submodule current discharges the capacitor through D4 and D5, and the output voltage is the negative capacitor voltage.
Claims
1. An improved equalization control method for the capacitor voltage of a full-bridge submodule in an MMC-type VSC-HVDC system, characterized in that, The system includes a converter comprising multiple bridge arms, each bridge arm comprising multiple identical full-bridge submodules, each full-bridge submodule comprising a capacitor; the control method includes the following steps: Step 1: Set the allowable fluctuation range of capacitor voltage to U. c_rate (100±ε)%, where U c_rate The capacitor voltage rating is given, and ε represents the allowable fluctuation error; the holding factor h is set to be higher than U. c_rate (100+ε)% of the number of full-bridge submodules N high and higher than U c_rate (100-ε)% of the number of full-bridge submodules N low ; Step 2: If the bridge arm current charges the bridge arm full-bridge submodule and NN high -N ref If the voltage is ≥0, then the full-bridge sub-module with the lower capacitor voltage will be triggered first, and the full-bridge sub-module with the voltage higher than the specified range will be negatively connected; N ref Indicates the number of full-bridge sub-modules deployed in real time; Step 3: If the bridge arm current charges the bridge arm full-bridge submodule and NN high -N ref If the voltage is less than 0, the full-bridge sub-module with the lower capacitor voltage will be triggered first, and the full-bridge sub-module with the voltage higher than the limit range will be partially negatively connected; Step 4: If the bridge arm current discharges to the bridge arm full-bridge submodule and NN low -N ref If the voltage is ≥0, then the full-bridge sub-module with the higher capacitor voltage will be triggered first, and the full-bridge sub-module with the voltage below the limit range will be partially positively connected; Step 5: If the bridge arm current discharges to the bridge arm full-bridge submodule and NN low -N ref If the voltage is ≥0, then the full-bridge sub-module with the higher capacitor voltage will be triggered first, and the full-bridge sub-module with the voltage below the limit range will be partially positively connected.
2. The improved equalization control method for the capacitor voltage of the full-bridge submodule of the MMC-type VSC-HVDC system according to claim 1, characterized in that, Step 2 specifically includes: for capacitor voltages lower than U... c_rate The (100-ε)% full-bridge submodule capacitor has its voltage value treated with a holding factor h to ensure its priority positive connection; for capacitor voltages between U... c_rate (100-ε)%~U c_rate For full-bridge submodule capacitors with voltages between (100+ε)% and not activated in the previous control cycle, their voltage values are multiplied by a holding factor h, thereby reducing the likelihood of them being activated in the next control cycle; for capacitors with voltages higher than U... c_rate The voltage value of the (100+ε)% full-bridge submodule capacitor is multiplied by -h and used as a negative input to reduce the full-bridge submodule capacitor voltage; after sorting the processed capacitor voltage values, N... ref +min(NN high -N ref N high The full-bridge submodule with the smallest capacitor voltage is positively connected, and min(NN) is used. high -N ref N high () Full-bridge submodules with negative capacitor voltage values are negatively connected.
3. The improved equalization control method for the capacitor voltage of the full-bridge submodule of the MMC-type VSC-HVDC system according to claim 1, characterized in that, Step 3 specifically includes: for capacitor voltages lower than U... c_rate The (100-ε)% full-bridge submodule capacitors have their voltage values treated with a holding factor h to ensure priority positive input; for capacitors with voltages higher than U... c_rate For full-bridge submodule capacitors that are (100-ε)% and not activated in the previous control cycle, their voltage values are multiplied by a holding factor h to reduce the likelihood of them being activated in the next control cycle; after sorting the processed capacitor voltage values, N... ref The full-bridge submodule with the lowest capacitor voltage is put into operation.
4. The improved equalization control method for the capacitor voltage of the full-bridge submodule of the MMC-type VSC-HVDC system according to claim 1, characterized in that, Step 4 specifically includes: for capacitor voltages higher than U... c_rate (100+ε)% of the full-bridge submodule capacitors, their voltage values divided by the holding factor h ensure their priority activation; for capacitor voltages between U... c_rate (100-ε)%~U c_rate For full-bridge submodule capacitors with voltages between (100+ε)% and not activated in the previous control cycle, their voltage values are divided by the holding factor h, thereby reducing the likelihood of them being activated in the next control cycle; for capacitors with voltages below U... c_rate The voltage value of the (100-ε)% full-bridge submodule capacitor is multiplied by -h and used as a negative input to reduce the full-bridge submodule capacitor voltage; after sorting the processed capacitor voltage values, N... ref +min(NN low -N ref N low The full-bridge submodule with the largest capacitor voltage is positively connected, and min(NN) is used. low -N ref N low () Full-bridge submodules with negative capacitor voltage values are negatively connected.
5. The improved equalization control method for the capacitor voltage of the full-bridge submodule of the MMC-type VSC-HVDC system according to claim 1, characterized in that, Step 5 specifically includes: for capacitor voltages higher than U... c_rate (100+ε)% of the full-bridge submodule capacitors, their voltage values divided by the holding factor h ensure their priority activation; for capacitors with voltages greater than U... c_rate For full-bridge submodule capacitors that are (100+ε)% and not activated in the previous control cycle, their voltage values are divided by the holding factor h to reduce the likelihood of them being activated in the next control cycle; after sorting the processed capacitor voltage values, N... ref The full-bridge submodule with the largest capacitor voltage is being put into operation.
6. An improved equalization control system for the capacitor voltage of the full-bridge submodule of the MMC-type VSC-HVDC system, characterized in that... The improved equalization control method for full-bridge submodule capacitor voltage of the MMC-type VSC-HVDC system described in any one of claims 1-5 is implemented; the converter includes 6 bridge arms; each bridge arm is composed of N identical full-bridge submodules, inductors and equivalent resistances connected in series.
7. The improved equalization control system for full-bridge submodule capacitor voltage of the MMC-type VSC-HVDC system according to claim 6, characterized in that, The full-bridge submodule includes a first insulated-gate bipolar transistor (IGBT) T3, a second IGBT T4, a third IGBT T5, a fourth IGBT T6, a first anti-parallel diode D3, a second anti-parallel diode D4, a third anti-parallel diode D5, a fourth anti-parallel diode D6, and a full-bridge submodule capacitor C0; the first anti-parallel diode D3, the second anti-parallel diode D4, the third anti-parallel diode D5, and the fourth anti-parallel diode D6 are respectively connected in parallel to the first IGBT T3. The system comprises a second insulated-gate bipolar transistor (IGBT) T4, a third insulated-gate bipolar transistor (IGBT) T5, and a fourth insulated-gate bipolar transistor (IGBT) T6; a first IGBT T3 connected in series with the second IGBT T4; a third IGBT T5 connected in series with the fourth IGBT T6; and a full-bridge submodule capacitor C0 connected in parallel between the first IGBT T3, the second IGBT T4, the third IGBT T5, and the fourth IGBT T6.
8. The improved equalization control system for full-bridge submodule capacitor voltage of the MMC-type VSC-HVDC system according to claim 7, characterized in that, The full-bridge submodule has four operating states: positive engagement, negative engagement, bypass, and locked. When the first insulated-gate bipolar transistor T3 and the fourth insulated-gate bipolar transistor T6 are given an on signal, and the second insulated-gate bipolar transistor T4 and the third insulated-gate bipolar transistor T5 are given an off signal, the system is in the positive input state. Based on the current flow direction of the full-bridge submodule, there are two operating modes: mode (a) and mode (b). In mode (a), the first anti-parallel diode D3 and the fourth anti-parallel diode D6 are turned on, while the first insulated-gate bipolar transistor T3 and the fourth insulated-gate bipolar transistor T6 are subjected to reverse voltage, despite the application of... When the signal is turned on, the current of the full-bridge submodule is still off. The current charges the capacitor through the first anti-parallel diode D3 and the fourth anti-parallel diode D6, and the output voltage is the capacitor voltage. In mode (b), the first insulated-gate bipolar transistor T3 and the fourth insulated-gate bipolar transistor T6 are turned on. The first anti-parallel diode D3 and the fourth anti-parallel diode D6 are turned off due to reverse voltage. The current of the full-bridge submodule discharges the capacitor through the first insulated-gate bipolar transistor T3 and the fourth insulated-gate bipolar transistor T6, and the output voltage is the capacitor voltage.
9. The improved equalization control system for full-bridge submodule capacitor voltage of the MMC-type VSC-HVDC system according to claim 8, characterized in that, When the second insulated-gate bipolar transistor T4 and the third insulated-gate bipolar transistor T5 are given an on signal, and the first insulated-gate bipolar transistor T3 and the fourth insulated-gate bipolar transistor T6 are given an off signal, this is called the negative input state. Based on the current flow direction of the full-bridge submodule, it is divided into two operating modes: mode (c) and mode (d). In mode (c), the second insulated-gate bipolar transistor T4 and the third insulated-gate bipolar transistor T5 are turned on, while the second anti-parallel diode D4 and the third anti-parallel diode D5 are subjected to reverse voltage, although... When the signal is turned on, the full-bridge submodule current charges the capacitor through the second insulated-gate bipolar transistor T4 and the third insulated-gate bipolar transistor T5, and the output voltage is a negative capacitor voltage. In mode (d), the second anti-parallel diode D4 and the third anti-parallel diode D5 are turned on, and the second insulated-gate bipolar transistor T4 and the third insulated-gate bipolar transistor T5 are turned off due to reverse voltage. The full-bridge submodule current discharges the capacitor through the second anti-parallel diode D4 and the third anti-parallel diode D5, and the output voltage is a negative capacitor voltage.
10. The MMC-type VSC-HVDC system full-bridge submodule capacitor voltage improved equalization control system according to claim 7, characterized in that, When the second insulated-gate bipolar transistor T4 and the fourth insulated-gate bipolar transistor T6 are turned off and the first insulated-gate bipolar transistor T3 and the third insulated-gate bipolar transistor T5 are turned on, or when the first insulated-gate bipolar transistor T3 and the third insulated-gate bipolar transistor T5 are turned off and the second insulated-gate bipolar transistor T4 and the fourth insulated-gate bipolar transistor T6 are turned on, this is called the bypass state. Based on the switch state, there are two operating modes: mode (e) and mode (f). In mode (e), when current flows into point A, the first anti-parallel diode D3 and the third insulated-gate bipolar transistor T5 are turned on, while the first insulated-gate bipolar transistor T3 and the third anti-parallel diode D5 are turned off due to reverse voltage. The full-bridge submodule current bypasses the capacitor, and the output voltage is 0. When current flows out of point A, the first insulated-gate bipolar transistor T3 and the third anti-parallel diode D5 are turned on, while the first anti-parallel diode D3 and the third insulated-gate bipolar transistor T5 are turned off due to reverse voltage. The full-bridge submodule... When current flows into the capacitor in mode (f), the second insulated-gate bipolar transistor T4 and the fourth anti-parallel diode D6 are turned on, while the second anti-parallel diode D4 and the fourth insulated-gate bipolar transistor T6 are turned off due to reverse voltage. The full-bridge submodule current bypasses the capacitor, resulting in a zero output voltage. When current flows out of the capacitor in mode (f), the second anti-parallel diode D4 and the fourth insulated-gate bipolar transistor T6 are turned on, while the second insulated-gate bipolar transistor T4 and the fourth anti-parallel diode D6 are turned off due to reverse voltage. The full-bridge submodule current bypasses the capacitor, resulting in a zero output voltage. When a turn-off signal is applied to the first insulated-gate bipolar transistor T3, the second insulated-gate bipolar transistor T4, the third insulated-gate bipolar transistor T5, and the fourth insulated-gate bipolar transistor T6, this is called the latch-up state. Based on the current flow direction of the full-bridge submodule, there are two operating modes: mode (g) and mode (h). In mode (e), when current flows in from point A, the first anti-parallel diode D3 and the fourth anti-parallel diode D6 are turned on, while the first insulated-gate bipolar transistor T3 and the fourth insulated-gate bipolar transistor T6 are subjected to reverse voltage. Although the applied turn-on signal is still in the off state, the full-bridge submodule current charges the capacitor through the first anti-parallel diode D3 and the fourth anti-parallel diode D6, and the output voltage is the capacitor voltage; for mode (h), the second anti-parallel diode D4 and the third anti-parallel diode D5 are turned on, and the second insulated-gate bipolar transistor T4 and the third insulated-gate bipolar transistor T5 are in the off state due to reverse voltage, and the full-bridge submodule current discharges the capacitor through the second anti-parallel diode D4 and the third anti-parallel diode D5, and the output voltage is the negative capacitor voltage.