Instruction execution method, device, equipment and storage medium in multiple scenarios

Abstract

The present application discloses a method, apparatus, device and storage medium for executing instructions in multiple scenarios. The method comprises: obtaining at least one instruction corresponding to multiple scenarios in a current execution cycle of an execution thread; executing the at least one instruction in the current execution cycle, and if the at least one instruction includes a delay instruction, determining a target execution cycle corresponding to the next instruction of the delay instruction; after the current execution cycle ends, taking the next execution cycle as the current execution cycle, and returning to the step of obtaining at least one instruction corresponding to multiple scenarios in the current execution cycle of the execution thread; wherein, when the current execution cycle reaches the target execution cycle, executing the next instruction of the delay instruction, thereby greatly improving the efficiency of instruction execution.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a method, apparatus, device and storage medium for executing instructions in multiple scenarios. Background Art

[0002] Usually, when a scene triggers multiple actions continuously, a delay operation needs to be added between the actions. For example, for the scene "turn on the TV box → wait for 3 seconds (turn on the TV) → switch to play news", there is a 3-second delay operation between turning on the TV box and switching to play news. When the execution thread executes the instructions of this scene, it first executes the instruction to turn on the TV box, then executes the delay instruction to wait for 3 seconds, and finally executes the instruction to switch to play news. After all the instructions are executed, the instructions of the next scene are executed in this way. Since a lot of time is spent on executing delayed instructions and no effective operations are performed, the efficiency of instruction execution is not high. Summary of the invention

[0003] The embodiments of the present application provide a method, apparatus, device and storage medium for executing instructions in multiple scenarios, which can improve the efficiency of executing scenario instructions.

[0004] In a first aspect, an embodiment of the present application provides an instruction execution method in multiple scenarios, including:

[0005] Obtain at least one instruction corresponding to multiple scenarios in the current execution cycle of the execution thread;

[0006] Executing the at least one instruction in the current execution cycle, and if the at least one instruction includes a delay instruction, determining a target execution cycle corresponding to a next instruction of the delay instruction;

[0007] After the current execution cycle ends, the next execution cycle is taken as the current execution cycle, and the step of obtaining at least one instruction corresponding to multiple scenarios in the current execution cycle of the execution thread is returned to execute; wherein, when the current execution cycle reaches the target execution cycle, the next instruction of the delayed instruction is executed.

[0008] In a second aspect, an embodiment of the present application provides an instruction execution device in multiple scenarios, including a processor and a memory, wherein a computer program is stored in the memory, and when the processor calls the computer program in the memory, the instruction execution method in multiple scenarios is executed.

[0009] In a third aspect, an embodiment of the present application provides an electronic device, including a body, a power supply disposed in the body, and the above-mentioned instruction execution device in multiple scenarios.

[0010] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which is used to store a computer program. When the computer program is executed by a processor, the processor implements the above-mentioned instruction execution method in multiple scenarios.

[0011] The embodiments of the present application provide an instruction execution method, apparatus, device and storage medium in multiple scenarios, by obtaining at least one instruction corresponding to multiple scenarios in the current execution cycle of the execution thread, executing the at least one instruction, when the at least one instruction executed includes a delay instruction, determining the target execution cycle corresponding to the next instruction of the delayed instruction, after the current execution cycle ends, executing other corresponding instructions of the multiple scenarios in the next execution cycle, wherein when the execution cycle reaches the target execution cycle, the next instruction of the delayed instruction is executed, and in this way, all instructions of the multiple scenarios are executed. Compared with executing one instruction after another in sequence, when the delayed instruction is executed, the only way is to wait, which greatly improves the efficiency of instruction execution. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 is a schematic block diagram of an electronic device provided by an embodiment of the present application;

[0014] Figure 2 This is a schematic flow chart of the steps of a method for executing instructions in multiple scenarios provided by an embodiment of the present application;

[0015] Figure 3 is a schematic diagram of a preset list provided in an embodiment of the present application;

[0016] Figure 4 It is a schematic block diagram of an instruction execution device in multiple scenarios provided by an embodiment of the present application. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0018] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may also be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0019] It should be understood that the terms used in this application specification are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in this application specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0020] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0021] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0022] When the scene triggers multiple actions continuously, it is usually necessary to add a delay operation between the actions. For example, for the scene "turn on the TV box → wait for 3 seconds (turn on the TV) → switch to play news", there is a 3s delay operation between turning on the TV box and switching to play news. When the execution thread executes the instructions of this scene, it first executes the instruction to turn on the TV box, then executes the delay instruction to wait for 3 seconds, and finally executes the instruction to switch to play news. After all the instructions are executed, the instructions of the next scene are executed in this way. Since most of the time, the delayed instructions are executed and no effective operations are performed, the efficiency of instruction execution is not high.

[0023] In order to solve the above problems, the embodiments of the present application provide a method, apparatus, device and storage medium for executing instructions in multiple scenarios, so as to improve the efficiency of executing scenario instructions.

[0024] See also Figure 1 , Figure 1 is a schematic block diagram of an electronic device provided by an embodiment of the present application. Figure 1 As shown, the electronic device 100 may include a body 110 , a power supply 120 and a control device 130 , wherein the power supply 120 and the control device 130 are both arranged in the body 110 , the power supply 120 and the control device 130 are connected, and the power supply 120 is used to supply power to the control device 130 .

[0025] The control device 130 includes a processor, and the processor is used to execute various scene instructions triggered by the electronic device 100 to implement various control operations of the electronic device 100.

[0026] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0027] Exemplarily, the electronic device 100 may include, but is not limited to, various types of electronic devices such as a smart phone, a tablet computer, a personal computer, a smart TV, a smart refrigerator, and an air conditioner.

[0028] It is understandable that the above-mentioned naming of the components of the electronic device is only for identification purposes and does not limit the embodiments of the present application.

[0029] The following will introduce in detail the instruction execution method in multiple scenarios provided by the embodiments of the present application based on electronic devices.

[0030] See also Figure 2 , Figure 2 This is a schematic flow chart of the steps of a method for executing instructions in multiple scenarios provided by an embodiment of the present application. The method for executing instructions in multiple scenarios is specifically applied to the electronic device provided by the above embodiment to improve the execution efficiency of instructions.

[0031] like Figure 2 As shown, the instruction execution method in multiple scenarios specifically includes steps S101 to S103.

[0032] S101. Obtain at least one instruction corresponding to multiple scenarios in a current execution cycle of an execution thread.

[0033] When the electronic device triggers multiple scenes, that is, there are multiple instructions of multiple scenes that need to be executed by the execution thread, the execution thread executes the multiple instructions of the multiple scenes in sequence according to the preset execution cycle. Specifically, first, according to the instructions of each scene, if the scene contains multiple instructions, the execution order of these multiple instructions is determined in sequence, and at least one instruction corresponding to the multiple scenes in the current execution cycle is determined, that is, at least one instruction of the multiple scenes that the execution thread is about to execute in the current execution cycle is determined. For example, for the first execution cycle, the first instruction corresponding to each scene is used as the instruction to be executed by the execution thread in the first execution cycle.

[0034] Among them, at least one instruction corresponding to multiple scenes in the current execution cycle contains valid instructions, such as an instruction to turn on the TV box switch, an instruction to switch to playing news, etc., and these valid instructions are executed to perform effective operations; at least one instruction corresponding to multiple scenes in the current execution cycle may also include a delay instruction, for example, an instruction to wait for 3 seconds.

[0035] S102: Execute the at least one instruction in the current execution cycle, and if the at least one instruction includes a delay instruction, determine a target execution cycle corresponding to a next instruction of the delay instruction.

[0036] When executing instructions, the execution thread executes at least one instruction of the determined multiple scenarios in the current execution cycle, unlike the existing instructions of one scenario being executed one by one in sequence. For example, if the triggered scenarios include scenario 1 and scenario 2, the instructions corresponding to scenario 1 include instruction 1 and instruction 2, and the instructions corresponding to scenario 2 include instruction 3 and instruction 4. If it is determined that at least one instruction of the corresponding multiple scenarios in the current execution cycle is instruction 1 and instruction 3, the execution thread executes instruction 1 and instruction 3 in the current execution cycle.

[0037] Optionally, when the execution thread executes the multiple instructions of the determined multiple scenarios in the current execution cycle, the multiple instructions may be executed synchronously or asynchronously.

[0038] When the execution thread executes at least one instruction of multiple scenarios in the current execution cycle, it may or may not execute the delay instruction. If the execution thread does not execute the delay instruction, that is, at least one instruction of multiple scenarios executed in the current execution cycle does not contain the delay instruction, then after the current execution cycle ends, the execution thread continues to execute other instructions of multiple scenarios corresponding to the next execution cycle.

[0039] If the execution thread executes a delay instruction, that is, at least one instruction of the multiple scenarios executed in the current execution cycle contains a delay instruction, then the execution cycle corresponding to the next instruction of the delay instruction is determined according to the delay instruction. For the convenience of distinguishing the description, the execution cycle corresponding to the next instruction is referred to as the target execution cycle below. Optionally, the target execution cycle corresponding to the next instruction is determined based on the delay duration corresponding to the delay instruction and the cycle duration corresponding to the execution cycle. For example, if the delay duration corresponding to the delay instruction is 3s and the cycle duration corresponding to the execution cycle is 1s, the target execution cycle corresponding to the next instruction is determined to be the third execution cycle after the current execution cycle.

[0040] S103. After the current execution cycle ends, the next execution cycle is used as the current execution cycle, and the step of obtaining at least one instruction corresponding to multiple scenarios in the current execution cycle of the execution thread is returned to execute; wherein, when the current execution cycle reaches the target execution cycle, the next instruction of the delayed instruction is executed.

[0041] After the current execution cycle ends, the execution thread obtains at least one other instruction to be executed corresponding to multiple scenarios in the next execution cycle according to the above steps, and executes at least one other instruction in the next execution cycle. The specific operation method can refer to the above steps and will not be repeated here. That is, the execution thread executes at least one instruction of multiple scenarios corresponding to each execution cycle in turn according to the execution cycle.

[0042] As the execution thread progresses, when the current execution cycle reaches the target execution cycle corresponding to the next instruction, the execution thread executes the next instruction of the delayed instruction. For example, if the next instruction of the first delayed instruction corresponds to the first target execution cycle, and the next instruction of the second delayed instruction corresponds to the second target execution cycle, then when the current execution cycle reaches the first target execution cycle, the execution thread executes the next instruction of the first delayed instruction; when the current execution cycle reaches the second target execution cycle, the execution thread executes the next instruction of the second delayed instruction.

[0043] In some embodiments, a corresponding preset list is pre-established, and the preset list includes multiple cache areas, each of which is used to cache corresponding instructions. For example, in redis, an array table of List type is established with delay_command_{id} as the key, where id is a unique address identifier corresponding to each cache area, and the value of id is optionally incremented from 0.

[0044] Optionally, first calculate the quotient m of the delay time divided by the cycle time according to the delay time corresponding to the delay instruction and the cycle time corresponding to each execution cycle of the execution thread, and then establish a preset list containing m cache areas. For example, based on the fact that the maximum delay time between instructions is usually no more than 60 seconds, the delay time corresponding to the delay instruction is set to 60s, and the cycle time corresponding to the execution cycle of the execution thread is 1s, then establish a preset list containing 60 cache areas, such as Figure 3 The execution thread traverses the preset list according to the execution cycle and polls each buffer area in the preset list in turn.

[0045] If at least one instruction executed in the current execution cycle includes a delayed instruction, the next instruction of the delayed instruction is cached in the corresponding target cache area in the preset list. When the current execution cycle reaches the target execution cycle, the execution thread polls the target cache area in the preset list and executes the next instruction cached in the target cache area.

[0046] In some embodiments, based on the current cache area polled by the execution thread in the current execution cycle, the cache area that the execution thread will poll after the target execution cycle is determined, the cache area is determined as the target cache area, and the next instruction of the delayed instruction is cached in the target cache area.

[0047] In some embodiments, based on the determined target execution cycle, the number n of cache areas between the current cache area polled by the execution thread in the current execution cycle and the target cache area for caching the next instruction is determined, and the nth cache area after the current cache area polled by the execution thread in the current execution cycle is determined as the target cache area corresponding to the next instruction. For example, if the target execution cycle corresponding to the next instruction of the delayed instruction is the third execution cycle after the current execution cycle, the number n of cache areas between the current cache area polled by the execution thread in the current execution cycle and the target cache area is determined to be 3, and the third cache area after the current cache area is determined as the target cache area for caching the next instruction of the delayed instruction.

[0048] Optionally, each cache area in the preset list is provided with a unique address identifier, such as an ID address. By obtaining a first address identifier of a current cache area polled by the execution thread in the current execution cycle, the first address identifier is added by n based on the target execution cycle corresponding to the next instruction of the delayed instruction, thereby obtaining a second address identifier corresponding to the target cache area for caching the next instruction, and according to the second address identifier, the cache area corresponding to the second address identifier is determined as the target cache area, and the next instruction of the delayed instruction is cached in the target cache area.

[0049] The above-mentioned embodiment obtains at least one instruction corresponding to multiple scenarios in the current execution cycle of the execution thread, executes the at least one instruction, and when the at least one instruction executed includes a delay instruction, determines the target execution cycle corresponding to the next instruction of the delay instruction, and after the current execution cycle ends, executes other corresponding instructions of the multiple scenarios in the next execution cycle, wherein when the execution cycle reaches the target execution cycle, the next instruction of the delay instruction is executed. In this way, all instructions of the multiple scenarios are executed, which greatly improves the efficiency of instruction execution compared to executing one instruction after another in sequence, when the delay instruction is executed, the only way is to wait.

[0050] See also Figure 4 , Figure 4 A schematic block diagram of an instruction execution device in multiple scenarios provided by an embodiment of the present application. Figure 4 As shown, the instruction execution device 400 in multiple scenarios may include a processor 410 and a memory 420. The processor 410 and the memory 420 are connected via a bus, such as an I2C (Inter-integrated Circuit) bus.

[0051] Specifically, the processor 410 may be a micro-controller unit (MCU), a central processing unit (CPU), or a digital signal processor (DSP).

[0052] Specifically, the memory 420 may be a Flash chip, a read-only memory (ROM) disk, an optical disk, a USB flash drive, or a mobile hard disk.

[0053] The processor is used to run a computer program stored in the memory, and implements the following steps when executing the computer program:

[0054] Obtain at least one instruction corresponding to multiple scenarios in the current execution cycle of the execution thread;

[0055] Executing the at least one instruction in the current execution cycle, and if the at least one instruction includes a delay instruction, determining a target execution cycle corresponding to a next instruction of the delay instruction;

[0056] After the current execution cycle ends, the next execution cycle is taken as the current execution cycle, and the step of obtaining at least one instruction corresponding to multiple scenarios in the current execution cycle of the execution thread is returned to execute; wherein, when the current execution cycle reaches the target execution cycle, the next instruction of the delayed instruction is executed.

[0057] In some embodiments, the processor, after executing the at least one instruction in the current execution cycle and determining a target execution cycle corresponding to a next instruction of the delayed instruction if the at least one instruction includes a delay instruction, further implements:

[0058] caching the next instruction into a corresponding target cache area in a preset list according to the target execution cycle;

[0059] When the current execution cycle reaches the target execution cycle, executing the next instruction of the delayed instruction includes:

[0060] When the current execution cycle reaches the target execution cycle, the target cache area is polled to execute the next instruction.

[0061] In some embodiments, before implementing the step of caching the next instruction into a corresponding target cache area in a preset list according to the target execution cycle, the processor further includes:

[0062] According to the delay duration corresponding to the delay instruction and the cycle duration corresponding to each execution cycle of the execution thread, calculate a quotient m of the delay duration divided by the cycle duration;

[0063] The preset list including m buffer areas is established.

[0064] In some embodiments, the cycle duration comprises 1 second.

[0065] In some embodiments, when the processor implements caching the next instruction to a corresponding target cache area in a preset list according to the target execution cycle, the processor specifically implements:

[0066] Determine, based on the current cache area polled by the execution thread in the current execution cycle, the target cache area that the execution thread will poll after the target execution cycle;

[0067] The next instruction is cached in the target cache area.

[0068] In some embodiments, when the processor implements determining, based on the current cache area polled by the execution thread in the current execution cycle, the target cache area that the execution thread will poll after the target execution cycle, the processor specifically implements:

[0069] Determine the number n of cache areas between the current cache area and the target cache area according to the target execution cycle;

[0070] The nth buffer area after the current buffer area is determined as the target buffer area.

[0071] In some embodiments, each cache area in the preset list corresponds to a unique address identifier, and when the processor implements determining the nth cache area after the current cache area as the target cache area, the processor specifically implements:

[0072] According to the first address identifier corresponding to the current cache area, add n to the first address identifier to obtain a second address identifier;

[0073] The cache area corresponding to the second address identifier is determined as the target cache area.

[0074] The embodiment of the present application also provides an electronic device, which can be used for example Figure 1 The electronic device shown in the figure includes a body, a power supply arranged in the body, and a multi-scenario instruction execution device. It should be noted that the multi-scenario instruction execution device can be Figure 4 An instruction execution device in multiple scenarios as exemplified in FIG.

[0075] The specific operations of the electronic device's execution process of the instructions for the triggered multiple scenes can be found in the previous embodiments, and will not be repeated here.

[0076] A computer-readable storage medium is also provided in an embodiment of the present application, wherein the computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and the processor executes the program instructions to implement the steps of the instruction execution method in multiple scenarios provided in the above embodiments.

[0077] The computer-readable storage medium may be an internal storage unit of the electronic device of the aforementioned embodiment, such as a hard disk or memory of the electronic device. The computer-readable storage medium may also be an external storage device of the electronic device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device.

[0078] Since the computer program stored in the computer-readable storage medium can execute any one of the instruction execution methods in multiple scenarios provided in the embodiments of the present application, the beneficial effects that can be achieved by any one of the instruction execution methods in multiple scenarios provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0079] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for executing instructions in multiple scenarios, characterized in that: include: Obtain at least one instruction corresponding to multiple scenarios in the current execution cycle of the execution thread; Executing the at least one instruction in the current execution cycle, and if the at least one instruction includes a delay instruction, determining a target execution cycle corresponding to a next instruction of the delay instruction; After the current execution cycle ends, the next execution cycle is used as the current execution cycle, and the step of obtaining at least one instruction corresponding to multiple scenarios in the current execution cycle of the execution thread is returned to execute; wherein, when the current execution cycle reaches the target execution cycle, the next instruction of the delayed instruction is executed; Wherein, executing the at least one instruction in the current execution cycle, if the at least one instruction includes a delay instruction, after determining a target execution cycle corresponding to a next instruction of the delay instruction, further comprises: According to the delay duration corresponding to the delay instruction and the cycle duration corresponding to each execution cycle of the execution thread, calculate a quotient m of the delay duration divided by the cycle duration; Create a preset list containing m buffer areas; caching the next instruction into a corresponding target cache area in a preset list according to the target execution cycle; When the current execution cycle reaches the target execution cycle, executing the next instruction of the delayed instruction includes: When the current execution cycle reaches the target execution cycle, polling the target cache area to execute the next instruction; The step of caching the next instruction into a corresponding target cache area in a preset list according to the target execution cycle includes: Determine the number n of cache areas between the current cache area and the target cache area according to the target execution cycle; Determine the nth cache area after the current cache area as the target cache area, and cache the next instruction in the target cache area; Each cache area in the preset list corresponds to a unique address identifier, and determining the nth cache area after the current cache area as the target cache area includes: According to the first address identifier corresponding to the current cache area, add n to the first address identifier to obtain a second address identifier; The cache area corresponding to the second address identifier is determined as the target cache area.

2. The instruction execution method in multiple scenarios according to claim 1, characterized in that: The cycle duration includes 1 second.

3. A multi-scenario instruction execution device, characterized in that: The method comprises a processor and a memory, wherein a computer program is stored in the memory, and when the processor calls the computer program in the memory, the method for executing instructions in multiple scenarios as described in any one of claims 1 to 2 is executed.

4. An electronic device, characterized in that: It comprises a body, a power supply arranged in the body, and the instruction execution device in multiple scenarios as claimed in claim 3.

5. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor implements the instruction execution method in multiple scenarios as described in any one of claims 1 to 2.

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