Semiconductor device package and method of manufacturing the same

Abstract

This disclosure provides a semiconductor device package. The semiconductor device package includes a dielectric layer. The semiconductor device package further includes an antenna structure disposed within the dielectric layer. The semiconductor device package further includes a semiconductor device disposed on the dielectric layer. The semiconductor device package further includes an encapsulating material covering the semiconductor device. The semiconductor device package further includes a conductive pillar having a first portion and a second portion. The first portion is surrounded by the encapsulating material, and the second portion is embedded in the dielectric layer.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor device package, and more specifically to a semiconductor device package including an antenna structure and a method for manufacturing the semiconductor device package. Background Technology

[0002] Wireless communication devices such as mobile phones may include one or more semiconductor device packages with antennas, such as antenna-on-package (AoP), for signal (e.g., radio frequency (RF) signals) transmission. The antennas are first manufactured and then mounted on the substrate of the semiconductor device package. Therefore, vias extending through the substrate of the semiconductor device package are required to connect the antennas and some electronic components. However, the cumbersome manufacturing of the antennas and vias results in a high cost for semiconductor device packages. Summary of the Invention

[0003] In one or more embodiments, a semiconductor device package includes a dielectric layer. The semiconductor device package further includes an antenna structure disposed within the dielectric layer. The semiconductor device package further includes a semiconductor device disposed on the dielectric layer. The semiconductor device package further includes an encapsulating material covering the semiconductor device. The semiconductor device package further includes a conductive pillar having a first portion and a second portion. The first portion is surrounded by the encapsulating material, and the second portion is embedded in the dielectric layer.

[0004] In one or more embodiments, a semiconductor device package includes a dielectric layer having a first surface and a second surface. The semiconductor device package further includes an antenna structure embedded in the dielectric layer. The semiconductor device package further includes a semiconductor device disposed on the first surface of the dielectric layer. The semiconductor device package further includes a conductive pillar having a first surface within the dielectric layer. The first surface of the conductive pillar and the first surface of the dielectric layer are discontinuous.

[0005] In one or more embodiments, a method of manufacturing a semiconductor device package includes: forming an antenna structure; forming a dielectric layer to cover the antenna structure; defining a hole in the dielectric layer to expose a portion of the antenna structure; forming a conductive pillar having a first portion in the hole for electrical connection to the exposed portion of the antenna structure and a second portion protruding from the dielectric layer; placing a semiconductor device on the dielectric layer; forming an encapsulant to cover the semiconductor device and the second portion of the conductive pillar; and forming a redistribution layer on the encapsulant to electrically connect the conductive pillar to the semiconductor device. Attached Figure Description

[0006] Various aspects of this disclosure can be readily understood from the following detailed description, which is read in conjunction with the accompanying drawings. It should be noted that the various features may not necessarily be drawn to scale. For clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1A A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0008] Figure 1B A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0009] Figure 2A A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0010] Figure 2B A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0011] Figure 3 A bottom view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0012] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4L , Figure 4M , Figure 4N , Figure 4O , Figure 4P , Figure 4Q , Figure 4R , Figure 4S and Figure 4T One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of this application are shown.

[0013] Figure 5 One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of this application are shown.

[0014] Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of this application are shown.

[0015] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F and Figure 7G One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of this application are shown.

[0016] Figure 8 One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of this application are shown.

[0017] Throughout the accompanying drawings and detailed description, common reference numerals are used to indicate the same or similar elements. This disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0020] Figure 1A A cross-sectional view of a semiconductor device package 1a according to some embodiments of the present disclosure is shown. The semiconductor device package 1a includes a dielectric layer 10, an antenna structure 11, a semiconductor device 12, an encapsulant 13, conductive pillars 14, a redistribution layer (RDL) 15, and electrical contacts 16.

[0021] The dielectric layer 10 has a surface 101 and a surface 102 opposite to the surface 101. The dielectric layer 10 may have a relatively low dielectric constant (Dk). The dielectric layer 10 may have a relatively low dissipation factor (Df). Compared to the encapsulant 13, the dielectric layer 10 may have a relatively large coefficient of thermal expansion (CTE). The dielectric layer 10 may comprise, for example, polyimide (PI), epoxy resin, Ajinomoto laminate (ABF), one or more molding materials, one or more prepreg composite fibers (e.g., prepreg fibers), borosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), or any combination thereof.

[0022] Antenna structure 11 is disposed within dielectric layer 10. Antenna structure 11 is embedded within dielectric layer 10. Antenna structure 11 is recessed from surface 102 of dielectric layer 10. Antenna structure 11 is closer to surface 102 than surface 101. In some embodiments, antenna structure 11 may not be exposed from surface 101. In other words, antenna structure 11 may be spaced apart from semiconductor device 12. In some embodiments, the thickness of each of antenna elements 11a, 11b is less than the thickness of dielectric layer 10. In some embodiments, antenna structure 11 may comprise a conductive material such as a metal or metal alloy. Examples of conductive materials include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof.

[0023] Antenna structure 11 includes an antenna element 11a substantially aligned with the conductive post 14. The antenna element 11a may be positioned below the conductive post 14. The antenna element 11a is close to the conductive post 14. The antenna element 11a may be electrically connected to the conductive post 14. The antenna element 11a may be in direct contact with the conductive post 14. The antenna element 11a is recessed from the surface 102 of the dielectric layer 10. In some embodiments, the width of the antenna element 11a may be equal to or greater than the width of the conductive post. Alternatively, the width of the antenna element 11a may be less than the width of the conductive post 14. Antenna structure 11 includes one or more antenna elements 11b. The distance from the antenna element 11b to the conductive post 14 is greater than the distance from the antenna element 11a to the conductive post 14. The antenna element 11b is recessed from the surface 102 of the dielectric layer 10. The antenna element 11b has a recess 11r located near the surface 102 of the dielectric layer 10. The antenna element 11b has a surface 111 exposed from the surface 102 of the dielectric layer 10. Surface 111 may contain a burr pattern. Surface 111 may contain a stripe pattern. Surface 111 may be non-planar. For example... Figure 1A As shown, antenna element 11a may also have a recess 11r similar to that of antenna element 11b, and a surface 111 similar to that of antenna element 11b.

[0024] Semiconductor device 12 is disposed on surface 101 of dielectric layer 10. Semiconductor device 12 has a surface 121 (e.g., active surface) facing away from dielectric layer 10 and a surface 122 (e.g., back surface) opposite to surface 121. The distance from surface 121 to surface 101 is greater than the distance from surface 122 to surface 101. Conductive terminals 12a and 12b are disposed on surface 121 of semiconductor device 12. Conductive terminal 12a faces away from surface 12a1 of semiconductor device 12. Conductive terminal 12b faces away from surface 12b1 of semiconductor device 12. Semiconductor device 12 is electrically connected to RDL 15 via conductive terminal 12a. Semiconductor device 12 is electrically connected to RDL 15 via conductive terminal 12b. Semiconductor device 12 may be, for example, a processor, controller (e.g., memory controller), microcontroller (MCU), memory die, high-speed input / output device, radio frequency integrated circuit (RFIC), or other electronic component.

[0025] In some embodiments, a ground layer (not shown) may be disposed between the semiconductor device 12 and the antenna structure 11 to reflect radiation from the antenna structure 11. The ground layer may be disposed on the dielectric layer 11. The ground layer may be embedded in the dielectric layer 11.

[0026] Encapsulant 13 is disposed on surface 101 of dielectric layer 10. Encapsulant 13 may be in direct contact with dielectric layer 10. Encapsulant 13 has a surface 131 facing away from dielectric layer 10. Dielectric layer 10 has side surface 103 and encapsulant 13 has side surface 133. Side surface 103 and side surface 133 are substantially coplanar. Encapsulant 13 covers semiconductor device 12. Encapsulant 13 surrounds conductive terminals 12a and 12b. Encapsulant 13 may contain epoxy resin. Encapsulant 13 may contain underfill material. Encapsulant 13 may contain molding raw material (e.g., epoxy molding raw material (EMC)) or encapsulation material. The dielectric constant (Dk) of encapsulant 13 may be greater than the dielectric constant (Dk) of dielectric layer 10. The dielectric constant (Df) of encapsulant 13 may be greater than the dielectric constant (Df) of dielectric layer 10. The dielectric constant (CTE) of encapsulant 13 may be less than the dielectric constant (CTE) of dielectric layer 10.

[0027] In some comparative embodiments, the antenna structure 11 may be embedded in an encapsulating material 13 or a similar material having relatively large Df and relatively large Dk. The encapsulating material 13 or a material having relatively large Df and relatively large Dk reduces transmission speed and causes significant transmission loss (or signal loss) between the antenna structure 11 and one or more external signal sources. In some embodiments of this disclosure, embedding the antenna structure 11 in a dielectric layer 10 with a Dk lower than the Dk of the encapsulating material 13 and a Df lower than the Df of the encapsulating material 13 can significantly improve transmission speed and reduce transmission loss from the antenna structure 11 to one or more external signal sources (and vice versa). Furthermore, the side surface 103 of the dielectric layer 10 is substantially coplanar with the side surface 133 of the encapsulating material 13, i.e., the side surface 103 is exposed and can improve the radiation efficiency (or antenna efficiency) of the antenna structure 11 in the lateral direction. Additionally, the dielectric layer 10 with a relatively large CTE can mitigate warpage of the semiconductor device package 1a.

[0028] Conductive post 14 extends from antenna element 11a of antenna structure 11 through encapsulation 13 to RDL 15. Conductive post 14 is electrically connected to antenna element 11a. In some embodiments, the interface between conductive post 14 and antenna element 11a is located within dielectric layer 10. For example, the interface between conductive post 14 and antenna element 11a is located between surface 101 and surface 102 of dielectric layer 10. Conductive post 14 can act as a feed element for transmitting or receiving signals to or from antenna structure 11. Conductive post 14 provides a transmission path and / or a reception path between semiconductor device 12 and antenna structure 11. In a comparative embodiment, the semiconductor device package includes a pre-fabricated antenna, pre-fabricated electronics, a substrate, and vias. The pre-fabricated antenna is disposed on one surface of the substrate and covered with a compound. The pre-fabricated electronics are disposed on another surface of the substrate and covered with another compound. The vias extend through the substrate and the compound to provide a connection path between the pre-fabricated electronics and the pre-fabricated antenna. However, the manufacturing processes for packaging prefabricated antennas and prefabricated electronic components, as well as the manufacturing processes for forming vias, are both cumbersome and costly. Furthermore, the transmission efficiency of prefabricated antennas can be reduced due to compounds with relatively high Dk and Df values. In some embodiments, this disclosure provides an antenna structure 11 with an embedded dielectric layer 10 having relatively low Dk and Df values ​​to improve transmission efficiency. Compared to the vias of the comparative embodiments, the conductive pillars 14 can provide a shorter transmission path between the antenna structure 11 and the semiconductor device 12. Furthermore, the integration of the antenna structure 11 and the dielectric layer 10 can reduce the overall size of the semiconductor device package 1a.

[0029] The conductive post 14 has a surface 141 facing away from the dielectric layer 10. Surface 141 and the surface 131 of the encapsulant 13 are substantially coplanar. Surface 141 and the surface 12a1 of the conductive terminal 12a are substantially at the same elevation. In some embodiments, surfaces 141 and 131 may be discontinuous. In some embodiments, surfaces 141 and 12a1 may be discontinuous. The conductive post 141 includes a surface 142 opposite to surface 141. Surface 142 is located within the dielectric layer 10. Surface 142 and the surface 101 of the dielectric layer are discontinuous. In some embodiments, surface 142 may be lower than surface 101. Surface 142 may be in direct contact with the antenna element 11a of the antenna structure 11.

[0030] The conductive post 14 includes a portion 14a, a portion 14b, and a seed layer 14s. The portion 14a is surrounded by an encapsulant 13. The portion 14a has a side surface 14a1 that is surrounded by and in direct contact with the encapsulant 13. The portion 14b is embedded in the dielectric layer 10. The portion 14b is surrounded by the seed layer 14s. The portion 14b has a side surface 14b1 that is surrounded by and in direct contact with the seed layer 14s. The side surfaces 14a1 and 14b1 are substantially coplanar. The seed layer 14s is disposed along the surface 142 of the conductive post 14. The seed layer 14s is disposed between the portion 14b and the antenna element 11a of the antenna structure 11. The seed layer 14s is surrounded by and in direct contact with the dielectric layer 10. The conductive post 14 may contain, for example, but not limited to, nickel, copper, gold, platinum, titanium, or one or more other suitable metallic materials.

[0031] RDL 15 includes a redistribution structure (or interconnect layer) 15a and a redistribution structure 15b, and a conductive pad 15c. The redistribution structure 15a has a portion that directly contacts the surface 12a1 of the conductive terminal 12a. The redistribution structure 15a electrically connects the conductive terminal 12a to the conductive pad 15c. The redistribution structure 15b has a portion that directly contacts the surface 12b1 of the conductive terminal 12b. The redistribution structure 15b of RDL 15 electrically connects the conductive post 14 to the conductive terminal 12b, which in turn is electrically connected to the semiconductor device 12.

[0032] RDL 15 may include a fan-out structure. RDL 15 may include one or more insulating materials or one or more dielectric materials. Figure 1A(Not shown in the text). RDL 15 may contain a core or relatively rigid material. The redistribution layer RDL 15 may contain a flexible or relatively soft material. Redistribution structures 15a and 15b may each contain a single-layer or multi-layer structure. Redistribution structures 15a and 15b may each contain a seed layer. Redistribution structures 15a and 15b may each contain conductive elements, such as, but not limited to, one or more conductive traces, one or more pads, one or more contacts, or one or more vias. Conductive pad 15c may contain a material similar to that of redistribution structures 15a and 15b. Conductive pad 15c may contain a material different from that of redistribution structures 15a and 15b.

[0033] Electrical contact 16 is disposed on conductive pad 15c. Electrical contact 16 is in direct contact with conductive pad 15c. Electrical contact 16 is electrically connected to semiconductor device 12 via RDL 15. Electrical contact 16 can provide electrical connection between semiconductor device package 1a and external components (e.g., external circuitry or circuit board). Electrical contact 16 may include solder balls or solder bumps. In some embodiments, electrical contact 16 may include controlled collapse chip connection (C4) bumps, ball grid array (BGA), or planar grid array (LGA).

[0034] Figure 1B A cross-sectional view of a semiconductor device package 1b according to some embodiments of the present disclosure is shown. Figure 1B Semiconductor device package 1b is similar to Figure 1A The semiconductor device package 1a is described below, and the differences therein are described.

[0035] The semiconductor device package 1b further includes a protective layer 17 disposed on the antenna structure 11. The protective layer 17 is disposed on the surface 102 of the dielectric layer 10. The protective layer 17 can be in direct contact with the antenna elements 11a and 11b of the antenna structure 11. The protective layer 17 has a portion in the recess 11r. The protective layer 17 can be in direct contact with the surface 111. The protective layer 17 can, for example, comprise a polymer material or a photoresist dry film. The protective layer 17 protects the antenna structure 11 from oxidation.

[0036] Figure 2A A cross-sectional view of a semiconductor device package 2a according to some embodiments of the present disclosure is shown. Figure 2A Semiconductor device package 2a is similar to Figure 1A The semiconductor device package 1a is described below, and the differences therein are described.

[0037] Semiconductor device package 2a includes antenna structure 21 and protective layer 17', instead of antenna structure 11 and protective layer 17' of semiconductor device package 1a. Antenna structure 21 is disposed in dielectric layer 10. Antenna structure 21 is embedded in dielectric layer 10. In some embodiments, antenna structure 21 may not be exposed from surface 101. In other words, antenna structure 21 may be spaced apart from semiconductor device 12. In some embodiments, the thickness of each antenna element in antenna elements 21a, 21b is less than the thickness of dielectric layer 10. In some embodiments, antenna structure 21 may comprise a conductive material such as a metal or metal alloy. Examples of conductive materials include gold (Au), silver (Ag), aluminum (Al), copper (Cu), titanium (Ti), or alloys thereof.

[0038] Antenna structure 21 includes an antenna element 21a substantially aligned with conductive post 14. Antenna element 21a may be positioned below conductive post 14. Antenna element 21a is close to conductive post 14. Antenna element 21a may be electrically connected to conductive post 14. Antenna element 21a may be in direct contact with conductive post 14. In some embodiments, the width of antenna element 21a may be equal to or greater than the width of conductive post 14. Alternatively, the width of antenna element 21a may be less than the width of conductive post 14. Antenna structure 21 includes one or more antenna elements 21b. The distance from antenna element 21b to conductive post 14 is greater than the distance from antenna element 21a to conductive post 14. Antenna structure 21 includes a seed layer 21c. Seed layer 21c is disposed between antenna structure 21 and protective layer 17'. Seed layer 21c has a surface 21c1 in direct contact with protective layer 17'. Surface 21c may be substantially planar. Surface 21c1 and surface 102 of dielectric layer 10 are substantially coplanar.

[0039] The protective layer 17' may, for example, comprise a polymer material or a photoresist dry film. The protective layer 17' protects the antenna structure 21 from oxidation.

[0040] Figure 2B A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown. Figure 2B Semiconductor device package 2b is similar to Figure 1A The semiconductor device package 1a is described below, and the differences therein are described.

[0041] Semiconductor device package 2b includes a conductive structure 24 (or conductive pillar) instead of the conductive pillar 14 of semiconductor device package 1a. Conductive structure 24 electrically connects antenna element 11a of antenna structure 11 to redistribution structure 15b, which in turn is electrically connected to semiconductor device 12 via conductive terminal 12b. Conductive structure 24 extends from antenna element 11a of antenna structure 11 through encapsulation 13 to RDL 15. Conductive structure 24 is electrically connected to antenna element 11a. In some embodiments, the interface between conductive structure 24 and antenna element 11a is located within dielectric layer 10. For example, the interface between conductive structure 24 and antenna element 11a is located between surfaces 101 and 102 of dielectric layer 10. Conductive structure 24 can act as a feed element for transmitting or receiving signals to or from antenna structure 11. Conductive structure 24 provides a transmission path and / or a reception path between semiconductor device 12 and antenna structure 11. Compared to the through-hole in the comparative embodiment, the conductive structure 24 can provide a shorter transmission path between the antenna structure 11 and the semiconductor device 12.

[0042] The conductive structure 24 has a surface 241 facing away from the dielectric layer 10 and a surface 242 opposite to surface 241. Surfaces 241 and 131 are substantially coplanar. Surfaces 241 and 12a1 or 12b1 are substantially at the same elevation. In some embodiments, surfaces 241 and 131 may be discontinuous. In some embodiments, surfaces 241 and 12a1 may be discontinuous. Surface 242 is located within the dielectric layer 10. Surface 242 and surface 101 are discontinuous. Surface 242 is in direct contact with the antenna element 11a of the antenna structure 11.

[0043] The conductive structure 24 includes a conductive element 24a and an electrical contact 24b. The conductive element 24a is disposed on the electrical contact 24b. The conductive element 24a is surrounded by an encapsulant 13. The conductive element may contain, for example, but not limited to, nickel, copper, gold, platinum, titanium, or one or more other suitable metallic materials. The electrical contact 24b (e.g., a solder ball or solder bump) has a portion 24b1 protruding from the surface 101 of the dielectric layer 10. The portion 24b1 covers a portion of the surface 101. The portion 24b1 may have a curved surface. The electrical contact 24b has a portion 24b2 embedded in the dielectric layer 10. In some embodiments, an intermetallic compound (IMC) may be disposed between the electrical contact 24b and the antenna element 11a. In some embodiments, an IMC may be disposed between the electrical contact 24b and the conductive element 24a.

[0044] Figure 3 A bottom view of a semiconductor device package 3 according to some embodiments of the present disclosure is shown. The semiconductor device package 3 includes a dielectric layer 30 and an antenna structure 31.

[0045] Dielectric layer 30 may have a relatively low Dk. Dielectric layer 30 may have a relatively low Df. Dielectric layer 30 may have a relatively large CTE. Dielectric layer 30 may comprise, for example, polyimide (PI), epoxy resin, Ajinomoto laminate (ABF), one or more molding materials, one or more prepreg composite fibers (e.g., prepreg fibers), borosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), or any combination thereof.

[0046] Antenna structure 31 is embedded in dielectric layer 30. Antenna structure 31 includes antenna element 31a, antenna element 31b, and antenna element 31c. Antenna element 31a can be connected to a feed element (e.g., Figure 1A (Conductive post 14 in the middle). Antenna element 31a can be connected to a ground wire. Antenna element 31b can contain a zigzag pattern. Antenna element 31b can contain a concentric rectangular pattern. Antenna element 31c can be connected to a feed element (e.g., Figure 1A (Conductive post 14 in the middle). Antenna element 31c can be connected to a grounding wire. Antenna structure 31 can have different antenna elements, such as, but not limited to, patch antennas, squirrel-cage antennas, planar inverted F-type antennas, etc.

[0047] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4L , Figure 4M , Figure 4N , Figure 4O , Figure 4P , Figure 4Q , Figure 4R , Figure 4S and Figure 4T One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of this application are shown.

[0048] refer to Figure 4A A substrate 40 is provided. The substrate 40 may comprise a planar substrate. A conductive layer 41 is formed on the substrate 40, for example, by an electroplating process. A conductive layer 41' opposite to the conductive layer 41 is formed on the substrate 40, for example, by an electroplating process. In some embodiments, the conductive layer 41 and the conductive layer 41' are formed by the same electroplating process.

[0049] refer to Figure 4BA photoresist layer 42 is formed on the conductive layer 41 through, for example, a coating process and a subsequent exposure process. The photoresist layer 42 defines gaps 42g on the conductive layer 41. (Reference) Figure 4C Antenna structure 11' is formed within gap 42g using, for example, an electroplating process, and said antenna structure is supported by conductive layer 41. The height of antenna structure 11' can be substantially the same as the height of photoresist layer 42. (Reference) Figure 4D The photoresist layer 42 is removed by, for example, plasma ashing.

[0050] refer to Figure 4E A dielectric layer 10 is formed on the antenna structure 11' and the conductive layer 41 using, for example, a coating process and a subsequent polishing process. The dielectric layer 10 surrounds the antenna structure 11'. (See reference...) Figure 4F A hole 43 is defined in the dielectric layer 10, for example, using a laser drilling process, to expose a portion 11a' of the antenna structure 11', while the remaining portions 11b' of the antenna structure 11' are covered by the dielectric layer 10. The hole 43 has a surface 431 exposed to the portion 11a'. The hole 43 has a side surface 432 exposed to the dielectric layer 10. The hole 43 has a height 43h relative to the upper surface of the portion 11a'.

[0051] refer to Figure 4G A photoresist layer 44 is formed on the dielectric layer 10 using, for example, a coating process. The photoresist layer 44 is patterned using, for example, an exposure process to define vias 45 that expose vias 43. The vias 45 have sidewalls 451 exposed to the photoresist layer 44. (Reference) Figure 4H A seed layer 46 is formed on the photoresist layer 44 by, for example, sputtering, along side 451, side 432, and surface 431. The seed layer 46 includes a portion 46a on the photoresist layer 44, a portion 46b along side 451, and a portion 46c along surface 431 and side 432.

[0052] refer to Figure 4I A conductive layer 47a is formed on a portion 46a of the seed layer 46 using, for example, an electroplating process. Conductive pillars 47b are formed within the through-holes 45 and 43 using, for example, an electroplating process. (See reference) Figure 4J The conductive layer 47a and a portion 46a of the seed layer 46 are removed, for example, by an etching process. In some embodiments, a portion of the photoresist layer 44, a portion of the conductive pillar 47b, or a portion of 46b may be removed by an etching process. (See reference...) Figure 4K The photoresist layer 44 is removed, for example, by a plasma ashing process. (See reference.) Figure 4L Part 46b is removed by, for example, an etching process.

[0053] refer to Figure 4M For example, a bonding process is used to attach a semiconductor device 12 having conductive terminals 48a and 48b to a dielectric layer 10 via an adhesive layer. (See reference...) Figure 4N For example, a molding process is used to form an encapsulating material 49 on the dielectric layer to cover the conductive pillar 47b and the semiconductor device 12.

[0054] refer to Figure 4O Conductive pillars 14 are formed by grinding conductive pillars 47b. Each conductive pillar 14 has a first portion 14a in a hole 43 for electrical connection to an exposed portion (e.g., portion 11a') of the antenna structure 11' and a portion 14b protruding from the dielectric layer 10. Encapsulating material 13 is formed by grinding encapsulating material 49. Conductive terminals 12a and 12b are formed by grinding conductive terminals 48a and 48b. In some embodiments, conductive pillars 14, encapsulating material 13, conductive terminals 12a and 12b may be formed using the same grinding process. The semiconductor device 12 remains intact during the grinding process.

[0055] Hole 43 has a space of height 43h, and conductive post 47b is partially embedded in hole 43, which prevents conductive post 47b from being peeled off during etching, molding or grinding processes.

[0056] refer to Figure 4P An RDL 15 is formed on the encapsulant 13 to electrically connect the conductive pillar 14 to the semiconductor device 12. The RDL 15 includes a redistribution structure (or interconnect layer) 15a electrically connected to the conductive terminal 12a. The RDL 15 includes a redistribution structure 15b electrically connected to the conductive pillar 14 and the conductive terminal 12b. The RDL 15 includes a conductive pad 15c disposed on and electrically connected to the redistribution structure 15a. Reference Figure 4Q Electrical contacts 16 are formed on conductive pad 15c.

[0057] refer to Figure 4R Remove substrate 40 and conductive layer 41'. (Reference) Figure 4S For example, tape 50 is formed on RDL 15 using a tape application process. (See reference) Figure 4T The antenna structure 11 is formed by removing the conductive layer 41 and polishing the antenna structure 11'. The antenna structure 11 is recessed from the surface 102 of the dielectric layer 10 (e.g., recess 11r). The antenna structure 11 has an exposed surface 111. Due to the polishing process, the surface 111 may contain burrs or stripe patterns. The antenna structure 11 is manufactured using a substrate-level process (e.g., a planar substrate-level process). The area utilization of a planar substrate-level process can be greater than that of a wafer-level process. The size of the planar substrate can be 300*300mm or 600*600mm, which is larger than the size of a wafer. Furthermore, integrating the antenna structure 11 into the dielectric layer 10 can save the cost of additional temporary carriers typically used in semiconductor device packages with antennas. Therefore, the manufacturing efficiency of the antenna structure 11 is improved and simplified, which in turn reduces the overall cost.

[0058] Furthermore, tape 50 can be removed, for example, by a tape removal process, and a single-cut operation can be performed to form some... Figure 1A The semiconductor device package 1a described and shown in the document.

[0059] In some embodiments, it is possible to Figure 4F The substrate 40 is removed before the stage shown.

[0060] Figure 5 One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of this application are shown. Figure 5 The stages in can be similar to Figures 4A to 4T It occurs several stages after the initial stage. (See reference) Figure 5 A protective layer 17 is formed on the antenna structure 11. Afterwards, the tape 50 can be removed, and a single-cut operation can be performed to form some... Figure 1B The semiconductor device package 1b described and shown in the document.

[0061] Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of this application are shown.

[0062] Figure 6A The stages in can be similar to Figures 4A to 4F It occurs several stages after the initial stage. (See reference) Figure 6A An electrical contact 50 (e.g., a solder ball) is formed in the hole 43. The electrical contact 50 includes a portion protruding from the dielectric layer 10. (See reference) Figure 6B The conductive element 51 can be attached to the electrical contact 50. The conductive element 51 may include conductive posts.

[0063] refer to Figure 6C For example, a bonding process is used to attach a semiconductor device 12 having conductive terminals 48a and 48b to a dielectric layer 10 via an adhesive layer. (See reference...) Figure 6D For example, a molding process is used to form an encapsulating material 49 on the dielectric layer to cover the conductive element 51, the electrical contact 50, and the semiconductor device 12.

[0064] refer to Figure 6EA conductive structure 24 is formed by grinding the conductive element 51. The conductive structure 24 includes a conductive element 24a surrounded by an encapsulant. The conductive structure 24 includes an electrical contact 24b that is in direct contact with a portion 11a' of the antenna structure 11'. An encapsulant 13 is formed by grinding the encapsulant 49. Conductive terminals 12a and 12b are formed by grinding the conductive terminals 48a and 48b. In some embodiments, the conductive structure 24, the encapsulant 13, the conductive terminals 12a and 12b may be formed using the same grinding process. The semiconductor device 12 remains intact during the grinding process.

[0065] Figure 6E The stages in can be similar to Figure 4P to Figure 4T This occurs several stages prior to the previous stage. Afterwards, tape 50 can be removed, and a single-cut operation can be performed to form some... Figure 2B The semiconductor device package 2b described and shown in the document.

[0066] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , Figure 7F and Figure 7G One or more stages of a method for manufacturing a semiconductor device package according to some embodiments of this application are shown.

[0067] refer to Figure 7A A substrate 70 is provided. A protective layer 17' is formed on the substrate 70 using, for example, a coating process. (See reference) Figure 7B Seed layer 72 is formed on protective layer 17' by, for example, sputtering process.

[0068] refer to Figure 7C A photoresist layer 73 is formed on the seed layer 72 through, for example, a coating process and a subsequent exposure process. The photoresist layer 73 defines a gap 73g on the seed layer 72. (Reference) Figure 7D Antenna structure 74 is formed within the gap 73g using, for example, an electroplating process. The height of antenna structure 74 can be substantially the same as the height of photoresist layer 73. (Reference) Figure 7E The photoresist layer 73 is removed by, for example, plasma ashing.

[0069] refer to Figure 7F Antenna structure 21 is formed by removing the portion of seed layer 72 exposed from antenna structure 74. Antenna structure 21 includes a seed layer in direct contact with protective layer 17'. (See reference...) Figure 7G A dielectric layer 10 is formed on the antenna structure 21 and the protective layer 72 using, for example, a coating process and a subsequent polishing process. The dielectric layer 10 surrounds the antenna structure 21.

[0070] Figure 7G The stage can be similar to Figures 4F to 4Q Several stages precede the formation of the phase. Figure 8 The encapsulation structure.

[0071] Figure 8 This application illustrates one or more stages of a method for manufacturing a semiconductor device package according to some embodiments. References Figure 8 The protective layer 17' can be exposed by removing the substrate 70, and a single-cut operation can be performed to form some... Figure 2A The semiconductor device package 2a described and shown in the document. Due to the omission of details such as... Figure 4T The described grinding process ensures that the surface of antenna structure 21 is free of burrs or stripe patterns.

[0072] In this document, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “left,” and “right” may be used for ease of description to describe the relationship between one element or feature as shown in the accompanying drawings and one or more other elements or features. In addition to the orientations depicted in the accompanying drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be an intermediate element present.

[0073] As used herein, the terms “approximately,” “substantially,” “essentially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurs precisely or instances where the event or situation is close to occurring. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified. The term “substantially coplanar” may mean that the positional difference between two surfaces located along the same plane is within a few micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm when located along the same plane. When a numerical value or characteristic is referred to as “substantially” the same, the term may refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said values.

[0074] The foregoing has summarized the features of several embodiments and detailed aspects of this disclosure. The embodiments described in this disclosure can readily serve as the basis for designing or modifying other processes and structures to achieve the same or similar purposes and / or realize the same or similar advantages of the embodiments described herein. Such equivalent constructions do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device package comprising: Dielectric layer; An antenna structure, wherein the antenna structure is disposed in the dielectric layer; A semiconductor device, wherein the semiconductor device is disposed on the dielectric layer; An encapsulating material that covers the semiconductor device, wherein the dielectric constant of the dielectric layer is less than the dielectric constant of the encapsulating material; as well as The conductive post has a first part and a second part. Seed layer, The first portion is surrounded by the encapsulating material and the second portion is embedded in the dielectric layer. The first portion completely overlaps the second portion perpendicularly, and the first portion and the second portion are integrally formed. The dielectric layer defines a hole to accommodate the seed layer and the second portion.

2. The semiconductor device package of claim 1, wherein the first portion has a first side facing the semiconductor device and the second portion has a second side facing the semiconductor device, and the first side and the second side are substantially coplanar.

3. The semiconductor device package of claim 1, further comprising a redistribution layer RDL disposed on the encapsulant, wherein the RDL electrically connects the conductive pillars to the semiconductor device.

4. The semiconductor device package of claim 1, wherein the conductive pillar is electrically connected to the antenna structure.

5. The semiconductor device package of claim 2, wherein the seed layer covers the second side surface of the second portion of the conductive pillar, but does not cover the first side surface of the first portion.

6. The semiconductor device package of claim 1, wherein the antenna structure comprises a plurality of antenna elements, wherein each of the plurality of antenna elements is recessed from a surface of the dielectric layer opposite to the semiconductor device, the dielectric layer having a lower surface and an opposing upper surface, and at least one antenna element having a recess adjacent to the lower surface of the dielectric layer.

7. The semiconductor device package of claim 1, wherein the antenna structure includes an antenna element substantially aligned with the conductive post and the width of the antenna element is greater than the width of the conductive post, the dielectric layer has a lower surface and an opposing upper surface, and at least one antenna element has a lower surface exposed through the lower surface of the dielectric layer, and the lower surface of the at least one antenna element is non-planar.

8. The semiconductor device package of claim 1, further comprising a protective layer disposed on the antenna structure.

9. The semiconductor device package of claim 8, wherein the side of the seed layer is substantially aligned with the side of the antenna structure.

10. The semiconductor device package of claim 1, further comprising a conductive terminal disposed on the semiconductor device and having a first surface, wherein the conductive terminal has a second surface, and wherein the first surface and the second surface are substantially at the same height.

11. The semiconductor device package of claim 1, wherein the semiconductor device is in direct contact with the dielectric layer.

12. The semiconductor device package of claim 1, wherein the dielectric layer has a first coefficient of thermal expansion and the encapsulant has a second coefficient of thermal expansion, and the first coefficient of thermal expansion is greater than the second coefficient of thermal expansion.

13. A semiconductor device package comprising: A dielectric layer having an upper surface and a lower surface; An antenna structure, wherein the antenna structure is embedded in the dielectric layer; A semiconductor device disposed on the upper surface of the dielectric layer; An encapsulating material is disposed on the upper surface of the dielectric layer, and the dielectric constant of the dielectric layer is less than the dielectric constant of the encapsulating material. The conductive post has a first part and a second part. Seed layer, The first portion is surrounded by the encapsulating material and the second portion is embedded in the dielectric layer, wherein the first portion has a first side facing the semiconductor device and the second portion has a second side facing the semiconductor device, and the first side and the second side are substantially aligned, and the first portion and the second portion are integrally formed, and the dielectric layer defining aperture accommodates the seed layer and the second portion.

14. The semiconductor device package of claim 13, wherein the sidewalls of the dielectric layer and the sidewalls of the encapsulant are substantially continuous, the antenna structure includes a plurality of antenna elements, and at least one antenna element has a lower surface exposed through the lower surface of the dielectric layer, and the lower surface of the at least one antenna element is non-planar.

15. The semiconductor device package of claim 13, further comprising a redistribution layer RDL, wherein the RDL electrically connects the semiconductor device to the conductive pillars.

16. The semiconductor device package of claim 13, wherein the second portion of the conductive pillar is separated from the dielectric layer by the seed layer, the first portion of the conductive pillar directly contacts the encapsulant, and the second portion of the conductive pillar directly contacts the seed layer.

17. The semiconductor device package of claim 13, wherein the conductive pillar comprises solder in direct contact with the antenna structure.

18. A method for manufacturing a semiconductor device package, the method comprising: Form an antenna structure; A dielectric layer is formed to cover the antenna structure; A hole is defined in the dielectric layer to expose a portion of the antenna structure; A photoresist layer is formed to cover the dielectric layer; Pattern the photoresist layer to form a through-hole that exposes the hole; A first seed layer is formed along the first side of the through hole; A second seed layer is formed along the second side surface of the hole and on the antenna structure; A conductive post is formed, the conductive post having a first portion located inside the hole and a second portion located inside the through hole, and the first portion and the second portion are integrally formed; Remove the photoresist layer and the first seed layer; A semiconductor device is placed on the dielectric layer; An encapsulation material is formed to cover the semiconductor device and the second portion of the conductive pillar, wherein the first portion of the conductive pillar has a first side facing the semiconductor device and the second portion of the conductive pillar has a second side facing the semiconductor device, and the first side and the second side are substantially aligned, and the dielectric constant of the dielectric layer is less than the dielectric constant of the encapsulation material. as well as A redistribution layer RDL is formed on the encapsulation material to electrically connect the conductive pillars to the semiconductor device.

19. The method of claim 18, further comprising: Provide flat substrates; A conductive layer is formed on the flat substrate to support the antenna structure; Remove the flat substrate; as well as The conductive layer is ground to expose the antenna structure. The antenna structure described therein has a recess that is recessed from the surface of the dielectric layer.

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