Memory device and method of manufacturing the same

Abstract

A memory device and a method for manufacturing the same, the memory device comprising an erase gate, an erase gate dielectric, first and second floating gates, first and second control gates, a first select gate, a second select gate, a common source strip, and a silicide pad. The erase gate is located above a first portion of a substrate. The first select gate is separated from the erase gate at least partially by the first control gate along a first direction. The second select gate is separated from the erase gate at least partially by the second control gate along the first direction. The common source strip is located on a second portion of the substrate, wherein the common source strip and the erase gate are arranged along a second direction perpendicular to the first direction. The silicide pad is located below the common source strip and in the second portion of the substrate, wherein the upper surface of the silicide pad is flat to the lower surface of the erase gate dielectric.

Description

Technical Field

[0001] The present invention relates to a memory device and a method for manufacturing the same. Background Art

[0002] Flash memories have certain advantages and benefits over other forms of solid-state non-volatile memory structures. These advantages and benefits are mostly related to, for example, facilitating read, write and / or erase speed, power consumption, compactness, cost, etc. Flash memories are often used in high-density data storage devices, such as cameras, mobile phones, recorders, external USB data storage devices (also called thumb drives or flash drives), etc. Generally speaking, in applications, flash memories are manufactured on a precision microchip, which is then coupled to another chip or multiple chips with suitable processing circuits, and can be configured in the same package, or configured in different packages and electrically coupled.

[0003] Processors with embedded flash memory are a more recent development. In these devices, a flash memory array is fabricated on a single chip along with logic or control circuits. These configurations are mostly used in microcontroller units (MCUs), i.e. small computer components mounted on a single chip that are designed to perform a specific task repeatedly with a specific number of operations. MCUs are often used in smart cards, wireless communication components, control units in automobiles, etc. The combination of memory and associated processing circuitry can increase processing speed while reducing size, power consumption, and cost. Summary of the invention

[0004] Some embodiments of the present disclosure are a memory device including an erase gate, an erase gate dielectric, first and second floating gates, first and second control gates, a first select gate, a second select gate, a common source strip, and a silicide pad. The erase gate is located above a first portion of a substrate. The erase gate dielectric is located between the erase gate and the first portion of the substrate. The first and second floating gates are located on opposite sides of the erase gate. The first and second control gates are located above the first and second floating gates, respectively. The first select gate is separated from the erase gate at least partially by the first control gate along a first direction. The second select gate is separated from the erase gate at least partially by the second control gate along the first direction. The common source strip is located on a second portion of the substrate, wherein the common source strip is arranged with the erase gate along a second direction perpendicular to the first direction. The silicide pad is located below the common source strip and within the second portion of the substrate, wherein the upper surface of the silicide pad is flat to the lower surface of the erase gate dielectric.

[0005] Some embodiments of the present disclosure are a memory device including an erase gate, an erase gate dielectric, first and second floating gates, first and second control gates, a first select gate, a second select gate, a first silicide pad, a first floating gate spacer, and a second floating gate spacer. The erase gate is located above a first portion of a substrate. The erase gate dielectric is located between the erase gate and the first portion of the substrate. The first and second floating gates are located on opposite sides of the erase gate. The first and second control gates are located above the first and second floating gates, respectively. The first select gate is separated from the erase gate at least partially by the first control gate along a first direction. The second select gate is separated from the erase gate at least partially by the second control gate along the first direction. The first silicide pad is located in the second portion of the substrate, wherein the first silicide pad and the erase gate are arranged along a second direction perpendicular to the first direction. The first floating gate spacer is located on a sidewall of the first floating gate, wherein the first silicide pad is separated from the first floating gate by the first floating gate spacer. The second floating gate spacer is located on a sidewall of the second floating gate, wherein the first silicide pad is separated from the second floating gate by the second floating gate spacer.

[0006] Some embodiments of the present disclosure are a method for manufacturing a memory element, comprising forming a first floating gate and a second floating gate on a substrate; forming a first control gate and a second control gate respectively above the first floating gate and the second floating gate; forming a patterned mask to cover the first control gate and the second control gate, wherein the patterned mask exposes a first portion of the substrate between the first control gate and the second control gate, and the patterned mask covers a second portion of the substrate between the first control gate and the second control gate; forming a common source region in the first portion of the substrate, wherein the patterned mask protects the second portion of the substrate during the formation of the common source region; removing the patterned mask; forming an erase gate above the first portion of the substrate; and forming a common source strip above the second portion of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description and the accompanying drawings may provide an understanding of the various aspects of the present disclosure. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased as desired to facilitate clarity of discussion.

[0008] Figure 1A A top view of a memory device according to some embodiments of the present disclosure;

[0009] Figure 1B For some embodiments of the present disclosure, Figure 1A A cross-sectional view of line BB;

[0010] Figure 1C For some embodiments of the present disclosure, Figure 1A A cross-sectional view of line CC;

[0011] Figure 1D For some embodiments of the present disclosure, Figure 1A A cross-sectional view of line DD;

[0012] FIG. 2A to FIG. 33D Schematic diagrams of methods for manufacturing memory devices at different stages according to some embodiments of the present disclosure;

[0013] FIG. 34A to FIG. 34C A method for manufacturing a memory device according to some embodiments of the present disclosure.

[0014]

Explanation of symbols

[0015] 100:Memory components

[0016] 104:Substrate

[0017] 104A: Part

[0018] 104B: Part

[0019] 104P: Active Zone

[0020] 106: Isolation Structure

[0021] 108: Split-gate flash memory cell

[0022] 108a, 108b: memory unit

[0023] 126, 126a, 126b: drain region

[0024] 128: shared source region

[0025] 130a, 130b: channel area

[0026] 134, 134a, 134b: floating gate

[0027] 138, 138a, 138b: control gate

[0028] 140: Gate spacer

[0029] 142: floating gate spacer

[0030] 144: Erase gate

[0031] 146: Erase gate dielectric

[0032] 148:Select gate spacer

[0033] 149: floating gate spacer

[0034] 150, 150a, 150b: selection gate

[0035] 156: Select gate dielectric

[0036] 158:Floating gate dielectric

[0037] 160: Control gate dielectric

[0038] 160CS: Common source strip

[0039] 160D: Drain Strip

[0040] 160EG: Erase gate strip

[0041] 170, 172: Silicide pad

[0042] 200, 202: interlayer dielectric layer

[0043] 210: Control gate hard mask

[0044] 300: Hard Mask

[0045] 302, 304: Patterned mask

[0046] 403: Gate Oxide

[0047] 602: floating gate layer

[0048] 702: Control gate stack

[0049] 704: Control gate dielectric layer

[0050] 706: Control gate layer

[0051] 708: Control gate hard mask

[0052] 902: Control gate spacer layer

[0053] 1502: Dielectric layer

[0054] 1504: Gate layer

[0055] 1702: Hard mask layer

[0056] M1, M2, M3, M4: Patterned Mask

[0057] O1, O2, O3, O4, O5: Open

[0058] W1, W2, W3, W4, W5: Width

[0059] AA, BB, CC: Line DETAILED DESCRIPTION

[0060] The following disclosure provides many different embodiments or examples for implementing different features of the main content provided by this case. The components and configuration of a specific example are described below to simplify this disclosure. Of course, this example is only illustrative and is not intended to be limiting. For example, the following description "a first feature is formed above or on a second feature" may include the first feature being in direct contact with the second feature in an embodiment, and may also include forming an additional feature between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may reuse component symbols and / or letters in each example. The purpose of this repetition is to simplify and clarify, and it does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0061] Additionally, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, are used herein to simplify descriptions to describe the relationship of one element or feature to another element or feature as illustrated in the accompanying drawings. In addition to depicting the illustrated orientation, the spatially relative terms also encompass different orientations of the elements in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0062] Flash memory can be formed in a bulk silicon substrate and uses different voltage conditions to read and write data values. For example, the third generation SUPERFLASH (ESF3) includes a group of symmetrical split gate memory cells, each of which includes a group of source / drain regions and a channel region located therebetween. In the ESF3 structure, one of the source / drain regions for each split gate memory cell is used as a common source / drain region and is shared with adjacent split gate memory cells, while the other source / drain region is an independent source / drain region within the cell. In each split gate memory cell, a floating gate is disposed on the channel region of the cell, and a control gate is disposed on the floating gate. A select gate is disposed on one side of the floating gate and the control gate (e.g., between the independent source / drain regions of the ESF3 cell and the sidewalls of the floating gate and / or the control gate). At least one cell is configured to store a variable charge value in the floating gate, wherein the charge value corresponds to a data state stored in the cell and is stored in a non-volatile form so that the stored charge / data is maintained in the absence of power.

[0063] By changing the amount of charge stored in the floating gate, the threshold voltage V th For example, when performing a program operation on a cell (e.g., writing logic "0", writing 0, high V th ), a voltage higher than the voltage across the channel region and / or the voltage applied to the select gate is applied to the control gate (e.g., at least an order of magnitude higher). This higher voltage promotes Fowler-Nordheim tunneling of carriers from the channel region toward the control gate. As the carriers tunnel toward the control gate, they are trapped by the floating gate and adjust the cell's V th On the contrary, when performing an erase operation (e.g., writing logic "1", writing 1, low V th ), a voltage higher than the voltage across the channel region and / or the voltage applied to the select gate (e.g., at least an order of magnitude higher) is applied to the erase gate. This higher voltage promotes Fowler-Nordheim tunneling of carriers from the floating gate toward the erase gate, thereby removing charge from the floating gate and re-adjusting the cell's V in a predictable manner. th Then, in the read operation, a voltage is applied to the select gate to induce a portion of the channel region to conduct. Applying a voltage to the select gate can attract carriers in a portion of the channel region next to the select gate. Once the select gate voltage is applied, the voltage greater than V th But less than V th +ΔV th (where ΔV th V is caused by the floating gate capturing charge th Another voltage (amount of change) is applied to the control gate. If the memory cell element is turned on (e.g., allows charge to flow), it is considered to have a first data state (e.g., read as a logic "1"). If the memory cell element is not turned on, it is considered to have a second data state (e.g., read as a logic "0").

[0064] Some embodiments of the present disclosure are directed to flash memory devices formed in recessed regions of a substrate. Although some embodiments depicted below are directed to split-gate flash memory, it should be understood that the concepts are not limited to split-gate flash memory cells and can be applied to other types of flash memory cells and other types of semiconductor devices, such as metal oxide field effect transistors (MOSFETs), fin field effect transistors (FinFETs), or the like.

[0065] Figure 1A FIG. 1 is a top view of a memory device 100 according to some embodiments of the present disclosure. Figure 1B For some embodiments of the present disclosure, Figure 1A A cross-sectional view of line BB. Figure 1C For some embodiments of the present disclosure, Figure 1A Cross-sectional view of line CC. Figure 1D For some embodiments of the present disclosure, Figure 1A A cross-sectional view of line DD.

[0066] The memory device 100 includes a substrate 104. In some embodiments, the substrate 104 includes an active region 104P and is horizontally surrounded by an isolation structure 106 composed of a dielectric material. The semiconductor substrate 104 can be or include, for example, a bulk silicon substrate, a III-V substrate, a silicon-on-insulator (SOI) substrate, other suitable semiconductor substrates, or the like. The isolation structure 106 can be a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, other suitable isolation structures, combinations thereof, or the like. In some embodiments, if the isolation structure 106 is composed of an oxide (e.g., silicon oxide), the active region 104P can also be referred to as an oxide defined (OD) region.

[0067] exist Figure 1A In the example shown, the memory device 100 includes a memory cell array. In the example shown, the memory cell array includes a plurality of split-gate flash memory cells 108, wherein each pair of split-gate flash memory cells 108 includes a first memory cell 108a and a second memory cell 108b.

[0068] like Figure 1A and Figure 1B As shown, Figure 1B 1 is a cross-sectional view along the length direction of the vertical erase gate 144 and through the erase gate 144. The first and second drain regions 126a, 126b (corresponding to the first and second memory cells 108a, 108b, respectively) are disposed in the substrate 104, and the common source region 128 (commonly used between the first and second memory cells 108a, 108b) is disposed in the substrate 104 and is separated from the first and second drain regions 126a, 126b in the horizontal direction. The first drain region 126a and the common source region 128 are separated by the first channel region 130a, and the common source region 128 and the second drain region 126b are separated by the second channel region 130b.

[0069] The erase gate 144 is disposed above the common source region 128 and is separated from the common source region 128 by an erase gate dielectric 146. The first and second floating gates 134a, 134b are respectively disposed above the first and second channel regions 130a, 130b of the substrate 104. The first and second control gates 138a, 138b cover the first and second floating gates 134a, 134b, respectively. The first and second select gates 150a, 150b cover the first and second channel regions 130a, 130b, respectively, and are separated in the horizontal direction by the first and second floating gates 134a, 134b and the erase gate 144.

[0070] In some embodiments, the erase gate dielectric 146 wraps around the bottom of the erase gate 144 and vertically separates the bottom of the erase gate 144 from the common source region 128, and horizontally separates the erase gate 144 from the first and second floating gates 134a and 134b. The erase gate dielectric 146 may have a convex upper surface and a convex lower surface, and may be doped polysilicon, metal, other suitable conductive materials, combinations thereof, or the like. In some embodiments, the erase gate dielectric 146 and the common source region 128 have a curved interface, and the erase gate dielectric 146 and the erase gate 144 have a curved interface.

[0071] The erase gate 144, the first and second control gates 138a, 138b, the first and second floating gates 134a, 134b, and the first and second select gates 150a, 150b can be doped polysilicon, metal, other suitable conductive materials, combinations thereof, or the like. The erase gate dielectric 146 can be or include, for example, oxide, nitride, other suitable dielectrics, combinations thereof, or the like.

[0072] A pair of gate spacers 140 are located above the first and second floating gates 134a, 134b and on opposite sidewalls of the first and second control gates 138a, 138b. A select gate dielectric 156 separates the first and second select gates 150a, 150b from the substrate 104, and a floating gate dielectric 158 separates the first and second floating gates 134a, 134b from the substrate 104. A control gate dielectric 160 separates the first and second floating gates 134a, 134b from the first and second control gates 138a, 138b, respectively. In some embodiments, at least two of the select gate dielectric 156, the floating gate dielectric 158, and / or the control gate dielectric 160 have the same composition and have the same thickness. However, in other embodiments, the select gate dielectric 156, the floating gate dielectric 158, and / or the control gate dielectric 160 each have a different composition and / or a different thickness.

[0073] The control gate spacers 140 may have a suitable composition. In some embodiments, the control gate spacers 140 may be or include, for example, nitrides, oxides, other suitable dielectrics, combinations thereof, or the like. In some embodiments, the control gate spacers 140 are homogenous materials. In other embodiments, each of the control gate spacers 140 is an ONO structure. For example, the control gate spacers 140 may include an oxide-nitride-oxide structure and have an outer oxide layer, an intermediate nitride layer, and an inner oxide layer.

[0074] The select gate dielectric 156 can be or include, for example, an oxide, a nitride, other suitable dielectrics, combinations thereof, or the like. The control gate dielectric 160 can be or include, for example, an oxide, a nitride, other suitable dielectrics, combinations thereof, or the like.

[0075] The floating gate spacer 142 separates the first and second select gates 150a and 150b from the first and second floating gates 134a and 134b, respectively, and from the first and second control gates 138a and 138b, respectively. The floating gate spacer 142 is located above the first and second channel regions 130a and 130b. Figure 1B In the embodiment of the present invention, each floating gate spacer 142 is located on the sidewalls of the first and second floating gates 134a and 134b, respectively. The select gate spacers 148 are located on the sidewalls of the first and second select gates 150a and 150b, respectively.

[0076] The floating gate spacer 142 may have a suitable composition. In some embodiments, the floating gate spacer 142 may be or include, for example, a nitride, an oxide, other suitable dielectric, a combination thereof, or the like. In some embodiments, the floating gate spacer 142 is a homogenous material. In other embodiments, each of the floating gate spacers 142 is an ONO structure. For example, the floating gate spacer 142 may include an oxide-nitride-oxide structure and have an outer oxide layer, an intermediate nitride layer, and an inner oxide layer. In some embodiments, the floating gate spacer 142 may have the same composition as the control gate spacer 140. The select gate spacer 148 may be or include, for example, a nitride, an oxide, other suitable dielectric, a combination thereof, or the like.

[0077] The silicide pad 170 is located above the first and second drain regions 126a and 126b, respectively. In some embodiments, the silicide pad 170 includes the same doping as the first and second drain regions 126a and 126b. In some embodiments, the silicide pad 170 can be nickel silicide (NiSi) or other suitable silicides, and can be formed by a suitable silicide process.

[0078] The first interlayer dielectric layer 200 is located above the first and second drain regions 126a, 126b and the silicide pad 170. In some embodiments, the silicide pad 170 separates the first interlayer dielectric layer 200 and the first and second drain regions 126a, 126b. The second interlayer dielectric layer 202 is located above the erase gate 144, the first and second control gates 138a, 138b, and the first and second select gates 150a, 150b. The drain strip 160D extends through the first and second interlayer dielectric layers 200, 202 to the silicide pad 170. In some embodiments, the drain strip 160D may also be referred to as a drain contact 160D.

[0079] In some embodiments, the first and second interlayer dielectric layers 200, 202 may be oxides, low-k dielectrics, other suitable dielectrics, combinations thereof, or the like. The low-k dielectrics referred to herein are dielectrics having a dielectric constant (k) lower than about 3.9. In some embodiments, if the first and second interlayer dielectric layers 200, 202 are made of the same material, the first and second interlayer dielectric layers 200, 202 may be fused together and may not have an identifiable interface therebetween. The drain strip 160D is a conductive material and may be tungsten, copper, aluminum, copper-aluminum, other suitable metals or conductive materials, combinations thereof, or the like.

[0080] like Figure 1A and Figure 1C As shown, Figure 1C FIG. 1 is a cross-sectional view along the length direction of the vertical erase gate 144 and through the common source strip 160CS. Figure 1C Some of the components in Figure 1B Therefore, these components are numbered the same and the related structural details will not be repeated. Figure 1B and Figure 1C have the same size, so Figure 1B and Figure 1C The proportions of the components are the same.

[0081] Figure 1CIn the embodiment, the upper surfaces of the first and second floating gates 134a and 134b are collinear with the upper surface of the isolation structure 106. In some embodiments, the control gate dielectric 160 located below the first control gate 138a extends from the upper surface of the first floating gate 134a to the upper surface of the isolation structure 106. The control gate dielectric 160 located below the second control gate 138b extends from the upper surface of the second floating gate 134b to the upper surface of the isolation structure 106. Figure 1C In the cross-sectional view of FIG. 1 , the first and second floating gates 134 a, 134 b and the floating gate dielectric are narrower than the first and second control gates 138 a, 138 b and the control gate dielectric 160. However, in FIG. Figure 1B In the cross-sectional view of , the first and second floating gates 134a, 134b and the floating gate dielectric are wider than the first and second control gates 138a, 138b and the control gate dielectric 160.

[0082] The silicide pad 172 is disposed on the substrate 104. The first interlayer dielectric layer 200 is located above and in contact with the silicide pad 172. The common source strip 160CS extends through the first and second interlayer dielectric layers 200, 202 to the silicide pad 172. In some embodiments, the common source strip 160CS may also be referred to as a common source contact 160CS. In some embodiments, the silicide pad 172 may be nickel silicide (NiSi) or other suitable silicides, and may be formed by a suitable silicidation process. In some embodiments, the doping concentration (e.g., implanted impurity concentration) of the silicide pad 172 may be lower than Figure 1B In some embodiments, the silicide pad 172 does not have the doping of the silicide pad 170 .

[0083] In the length direction of the vertical erase gate 144, the upper surface ( Figure 1C ) compared to the lower surface of the erased gate dielectric 146 ( Figure 1B For example, the lower surface of the erase gate dielectric 146 is curved, while the upper surface of the silicide pad 172 is substantially flat.

[0084] exist Figure 1CIn some embodiments, the floating gate spacer 149 is located on the sidewalls of the first and second floating gates 134a and 134b, the sidewalls of the floating gate dielectric 158, and the sidewalls of the control gate spacer 140 to separate the first and second floating gates 134a and 134b, the floating gate dielectric 158, the control gate spacer 140, and the first interlayer dielectric layer 200. In some embodiments, at least a portion of the portion of the substrate 104 directly below the floating gate spacer 149 does not have a silicide pad 172. In some embodiments, the silicide pad 172 is separated from the first and second floating gates 134a and 134b and the floating gate dielectric 158 in the horizontal direction by the floating gate spacer 149. That is, the silicide pad 172 is separated from the first and second floating gates 134a and 134b by a non-zero distance, respectively. In some embodiments, the floating gate spacer 149 is composed of nitride, and the first interlayer dielectric layer 200 is composed of oxide. In some embodiments, the thickness of the floating gate spacer 149 is less than about 10 nm and greater than about 5 nm.

[0085] It should be understood that the floating gate spacer 149 is Figure 1B does not exist in the cross-section diagram, so Figure 1B The erase gate dielectric 146 is disposed along and in contact with the sidewalls of the first and second floating gates 134a, 134b, the sidewalls of the floating gate dielectric 158, and the sidewalls of the control gate spacer 140. In some embodiments, the width of the silicide pad 172 is smaller than the width of the erase gate dielectric 146 and the width of the common source region 128. For example, the erase gate dielectric 146 has a maximum width W1 ( Figure 1B ), and the silicide pad 172 has a width W2 ( Figure 1C ), wherein the width W1 is greater than the width W2. On the other hand, the width W2 of the silicide pad 172 is less than the distance between the first and second floating gates 134a and 134b.

[0086] like Figure 1A and Figure 1D As shown, Figure 1D FIG. 1 is a cross-sectional view along the length direction of the erase gate 144 and through the erase gate 144 and the common source strip 160CS. Figure 1D Some of the components in Figure 1B and Figure 1C Therefore, these components are numbered the same and the related structural details will not be repeated. Figure 1B , Figure 1C and Figure 1D have the same size, so Figure 1B , Figure 1C and Figure 1D The proportions of the components are the same.

[0087] exist Figure 1DIn the cross-sectional view of FIG. 1 , the erase gate 144 is divided into a first portion 144A and a second portion 144B by the common gate strip 160CS and the first interlayer dielectric layer 200. A plurality of erase gate strips 160EG extend through the second interlayer dielectric layer 202 and contact the first portion 144A and the second portion 144B of the erase gate 144, respectively. In some embodiments, the upper surface of the silicide pad 172 is lower than the upper surface of the erase gate dielectric 146 and higher than the lower surface of the erase gate dielectric 146. In some embodiments, Figure 1D , the silicide pad 172 has a width W3, wherein the width W3 ranges from about 80 nm to about 120 nm. The silicide pad 172 contacts the common source region 128 and the common source strip 160CS, thereby electrically connecting the common source strip 160CS to the common source region 128. In some embodiments, the doping concentration (e.g., implanted impurities) in the silicide pad 172 (or the region below the silicide pad 172) is lower than the doping concentration of the common source region 128. In some embodiments, the silicide pad 172 does not substantially have the dopant of the common source region 128.

[0088] FIG. 2A to FIG. 33D Schematic diagram of a method for manufacturing a memory device according to some embodiments of the present disclosure at different stages. FIG. 2A to FIG. 33D For manufacturing Figures 1A to 1D A method of storing a memory device 100.

[0089] Reference FIG. 2A to FIG. 2C ,in Figure 2A for Figure 1A The initial structure of the memory element 100, and Figure 1A With the same top view, Figure 2B For along Figure 2A The cross-section of line BB, Figure 2C For along Figure 2A . A semiconductor substrate 104 is shown. In some embodiments, the semiconductor substrate 104 may be or include, for example, a bulk silicon substrate, a III-V substrate, a silicon-on-insulator (SOI) substrate, other suitable semiconductor substrates, or the like. The semiconductor substrate 104 may be a binary semiconductor substrate (e.g., GaAs), a ternary semiconductor substrate (e.g., AlGaAs), or a polysilicon substrate. In some embodiments, the semiconductor substrate 104 includes an active region 104P, wherein the active region 104P may be formed by recessing the substrate 104 according to a predetermined pattern.

[0090] Isolation structures 106 are then formed in the substrate 104 and surround the active regions 104P, thereby providing electrical isolation between the active regions 104P. FIG. 2A to FIG. 2C. In some embodiments, the isolation structure 106 may be a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, other suitable isolation structures, a combination of the above, or the like. In some embodiments, forming the isolation structure 106 includes, for example, forming an oxide layer above the substrate and a nitride layer above the oxide layer. Forming a patterned mask above the nitride layer. Using the patterned mask as an etching mask, etching the nitride layer and the oxide layer into the substrate 104. An isolation structure 106 composed of oxide is formed by depositing oxide or an oxide precursor. Performing a chemical mechanical polishing process (CMP) to planarize the isolation structure 106 and the nitride. The nitride layer and the oxide layer are then removed from above the substrate 104. Therefore, the upper surface of the isolation structure 106 will be higher than the upper surface of the active region 104P of the substrate 104, such as Figure 2C For example, the height difference between the upper surface of the isolation structure 106 and the upper surface of the active region 104P of the substrate 104 is equal to the total thickness of the removed nitride layer and oxide layer, but the present disclosure is not limited thereto.

[0091] Reference FIG. 3A to FIG. 3C ,in Figure 3A For Figures 1A to 1C A top view of the memory device 100 after operation, and Figure 2A With the same top view, Figure 3B For along Figure 3A The cross-section of line BB, Figure 3C For along Figure 3A For simplicity, Figure 3B and Figure 3C Some components of Figure 3A The gate oxide 403 is grown on the exposed portion of the semiconductor substrate 104. In some embodiments, the gate oxide 403 may be selectively grown on the exposed portion of the semiconductor substrate 104 by a selective oxidation process (e.g., wet oxidation and / or thermal oxidation), so that the upper surface of the isolation structure 106 is substantially not covered by the gate oxide 403.

[0092] A floating gate layer 602 is then formed over the semiconductor substrate 104. The floating gate layer 602 may be conformally formed and may be doped polysilicon or other suitable conductive material. In some embodiments, the floating gate layer 602 may be formed by CVD, PVD, sputtering, or other suitable deposition processes. Next, a planarization process may be performed to remove the floating gate layer 602 over the isolation structure 106 until the isolation structure 106 is exposed. The planarization process recesses the top surface of the floating gate layer 602 so that it is substantially level with the top surface of the isolation structure 106. In some embodiments, the planarization process may be CMP or other suitable planarization process.

[0093] A control gate stack 702 may then be formed on the planarized surface of the floating gate layer 602 and the isolation structure 106. In some embodiments, the control gate stack 702 includes a control gate dielectric layer 704, a control gate layer 706, and a control gate hard mask 708. The control gate dielectric layer 704 may be formed by CVD, PVD, other suitable deposition processes, combinations thereof, or the like. In some embodiments, the total thickness of the control gate dielectric layer 704 is approximately In some embodiments, the total thickness of the control gate dielectric layer 704 is approximately

[0094] The control gate layer 706 may be formed conformally and may be doped polysilicon or other suitable conductive material. In some embodiments, forming the control gate layer 706 includes depositing a material, implanting dopants into the material, and annealing to activate the dopants. The material of the control gate layer 706 may be formed by CVD, PVD, or other suitable deposition processes. In some embodiments, the thickness of the control gate layer 706 is about In some embodiments, the thickness of the control gate layer 706 is approximately In some embodiments, the thickness of the control gate layer 706 is approximately

[0095] The control gate hard mask 708 may include multiple layers of different materials. The control gate hard mask 708 may include an oxide, a nitride, or a suitable material. In some embodiments, the control gate hard mask 708 includes an oxide layer located above a first nitride layer. In some embodiments, the thickness of these layers is about In some embodiments, the thickness of these layers is about In some embodiments, the thickness of these layers is about In some embodiments, the control gate hard mask 708 further includes a second nitride layer on the oxide layer. The control gate hard mask 708 can be formed by CVD, PVD, other suitable deposition processes, or a combination thereof.

[0096] Reference FIG. 4A to FIG. 4C ,in Figure 4A For FIG. 4A to FIG. 4C A top view of the memory device 100 after operation, and Figure 3A With the same top view, Figure 4B For along Figure 4A The cross-section of line BB, Figure 4C For along Figure 4A For simplicity, Figure 4B and Figure 4C Some components of Figure 4A602. A selective etch is performed to remove a portion of the control gate stack 702, thereby forming a control gate hard mask 210, a control gate 138, and a control gate dielectric 160 on the floating gate layer 602. In some embodiments, the process of performing the selective etch includes forming a photoresist layer. The photoresist layer may be patterned to define a pattern of the control gate 138. An etching process is then performed using the photoresist layer until the floating gate layer 602 is exposed. In some embodiments, the photoresist layer may then be removed.

[0097] Reference Figure 5A and Figure 5B ,in Figure 5A and Figure 4B have the same cross section, and Figure 5B and Figure 4C A control gate spacer layer 902 is conformally formed on the floating gate layer 602, the control gate dielectric 160, the control gate 138, and the control gate hard mask 210. In some embodiments, the control gate spacer layer 902 can be formed by CVD, PVD, or other suitable deposition processes.

[0098] Reference Fig. 6A and Figure 6B ,in Fig. 6A and Figure 5A have the same cross section, and Figure 6B and Figure 5B The control gate spacer layer 902 is etched (see Figure 5A and Figure 5B ) to form a control gate spacer 140. As a result of etching, the control gate spacer 140 covers the opposite sidewalls of the control gate 138. In some embodiments, the control gate spacer 140 is located on the isolation structure 106, such as Figure 6B As shown. The etching process includes plasma etching or other etching processes, which selectively removes the horizontal portion of the control gate spacer layer 902. In more detail, these spacers may have rounded corners and smoothly inclined sidewall surfaces at the upper portion. On the other hand, the floating gate layer 602 and the gate oxide 403 (see Figure 5A and Figure 5B ) Another etching process is performed to form the floating gate 134 and the floating gate dielectric 158. In some embodiments, the control gate spacer 140 and the control gate hard mask 210 can be used as an etching mask in this etching step.

[0099] Reference Fig. 7A and Figure 7B ,in Fig. 7A and Fig. 6A have the same cross section, and Figure 7B and Figure 6BA plurality of floating gate spacers 142 are formed on opposite sidewalls of the floating gate 134 and on the sidewalls of each control gate spacer 140. In some embodiments, the process of forming the floating gate spacers 142 includes depositing a floating gate spacer layer on the Fig. 6A and Figure 6B In the structure shown, plasma etching or other suitable etching process is then performed to remove the horizontal portion of the floating gate spacer layer. The floating gate spacer 142 can be formed by CVD, PVD, or other suitable deposition process. For ease of description, the floating gate spacer 142 is drawn as having vertical sidewalls. In other embodiments, the floating gate spacer 142 may have rounded corners and smoothly inclined sidewall surfaces at the upper portion.

[0100] Reference FIG. 8A to FIG. 8D ,in Fig. 8A For Fig. 7A and Figure 7B A top view of the memory device 100 after operation, and Figure 4A With the same top view, Figure 8B For along Fig. 8A The cross-section of line BB, Figure 8C For along Fig. 8A The cross-sectional view of line CC, and Fig.8D For along Fig. 8A For simplicity, FIG. 8B to FIG. 8D Some components of Fig. 8A A patterned mask M1 is formed on the substrate 104. In some embodiments, the patterned mask M1 may be a photoresist layer. The patterned mask M1 may be patterned by a photolithography process.

[0101] In some embodiments, the patterned mask M1 has a plurality of openings exposing a portion 104A of the substrate 104. On the other hand, along a direction parallel to the length direction of the control gate 138, the patterned mask M1 covers a portion 104B of the substrate 104 (see Fig. 8A In detail, portion 104B defines the location of a subsequently formed common source strip (eg, FIG. 32A to FIG. 32D Therefore, the portion 104B may also be referred to as a common source strip forming region. On the other hand, the patterned mask M1 exposes a portion 104A of the substrate 104, wherein the portion 104A defines the location of the erase gate to be subsequently formed (eg, FIG. 22A to FIG. 22C The erase gate 144).

[0102] Fig.8DIn the embodiment, along the direction parallel to the length direction of the control gate 138, the covered portion 104B of the substrate 104 is located between the exposed portions 104A of the substrate 104. In other words, the exposed portions 104A of the substrate 104 are located on both sides of the covered portion 104B of the substrate 104.

[0103] Reference 9A to 9C ,in 9A to 9C Respectively and FIG. 8B to FIG. 8D The common source regions 128 are formed in the substrate 104 and between the floating gates 134. In some embodiments, the process of forming the common source regions 128 includes ion implantation or other suitable doping processes. In some embodiments, dopants are introduced into the exposed portion 104A of the substrate 104 through the opening O1 of the patterned mask M1 to form the common source regions 128 in the substrate 104. On the other hand, the covered portion 104B of the substrate 104 is protected by the patterned mask M1 during the ion implantation, so that the covered portion 104B of the substrate 104 does not have the dopants of the common source regions 128. It is intended that the dopant concentration of the covered portion 104B of the substrate 104 will be lower than the dopant concentration of the common source regions 128 (the exposed portion 104A of the substrate 104).

[0104] Reference FIG. 10A to FIG. 10C ,in FIG. 10A to FIG. 10C Respectively and 9A to 9C The floating gate spacer 142 exposed through the opening O1 of the patterned mask M1 is removed. The process of removing the floating gate spacer 142 may include an etching process, and the patterned mask M1 is used as an etching mask.

[0105] Reference FIG. 11A to FIG. 11C ,in FIG. 11A to FIG. 11C Respectively and FIG. 10A to FIG. 10C have the same cross-section. The patterned mask M1 is removed by an appropriate process, such as stripping. An erase gate dielectric 146 is formed to cover the common source region 128 and to attach to the sidewalls of the floating gate 134 and the sidewalls of the control gate spacer 140. The process for forming the erase gate dielectric 146 may include high temperature oxidation (HTO), in-situ steam generation (ISSG) oxidation, other suitable deposition or growth processes, combinations of the above, or the like. In some embodiments. The erase gate dielectric 146 can be formed by an oxide deposition process followed by an oxide growth process. In some embodiments, such as Fig.11AAs shown in the cross-sectional view of FIG. 1 , the erased gate dielectric 146 produces a curved or bulbous surface profile due to the ion implantation of the common source region 128. The central region of the common source region 128 receives a higher dose of dopants, so the central region of the common source region 128 will be more damaged than the peripheral region. Therefore, the oxide will have a faster growth rate in the central region than in the peripheral region.

[0106] exist Fig. 11B and Fig. 11C In the embodiment of the present invention, as mentioned above, since the exposed portion 104B of the substrate 104 is a region without dopants, the growth rate of the erase gate dielectric 146 on the undoped portion 104B of the substrate 104 is lower than the growth rate on the doped portion 104A of the substrate 104. Therefore, the erase gate dielectric 146 has a thickness T1 above the doped portion 104A of the substrate 104, and the erase gate dielectric 146 has a thickness T2 above the undoped portion 104B of the substrate 104, wherein the thickness T1 is greater than the thickness T2. In other words, the thickness of the erase gate dielectric 146 on the doped portion 104A is greater than the thickness of the erase gate dielectric 146 on the undoped portion 104B. Fig. 11B In the cross-sectional view of , the erase gate dielectric 146 has a substantially flat bottom surface above the undoped portion 104B. That is, in a direction along the length direction perpendicular to the control gate 138, the bottom surface of the portion of the erase gate dielectric 146 above the undoped portion 104B is flatter than the bottom surface of the portion of the erase gate dielectric 146 on the doped portion 104A.

[0107] Reference FIG. 12A to FIG. 12D ,in Fig. 12A For FIG. 11A to FIG. 11C A top view of the memory device 100 after operation, and Fig. 8A With the same top view, Fig. 12B For along Fig. 12A The cross-section of line BB, Fig. 12C For along Fig. 12A The cross-sectional view of line CC, and Fig.12D For along Fig. 12AA cross-sectional view of line DD of the substrate 104 is shown. A patterned mask M2 is formed on the substrate 104. Next, an etching process is performed to remove the unnecessary portion of the erase gate dielectric 146. In detail, the patterned mask M2 is formed on and protects the erase gate dielectric 146 above the common source region 128. For example, the erase gate dielectric 146 covers the portion 104A of the substrate 104 and exposes the portion 104B of the substrate 104. Therefore, the erase gate dielectric 146 above the portion 104B of the substrate 104 is removed through the patterned mask M2, so that the portion 104B of the substrate 104 is exposed to the patterned mask M2. In some embodiments, the pattern of the patterned mask M2 is substantially the same as Fig. 8A The pattern of the patterned mask M1 is shown to be reversed.

[0108] Reference FIG. 13A to FIG. 13D ,in Fig.13A For FIG. 12A to FIG. 12D A top view of the memory device 100 after operation, and Fig. 12A With the same top view, Fig. 13B For along Fig.13A The cross-section of line BB, Fig. 13C For along Fig.13A The cross-sectional view of line CC, and Fig.13D For along Fig.13A DD. The patterned mask M2 is removed. A dielectric layer 1502 is selectively formed on the exposed surface of the substrate 104. For example, the dielectric layer 1502 covers a portion 104B of the substrate 104. The process for forming the dielectric layer 1502 may include high temperature oxidation, in-situ vapor generation oxidation, other suitable deposition or growth processes, combinations thereof, or the like.

[0109] Reference FIG. 14A to FIG. 14D ,in Fig.14A For FIG. 13A to FIG. 13D A top view of the memory device 100 after operation, and Fig.13A With the same top view, Fig. 14B For along Fig.14A The cross-section of line BB, Fig. 14C For along Fig.14A The cross-sectional view of line CC, and Fig.14D For along Fig.14A A gate layer 1504 is formed on the substrate 104 and covers the dielectric layer 1502. The gate layer 1504 may be made of doped polysilicon, metal, or other suitable conductive materials, and may be formed by CVD, PVD, or other suitable methods.

[0110] Reference FIG. 15A to FIG. 15D ,in Fig.15A For FIG. 14A to FIG. 14DA top view of the memory device 100 after operation, and Fig.14A With the same top view, Fig. 15B For along Fig.15A The cross-section of line BB, Fig. 15C For along Fig.15A The cross-sectional view of line CC, and Fig.15D For along Fig.15A DD. The gate layer 1504 is etched back until the upper surface of the gate layer 1504 is lower than the upper surface of the control gate hard mask 210. In some embodiments, the upper surface of the gate layer 1504 is substantially flush with the upper surface of the control gate 138. In some embodiments, the etching process causes the recessed gate layer 1504 to have a substantially flat surface. After the etching process, dopants may be implanted into the gate layer 1504, and then an annealing process may be performed to activate the dopants. In some embodiments, the portion of the gate layer 1504 that remains above the erase gate dielectric 146 is referred to as the erase gate 144.

[0111] Reference FIG. 16A to FIG. 16C ,in FIG. 16A to FIG. 16C Respectively and FIG. 15B to FIG. 15D The hard mask layer 1702 is conformally formed on the substrate 104. The hard mask layer 1702 can be formed by CVD, PVD, or other suitable deposition methods.

[0112] Reference FIG. 17A to FIG. 17D ,in Fig.17A For FIG. 16A to FIG. 16C A top view of the memory device 100 after operation, and Fig.15A With the same top view, Fig. 17B For along Fig.17A The cross-section of line BB, Fig. 17C For along Fig.17A The cross-sectional view of line CC, and Fig.17D For along Fig.17A A patterned mask M3 is formed above the substrate 104. Then, an etching process is performed through the patterned mask M3 to pattern the hard mask layer 1702 and the gate layer 1504 (see FIG. 16A to FIG. 16C ) to form the selection gate 150. In some embodiments, the patterned mask M3 may be a photoresist.

[0113] Reference 18A to 18D ,in Fig.18A For FIG. 17A to FIG. 17D A top view of the memory device 100 after operation, and Fig.17A With the same top view, Fig.18B For along Fig.18A The cross-section of line BB, Fig. 18C For along Fig.18A The cross-sectional view of line CC, and Fig.18D For along Fig.18A Remove the patterned mask M3 (refer to FIG. 17A to FIG. 17D ). In some embodiments, the patterned mask M3 can be removed by a suitable method, such as stripping. A select gate spacer 148 is formed along the outer sidewall of the select gate 150. The select gate spacer 148 can be formed by depositing a spacer layer and removing the thinnest portion of the spacer layer. The select gate spacer 148 can be formed by CVD, PVD, other suitable deposition processes, combinations thereof, or the like.

[0114] Reference FIG. 19A to FIG. 19C ,in FIG. 19A to FIG. 19C Respectively and FIG. 18B to FIG. 18D The hard mask 300 is formed above the substrate 104 and adjacent to the select gate spacer 148. In some embodiments, the hard mask 300 may be formed with a planarized upper surface. The process of forming the hard mask 300 includes spin coating an organic anti-reflective coating (ARC) coating.

[0115] Reference FIG. 20A to FIG. 20D ,in Fig. 20A For FIG. 19A to FIG. 19C A top view of the memory device 100 after operation, and Fig.18A With the same top view, Fig. 20B For along Fig. 20A The cross-section of line BB, Fig. 20C For along Fig. 20A The cross-sectional view of line CC, and Fig.20D For along Fig. 20A A patterned mask M4 is formed above the substrate 104. In some embodiments, the patterned mask M4 has an opening O2 located above the portion 104B of the substrate 104. For example, the gate layer 1504 above the portion 104B of the substrate 104 is exposed through the patterned mask M4. Fig. 20A In the embodiment, a portion of the selection gate 150 is exposed through the patterned mask M4. In some embodiments, the patterned mask M4 is a photoresist.

[0116] Reference FIG. 21A to FIG. 21D ,in Fig.21A For FIG. 20A to FIG. 20D A top view of the memory device 100 after operation, and Fig. 20A With the same top view, Fig.21B For along Fig.21A The cross-section of line BB, Fig. 21C For along Fig.21AThe cross-sectional view of line CC, and Fig.21D For along Fig.21A DD. The etching process is performed to remove the portion of the gate layer 1504 above the portion 104B of the substrate 104 through the opening O2. Therefore, the portion 104B of the substrate 104 is exposed through the patterned mask M4 after the etching process. On the other hand, the portion of the select gate 150 exposed through the patterned mask M4 is removed, as shown in FIG. Fig.21A shown.

[0117] Reference FIG. 22A to FIG. 22D ,in Fig.22A For FIG. 21A to FIG. 21D A top view of the memory device 100 after operation, and Fig.21A With the same top view, Fig. 22B For along Fig.22A The cross-section of line BB, Fig. 22C For along Fig.22A The cross-sectional view of line CC, and Fig.22D For along Fig.22A The patterned mask M4 is removed by a suitable method, such as stripping. Then, the hard mask 300 is removed. In some embodiments, the hard mask 300 can be removed by a suitable etching process.

[0118] Reference FIG. 23A to FIG. 23D ,in Fig.23A For FIG. 22A to FIG. 22D A top view of the memory device 100 after operation, and Fig.22A With the same top view, Fig. 23B For along Fig.23A The cross-section of line BB, Fig.23C For along Fig.23A The cross-sectional view of line CC, and Fig.23D For along Fig.23A DD. A patterned mask 302 is formed to cover a portion 104B of the substrate 104. The patterned mask 302 may be a photoresist and may be formed by a photolithography process. Next, an etching process is performed to remove the exposed dielectric layer 1502, thereby forming a select gate dielectric 156 under the select gate 150.

[0119] Reference FIG. 24A to FIG. 24C ,in FIG. 24A to FIG. 24C Respectively and FIG. 23B to FIG. 23D An ion implantation process is performed to form drain regions 126 in the substrate 104. In some embodiments, the drain regions 126 are respectively adjacent to the select gate dielectric 156. In some embodiments, the ion implantation can be performed through a series of steps with multiple layers of masks to form different levels of doping in the drain regions 126.

[0120] Reference FIG. 25A to FIG. 25C ,in FIG. 25A to FIG. 25C Respectively and FIG. 24A to FIG. 24C A silicide pad 170 is formed in the substrate 104 and above the drain region 126. In some embodiments, the silicide pad 170 may be nickel silicide or other suitable silicides, and may be formed by a suitable silicide process.

[0121] Reference FIG. 26A to FIG. 26C ,in FIG. 26A to FIG. 26C Respectively and FIG. 25A to FIG. 25C The patterned mask 302 located above the portion 104B of the substrate 104 is removed. In some embodiments, the patterned mask 302 can be removed by stripping. After the patterned mask 302 is removed, the floating gate spacer 142 and the portion 104B of the substrate 104 are exposed.

[0122] Reference FIG. 27A to FIG. 27C ,in FIG. 27A to FIG. 27C Respectively and FIG. 26A to FIG. 26C A patterned mask 304 is formed on the substrate 104 and covers the drain region 126. The patterned mask 304 may be a photoresist and may be formed by a photolithography process.

[0123] exist Fig.27B In the embodiment, the exposed surface of the portion 104B of the substrate 104 has a width W4 along a direction perpendicular to the length of the erase gate 144. In some embodiments, the width W4 ranges from about 80 nm to about 120 nm. In some embodiments, the width W4 is the cell pitch, which is a key factor in selecting the critical dimension of the gate. If the width W4 is too small, it will be difficult to fill the material to this narrow area (for example, the spacing between the floating gate spacers 142) in the subsequent steps, and it will cause undesirable pores to be formed in this area. On the other hand, if the width W4 is too large, the device will be too large and the desired device density cannot be achieved.

[0124] exist Fig.27CIn the embodiment, the exposed surface of the portion 104B of the substrate 104 has a width W5 along the length direction of the erase gate 144. In some embodiments, the width W5 ranges from about 80 nm to about 120 nm. In some embodiments, the width W5 is the spacing between the erase gates 144. If the width W5 is too small, the exposed area will be too small to accommodate the common source strip (e.g., the common source strip 160CS) formed in the subsequent step. On the other hand, the distance D1 between the upper surface of the portion 104B of the substrate 104 and the upper surface of the erase gate dielectric 146 ranges from about 30 nm to about 50 nm. If the distance D1 is too small (e.g., the erase gate dielectric 146 is too thin), the erase gate dielectric 146 will not be able to separate the erase gate 144 from the substrate 104. On the other hand, if the distance D1 is too large (e.g., the erase gate dielectric 146 is too thick), the erase gate dielectric 146 may cause unsatisfactory device performance. In some embodiments, the ratio of the width W4 to the width W5 is about 0.66 to about 1.5. In some embodiments, the ratio of the width W5 to the distance D1 is about 1.6 to about 4.

[0125] Reference FIG. 28A to FIG. 28C ,in FIG. 28A to FIG. 28C Respectively and FIG. 27A to FIG. 27C The silicide pad 172 is formed on the portion 104B of the substrate 104. In some embodiments, the silicide pad 172 may be nickel silicide or other suitable silicides and may be formed by an appropriate silicide process. Fig.28C In the embodiment, the silicide pad 172 at least partially contacts the common source region 128 , thereby forming an electrical connection between the silicide pad 172 and the common source region 128 .

[0126] like 9A to 9C As discussed, portion 104B of substrate 104 is masked during the formation of common source region 128, and portion 104B of substrate 104 substantially does not have the dopant of common source region 128. In addition, in the process discussed herein, no other intentional doping process is performed on portion 104B of substrate 104. Therefore, portion 104B of substrate 104 does not have doping, or has negligible doping. On the other hand, since silicide pad 172 is formed on portion 104B of substrate 104, silicide pad 172 does not have doping, or has negligible doping. In other words, the dopant concentration of silicide pad 172 is less than the dopant concentration of common source region 128.

[0127] Reference Fig.24AAs mentioned above, the silicide pad 170 is formed directly on the drain region 126 of the substrate 104 by ion implantation. Therefore, the silicide pad 170 above the drain region 126 may have the dopant of the drain region 126. In contrast, the silicide pad 172 connected to the common source region 128 has no doping or has negligible doping. In other words, the dopant concentration of the silicide pad 172 is less than the dopant concentration of the silicide pad 170.

[0128] In some embodiments of the present disclosure, since the portion 104B of the substrate 104 is masked during the formation of the common source region 128, the erase gate dielectric 146 having a curved or bulbous surface profile formed in the common source region 128 by ion implantation will not be formed above the portion 104B of the substrate 104 (since there is no common source region 128 there). Therefore, the portion 104B of the substrate 104 still has a substantially flat upper surface at this step, and thus results in a silicide pad 172 having a flat upper surface. Therefore, in some embodiments, the upper surface of the silicide pad 172 is substantially flush with the upper surface of the silicide pad 170. Such a configuration is beneficial to the subsequent formation of strips (e.g., FIG. 33A to FIG. 33C The common source strip 160CS and drain strip 160D in the embodiment.

[0129] On the other hand, FIG. 21A to FIG. 21D As mentioned, the gate layer 1504 over the portion 104B of the substrate 104 is removed using the same mask as the select gate 150. However, if the erase gate dielectric 146 over the portion 104B of the substrate 104 has a curved or bulbous surface profile, an additional mask is required to expose this area and remove the erase gate dielectric 146 over the portion 104B of the substrate 104, thereby incurring additional overhead to the process.

[0130] Reference FIG. 29A to FIG. 29C ,in FIG. 29A to FIG. 29C Respectively and FIG. 28A to FIG. 28C The patterned mask 304 is removed, and a first interlayer dielectric layer 200 is formed over the substrate 104. In some embodiments, the first interlayer dielectric layer 200 fills the area over the silicide pads 170 and 172. The first interlayer dielectric layer 200 can be an oxide, a low-k dielectric, other suitable dielectrics, combinations thereof, or the like. The first interlayer dielectric layer 200 can be formed by CVD, PVD, sputtering, or other suitable deposition processes.

[0131] Reference FIG. 30A to FIG. 30C ,in FIG. 30A to FIG. 30C Respectively and FIG. 29A to FIG. 29CA chemical mechanical polishing process is performed to remove excess first interlayer dielectric layer 200 until the erase gate 144, the control gate 138, and the select gate 150 are exposed.

[0132] Reference FIG. 31A to FIG. 31C ,in FIG. 31A to FIG. 31C Respectively and FIG. 30A to FIG. 30C The second interlayer dielectric layer 202 is formed on the substrate 104. The second interlayer dielectric layer 202 can be an oxide, a low-k dielectric, other suitable dielectrics, combinations thereof, or the like. The second interlayer dielectric layer 202 can be formed by CVD, PVD, sputtering, or other suitable deposition processes.

[0133] Reference FIG. 32A to FIG. 32D ,in Fig.32A For FIG. 31A to FIG. 31C A top view of the memory device 100 after operation, and Fig.23A With the same top view, Fig.32B For along Fig.32A The cross-section of line BB, Fig.32C For along Fig.32A The cross-sectional view of line CC, and Fig.32D For along Fig.32A DD. The first and second interlayer dielectric layers 200 and 202 are etched (or patterned) to form openings O3, O4, and O5. In some embodiments, the opening O3 exposes the silicide pad 172 above the drain region 126, the opening O4 exposes the silicide pad 172, and the opening O5 exposes the erase gate 144. As mentioned above, since the silicide pad 172 has a substantially flat upper surface and is flush with the upper surface of the silicide pad 170, the etchant will reach the silicide pads 170 and 172 at substantially the same time. In some embodiments, if the upper surfaces of the silicide pads 170 and 172 are located at different levels, the one with the higher upper surface will be over-etched, thereby affecting the device performance.

[0134] Reference FIG. 33A to FIG. 33D ,in Fig.33A For FIG. 32A to FIG. 32D A top view of the memory device 100 after operation, and Fig.32A With the same top view, Fig.33B For along Fig.33A The cross-section of line BB, Fig.33C For along Fig.33A The cross-sectional view of line CC, and Fig.33D For along Fig.33ADD. Drain strip 160D, common source strip 160CS and erase gate strip 160EG are formed in openings O3, O4 and O5 respectively. In some embodiments, drain strip 160D in opening O3 may also be referred to as drain contact 160D. Common source strip 160CS in opening O4 may also be referred to as common source contact 160CS. Erase gate strip 160EG in opening O5 may also be referred to as erase gate contact 160EG. Drain strip 160D, common source strip 160CS and erase gate strip 160EG are conductive and may be tungsten, copper, aluminum, copper-aluminum, other suitable metals or conductive materials, combinations thereof, or the like. The drain strip 160D, the common source strip 160CS and the erase gate strip 160EG may be formed by, for example, depositing a conductive material over the substrate 104 and filling the openings O3 , O4 , O5 , and then performing a CMP process to remove excess conductive material until the second interlayer dielectric layer 202 is exposed.

[0135] FIG. 34A to FIG. 34C Method 1000 for forming a memory element for some embodiments of the present disclosure. Although method 100 is described by a series of operations or steps, it should be understood that the method does not limit the operations or their order. Therefore, in some embodiments, these operations or steps can be performed in different orders and / or simultaneously. In addition, in some embodiments, the described operations or steps can be divided into multiple operations or steps, which can be performed at different time points or at the same time point with other operations or sub-operations. In some embodiments, the described operations or steps can be omitted, or include other operations or steps that are not described.

[0136] In block S101 , an isolation structure is formed on a substrate. FIG. 2A to FIG. 2C It is a schematic diagram of some embodiments corresponding to block S101.

[0137] In block S102 , a gate oxide, a floating gate layer, a control gate dielectric layer, a control gate layer, and a control gate hard mask are formed on a substrate. FIG. 3A to FIG. 3C It is a schematic diagram of some embodiments corresponding to block S102.

[0138] In block S103 , the control gate hard mask, the control gate layer, and the control gate dielectric layer are etched to form a control gate and a control gate dielectric. FIG. 4A to FIG. 4C It is a schematic diagram of a partial embodiment corresponding to block S103.

[0139] In block S104 , a control gate spacer layer is formed on the substrate. Figure 5A and Figure 5B It is a schematic diagram of a partial embodiment corresponding to block S104.

[0140] In block S105 , the control gate spacer layer is etched to form control gate spacers on opposite sidewalls of the control gate, and the floating gate layer and the gate oxide are etched to form a floating gate and a floating gate dielectric. Fig. 6A and Figure 6B It is a schematic diagram of a partial embodiment corresponding to block S105.

[0141] In block S106 , floating gate spacers are formed on opposite sidewalls of the floating gate. Fig. 7A and Figure 7B It is a schematic diagram of a partial embodiment corresponding to block S106.

[0142] In block S107 , a first patterned mask is formed on the substrate, wherein the first patterned mask exposes a first portion of the substrate and covers a second portion of the substrate. FIG. 8A to FIG. 8D It is a schematic diagram of a partial embodiment corresponding to block S107.

[0143] In block S108 , a common source region is formed in the first portion of the substrate. 9A to 9C It is a schematic diagram of a partial embodiment corresponding to block S108.

[0144] In block S109 , the floating gate spacers exposed by the first patterned mask are removed. FIG. 10A to FIG. 10C It is a schematic diagram of a partial embodiment corresponding to block S109.

[0145] In block S110 , the first patterned mask is removed, and an erase gate dielectric layer is formed above the common source region. FIG. 11A to FIG. 11C It is a schematic diagram of some embodiments corresponding to block S110.

[0146] In block S111 , a second patterned mask is formed on the substrate, wherein the second patterned mask covers a first portion of the substrate, and the erase gate dielectric layer exposed through the second patterned mask is removed. FIG. 12A to FIG. 12D It is a schematic diagram of some embodiments corresponding to block S111.

[0147] In block S112 , a first dielectric layer is formed on the substrate. FIG. 13A to FIG. 13D It is a schematic diagram of some embodiments corresponding to block S112.

[0148] In block S113 , a gate layer is formed on the substrate. FIG. 14A to FIG. 14D It is a schematic diagram of a partial embodiment corresponding to block S113.

[0149] In block S114 , the gate layer is etched back to form an erase gate. FIG. 15A to FIG. 15D It is a schematic diagram of a partial embodiment corresponding to block S114.

[0150] In block S115 , a hard mask layer is formed on the substrate. FIG. 16A to FIG. 16C It is a schematic diagram of a partial embodiment corresponding to block S115.

[0151] In block S116 , a third patterned mask is formed on the substrate, and the gate layer is etched to form a select gate. FIG. 17A to FIG. 17D It is a schematic diagram of a partial embodiment corresponding to block S116.

[0152] In block S117 , the third patterned mask is removed, and a select gate spacer is formed on the sidewall of the select gate. 18A to 18D It is a schematic diagram of a partial embodiment corresponding to block S117.

[0153] In block S118, a hard mask is formed on the substrate and next to the select gate spacers. FIG. 19A to FIG. 19C It is a schematic diagram of a partial embodiment corresponding to block S118.

[0154] In block S119 , a fourth patterned mask is formed on the substrate, wherein the fourth patterned mask exposes the second portion of the substrate. FIG. 20A to FIG. 20D It is a schematic diagram of a partial embodiment corresponding to block S119.

[0155] In block S120 , the gate layer over the second portion of the substrate is removed. FIG. 21A to FIG. 21D It is a schematic diagram of some embodiments corresponding to block S120.

[0156] In block S121 , the fourth patterned mask and the hard mask are removed. FIG. 22A to FIG. 22D It is a schematic diagram of a partial embodiment corresponding to block S121.

[0157] In block S122 , a fifth patterned mask is formed over the second portion of the substrate. FIG. 23A to FIG. 23D It is a schematic diagram of a partial embodiment corresponding to block S122.

[0158] In block S123 , ion implantation is performed to form a drain region in the substrate. FIG. 24A to FIG. 24C It is a schematic diagram of a partial embodiment corresponding to block S123.

[0159] In block S124 , a first silicide pad is formed over the drain region. FIG. 25A to FIG. 25C It is a schematic diagram of a partial embodiment corresponding to block S124.

[0160] In block S125 , the fifth patterned mask is removed to expose the second portion of the substrate. FIG. 26A to FIG. 26C It is a schematic diagram of a partial embodiment corresponding to block S125.

[0161] In block S126 , a sixth patterned mask is formed over the substrate and covers the drain region. FIG. 27A to FIG. 27C It is a schematic diagram of a partial embodiment corresponding to block S126.

[0162] In block S127 , a second silicide pad is formed in a second portion of the substrate. FIG. 28A to FIG. 28C It is a schematic diagram of a partial embodiment corresponding to block S127.

[0163] In block S128 , the sixth patterned mask is removed, and a first interlayer dielectric layer is formed on the substrate. FIG. 29A to FIG. 29C It is a schematic diagram of a partial embodiment corresponding to block S128.

[0164] In block S129, a CMP process is performed until the erase gate is exposed. FIG. 30A to FIG. 30C It is a schematic diagram of a partial embodiment corresponding to block S129.

[0165] In block S130 , a second interlayer dielectric layer is formed over the substrate. FIG. 31A to FIG. 31C It is a schematic diagram of some embodiments corresponding to block S130.

[0166] In block S131 , the first and second interlayer dielectric layers are etched to form openings. FIG. 32A to FIG. 32D It is a schematic diagram of a partial embodiment corresponding to block S131.

[0167] In block S132, a conductive material is filled in the opening. FIG. 33A to FIG. 33D It is a schematic diagram of a partial embodiment corresponding to block S132.

[0168] Based on the above discussion, it can be seen that some embodiments of the present disclosure provide advantages. However, it should be understood that these embodiments can provide other advantages, and not all advantages need to be discussed here, and not all embodiments have specific advantages. One advantage is that the areas on the substrate that define the common source strips are masked during the formation of the common source region. Therefore, erase gate dielectrics with curved or bulbous surface profiles will not be formed on these areas of the substrate. Therefore, the outer mask for removing erase gate dielectrics with curved or bulbous surface profiles can be omitted and process costs can be saved. On the other hand, the upper surface of these areas of the substrate is substantially flat, so that the silicide pads formed in this area also have a flat upper surface. This helps the subsequent process of forming contacts above the silicide pads.

[0169] Some embodiments of the present disclosure are a memory device including an erase gate, an erase gate dielectric, first and second floating gates, first and second control gates, a first select gate, a second select gate, a common source strip, and a silicide pad. The erase gate is located above a first portion of a substrate. The erase gate dielectric is located between the erase gate and the first portion of the substrate. The first and second floating gates are located on opposite sides of the erase gate. The first and second control gates are located above the first and second floating gates, respectively. The first select gate is separated from the erase gate at least partially by the first control gate along a first direction. The second select gate is separated from the erase gate at least partially by the second control gate along the first direction. The common source strip is located on a second portion of the substrate, wherein the common source strip is arranged with the erase gate along a second direction perpendicular to the first direction. The silicide pad is located below the common source strip and within the second portion of the substrate, wherein the upper surface of the silicide pad is flat to the lower surface of the erase gate dielectric.

[0170] According to some embodiments, the lower surface of the erase gate dielectric is curved.

[0171] According to some embodiments, a common source region is further included, located below the erase gate dielectric and in the first portion of the substrate, wherein the silicide pad does not have dopants in the common source region.

[0172] According to some embodiments, in a cross section along the first direction, a horizontal width of the silicide pad is smaller than a horizontal width of the erase gate dielectric.

[0173] According to some embodiments, in a cross section along the second direction, the silicide pad contacts a sidewall of the erase gate dielectric.

[0174] According to some embodiments, in a cross section along the second direction, the silicide pad is spaced apart from the first and second floating gates by a non-zero distance.

[0175] According to some embodiments, in a cross section along the second direction, an upper surface of the silicide pad is lower than an upper surface of the erase gate dielectric and higher than a lower surface of the erase gate dielectric.

[0176] Some embodiments of the present disclosure are a memory device including an erase gate, an erase gate dielectric, first and second floating gates, first and second control gates, a first select gate, a second select gate, a first silicide pad, a first floating gate spacer, and a second floating gate spacer. The erase gate is located above a first portion of a substrate. The erase gate dielectric is located between the erase gate and the first portion of the substrate. The first and second floating gates are located on opposite sides of the erase gate. The first and second control gates are located above the first and second floating gates, respectively. The first select gate is separated from the erase gate at least partially by the first control gate along a first direction. The second select gate is separated from the erase gate at least partially by the second control gate along the first direction. The first silicide pad is located in the second portion of the substrate, wherein the first silicide pad and the erase gate are arranged along a second direction perpendicular to the first direction. The first floating gate spacer is located on a sidewall of the first floating gate, wherein the first silicide pad is separated from the first floating gate by the first floating gate spacer. The second floating gate spacer is located on a sidewall of the second floating gate, wherein the first silicide pad is separated from the second floating gate by the second floating gate spacer.

[0177] According to some embodiments, an interlayer dielectric layer is further included between the first floating gate spacer and the second first floating gate spacer, and a common source strip extends through the interlayer dielectric layer and contacts the first silicide pad.

[0178] According to some embodiments, a common source region is further included, located in the first portion of the substrate and below the erase gate, wherein in a cross section along the second direction, the common source strip is electrically connected to the common source region through the first silicide pad.

[0179] According to some embodiments, the first floating gate spacer and the second floating gate spacer are made of nitride.

[0180] According to some embodiments, the device further comprises a drain region located in the substrate and adjacent to the first selection gate, a second silicide located in the drain region, wherein the dopant concentration of the second silicide is lower than the dopant concentration of the first silicide, and a drain strip located above the second silicide and in contact with the second silicide.

[0181] According to some embodiments, it also includes a first control gate spacer and a second control gate spacer, which are respectively located on the sidewalls of the first control gate and the sidewalls of the second control gate, wherein in a first cross-section along the first direction and passing through the first silicide, the first floating gate spacer and the second floating gate spacer are in contact with the first control gate spacer and the second control gate spacer, respectively.

[0182] According to some embodiments, in a second cross section along the first direction and passing through the erase gate, the erase gate is in contact with the first control gate spacer and the second control gate spacer.

[0183] According to some embodiments, in a first cross section along the first direction and passing through the first silicide, a width of the first silicide is smaller than a distance between the first floating gate spacer and the second floating gate spacer.

[0184] Some embodiments of the present disclosure are a method for manufacturing a memory element, comprising forming a first floating gate and a second floating gate on a substrate; forming a first control gate and a second control gate respectively above the first floating gate and the second floating gate; forming a patterned mask to cover the first control gate and the second control gate, wherein the patterned mask exposes a first portion of the substrate between the first control gate and the second control gate, and the patterned mask exposes a second portion of the substrate between the first control gate and the second control gate; forming a common source region in the first portion of the substrate, wherein the patterned mask protects the second portion of the substrate during the formation of the common source region; removing the patterned mask; forming an erase gate above the first portion of the substrate; and forming a common source stripe above the second portion of the substrate.

[0185] According to some embodiments, the method further includes forming a silicide pad in the second portion of the substrate before forming the common source strip.

[0186] According to some embodiments, the method further includes forming an erase gate dielectric over the first portion and the second portion of the substrate, wherein the erase gate dielectric has a faster growth rate on the first portion of the substrate than on the second portion of the substrate.

[0187] According to some embodiments, forming the erase gate includes forming an erase gate layer over the first portion and the second portion of the substrate; and removing the erase gate layer from over the second portion of the substrate.

[0188] According to some embodiments, the method further includes forming a first floating gate spacer and a second floating gate spacer on the sidewalls of the first floating gate and the second floating gate, respectively, before forming the patterned mask; and removing the first floating gate spacer and the second floating gate spacer above the first portion of the substrate after forming the patterned mask, wherein the first floating gate spacer and the second floating gate spacer remain above the second portion of the substrate.

[0189] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures to achieve the same purpose and / or achieve the same advantages. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions and modifications may be made to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, characterized in that: Include: an erase gate disposed above a first portion of a substrate; an erase gate dielectric disposed between the erase gate and the first portion of the substrate; first and second floating gates located on opposite sides of the erase gate; First and second control gates are respectively located above the first and second floating gates; a first select gate separated from the erase gate at least partially by the first control gate along a first direction; a second select gate separated from the erase gate at least partially by the second control gate along the first direction; A common source strip located on a second portion of the substrate, wherein the common source strip and the erase gate are arranged along a second direction perpendicular to the first direction; as well as A silicide pad is located below the common source strip and in the second portion of the substrate, wherein an upper surface of the silicide pad is flat with a lower surface of the erase gate dielectric, and in a cross section along the second direction, the silicide pad contacts a sidewall of the erase gate dielectric.

2. The memory device according to claim 1, wherein: The lower surface of the erase gate dielectric is curved.

3. The memory device according to claim 1, wherein: Also included is a common source region located below the erase gate dielectric and within the first portion of the substrate, wherein the silicide pad is free of a dopant within the common source region.

4. The memory device according to claim 1, wherein: In a cross section along the first direction, a horizontal width of the silicide pad is smaller than a horizontal width of the erase gate dielectric.

5. The memory device according to claim 1, wherein: In a cross section along the second direction, the silicide pad is spaced apart from the first and second floating gates by a non-zero distance.

6. The memory device according to claim 1, wherein: In the cross section along the second direction, the upper surface of the silicide pad is lower than an upper surface of the erase gate dielectric and higher than the lower surface of the erase gate dielectric.

7. A memory device, characterized in that: Include: an erase gate disposed above a first portion of a substrate; an erase gate dielectric disposed between the erase gate and the first portion of the substrate; first and second floating gates located on opposite sides of the erase gate; First and second control gates are respectively located above the first and second floating gates; a first select gate separated from the erase gate at least partially by the first control gate along a first direction; a second select gate separated from the erase gate at least partially by the second control gate along the first direction; a first silicide pad located in a second portion of the substrate, wherein the first silicide pad and the erase gate are arranged along a second direction perpendicular to the first direction; a first floating gate spacer located on a sidewall of the first floating gate, wherein the first silicide pad is separated from the first floating gate by the first floating gate spacer; a second floating gate spacer located on a sidewall of the second floating gate, wherein the first silicide pad is separated from the second floating gate by the second floating gate spacer; a drain region located in the substrate and adjacent to the first selection gate; a second silicide located in the drain region, wherein a dopant concentration of the second silicide is lower than a dopant concentration of the first silicide; and A drain strip is located above the second silicide and contacts the second silicide.

8. The memory device according to claim 7, characterized in that: Also includes: an interlayer dielectric layer disposed between the first floating gate spacer and the second floating gate spacer; and A common source strip extends through the interlayer dielectric layer and contacts the first silicide pad.

9. The memory device according to claim 8, characterized in that: The invention also comprises a common source region located in the first part of the substrate and below the erase gate, wherein in the cross section along the second direction, the common source strip is electrically connected to the common source region through the first silicide pad.

10. The memory device according to claim 7, characterized in that The first floating gate spacer and the second floating gate spacer are made of nitride.

11. The memory device according to claim 7, characterized in that: It also includes a first control gate spacer and a second control gate spacer, which are respectively located on a side wall of the first control gate and a side wall of the second control gate, wherein in a first cross-section along the first direction and passing through the first silicide, the first floating gate spacer and the second floating gate spacer are respectively in contact with the first control gate spacer and the second control gate spacer.

12. The memory device according to claim 11, characterized in that In a second cross section along the first direction and passing through the erase gate, the erase gate is in contact with the first control gate spacer and the second control gate spacer.

13. The memory device according to claim 7, characterized in that In a first cross section along the first direction and passing through the first silicide, a width of the first silicide is smaller than a distance between the first floating gate spacer and the second floating gate spacer.

14. A method for manufacturing a memory device, characterized in that: Include: forming a first floating gate and a second floating gate on a substrate; forming a first control gate and a second control gate respectively on the first floating gate and the second floating gate; forming a patterned mask to cover the first control gate and the second control gate, wherein the patterned mask exposes a first portion of the substrate between the first control gate and the second control gate, and the patterned mask covers a second portion of the substrate between the first control gate and the second control gate; forming a common source region in the first portion of the substrate, wherein the patterned mask protects the second portion of the substrate during the formation of the common source region; removing the patterned mask; forming an erase gate over the first portion of the substrate; as well as A common source strip is formed over the second portion of the substrate.

15. The method according to claim 14, characterized in that The method also includes forming a silicide pad in the second portion of the substrate before forming the common source strip.

16. The method according to claim 14, characterized in that Also included is forming an erase gate dielectric over the first portion and the second portion of the substrate, wherein the erase gate dielectric has a faster growth rate on the first portion of the substrate than on the second portion of the substrate.

17. The method according to claim 14, characterized in that Forming the erase gate includes: forming an erase gate layer over the first portion and the second portion of the substrate; and The erase gate layer is removed from above the second portion of the substrate.

18. The method according to claim 14, characterized in that Also includes: Before forming the patterned mask, forming a first floating gate spacer and a second floating gate spacer on a side wall of the first floating gate and a side wall of the second floating gate respectively; and After forming the patterned mask, the first floating gate spacer and the second floating gate spacer over the first portion of the substrate are removed, wherein the first floating gate spacer and the second floating gate spacer remain over the second portion of the substrate.

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