Semiconductor device including a support and method of manufacturing thereof

Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate including a cell region and a connection region. The connection region includes a plurality of pad regions and a through electrode region. A horizontal conductive layer is on the substrate. A support is on the horizontal conductive layer. The support includes a first portion in the cell region, a second portion in the plurality of pad regions, and a third portion in the through electrode region. A connection conductive layer is between the first portion and the horizontal conductive layer. A connection molding layer is between the third portion and the horizontal conductive layer. A first buried insulating layer is provided through the third portion, the connection molding layer, and the horizontal conductive layer. A stack structure is on the substrate. A through electrode is provided through the first buried insulating layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0007187, filed on January 20, 2020, with the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device including a support member and a method for manufacturing the semiconductor device. Background Technology

[0004] With the increasing integration of semiconductor devices, techniques are being developed to place source lines on a substrate and form stacked structures on those lines. The stacked structure can include multiple insulating layers and multiple wiring layers stacked alternately and repeatedly. Channel structures can be configured to pass through the stacked structure and connect to the source lines. The increased leakage current between the multiple wiring layers and the source lines leads to defective characteristics in the semiconductor device. Summary of the Invention

[0005] The exemplary embodiments of this disclosure provide semiconductor devices and methods of manufacturing thereof, which improve production efficiency and / or reduce or minimize leakage current.

[0006] A semiconductor device according to an example embodiment of the present disclosure may include a substrate including cell regions and connection regions. Connection regions may be connected to the cell regions. Connection regions may include a plurality of pad regions and a through-electrode region located between the plurality of pad regions. A horizontal conductive layer may be located on the substrate. A support member may be provided, located on the horizontal conductive layer, and including a first portion in the cell regions, a second portion in the plurality of pad regions, and a third portion in the through-electrode region. A connection conductive layer may be located between the first portion of the support member and the horizontal conductive layer. A connection molding layer may be located between the third portion of the support member and the horizontal conductive layer. A first buried insulating layer may be provided, located in the through-electrode region, and passing through the third portion, the connection molding layer, and the horizontal conductive layer. A stacked structure wherein a plurality of insulating layers and a plurality of wiring layers are alternately stacked may be located on the substrate. A cell channel structure may be provided, located in the cell regions, passing through the stacked structure and the first portion, and extending into the interior of the horizontal conductive layer. A through-electrode may be provided, located in the through-electrode region, and passing through the first buried insulating layer.

[0007] A semiconductor device according to an example embodiment of the present disclosure may include a substrate including cell regions and connection regions. Connection regions may be connected to the cell regions. Connection regions may include a plurality of pad regions and a through-electrode region located between the plurality of pad regions. A horizontal conductive layer may be located on the substrate. A support member may be provided, located on the horizontal conductive layer, and including a first portion in the cell regions, a second portion in the plurality of pad regions, and a third portion in the through-electrode region. A connection conductive layer may be located between the first portion of the support member and the horizontal conductive layer. A connection molding layer may be located between the third portion of the support member and the horizontal conductive layer. A first buried insulating layer may be provided, located in the through-electrode region, and passing through the third portion, the connection molding layer, and the horizontal conductive layer. A second buried insulating layer may be provided, located in the plurality of pad regions, and covering the second portions. A stack structure wherein a plurality of insulating layers and a plurality of wiring layers are alternately stacked may be located on the support member, the first buried insulating layer, and the second buried insulating layer. A cell channel structure may be provided, located in the cell regions, passing through the stack structure and the first portion, and extending into the interior of the horizontal conductive layer. A pseudo-channel structure can be configured, located within multiple pad areas, passing through the stack structure, the second buried insulating layer, and the second portion, and extending into the interior of the horizontal conductive layer. A through-electrode can be configured, located within the through-electrode area, and passing through the stack structure and the first buried insulating layer.

[0008] A semiconductor device according to an example embodiment of the present disclosure may include a substrate including cell regions and connection regions. Connection regions may be connected to the cell regions. Connection regions may include a plurality of pad regions and a through-electrode region located between the plurality of pad regions. A horizontal conductive layer may be located on the substrate. A support member may be provided on the horizontal conductive layer and includes a first portion in the cell regions, a second portion in the plurality of pad regions, and a third portion in the through-electrode region. A connection conductive layer may be located between the first portion of the support member and the horizontal conductive layer. A connection molding layer may be located between the third portion of the support member and the horizontal conductive layer. A first buried insulating layer may be provided located in the through-electrode region and passes through the third portion, the connection molding layer, and the horizontal conductive layer. A second buried insulating layer may be provided located in the plurality of pad regions and covers the second portions. A cell channel structure may be provided located in the cell regions, passing through a stack structure in which a plurality of insulating layers and a plurality of wiring layers are alternately stacked and the first portion, and extending into the interior of the horizontal conductive layer. A through-electrode may be provided located in the through-electrode region and passes through the first buried insulating layer. Bit lines can be configured, which are located on the stack structure and connected to the cell channel structure.

[0009] A method of manufacturing a semiconductor device according to an example embodiment of the present disclosure may include: providing a substrate including cell regions and connection regions connected to the cell regions. The connection regions may include a plurality of pad regions and a through-electrode region located between the plurality of pad regions. A horizontal conductive layer may be formed on the substrate. A support may be formed on the horizontal conductive layer. The support may include a first portion in the cell regions, a second portion in the plurality of pad regions, and a third portion in the through-electrode region. A connection conductive layer may be formed between the first portion of the support and the horizontal conductive layer. A connection molding layer may be formed between the third portion of the support and the horizontal conductive layer. A first buried insulating layer may be formed in the through-electrode region, passing through the third portion, the connection molding layer, and the horizontal conductive layer. A stacked structure in which a plurality of insulating layers and a plurality of wiring layers are alternately stacked may be formed on the substrate. A cell channel structure may be formed in the cell regions, passing through the stacked structure and the first portion and extending into the interior of the horizontal conductive layer. A through-electrode passing through the first buried insulating layer may be located in the through-electrode region.

[0010] A semiconductor device according to an example embodiment of the present disclosure may include a substrate including cell regions and connection regions. The connection regions may be connected to the cell regions. The connection regions may include a plurality of pad regions and a through-electrode region located between the plurality of pad regions. A horizontal conductive layer may be located on the substrate. A support member may be provided, located on the horizontal conductive layer, and including a first portion in the cell regions, a second portion in the plurality of pad regions, and a third portion in the through-electrode region. A connection conductive layer may be located between the first portion of the support member and the horizontal conductive layer. A connection molding layer may be located between the third portion of the support member and the horizontal conductive layer. A stacked structure wherein a plurality of insulating layers and a plurality of wiring layers are alternately stacked may be located on the substrate. A cell channel structure may be provided, located in the cell regions, passing through the stacked structure and the first portion, and extending into the interior of the horizontal conductive layer. A through-electrode may be provided, located in the through-electrode region, and passing through the third portion, the connection molding layer, and the horizontal conductive layer. Contact spacers may be provided around the side surface of the through-electrode.

[0011] A semiconductor device according to an example embodiment of the present disclosure may include a substrate including cell regions and connection regions. Connection regions may be connected to the cell regions. Connection regions may include a plurality of pad regions and a through-electrode region located between the plurality of pad regions. A horizontal conductive layer may be located on the substrate. A support member may be provided on the horizontal conductive layer and includes a first portion in the cell regions and a second portion in the plurality of pad regions. A connection conductive layer may be located between the first portion of the support member and the horizontal conductive layer. A first buried insulating layer may be provided, located in the through-electrode region and passing through the second portion and the horizontal conductive layer. A stack structure wherein a plurality of insulating layers and a plurality of wiring layers are alternately stacked may be located on the support member and the first buried insulating layer. A cell channel structure may be provided, located in the cell regions, passing through the stack structure, the first portion, and the connection conductive layer, and extending into the interior of the horizontal conductive layer. A pseudo-channel structure may be provided, located in the connection regions, passing through the stack structure and the second portion, and extending into the interior of the horizontal conductive layer. A through-electrode may be provided, located in the through-electrode region and passing through the stack structure and the first buried insulating layer. The distance between the top of the second part and the top surface of the substrate can be shorter than the distance between the top of the first part and the top surface of the substrate. Attached Figure Description

[0012] Figure 1 , Figure 2 , Figure 10 , Figure 11 , Figure 14 , Figure 15 , Figure 18 , Figure 19 , Figure 20 and Figure 21 This is a cross-sectional view used to describe a semiconductor device according to an example embodiment of the present disclosure.

[0013] Figure 3 , Figure 8 , Figure 12 and Figure 16 This is used to describe the layout of a semiconductor device according to an example embodiment of the present disclosure.

[0014] Figure 4 , Figure 9 , Figure 13 and Figure 17 This is a perspective view used to describe some elements of a semiconductor device according to an example embodiment of the present disclosure.

[0015] Figures 5 to 7 It shows Figure 1 A magnified view of a portion of it.

[0016] Figures 22 to 40 This is a cross-sectional view used to describe a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0017] Figures 41 to 43 This is a cross-sectional view used to describe a semiconductor device according to an example embodiment of the present disclosure. Detailed Implementation

[0018] Figure 1 and Figure 2 This is a cross-sectional view used to describe a semiconductor device according to an exemplary embodiment of the present disclosure. Figure 3 It is used to describe the layout of semiconductor devices. Figure 4 It is used to describe Figures 1 to 3 Perspective views of some components, Figures 5 to 7 It shows Figure 1 A magnified view of a portion of it. Figure 1 It is along Figure 3 The cross-sectional view taken from lines 1-1' and 2-2'. Figure 2 It is along Figure 3 The cross-sectional view is taken from line 3-3'. A semiconductor device according to an exemplary embodiment of this disclosure may include non-volatile memory (such as VNAND or three-dimensional (3D) flash memory). A semiconductor device according to an exemplary embodiment of this disclosure can be interpreted as including a cell-on-periphery (COP) structure.

[0019] Reference Figure 1 A semiconductor device according to an example embodiment of the present disclosure may include a substrate 21, an isolation layer 23, a plurality of transistors 25, a first lower insulating layer 27, a plurality of peripheral circuit wirings 29, a second lower insulating layer 31, a cover layer 33, a third lower insulating layer 35, a horizontal conductive layer 41, a connection molding layer 43, a connection conductive layer 45, a support member 47, a first buried insulating layer 48, a second buried insulating layer 49, a stacked structure 50, an interlayer insulating layer 59, a plurality of cell channel structures 69, a plurality of pseudo-channel structures 69D, a first upper insulating layer 72, a plurality of separator patterns 75, a plurality of intermediate separator patterns 76, a second upper insulating layer 79, a plurality of bit line plugs 81, a plurality of bit lines 83, a plurality of through electrodes 85 and / or a plurality of upper wirings 87.

[0020] The substrate 21 may include a cell region CE and a connection region EX connected to the cell region CE. The connection region EX may include multiple pad regions EXP and a through electrode region EXC between the multiple pad regions EXP. The connection molding layer 43 may include a lower molding layer 43L, an intermediate molding layer 43M, and an upper molding layer 43U.

[0021] The support 47 may include a first portion 47A in the cell region CE, a second portion 47B in the plurality of pad regions EXP, and a third portion 47C in the through electrode region EXC. The stack structure 50 may include a plurality of insulating layers 51 and a plurality of wiring layers 53 stacked alternately and repeatedly. Each of the plurality of wiring layers 53 may include an electrode layer 53C and a molding layer 53M connected to the electrode layer 53C. A portion of the electrode layer 53C may be used as a pad 53CP.

[0022] Reference Figure 2 The connecting molding layer 43 can be disposed on the horizontal conductive layer 41 in the through electrode region EXC. The third portion 47C of the support member 47 can be disposed on the connecting molding layer 43. The molding layer 53M can be aligned on the third portion 47C. The second portion 47B of the support member 47 can be disposed on the horizontal conductive layer 41 in the plurality of pad regions EXP. The second buried insulating layer 49 can be disposed on the second portion 47B.

[0023] Reference Figure 3 The substrate 21 may include a cell region CE and a connection region EX connected to the cell region CE. The connection region EX may include multiple pad regions EXP and multiple through electrode regions EXC between the multiple pad regions EXP. Multiple separator patterns 75 spanning the cell region CE and the connection region EX may be disposed on the substrate 21. Multiple intermediate separator patterns 76 may be disposed between the multiple separator patterns 75. Multiple cell channel structures 69 may be disposed in the cell region CE. Multiple pseudo-channel structures 69D may be disposed in the connection region EX. Multiple gate contact plugs 84 may be disposed in the multiple pad regions EXP. A first buried insulating layer 48 may be disposed in the multiple through electrode regions EXC. Multiple through electrodes 85 may be disposed in the first buried insulating layer 48.

[0024] Reference Figure 3 and Figure 4 The connecting conductive layer 45 can be disposed on the horizontal conductive layer 41 in the unit region CE. The connecting molding layer 43 can be disposed on the horizontal conductive layer 41 in multiple through electrode regions EXC.

[0025] The support member 47 may include a first part 47A, a second part 47B, and a third part 47C. The first part 47A may be disposed on the connection conductive layer 45 in the cell region CE. The second part 47B may be connected to the first part 47A. The second part 47B may be disposed on the horizontal conductive layer 41 in the connection region EX. The second part 47B may be disposed on the horizontal conductive layer 41 in the multiple pad regions EXP. The bottom surface of the second part 47B may directly contact the top surface of the horizontal conductive layer 41 in the multiple pad regions EXP. The connection area between the first part 47A and the second part 47B may have a step. The third part 47C may be connected to the second part 47B. The third part 47C may be disposed on the connection molding layer 43 in the multiple through electrode regions EXC. The connection area between the second part 47B and the third part 47C may have a step.

[0026] A first embedded insulating layer 48, passing through the third portion 47C and connecting the molding layer 43 and the horizontal conductive layer 41, can be disposed in a plurality of through electrode regions EXC. The top surfaces of the first portion 47A, the third portion 47C, and the first embedded insulating layer 48 can be substantially coplanar. The top surface of the second portion 47B can be disposed at a level lower than the top surfaces of the first portion 47A, the third portion 47C, and the first embedded insulating layer 48.

[0027] Reference Figure 5 Each of the multiple unit channel structures 69 may include a core pattern 61, a channel layer 62 surrounding the core pattern 61, an information storage pattern 66 surrounding the channel layer 62, and bit line pads 67. The information storage pattern 66 may include a tunneling insulating layer 63 surrounding the channel layer 62, a charge storage layer 64 surrounding the tunneling insulating layer 63, and a barrier layer 65 surrounding the charge storage layer 64.

[0028] The core pattern 61 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, polysilicon, or combinations thereof. The channel layer 62 may include a semiconductor layer, such as polysilicon, amorphous silicon, crystalline silicon, or combinations thereof. The tunneling insulating layer 63 may include an insulating layer, such as silicon nitride. The charge storage layer 64 may include an insulating layer, such as silicon nitride. The barrier layer 65 may include an insulating layer, such as silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric, or combinations thereof. The bit line pad 67 may include a conductive layer, such as metal, metal nitride, metal oxide, metal silicide, conductive carbon, polysilicon, or combinations thereof.

[0029] Reference Figure 6Each of the plurality of pseudo-channel structures 69D may include a construction similar to that of each of the plurality of unit channel structures 69. Each of the plurality of pseudo-channel structures 69D may include a core pattern 61, a channel layer 62, an information storage pattern 66, and a bit line pad 67. The information storage pattern 66 may include a tunneling insulating layer 63, a charge storage layer 64, and a barrier layer 65.

[0030] Reference Figure 7 The conductive layer 45 can be disposed between the first portion 47A of the support member 47 and the horizontal conductive layer 41. The conductive layer 45 can pass through the information storage pattern 66 and can directly contact the side surface of the channel layer 62.

[0031] Refer again Figures 1 to 7 The horizontal conductive layer 41 can correspond to a source line or a common-source line (CSL). The bottommost layer of the plurality of electrode layers 53C can correspond to a gate-induced drain leakage (GIDL) control line. The second layer of the plurality of electrode layers 53C relative to the bottom can correspond to a ground select line (GSL). The topmost layer of the plurality of electrode layers 53C can correspond to a GIDL control line. The second and third layers of the plurality of electrode layers 53C relative to the top can each correspond to a serial select line (SSL) or a drain select line (DSL). Some of the plurality of electrode layers 53C can each correspond to a word line. The plurality of separator patterns 75 and the plurality of intermediate separator patterns 76 can each correspond to a word line cut.

[0032] A horizontal conductive layer 41 can be disposed on the substrate 21. A support member 47 can be disposed on the horizontal conductive layer 41. A connecting conductive layer 45 can be disposed between the first portion 47A of the support member 47 and the horizontal conductive layer 41. The bottom surface of the second portion 47B of the support member 47 can directly contact the horizontal conductive layer 41. A second embedded insulating layer 49 can be disposed on the second portion 47B.

[0033] The connecting molding layer 43 can be disposed between the third portion 47C of the support member 47 and the horizontal conductive layer 41. The thickness of the connecting molding layer 43 can be the same as or substantially the same as the spacing between the first portion 47A and the horizontal conductive layer 41. The first embedded insulating layer 48 can be disposed in the through electrode region EXC. The first embedded insulating layer 48 can pass through the third portion 47C, the connecting molding layer 43, and the horizontal conductive layer 41. The first embedded insulating layer 48 can directly contact the side surface of the third portion 47C, the side surface of the connecting molding layer 43, and the side surface of the horizontal conductive layer 41.

[0034] The distance between the uppermost point of the second part 47B and the top surface of the substrate 21 can be shorter than the distance between the uppermost point of the first part 47A and the top surface of the substrate 21. The distance between the uppermost point of the second part 47B and the top surface of the substrate 21 can be shorter than the distance between the uppermost point of the third part 47C and the top surface of the substrate 21. The top surfaces of the first part 47A, the second buried insulating layer 49, the third part 47C, and the first buried insulating layer 48 can be substantially coplanar.

[0035] A stacked structure 50 may be disposed on the support 47, the second buried insulating layer 49, the third portion 47C, and the first buried insulating layer 48. The minimum spacing between the wiring layer 53 and the second portion 47B may be greater than the minimum spacing between the wiring layer 53 and the first portion 47A. The minimum spacing between the electrode layer 53C and the first portion 47A may be a first distance d1. The minimum spacing between the electrode layer 53C and the second portion 47B may be a second distance d2. The second distance d2 may be greater than the first distance d1. The molding layer 53M may be aligned on the third portion 47C. The molding layer 53M may cover the third portion 47C. The horizontal width of the molding layer 53M may be greater than the horizontal width of the third portion 47C. The minimum spacing between the electrode layer 53C and the third portion 47C may be a third distance d3. In a semiconductor device according to an exemplary embodiment of the present disclosure, leakage current between the support 47 and the electrode layer 53C can be significantly reduced.

[0036] Each of the plurality of unit channel structures 69 can pass through the stack structure 50, the first portion 47A and the connecting conductive layer 45, and can extend into the interior of the horizontal conductive layer 41. Each of the plurality of pseudo-channel structures 69D can pass through the interlayer insulating layer 59, the stack structure 50, the second buried insulating layer 49 and the second portion 47B, and can extend into the interior of the horizontal conductive layer 41.

[0037] Multiple through electrodes 85, passing through the second upper insulating layer 79, the first upper insulating layer 72, the interlayer insulating layer 59, the stacked structure 50, the first buried insulating layer 48, the third lower insulating layer 35, the cover layer 33, and the second lower insulating layer 31 and connected to multiple peripheral circuit wirings 29, can be disposed in the through electrode region EXC. The molding layer 53M can be aligned on the first buried insulating layer 48. The molding layer 53M can cover the first buried insulating layer 48. The horizontal width of the molding layer 53M can be greater than the horizontal width of the first buried insulating layer 48. The multiple through electrodes 85 can pass through the molding layer 53M.

[0038] Figure 8 This is for describing the layout of a semiconductor device according to an example embodiment of the present disclosure. Figure 9 It is a perspective view used to describe a semiconductor device. Figure 10 It is along Figure 8 The cross-sectional view taken from lines 4-4' and 5-5'. Figure 11 It is along Figure 8 The cross-sectional view taken from line 6-6'.

[0039] Reference Figures 8 to 11 The first embedded insulating layer 48 can completely span the third portion 47C of the support member 47. The third portion 47C can be divided into multiple parts by the first embedded insulating layer 48, which can completely span the connecting molding layer 43. The connecting molding layer 43 can be divided into multiple parts by the first embedded insulating layer 48.

[0040] Figure 12 This is for describing the layout of a semiconductor device according to an example embodiment of the present disclosure. Figure 13 It is a perspective view used to describe a semiconductor device. Figure 14 yes Figure 12 Cross-sectional views taken along lines 7-7' and 8-8'. Figure 15 It is along Figure 12 The cross-sectional view taken from line 9-9'.

[0041] Reference Figures 12 to 15 A horizontal conductive layer 41 can be disposed on the substrate 21. A support member 47 can be disposed on the horizontal conductive layer 41. A connecting conductive layer 45 can be disposed between the first portion 47A of the support member 47 and the horizontal conductive layer 41. The bottom surface of the second portion 47B of the support member 47 can directly contact the horizontal conductive layer 41. A second embedded insulating layer 49 can be disposed on the second portion 47B. In some example embodiments, the second embedded insulating layer 49 can be referred to as an embedded insulating layer. A connecting molding layer 43 can be disposed between the third portion 47C of the support member 47 and the horizontal conductive layer 41. The thickness of the connecting molding layer 43 can be the same as or substantially the same as the spacing between the first portion 47A and the horizontal conductive layer 41.

[0042] The distance between the uppermost end of the second portion 47B and the top surface of the substrate 21 can be shorter than the distance between the uppermost end of the first portion 47A and the top surface of the substrate 21. The top surfaces of the first portion 47A, the second buried insulating layer 49, and the third portion 47C can be substantially coplanar. A stacked structure 50, in which multiple insulating layers 51 and multiple wiring layers 53 are alternately stacked, can be disposed on the support 47 and the second buried insulating layer 49.

[0043] The minimum spacing between wiring layer 53 and the second portion 47B can be greater than the minimum spacing between wiring layer 53 and the first portion 47A. The minimum spacing between electrode layer 53C and the first portion 47A can be a first distance d1. The minimum spacing between electrode layer 53C and the second portion 47B can be a second distance d2. Molding layer 53M can be aligned on the third portion 47C. The minimum spacing between electrode layer 53C and the third portion 47C can be a third distance d3. The third distance d3 can be greater than the first distance d1.

[0044] Multiple cell channel structures 69, passing through the stacked structure 50, the first portion 47A, and the connecting conductive layer 45 and extending into the interior of the horizontal conductive layer 41, can be disposed in the cell region CE. Multiple pseudo-channel structures 69D, passing through the interlayer insulating layer 59, the stacked structure 50, the second buried insulating layer 49, and the second portion 47B and extending into the interior of the horizontal conductive layer 41, can be disposed in the connection region EX.

[0045] Multiple through electrodes 85, passing through the second upper insulating layer 79, the first upper insulating layer 72, the interlayer insulating layer 59, the stacked structure 50, the third part 47C, the connecting molding layer 43, the horizontal conductive layer 41, the third lower insulating layer 35, the cover layer 33 and the second lower insulating layer 31 and connected to multiple peripheral circuit wirings 29, can be disposed in multiple through electrode regions EXC.

[0046] Contact spacers 86 may be provided around the side surfaces of each of the plurality of through electrodes 85. The contact spacers 86 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or combinations thereof. The contact spacers 86 may be located between the plurality of through electrodes 85 and the molding layer 53M, between the plurality of through electrodes 85 and the third portion 47C, between the plurality of through electrodes 85 and the connecting molding layer 43, and between the plurality of through electrodes 85 and the horizontal conductive layer 41.

[0047] Figure 16 This is for describing the layout of a semiconductor device according to an example embodiment of the present disclosure. Figure 17 It is a perspective view used to describe a semiconductor device. Figure 18 It is along Figure 16 The cross-sectional views taken from lines 10-10' and 11-11'. Figure 19 It is along Figure 16 The cross-sectional view taken from line 12-12'.

[0048] Reference Figures 16 to 19A horizontal conductive layer 41 may be disposed on the substrate 21. A support member 47 may be disposed on the horizontal conductive layer 41. The support member 47 may include a first portion 47A and a second portion 47B. A connecting conductive layer 45 may be disposed between the first portion 47A of the support member 47 and the horizontal conductive layer 41. The first portion 47A may be disposed on the connecting conductive layer 45 in the cell region CE.

[0049] The second part 47B can be connected to the first part 47A. The second part 47B can be disposed on the horizontal conductive layer 41 in the connection area EX. The second part 47B can be disposed on the horizontal conductive layer 41 in the multiple pad areas EXP. The bottom surface of the second part 47B can directly contact the top surface of the horizontal conductive layer 41 in the multiple pad areas EXP. The connection area between the first part 47A and the second part 47B can have a step. The distance between the uppermost end of the second part 47B and the top surface of the substrate 21 can be shorter than the distance between the uppermost end of the first part 47A and the top surface of the substrate 21.

[0050] A second embedded insulating layer 49 can be disposed on the second portion 47B. A first embedded insulating layer 48 passing through the second portion 47B and the horizontal conductive layer 41 can be disposed in multiple through electrode regions EXC. The top surfaces of the first portion 47A, the second embedded insulating layer 49, and the first embedded insulating layer 48 can be substantially coplanar. A stacked structure 50, in which multiple insulating layers 51 and multiple wiring layers 53 are alternately stacked, can be disposed on the support 47, the second embedded insulating layer 49, and the first embedded insulating layer 48. The minimum spacing between the wiring layer 53 and the second portion 47B can be greater than the minimum spacing between the wiring layer 53 and the first portion 47A.

[0051] Multiple cell channel structures 69, passing through the stacked structure 50, the first portion 47A, and the connecting conductive layer 45 and extending into the interior of the horizontal conductive layer 41, can be disposed in the cell region CE. Multiple pseudo-channel structures 69D, passing through the interlayer insulating layer 59, the stacked structure 50, the second buried insulating layer 49, and the second portion 47B and extending into the interior of the horizontal conductive layer 41, can be disposed in the connection region EX.

[0052] Multiple through electrodes 85 that pass through the second upper insulating layer 79, the first upper insulating layer 72, the interlayer insulating layer 59, the stacked structure 50, the first buried insulating layer 48, the third lower insulating layer 35, the cover layer 33, and the second lower insulating layer 31 and are connected to multiple peripheral circuit wirings 29 can be disposed in multiple through electrode regions EXC.

[0053] Figure 20 and Figure 21 This is for describing the semiconductor device according to an example embodiment of the present disclosure. Figure 3The cross-sectional view taken from lines 1-1' and 2-2'.

[0054] Reference Figure 20 The horizontal conductive layer 41 can be connected to a plurality of transistors 25 via some of the corresponding peripheral circuit wirings 29. Some of the peripheral circuit wirings 29 can extend into the interior of each of the first lower insulating layer 27, the second lower insulating layer 31, the cover layer 33 and the third lower insulating layer 35, and can contact the bottom surface of the horizontal conductive layer 41.

[0055] Reference Figure 21 Semiconductor devices according to exemplary embodiments of the present disclosure can be formed using wafer bonding techniques. For example, a first bonding layer 37 and a second bonding layer 38 may be disposed between a third lower insulating layer 35 and a horizontal conductive layer 41. The first bonding layer 37 and the second bonding layer 38 may extend to a portion between the third lower insulating layer 35 and the first buried insulating layer 48. A plurality of through electrodes 85 passing through the second upper insulating layer 79, the first upper insulating layer 72, the interlayer insulating layer 59, the stack structure 50, the first buried insulating layer 48, the second bonding layer 38, the first bonding layer 37, the third lower insulating layer 35, the cover layer 33, and the second lower insulating layer 31 and connected to a plurality of peripheral circuit wirings 29 may be disposed in the through electrode region EXC.

[0056] The first bonding layer 37 may be formed on the third lower insulating layer 35. The second bonding layer 38 may be disposed on the bottom surface of the horizontal conductive layer 41. The second bonding layer 38 may contact the first bonding layer 37. Each of the first bonding layer 37 and the second bonding layer 38 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof.

[0057] Figure 22 , Figure 24 , Figure 26 , Figure 28 , Figure 30 , Figure 32 , Figure 34 , Figure 36 and Figure 38 This is a description of a method for manufacturing a semiconductor device according to embodiments of the present disclosure. Figure 3 The cross-sectional view taken from lines 1-1' and 2-2'. Figure 23 , Figure 25 , Figure 27 , Figure 29 , Figure 31 , Figure 33 , Figure 35 and Figure 37 It is used to describe the methods of manufacturing semiconductor devices. Figure 3 The cross-sectional view taken from line 3-3'.

[0058] Reference Figure 3 , Figure 22 and Figure 23 An isolation layer 23, multiple transistors 25, a first lower insulating layer 27, multiple peripheral circuit wirings 29, a second lower insulating layer 31, a cover layer 33, and a third lower insulating layer 35 can be formed on the substrate 21.

[0059] Substrate 21 may include a semiconductor substrate such as a silicon wafer. Each of the isolation layer 23, the first lower insulating layer 27, the second lower insulating layer 31, and the third lower insulating layer 35 may include a compound comprising silicon (Si) and oxygen (O), a compound comprising Si and nitrogen (N), silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. Isolation layer 23 may include an insulating layer formed using a shallow trench isolation (STI) method. Capping layer 33 may include a material different from the material of each of the second lower insulating layer 31 and the third lower insulating layer 35. In some example embodiments, capping layer 33 may include a compound comprising Si and N, silicon nitride, silicon oxynitride, silicon boron nitride (SiBN), silicon carbon nitride (SiCN), or a combination thereof. The top surface of the third lower insulating layer 35 may be planarized.

[0060] Multiple transistors 25 can be formed in / on the substrate 21 by various methods. The multiple transistors may include fin field-effect transistors (finFETs), multi-bridge channel (MBC) transistors, nanowire transistors, vertical transistors, groove channel transistors, 3D transistors, planar transistors, or combinations thereof.

[0061] The first lower insulating layer 27 can cover the isolation layer 23 and multiple transistors 25. A second lower insulating layer 31, a cover layer 33, and a third lower insulating layer 35 can be sequentially formed on the first lower insulating layer 27. Multiple peripheral circuit wirings 29 can be formed in the first lower insulating layer 27. Each of the multiple peripheral circuit wirings 29 can comprise a metal, metal nitride, metal silicide, metal oxide, conductive carbon, polysilicon, or a combination thereof. The multiple peripheral circuit wirings 29 can be connected to multiple transistors 25. The multiple peripheral circuit wirings 29 can include horizontal and vertical wirings each having various shapes. The multiple transistors 25 and the multiple peripheral circuit wirings 29 can construct a peripheral circuit.

[0062] Reference Figure 3 , Figure 24 and Figure 25 A horizontal conductive layer 41 may be formed on the third lower insulating layer 35. A connecting molding layer 43 may be formed on the horizontal conductive layer 41.

[0063] The horizontal conductive layer 41 may include a metal, a metal nitride, a metal silicide, a metal oxide, conductive carbon, polysilicon, or a combination thereof. In some example embodiments, the horizontal conductive layer 41 may include a doped polysilicon layer. The horizontal conductive layer 41 may be a single layer or multiple layers. The horizontal conductive layer 41 may include a polysilicon layer, a tungsten silicide (WSi) layer, a tungsten (W) layer, a cobalt silicide (CoSi) layer, a nickel silicide (NiSi) layer, a titanium (Ti) layer, a titanium nitride (TiN) layer, a titanium silicide (TiSi) layer, a tantalum (Ta) layer, a tantalum nitride (TaN) layer, a tantalum silicide (TaSi) layer, or a combination thereof.

[0064] The bonding molding layer 43 may include a material that is etch-selective relative to the horizontal conductive layer 41. The bonding molding layer 43 may include a lower molding layer 43L, an intermediate molding layer 43M, and an upper molding layer 43U stacked in sequence. Each of the lower molding layer 43L and the upper molding layer 43U may be thinner than the intermediate molding layer 43M. In some example embodiments, the lower molding layer 43L and the upper molding layer 43U may include compounds comprising Si and O (e.g., silicon oxide), and the intermediate molding layer 43M may include compounds comprising Si and N (e.g., silicon nitride).

[0065] Reference Figure 2 , Figure 26 and Figure 27 The top surface of the horizontal conductive layer 41 can be exposed in multiple pad areas EXP by partially removing the connection molding layer 43 using a patterning process. The connection molding layer 43 can be retained on the horizontal conductive layer 41 in the cell area CE and the through electrode area EXC.

[0066] Reference Figure 3 , Figure 28 and Figure 29 A support member 47 can be formed on the horizontal conductive layer 41 and the connecting molding layer 43. The support member 47 can directly contact the top and side surfaces of the connecting molding layer 43. The support member 47 can directly contact the top surface of the horizontal conductive layer 41 in the multiple pad areas EXP. A second buried insulating layer 49 can be formed on the support member 47.

[0067] The support 47 may include a material that is etch-selective relative to the connecting molding layer 43. For example, the support 47 may include a polysilicon layer. The second buried insulating layer 49 may include a compound containing Si and O (e.g., silicon oxide), a compound containing Si and N (e.g., silicon nitride), silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. For example, the second buried insulating layer 49 may include a silicon oxide layer.

[0068] Reference Figure 3 , Figure 30 and Figure 31A first buried insulating layer 48 may be formed on the second buried insulating layer 49. The first buried insulating layer 48 may extend into the interior of each of the second buried insulating layer 49, the support 47, the connecting molding layer 43, and the horizontal conductive layer 41 within the through electrode region EXC. The first buried insulating layer 48 may completely penetrate the second buried insulating layer 49, the support 47, the connecting molding layer 43, and the horizontal conductive layer 41 within the through electrode region EXC and may directly contact the third lower insulating layer 35. The first buried insulating layer 48 may include compounds containing Si and O, compounds containing Si and N, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, high-k dielectrics, or combinations thereof. For example, the first buried insulating layer 48 may include a silicon oxide layer.

[0069] Reference Figure 3 , Figure 32 and Figure 33 The top surface of the support 47 can be partially exposed by planarizing the first embedded insulating layer 48 and the second embedded insulating layer 49. Chemical mechanical polishing (CMP), etching back, or a combination thereof can be applied to planarize the first embedded insulating layer 48 and the second embedded insulating layer 49.

[0070] The support 47 may include a first portion 47A in the cell region CE, a second portion 47B in the plurality of pad regions EXP, and a third portion 47C in the through electrode region EXC. A first buried insulating layer 48 may be retained in the through electrode region EXC. The first buried insulating layer 48 may extend into the interior of the third portion 47C, the connecting molding layer 43, and the horizontal conductive layer 41. The first buried insulating layer 48 may completely penetrate the third portion 47C, the connecting molding layer 43, and the horizontal conductive layer 41, and may directly contact the third lower insulating layer 35. A second buried insulating layer 49 may cover the second portion 47B. The top surfaces of the first portion 47A, the second buried insulating layer 49, the third portion 47C, and the first buried insulating layer 48 may be exposed in the same plane or substantially the same plane.

[0071] The third part 47C of the support member 47 can perform the function of maintaining the coplanar surfaces of the top surface of the first part 47A, the top surface of the second embedded insulating layer 49, the top surface of the third part 47C and the top surface of the first embedded insulating layer 48 while performing a planarization process.

[0072] Reference Figure 3 , Figure 34 and Figure 35An initial stacked structure 50T can be formed on the first portion 47A, the second buried insulating layer 49, the third portion 47C, and the first buried insulating layer 48. The initial stacked structure 50T may include a plurality of insulating layers 51 and a plurality of molding layers 53M stacked alternately and repeatedly. The plurality of molding layers 53M may include a material having etch selectivity relative to the plurality of insulating layers 51. In some example embodiments, the plurality of insulating layers 51 may include a compound layer comprising Si and O (e.g., silicon oxide), and the plurality of molding layers 53M may include a compound layer comprising Si and N (e.g., silicon nitride).

[0073] Reference Figure 3 , Figure 36 and Figure 37 The initial stacked structure 50T can be partially removed, and an interlayer insulating layer 59 can be formed. The interlayer insulating layer 59 can cover the initial stacked structure 50T in the connection region EX. The interlayer insulating layer 59 can include compounds containing Si and O, compounds containing Si and N, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or combinations thereof. For example, the interlayer insulating layer 59 can include a silicon oxide layer.

[0074] Reference Figure 2 , Figure 3 and Figure 38 Multiple cell channel structures 69 and multiple pseudo-channel structures 69D can be formed, each passing through the initial stack structure 50T. Each of the multiple cell channel structures 69 can be disposed in the cell region CE. Each of the multiple cell channel structures 69 can pass through the initial stack structure 50T, the first portion 47A, and the connecting molding layer 43, and can extend into the interior of the horizontal conductive layer 41. Each of the multiple cell channel structures 69 may include Figure 5 and Figure 7 The configuration is shown. Each of the plurality of pseudo-channel structures 69D can be disposed in the connection region EX. Each of the plurality of pseudo-channel structures 69D can pass through the interlayer insulating layer 59, the initial stack structure 50T, the second buried insulating layer 49, and the second portion 47B, and can extend into the interior of the horizontal conductive layer 41. Each of the plurality of pseudo-channel structures 69D may include Figure 6 The construction shown.

[0075] A first upper insulating layer 72 can be formed on the initial stacked structure 50T, multiple cell channel structures 69, multiple pseudo-channel structures 69D, and interlayer insulating layer 59. The connection molding layer 43 in the cell region CE can be removed, and a connection conductive layer 45 can be formed. The connection conductive layer 45 can be formed between the first portion 47A in the cell region CE and the horizontal conductive layer 41. The connection conductive layer 45 may include a metal, metal nitride, metal silicide, metal oxide, conductive carbon, polysilicon, or a combination thereof. For example, the connection conductive layer 45 may include a doped polysilicon layer. Figure 7 As shown, the conductive layer 45 can pass through the information storage pattern 66 and can directly contact the side surface of the channel layer 62. The molded layer 43 can be partially retained in the through electrode region EXC.

[0076] Multiple molding layers 53M can be partially removed, and multiple electrode layers 53C can be formed. Multiple molding layers 53M can remain within the electrode region EXC. Multiple electrode layers 53C and multiple molding layers 53M can construct multiple wiring layers 53. Multiple insulating layers 51 and multiple wiring layers 53 can construct a stacked structure 50. Each of the multiple electrode layers 53C can include a metal, a metal nitride, a metal silicide, a metal oxide, conductive carbon, polysilicon, or a combination thereof.

[0077] Multiple separator patterns 75 and multiple intermediate separator patterns 76 can be formed across the stacked structure 50. Multiple intermediate separator patterns 76 can be formed between the multiple separator patterns 75. The multiple separator patterns 75 and multiple intermediate separator patterns 76 can each include a compound containing Si and O, a compound containing Si and N, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. For example, the multiple separator patterns 75 and multiple intermediate separator patterns 76 can each include a silicon oxide layer.

[0078] In the cell region CE, each of the plurality of separator patterns 75 and the plurality of intermediate separator patterns 76 can pass through the first upper insulating layer 72, the stacked structure 50, the first portion 47A, and the connecting molding layer 43, and can extend into the interior of the horizontal conductive layer 41. In the connection region EX, each of the plurality of separator patterns 75 and the plurality of intermediate separator patterns 76 can pass through the first upper insulating layer 72, the interlayer insulating layer 59, the stacked structure 50, the second buried insulating layer 49, and the second portion 47B, and can extend into the interior of the horizontal conductive layer 41.

[0079] Multiple bit line plugs 81 can be formed in the cell region CE, passing through the first upper insulating layer 72 and connecting to multiple cell channel structures 69. Multiple bit lines 83 connected to the multiple bit line plugs 81 can be formed on the first upper insulating layer 72. A second upper insulating layer 79 can be formed on the first upper insulating layer 72, multiple separator patterns 75, multiple intermediate separator patterns 76, and multiple bit lines 83.

[0080] Multiple through electrodes 85 can be formed in the through electrode region EXC, passing through the second upper insulating layer 79, the first upper insulating layer 72, the interlayer insulating layer 59, the stacked structure 50, the first buried insulating layer 48, the third lower insulating layer 35, the cover layer 33, and the second lower insulating layer 31, and connected to multiple peripheral circuit wirings 29. The multiple through electrodes 85 can pass through multiple molding layers 53M. The multiple through electrodes 85 can be electrically connected to multiple transistors 25.

[0081] Each of the first upper insulating layer 72 and the second upper insulating layer 79 may include a compound containing Si and O, a compound containing Si and N, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. For example, each of the first upper insulating layer 72 and the second upper insulating layer 79 may include a silicon oxide layer. The plurality of bit line plugs 81, the plurality of bit lines 83, and the plurality of through electrodes 85 may each include a metal, a metal nitride, a metal silicide, a metal oxide, conductive carbon, polysilicon, or a combination thereof.

[0082] Refer again Figures 1 to 3 Multiple upper wirings 87 connected to multiple through electrodes 85 can be formed on the second upper insulating layer 79. The multiple upper wirings 87 may include metal, metal nitride, metal silicide, metal oxide, conductive carbon, polysilicon, or combinations thereof.

[0083] Figure 39 This is a description of a method for manufacturing a semiconductor device according to exemplary embodiments of the present disclosure. Figure 3 The cross-sectional view taken from lines 1-1' and 2-2'. Figure 40 It is used to describe the methods for manufacturing semiconductor devices. Figure 3 A cross-sectional view taken from line 3-3'.

[0084] Reference Figure 3 , Figure 39 and Figure 40The top surface of the second buried insulating layer 49A may be formed at a level lower than the top surfaces of the first portion 47A and the third portion 47C. The distance between the top surface of the second buried insulating layer 49A and the top surface of the substrate 21 may be shorter than the distance between the top surface of the third portion 47C and the top surface of the substrate 21. The distance between the top surface of the second buried insulating layer 49A and the top surface of the substrate 21 may be shorter than the distance between the top surface of the first portion 47A and the top surface of the substrate 21. In some example embodiments, the top surface of the second buried insulating layer 49A may be formed at a level lower than the top surfaces of the first portion 47A, the third portion 47C, and the first buried insulating layer 48.

[0085] Figure 41 This is for describing the semiconductor device according to an example embodiment of the present disclosure. Figure 3 The cross-sectional view taken from lines 1-1' and 2-2'. Figure 42 It is used to describe the edges of semiconductor devices Figure 3 The cross-sectional view taken from line 3-3'. Figure 43 It is used to describe the edges of semiconductor devices Figure 3 The cross-sectional view taken from line 13-13'.

[0086] Reference Figure 3 and Figures 41 to 43 The top surface of the second embedded insulating layer 49A may be formed at a level lower than the top surface of the first portion 47A and the top surface of the third portion 47C. The lowermost wiring layer of the plurality of wiring layers 53 may include a first region overlapping the first portion 47A, a second region overlapping the second portion 47B, and a third region overlapping the third portion 47C. The top surface of the third region may be formed at the same or substantially the same level as the top surface of the first region. The top surface of the second region may be formed at a level lower than the top surfaces of the first and third regions.

[0087] Each of the plurality of wiring layers 53 may include an electrode layer 53C and a molding layer 53M connected to the side surface of the electrode layer 53C. The molding layer 53M may be aligned on the first buried insulating layer 48 and the third portion 47C. The molding layer 53M may overlap with the first buried insulating layer 48 and the third portion 47C. The horizontal width of the molding layer 53M may be greater than the horizontal width of the first buried insulating layer 48. The horizontal width of the molding layer 53M may be greater than the horizontal width of the third portion 47C. Each of the first region and the second region may include the electrode layer 53C. The third region may include the molding layer 53M.

[0088] According to some exemplary embodiments of this disclosure, a support member can be provided comprising a first portion, a second portion formed at a level below the first portion, and a third portion formed at the same level as the first portion. A first buried insulating layer can be provided through the third portion. A second buried insulating layer can be provided on the second portion. Leakage current between the wiring layer and the support member can be significantly reduced. The third portion of the support member can function to maintain the top surfaces of the first portion, the first buried insulating layer, the third portion, and the second buried insulating layer as coplanar surfaces while a planarization process is performed. Therefore, a semiconductor for improving or maximizing manufacturing efficiency and / or reducing or minimizing leakage current can be realized.

[0089] In the foregoing, exemplary embodiments of the present disclosure have been described with reference to the accompanying drawings. However, it will be understood that those skilled in the art can implement the embodiments in another detailed form without altering the inventive concept or essential features. It should be understood that the above exemplary embodiments are merely examples of all aspects and are not limiting.

Claims

1. A semiconductor device comprising: a substrate including a cell region and a connection region connected to the cell region, the connection region including a plurality of pad regions and a through-electrode region between the plurality of pad regions; a horizontal conductive layer on the substrate; a support on the horizontal conductive layer, the support including a first portion in the cell region, a second portion in the plurality of pad regions, and a third portion in the through-electrode region; a connection conductive layer between the first portion of the support and the horizontal conductive layer; a connection molding layer between the third portion of the support and the horizontal conductive layer; a first buried insulating layer in the through-electrode region to pass through the third portion, the connection molding layer, and the horizontal conductive layer; a cell channel structure in the cell region to pass through a stacked structure in which a plurality of insulating layers and a plurality of wiring layers are alternately stacked and the first portion, and to extend to an inside of the horizontal conductive layer; and a through-electrode in the through-electrode region to pass through the first buried insulating layer. A top surface of the third portion and a top surface of the first portion are substantially coplanar.

2. The semiconductor device according to claim 1, wherein A distance between an uppermost end of the second portion and a top surface of the substrate is shorter than a distance between an uppermost end of the first portion and the top surface of the substrate.

3. The semiconductor device according to claim 1, wherein A bottom surface of the second portion contacts the horizontal conductive layer.

4. The semiconductor device according to claim 1, wherein A top surface of the first portion, a top surface of the third portion, and a top surface of the first buried insulating layer are substantially coplanar.

5. The semiconductor device according to claim 1, wherein 6. The semiconductor device according to claim 1, wherein the stacked structure extends to an inside of each of the plurality of pad regions, and a minimum spacing between a corresponding wiring layer of the plurality of wiring layers and the second portion is greater than a minimum spacing between the corresponding wiring layer and the first portion.

7. The semiconductor device according to claim 1, wherein the stacked structure extends to an inside of each of the plurality of pad regions and the through-electrode region, each of the plurality of wiring layers includes an electrode layer and a wiring molding layer connected to a side surface of the electrode layer, and a minimum spacing between the electrode layer and the third portion is greater than a minimum spacing between the electrode layer and the first portion.

8. The semiconductor device according to claim 7, wherein a plurality of the wiring molding layers of the plurality of wiring layers are aligned with each other on the first buried insulating layer, and the through-electrode passes through the wiring molding layers. A thickness of the connection molding layer and a spacing between the first portion and the horizontal conductive layer are substantially the same.

9. The semiconductor device according to claim 1, wherein 10. The semiconductor device according to claim 1, wherein the stacked structure extends to an inside of each of the plurality of pad regions, the semiconductor device further includes a second buried insulating layer between the second portion and the stacked structure, and a top surface of the first portion, a top surface of the third portion, a top surface of the first buried insulating layer, and a top surface of the second buried insulating layer are substantially coplanar.

11. The semiconductor device according to claim 1, wherein ​ the stack structure extends inside each of the plurality of pad regions, the semiconductor device further includes a second buried insulating layer between the second portion and the stack structure, a distance between a top surface of the second buried insulating layer and a top surface of the substrate is shorter than a distance between an uppermost end of the first portion and the top surface of the substrate, and a distance between a top surface of the second buried insulating layer and a top surface of the substrate is shorter than a distance between an uppermost end of the third portion and the top surface of the substrate.

12. The semiconductor device according to claim 1, wherein the stack structure extends inside each of the plurality of pad regions and the through-electrode region, each of the plurality of wiring layers includes an electrode layer and a wiring molding layer connected to a side surface of the electrode layer, and the semiconductor device further includes a second buried insulating layer between the second portion and the stack structure, a plurality of the wiring molding layers in the plurality of wiring layers are aligned with each other on the first buried insulating layer, and a width of the wiring molding layer is greater than a width of the first buried insulating layer.

13. The semiconductor device according to claim 12, wherein the wiring molding layer overlaps the third portion, and a width of the wiring molding layer is greater than a width of the third portion.

14. The semiconductor device according to claim 12, wherein a lowermost wiring layer in the plurality of wiring layers includes a first region overlapping the first portion, a second region overlapping the second portion, and a third region overlapping the third portion, a top surface of the third region is located at substantially the same level as a top surface of the first region, and a top surface of the second region is located at a level lower than the top surface of the first region and the top surface of the third region.

15. The semiconductor device according to claim 14, wherein the third region of the lowermost wiring layer includes the wiring molding layer.

16. A semiconductor device comprising: a substrate including a cell region and a connection region connected to the cell region, the connection region including a plurality of pad regions and a through-electrode region between the plurality of pad regions; a horizontal conductive layer on the substrate; a support on the horizontal conductive layer, the support including a first portion in the cell region, a second portion in the plurality of pad regions, and a third portion in the through-electrode region; a connection conductive layer between the first portion of the support and the horizontal conductive layer; a connection molding layer between the third portion of the support and the horizontal conductive layer; a first buried insulating layer in the through-electrode region to pass through the third portion, the connection molding layer, and the horizontal conductive layer; a second buried insulating layer in the plurality of pad regions to cover the second portion; a stack structure in which a plurality of insulating layers and a plurality of wiring layers are alternately stacked on the support, the first buried insulating layer, and the second buried insulating layer; a cell channel structure in the cell region to pass through the stack structure and the first portion, and to extend inside the horizontal conductive layer; a dummy trench structure located in the plurality of pad regions to pass through the stack structure, the second buried insulating layer, and the second portion, and to extend to an inside of the horizontal conductive layer; and a through electrode located in the through electrode region to pass through the stack structure and the first buried insulating layer.

17. The semiconductor device according to claim 16, wherein a distance between a top surface of the second buried insulating layer and a top surface of the substrate is shorter than a distance between an uppermost end of the first portion and the top surface of the substrate, and a distance between a top surface of the second buried insulating layer and a top surface of the substrate is shorter than a distance between an uppermost end of the third portion and the top surface of the substrate.

18. The semiconductor device according to claim 16, wherein a lowermost one of the plurality of wiring layers includes a first region overlapping with the first portion, a second region overlapping with the second portion, and a third region overlapping with the third portion, a top surface of the third region is located substantially at the same level as a top surface of the first region, and a top surface of the second region is located at a level lower than the top surface of the first region and the top surface of the third region.

19. A semiconductor device comprising: a substrate including a cell region and a connection region connected to the cell region, the connection region including a plurality of pad regions and a through electrode region located between the plurality of pad regions; a horizontal conductive layer located on the substrate; a support located on the horizontal conductive layer, the support including a first portion in the cell region, a second portion in the plurality of pad regions, and a third portion in the through electrode region; a connection conductive layer located between the first portion of the support and the horizontal conductive layer; a connection molding layer located between the third portion of the support and the horizontal conductive layer; a first buried insulating layer located in the through electrode region to pass through the third portion, the connection molding layer, and the horizontal conductive layer; a second buried insulating layer located in the plurality of pad regions to cover the second portion; a cell trench structure located in the cell region to pass through a stack structure in which a plurality of insulating layers and a plurality of wiring layers are alternately stacked and the first portion, and to extend to an inside of the horizontal conductive layer; a through electrode located in the through electrode region to pass through the first buried insulating layer; and a bit line located on the stack structure and connected to the cell trench structure.

20. The semiconductor device according to claim 19, wherein top surfaces of the first portion, the third portion, a top surface of the first buried insulating layer, and a top surface of the second buried insulating layer are substantially coplanar.

21. A method of manufacturing a semiconductor device, the method comprising: providing a substrate including a cell region and a connection region connected to the cell region, the connection region including a plurality of pad regions and a through electrode region located between the plurality of pad regions; forming a horizontal conductive layer on the substrate; forming a support on the horizontal conductive layer, the support including a first portion in the cell region, a second portion in the plurality of pad regions, and a third portion in the through electrode region; a connection conductive layer is formed between the first portion of the support and the horizontal conductive layer; a connection molding layer is formed between the third portion of the support and the horizontal conductive layer; a first buried insulating layer is formed in the through-electrode region, the first buried insulating layer passing through the third portion, the connection molding layer, and the horizontal conductive layer; a stack structure in which a plurality of insulating layers and a plurality of wiring layers are alternately stacked is formed on the substrate; a cell channel structure is formed in the cell region, the cell channel structure passing through the stack structure and the first portion and extending to an inside of the horizontal conductive layer; and a through-electrode is formed in the through-electrode region, the through-electrode passing through the first buried insulating layer. forming the support includes:

22. The method of claim 21, wherein, forming the connection molding layer on the horizontal conductive layer; partially removing the connection molding layer to expose the horizontal conductive layer in the plurality of pad regions; and forming the support on the exposed horizontal conductive layer and the connection molding layer. a top surface of the third portion and a top surface of the first portion are substantially coplanar.

23. The method of claim 21, wherein, a distance between an uppermost end of the second portion and a top surface of the substrate is shorter than a distance between an uppermost end of the first portion and the top surface of the substrate.

24. The method of claim 21, wherein, a thickness of the connection molding layer and a spacing between the first portion and the horizontal conductive layer are substantially the same.

25. The method of claim 21, wherein, ​

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